32nd week of 2022 patent applcation highlights part 63 |
Patent application number | Title | Published |
20220254804 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BRIDGES FOR ENHANCED STRUCTURAL SUPPORT AND METHODS OF FORMING THE SAME - A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region. | 2022-08-11 |
20220254805 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar. | 2022-08-11 |
20220254806 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers. | 2022-08-11 |
20220254807 | SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level. | 2022-08-11 |
20220254808 | VERTICAL MEMORY DEVICES - A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction. | 2022-08-11 |
20220254809 | INTERCONNECT STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another. | 2022-08-11 |
20220254810 | Integrated Assemblies, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly. | 2022-08-11 |
20220254811 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors. | 2022-08-11 |
20220254812 | FRONT END INTEGRATED CIRCUITS INCORPORATING DIFFERING SILICON-ON-INSULATOR TECHNOLOGIES - SOI-based technology platforms are described that provide fully integrated front end integrated circuits (FEICs) that include switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick film region of the integrated circuit, resulting in a partially depleted silicon-on-insulator (PDSOI) PA, and the switches and LNAs can be built in a thin film region of the integrated circuit, resulting in fully depleted silicon-on-insulator (FDSOI) switches and LNAs. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film region, the thin film region, or both regions. | 2022-08-11 |
20220254813 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a first substrate, a first electrode on the first substrate, a second electrode on the first substrate and spaced from the first electrode, a plurality of light-emitting elements each having respective end portions on the first and second electrodes, a first transistor having a first end connected to the first electrode and a second end grounded, and a second transistor having a first end connected to the second electrode and a second end grounded, wherein the first transistor is forward-biased to the first electrode, and the second transistor is reverse-biased to the second electrode. | 2022-08-11 |
20220254814 | ACTIVE MATRIX SUBSTRATE - An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film. | 2022-08-11 |
20220254815 | ARRAY SUBSTRATE, ELECTRONIC DEVICE SUBSTRATE AND ELECTRONIC DEVICE - Provided is an array substrate, comprising a plurality of opening regions. The array substrate further comprises a substrate and at least one functional layer stacked on one side of the substrate. The functional layer comprises a plurality of functional patterns and at least one supplementary pattern, the plurality of functional patterns are configured to transmit electrical signals, and there is a gas region between the plurality of functional patterns; the at least one supplementary pattern is at least provided in at least one opening region, and the supplementary pattern is located in the gap region between the plurality of functional patterns. The plurality of functional patterns and the at least one supplementary pattern are spaced apart, and the plurality of functional patterns and the at least one supplementary pattern are arranged at substantially equal intervals. | 2022-08-11 |
20220254816 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area adjacent to the display area, a plurality of pixels being located in the display area, a driver located in the non-display area, a data line electrically connected to the driver to transmit a data signal to each of the plurality of pixels, a first driving voltage line and a second driving voltage line in the non-display area, and an antistatic portion in the non-display area and connected between the data line and the first driving voltage line. The display area further includes at least one first area electrically connected to one side of the driver and at least one second area electrically connected to another side of the driver. In addition, the non-display area includes a first non-display area corresponding to the first area and a second non-display area corresponding to the second area. | 2022-08-11 |
20220254817 | IMAGING DEVICE, IMAGING SYSTEM, AND MOVING BODY - An imaging device includes a first transmission line connected to a plurality of bit memories, a plurality of second bit memories disposed outside the memory area, and connected to the first transmission line, and each are configured to hold a digital signal of one bit that is one of different bits among a plurality of bits, a second transmission line connected to a part of the plurality of second bit memories, and a third transmission line connected to another part of the plurality of second bit memories. | 2022-08-11 |
20220254818 | IMAGE SENSING DEVICE - Image sensing devices are disclosed. In some implementations, an image sensing device may include a substrate having an upper surface and a lower surface, a photoelectric conversion device formed in the substrate and structured to convert incident light into an electrical signal carrying information associated with the incident light, and an isolation structure formed in the substrate along at least a side surface and a bottom surface of the photoelectric conversion device. The isolation structure comprises a first isolation region which extends from the upper surface of the substrate to a first depth in the substrate to surround the side surface of the photoelectric conversion device, and a second isolation region which is formed in the substrate below the bottom surface of the photoelectric conversion device, the second isolation region electrically connected with the first isolation region. | 2022-08-11 |
20220254819 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes: a semiconductor substrate; a photoelectric converter having a predetermined dimension in a thickness direction of the semiconductor substrate; a first charge accumulator that is provided in the semiconductor substrate and accumulates a signal charge generated by the photoelectric converter; and a transfer gate including a first electrode section and a second electrode section, the first electrode section being embedded in the semiconductor substrate, having a first dimension in the thickness direction of the semiconductor substrate, and being provided on a side of the photoelectric converter, and the second electrode section being selectively provided at a position closer to the first charge accumulator than the first electrode section and having a second dimension in the thickness direction of the semiconductor substrate smaller than the first dimension. | 2022-08-11 |
20220254820 | APPARATUS, SYSTEM, AND MOVING BODY - An apparatus includes pixels on a substrate. Each pixel includes a first portion, a second, and a microlens. The substrate has a first surface on an incidence side and a second surface opposite to the first surface, and includes an inter-pixel portion isolating adjacent pixels from each other, and an intra-pixel portion isolating the first and second portions from each other. The inter-pixel portion includes a first region located adjacently to the first surface, and a second region located adjacently to the second surface. The intra-pixel portion includes a third region located adjacently to the first surface, and a fourth region located adjacently to the second surface. The first and third regions are shifted with respect to the second and fourth regions, respectively, in an identical direction that is a direction orthogonal to a longitudinal direction of the intra-pixel portion in plan view from the first surface. | 2022-08-11 |
20220254821 | POWER SUPPLY CONTACT SHARING FOR IMAGING DEVICES - An imaging device includes a first pixel # | 2022-08-11 |
20220254822 | UTTB PHOTODETECTOR PIXEL UNIT, ARRAY AND METHOD - The present application discloses a UTBB photodetector pixel unit, array and method, including: a silicon film layer, a buried oxide layer, a charge collection layer and a substrate, the silicon film layer, the buried oxide layer, the charge collection layer and the substrate being arranged in sequence from top to bottom; the silicon film layer includes NMOS transistors or PMOS transistors; the charge collection layer includes charge collection control regions and charge accumulation regions; and the substrate includes an N-type substrate or a P-type substrate. A centripetal electric field is formed around the charge accumulation regions, and photo-generated charges are accumulated in the corresponding pixel units under the action of the centripetal electric field. The existence of the centripetal electric field improves the photoelectric conversion efficiency, suppresses the crosstalk between pixels, saves the area of shallow trench isolation, reduces the size, and makes it more suitable for sub-micron pixels. | 2022-08-11 |
20220254823 | IMAGING DEVICE - An imaging device according to an embodiment of the present disclosure includes: a photoelectric converter that is provided on an inner side than one principal surface of a semiconductor substrate; a transfer gate electrode that includes a first electrode section and a second electrode section, and provides as a transfer path which reads electric charge that has been photoelectrically converted by the photoelectric converter, the first electrode section extending, in a columnar shape, from the one principal surface of the semiconductor substrate in a depth direction of the semiconductor substrate, the second electrode section further extending, in a columnar shape, from the first electrode section in the depth direction; and a first conduction-type region that includes a first conduction-type impurity and is provided on a lateral part of the transfer gate electrode. A width of the second electrode section in at least one direction in a plane of the one principal surface is smaller than a width of the first electrode section in the at least one direction. The first conduction-type region is provided at least in a region of an under part of the first electrode section and a lateral part of the second electrode section, in the at least one direction. | 2022-08-11 |
20220254824 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - To arrange a protective material horizontally with respect to a substrate plane without the protective material coming into contact with wires in a wire-bonded semiconductor package. | 2022-08-11 |
20220254825 | THERMAL SENSOR MODULE WITH DUAL PACKAGE - A thermal sensor module is disclosed and includes a substrate; a thermal sensor disposed on the substrate; an inner package structure disposed on the substrate, surrounding the thermal sensor, and encapsulating the thermal sensor together with the substrate; wherein the inner package structure includes an inner top window; an outer package structure disposed on the substrate, surrounding the inner package structure, and packaging the thermal sensor together with the substrate; wherein the outer package structure includes an outer top window; wherein an orthographic projection of the inner top window projected on the substrate at least partially covers the thermal sensor, and an orthographic projection of the outer top window projected on the substrate at least partially covers the orthographic projection of the inner top window projected on this substrate. | 2022-08-11 |
20220254826 | METHOD OF MANUFACTURING IMAGE SENSING CHIP PACKAGE STRUCTURE INCLUDING AN ADHESIVE LOOP - An image sensing chip package structure includes a chip, an adhesive loop and a light-transmissible substrate member. The chip includes an image sensing region. The adhesive loop is connected to the chip, and has an inner peripheral surface that defines a plurality of protrusions which surround the image sensing region of the chip. The light-transmissible substrate member is connected to the adhesive loop oppositely of the chip to cover the image sensing region of the chip. Methods of manufacturing the image sensing chip package structures are also provided. | 2022-08-11 |
20220254827 | SEMICONDUCTOR PACKAGE INCLUDING AN IMAGE SENSOR CHIP AND A METHOD OF FABRICATING THE SAME - Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip. | 2022-08-11 |
20220254828 | PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR - The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance. | 2022-08-11 |
20220254829 | BACK-ILLUMINATED SENSOR WITH BORON LAYER DEPOSITED USING PLASMA ATOMIC LAYER DEPOSITION - Back-illuminated DUV/VUV/EUV radiation or charged particle image sensors are fabricated using a method that utilizes a plasma atomic layer deposition (plasma ALD) process to generate a thin pinhole-free pure boron layer over active sensor areas. Circuit elements are formed on a semiconductor membrane's frontside surface, and then an optional preliminary hydrogen plasma cleaning process is performed on the membrane's backside surface. The plasma ALD process includes performing multiple plasma ALD cycles, with each cycle including forming an adsorbed boron precursor layer during a first cycle phase, and then generating a hydrogen plasma to convert the precursor layer into an associated boron nanolayer during a second cycle phase. Gasses are purged from the plasma ALD process chamber after each cycle phase. The plasma ALD cycles are repeated until the resulting stack of boron nanolayers has a cumulative stack height (thickness) that is equal to a selected target thickness. | 2022-08-11 |
20220254830 | DISPLAY DEVICE - A display device includes a light emitting area, a non-light emitting area surrounding the light emitting area, and a separation area spaced apart from the light emitting area, the non-light emitting area disposed between the light emitting area and the separation area; a bank disposed in the non-light emitting area; a first alignment electrode and a second alignment electrode that extend from the light emitting area through the non-light emitting area to the separation area; light emitting elements electrically connected to at least one of the first alignment electrode and the second alignment electrode; a first contact electrode disposed in the separation area and electrically connected to the first alignment electrode; and a second contact electrode disposed in the separation area and electrically connected to the second alignment electrode. | 2022-08-11 |
20220254831 | DOUBLE COLOR MICRO LED DISPLAY PANEL - The present invention discloses a double color micro LED display panel including a plurality of pixels. Each of the pixels includes a substrate, a first semiconductor layer configured on the substrate, a second semiconductor layer configured on the first semiconductor layer, and a third semiconductor layer configured between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are P type, and the third semiconductor layer is N type. The first semiconductor layer and the third semiconductor layer form a first light emitting diode to emit a first light, and the second semiconductor layer and the third semiconductor layer form a second light emitting diode to emit a second light. | 2022-08-11 |
20220254832 | High Density Interconnect For Segmented LEDS - A light emitting diode (LED) may include a conductive via in a first portion of an epitaxial layer and a first contact on a second portion of the epitaxial layer. The first portion and the second portion may be separated by an isolation region. The LED may include a transparent conductive layer on the epitaxial layer. | 2022-08-11 |
20220254833 | SEMICONDUCTOR MEMORY DEVICES - The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode. | 2022-08-11 |
20220254834 | METHODS OF FORMING ELECTRONIC DEVICES, AND RELATED ELECTRONIC DEVICES, MEMORY DEVICES, AND SYSTEMS - A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described. | 2022-08-11 |
20220254835 | ELECTRONIC DEVICE - An electronic device includes a display panel including a bending portion, a first non-bending portion, and a second non-bending portion spaced from the first non-bending portion with the bending portion therebetween in a first direction, an input sensing part on the first non-bending portion, and including a sensing electrode, a signal line on the second non-bending portion, electrically connected to the sensing electrode, and including a first portion extending substantially parallel to the first direction, and a second portion extending in a second direction that is different from the first direction, and located between the sensing electrode and the first portion, an electronic part on the second non-bending portion, and not overlapping the signal line, and a reinforcing member on the second non-bending portion, at least partially surrounding the electronic part, and overlapping the first portion while not overlapping the second portion in a plan view. | 2022-08-11 |
20220254836 | TOUCH DISPLAY SCREEN AND DISPLAY APPARATUS - The touch display screen includes a display panel, a touch electrode structure on a light-emitting side of the display panel and a bezel cover layer. The touch display screen includes a display area and a bezel area, and the bezel area has a protrusion sub-area toward the display area. The bezel cover layer is located in the bezel area. The touch electrode structure includes a plurality of touch electrodes and a plurality of leads. The plurality of touch electrodes are located in the display area, and the plurality of leads are arranged in the bezel area along an edge of the display area. The portion of each of the plurality of leads adjacent to the protrusion sub-area is a preset lead portion. An orthographic projection of the bezel cover layer on the display panel covers an orthographic projection of at least one the preset lead portion on the display panel. | 2022-08-11 |
20220254837 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a display panel layer, a touch sensing layer, a reflection prevention layer, and a window layer. The touch sensing layer is disposed directly on a first display panel surface, a second display panel surface facing the first display panel surface in a thickness direction, or a second base surface of the reflection prevention layer. The reflection prevention layer is disposed directly on the second display panel surface or a first base surface of the touch sensing layer. The window layer is disposed directly on the first base surface or the second base surface. | 2022-08-11 |
20220254838 | OLED DISPLAY PANEL AND OLED DISPLAY DEVICE - Provided is an OLED display panel, the OLED display panel includes a touch layer, wherein the touch layer includes a via hole structure including: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven; wherein the uneven surface has a roughness in a value range of 0.05d≤r≤0.19d, where r represents the roughness, and d represents a thickness of the interlayer insulating layer, the roughness of the uneven surface being a distance between a top of convex and a bottom of concave in the uneven surface. | 2022-08-11 |
20220254839 | DISPLAY PANEL, MANUFACTURE METHOD THEREOF AND DISPLAY APPARATUS - A display panel, a manufacture method thereof and a display apparatus are provided. The display panel includes a display area, which includes a plurality of pixel units, wherein the pixel units include electroluminescent display devices and pixel drive circuits for driving the electroluminescent display devices to emit light; the electroluminescent display devices include light-emitting devices and virtual light-emitting devices; the light-emitting devices are electrically connected with the pixel drive circuits, while the virtual light-emitting devices are not connected with the corresponding pixel drive circuits; the display area includes a first display area and a second display area; and in the first display area and the second display area, the distribution density of the electroluminescent display devices is the same, and the density of the pixel drive circuits in the second display area is less than that of the pixel drive circuits in the first display area. | 2022-08-11 |
20220254840 | DISPLAY APPARATUS HAVING A LIGHT-EMITTING DEVICE - A display apparatus including two lines is provided. The two lines may extend in a first direction. A light-emitting device may be disposed between the two lines. Each line may be bent or extended in the direction of the device substrate which supports the light-emitting device. Thus, in the display apparatus, mixing of light emitted to the outside through the device substrate may be prevented. Therefore, in the display apparatus, the quality of realized image may be improved. | 2022-08-11 |
20220254841 | PIXEL STRUCTURE, DISPLAYING SUBSTRATE, DISPLAYING DEVICE AND DISPLAYING METHOD - The present disclosure provides a pixel structure, a displaying substrate, a displaying device and a displaying method, wherein the pixel structure includes first sub-pixels, second sub-pixels and third sub-pixels that are located within a first virtual tetragon; the first sub-pixels are located individually adjacent to midpoints of four side edges of the first virtual tetragon; the second sub-pixels are located individually at four interior angles of the first virtual tetragon; and two center lines of the first virtual tetragon delimit the first virtual tetragon into four second virtual tetragons, and the third sub-pixels are located individually at first interior angles within the four second virtual tetragons. | 2022-08-11 |
20220254842 | DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure provides a display panel and a light-emitting region of a display device. A display panel, comprising: a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels; wherein the first sub-pixel comprises a first light-emitting device which comprises a first effective light-emitting region; the second sub-pixel comprises a second light-emitting device which comprises a second effective light-emitting region; and the third sub-pixel comprises a third light-emitting device which comprises a third effective light-emitting region. | 2022-08-11 |
20220254843 | SENSING AMBIENT LIGHT FROM BEHIND OLED DISPLAY - One example provides a method enacted on a display device comprising an organic light emitting diode (OLED) display panel and a light sensor positioned behind the OLED display panel with respect to a viewing surface of the OLED display panel. The method comprises receiving data samples from the light sensor and determining a temporal location for each of one or more non-emissive states of the OLED display panel. The method further comprises determining an ambient light characteristic using one or more data samples acquired during the one or more non-emissive states of the OLED display panel and adjusting an emission characteristic of the OLED display panel based at least in part on the ambient light characteristic determined. | 2022-08-11 |
20220254844 | FINGERPRINT SENSOR AND DISPLAY DEVICE INCLUDING THE SAME - A fingerprint sensor includes: a substrate; a circuit element layer on a first surface of the substrate and including a plurality of conductive layers; a light emitting element layer on the circuit element layer and including light emitting elements and a light shielding layer; and a light sensor layer on a second surface of the substrate and including light sensors, wherein the light shielding layer includes contact holes exposing first electrodes of the light emitting elements, and first opening portions exposing a portion of the circuit element layer, and the circuit element layer includes second opening portions formed in the plurality of conductive layers and includes a light transmission hole of which at least a portion overlaps the first opening portions. | 2022-08-11 |
20220254845 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display panel and a method of manufacturing the display panel are disclosed. A pixel definition layer and an organic light-emitting layer are fabricated on a substrate provided with a first auxiliary cathode layer and a second auxiliary cathode layer. A connecting hole is formed on the pixel definition layer corresponding to the second auxiliary cathode layer. A solvent is printed in the connecting hole to allow the organic light-emitting layer to be dissolved around the connecting hole to the pixel definition layer, so that the second auxiliary cathode layer is exposed. A cathode layer is connected in parallel with the second auxiliary cathode layer and the first auxiliary cathode layer through the connecting hole. | 2022-08-11 |
20220254846 | ORGANIC EL DISPLAY PANEL AND METHOD FOR MANUFACTURING ORGANIC EL DISPLAY PANEL - An organic electro luminescence display panel includes pixel electrodes, a plurality of elongated column banks, a missing portion at which part of the elongated column banks does not exist, a pair of repair banks formed, above the pixel electrodes, in each of two gaps between a column bank that has the missing portion and column banks adjacent on opposite sides in a row direction of the column bank, a light emitting layer composed of an application film formed in each of gaps between the plurality of column banks, and a common electrode provided above the light emitting layer. The repair banks include a pair of repair row banks formed at positions spaced by a predetermined distance or more in a column direction above the pixel electrodes that exist in the two gaps and whose positions in the column direction are same, at least at part thereof, as that of the missing portion, and repair column banks that connect, in the column direction, an end portion of each of the repair row banks that are not connected in the row direction to the column bank that has the missing portion to a closest portion of the column bank. | 2022-08-11 |
20220254847 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY APPARATUS - The present disclosure provides a display substrate and a method of manufacturing the same, a display panel, and a display apparatus. The display substrate includes a base substrate, pixel units are arranged in an array on the base substrate, each pixel unit includes an anode, a light-emitting functional layer and a cathode, a pixel definition layer is provided, and has a plurality of openings, and each opening exposes a portion of an anode; the light-emitting functional layer is located in the opening; at least a portion of two opposite ends of the anode along a first direction is warped in a direction toward the cathode, an orthographic projection of the warped portion of the anode on the base substrate does not overlap with that of the cathode on the base substrate, and a hollow region is provided at a position of the cathode at least corresponding to the warped portion. | 2022-08-11 |
20220254848 | DISPLAY DEVICE - The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area. | 2022-08-11 |
20220254849 | DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME - A display panel includes: a substrate including a first area, a second area, and a third area, first display elements in the first area, and second display elements in the second area; first pixel circuits in the first area and respectively connected to the first display elements; second pixel circuits in the third area and respectively connected to the second display elements; a first organic insulating layer covering the first pixel circuits; and connection wirings respectively connecting the second pixel circuits to the second display elements, wherein the connection wirings include a first connection wiring and a second connection wiring, the first connection wiring being disposed on the first organic insulating layer, and the second connection wiring being disposed under the first organic insulating layer. | 2022-08-11 |
20220254850 | DISPLAY DEVICE - A display device includes a base substrate which is flexible, first and second active patterns disposed on the base substrate, an inorganic insulating layer disposed on the first and second active patterns and defining an opening area, a first organic insulating pattern disposed inside the opening area, a bridge electrode disposed on the first organic insulating pattern, a second organic insulating layer disposed on the bridge electrode, a fourth organic insulating layer disposed on the second organic insulating layer, first and second pixel electrodes disposed on the fourth organic insulating layer and electrically connected to the first and second active patterns, respectively, and a third organic insulating pattern disposed between the second organic insulating layer and the fourth organic insulating layer, overlapping the second pixel electrode, and not overlapping the first pixel electrode. | 2022-08-11 |
20220254851 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes a base substrate, and one or more first transistors and one or more second transistors over the base substrate. A first transistor of the one or more first transistors includes a first active layer, and the first active layer contains silicon. A second transistor of the one or more second transistors includes a second active layer, and the second active layer contains an oxide semiconductor material. The display panel also includes a shielding layer. The shielding layer is disposed on a side of the first active layer facing away from the base substrate, and is disposed on a side of the second active layer facing away from the base substrate. Along a projection direction perpendicular to the base substrate, the shielding layer fully covers the second active layer. | 2022-08-11 |
20220254852 | METHOD FOR FABRICATING DISPLAYING BACKPLANE, DISPLAYING BACKPLANE AND DISPLAYING DEVICE - The present disclosure provides a method for fabricating a displaying backplane, a displaying backplane and a displaying device, and relates to the technical field of displaying. The method includes forming a first active layer and a second active layer on a substrate base plate; forming a first grid insulating layer covering the first active layer and the second active layer; forming a first grid on the first grid insulating layer; performing ion implantation to the first no-channel regions, the second no-channel regions and the second channel region, to reduce oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region; and forming a second grid on the first grid insulating layer. | 2022-08-11 |
20220254853 | DISPLAY APPARATUS - A display apparatus includes a substrate a first pixel circuit arranged on the substrate, and a plurality of light-emitting elements arranged in a matrix on the substrate. The first pixel circuit is configured to commonly drive a first light-emitting element located in a first row and a second light-emitting element located in a second row different from the first row from among the plurality of light-emitting elements. | 2022-08-11 |
20220254854 | DRIVE CIRCUIT ARRAY SUBSTRATE, DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A display device according to the present disclosure includes: a drive circuit array substrate including drive circuits arranged in an array pattern on a semiconductor substrate; and light emitting elements arranged in an array pattern over the drive circuits and driven by the drive circuits, in which in a drive circuit group including a plurality of the drive circuits that are adjacent to each other, a well tap is provided in a part of the drive circuits of the plurality of the drive circuits included in the drive circuit group. | 2022-08-11 |
20220254855 | DISPLAY PANEL AND DISPLAY DEVICE - Provided is a display panel, including a display pixel unit located in a display region, the display pixel unit including a threshold compensation transistor, the threshold compensation transistor including a first channel and a second channel being connected by a conductive connection portion; a dummy pixel unit located in a dummy region; a first signal line located in the dummy region and configured to provide a constant voltage; and a first conductive block connected to the first signal line. The display pixel unit includes a first display pixel unit, the first display pixel unit is a display pixel unit adjacent to the dummy pixel unit in a row direction, and in a plan view of the display panel, the first conductive block at least partially overlaps the conductive connection portion of the threshold compensation transistor of the first display pixel unit. A display device is further provided. | 2022-08-11 |
20220254856 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device are provided. The display substrate includes a sub-pixel and the sub-pixel includes a pixel circuit including a data writing sub-circuit, a storage sub-circuit and a driving sub-circuit. The display substrate further includes a first connection electrode and the storage sub-circuit includes a storage capacitor; the first connection electrode is in a same layer as the second capacitor electrode and is insulated form the second capacitor electrode, and the second capacitor electrode electrically connects the first capacitor electrode to the data writing sub-circuit. | 2022-08-11 |
20220254857 | Display Substrate and Display Apparatus - Provided are a display substrate and display apparatus. The display substrate includes a display region and non-display region; base substrate, driving structure layer and wiring layer. The driving structure layer located in the display region includes a first power supply line, data signal line and reference signal line extending along a first direction; the wiring layer located in the non-display region includes a first power supply wiring electrically connected to first power supply line and located on first side of the display region, a data wiring located on second side, different from the first side, of the display region, and a reference wiring located on second side of the display region. For the first power supply line, data signal line and reference signal line with the same length, resistance of first power supply line is greater than that of the data signal line and that of the reference signal line. | 2022-08-11 |
20220254858 | DISPLAY PANEL AND ELECTRONIC DEVICE - A display panel is provided. The display panel includes a base substrate and a plurality of display units disposed on the base substrate. The display unit includes a signal line, a light-emitting device and a drive unit. The light-emitting device is disposed in a flexible display region of the base substrate, the drive unit is disposed in a pixel circuit region of the base substrate, and the signal line is connected with the light-emitting device and the drive unit. | 2022-08-11 |
20220254859 | DISPLAY DEVICE - A display device includes a substrate, a circuit element layer on the substrate, a display element layer on the circuit element layer, a sealing film on the display element layer, an oxide film on the sealing film, a barrier metal layer on the oxide film, and a wiring layer on the barrier metal layer, wherein a surface of the sealing film in contact with the oxide film has concave/convexities, and the barrier metal layer is formed by titanium nitride. A height of the concave/convexities of the surface of the sealing film may be less than 30 nm. A thickness of the oxide film may be 5 nm or less. | 2022-08-11 |
20220254860 | DISPLAY DEVICE - A display device that can easily achieve higher definition is provided The display device includes a pixel, a first wiring, and a second wiring. The pixel includes first to fourth transistors, a first capacitor, and a light-emitting element. One of a source and a drain of the first transistor is connected to the first wiring, and the other of the source and the drain of the first transistor is connected to a gate of the second transistor and to the first capacitor. The light-emitting element is connected to one of a source and a drain of the second transistor. The first wiring is supplied with a first data potential. The second wiring is supplied with a second data potential and a reset potential in different periods. The third transistor supplies the second data potential to the first capacitor. The fourth transistor supplies the reset potential to the light-emitting element. | 2022-08-11 |
20220254861 | ORGANIC LIGHT-EMITTING DISPLAY PANEL AND DISPLAY DEVICE - Provided are an organic light-emitting display panel and a display device. The organic light-emitting display panel includes: a plurality of organic light-emitting units, a first display area and a second display area. The plurality of organic light-emitting units includes first organic light-emitting units in the first display area and second organic light-emitting units in the second display area. The first organic light-emitting units share a first cathode. The second organic light-emitting units include at least one organic light-emitting unit group, each of the at least one organic light-emitting unit group includes at least one organic light-emitting unit. The at least one organic light-emitting unit in a same organic light-emitting unit group shares a second cathode. The second cathode has a zigzag edge segment. | 2022-08-11 |
20220254862 | DISPLAY APPARATUS - A display apparatus includes a substrate, a display unit disposed on the substrate, an insulating layer disposed on the substrate, a power supply wire disposed on the insulating layer outside the display unit, and a cladding layer. The display unit includes a pixel circuit and a display element electrically connected to the pixel circuit. The insulating layer extends from the display unit to an edge of the substrate. The power supply wire is electrically connected to the display element and includes an alignment pattern that exposes at least a portion of the insulating layer. The cladding layer covers an inner surface of the alignment pattern and contacts the at least a portion of the insulating layer. | 2022-08-11 |
20220254863 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND A MANUFACTURING METHOD THEREOF - An organic light emitting diode display including: a substrate; a TFT on the substrate; a planarization layer on the TFT; a pixel electrode on the planarization layer, wherein the pixel electrode includes upper and lower layers including a transparent conductive oxide and an intermediate layer including silver; an etch stop layer on the pixel electrode, wherein an upper surface of the pixel electrode is exposed by the etch stop layer; a partition on the etch stop layer, wherein the upper surface of the pixel electrode is exposed by the partition; an organic emission layer on the upper surface of the pixel electrode where the upper surface of the pixel electrode is exposed by the etch stop layer and the partition; and a common electrode on the organic emission layer and the partition, wherein the etch stop layer covers an edge and a side surface of the pixel electrode. | 2022-08-11 |
20220254864 | DISPLAY DEVICE - A display device includes: a light-emitting diode including a first electrode, a second electrode arranged on the first electrode, and an intermediate layer between the first electrode and the second electrode; a bus electrode spaced apart from the first electrode of the light-emitting diode; a bank layer covering an edge of the first electrode and an edge of the bus electrode, and exposing a portion of the first electrode and a portion of the bus electrode; and an insulating pattern layer arranged on the bus electrode, and including a first opening overlapping a first opening, wherein the second electrode contacts the bus electrode through the first opening of the insulating pattern layer. | 2022-08-11 |
20220254865 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - The present disclosure provides a display substrate, a manufacturing method thereof and a display device, and relates to the field of display technology. The display substrate includes a base substrate, and a driving circuitry layer and a light-emitting unit arranged on the base substrate. The driving circuitry layer includes a first gate metal layer, and a pattern of the first gate metal layer includes a gate line. The first gate metal layer includes a first conductive layer with resistivity less than a first threshold and a Young's modulus less than a second threshold, and a first conductive protection layer arranged at a side of the first conductive layer away from the base substrate. | 2022-08-11 |
20220254866 | DISPLAY DEVICE HAVING A BENDING AREA - A display device includes a substrate including a bending area located between a first area and a second area. The substrate is bent in relation to a bending axis. A first wiring unit including a plurality of first wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. First central axes included in each of the plurality of first wirings are spaced apart from each other by a first pitch in the bending area. A second wiring unit including a plurality of second wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. Second central axes included in each of the plurality of second wirings are spaced apart from each other by a second pitch greater than the first pitch in the bending area. | 2022-08-11 |
20220254867 | TILED DEVICE AND ELECTRONIC DEVICE - An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2. | 2022-08-11 |
20220254868 | ASYMMETRIC 8-SHAPED INDUCTOR AND CORRESPONDING SWITCHED CAPACITOR ARRAY - A semiconductor device includes a substrate; a first terminal and a second terminal; and a conductor arranged on the substrate between the first terminal and the second terminal to constitute an inductor shaped for forming a first loop and a second loop. A first crossing of the conductor with itself is present between the first loop and the second loop. The first loop and the second loop define a first enclosed area and a second enclosed area, respectively. The first enclosed area is smaller than the second enclosed area. | 2022-08-11 |
20220254869 | INDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF, ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF, AND METHOD FOR FABRICATING PACKAGING CARRIER - An inductor structure is provided. A plurality of first and second conductive posts have end surfaces corresponding in profile to ends of first conductive sheets, respectively. As such, the profiles of the end surfaces of the first and second conductive posts are non-cylindrical so as to increase the contact area between the first conductive sheets and the first and second conductive posts, thereby improving the conductive quality and performance of the inductor. Further, since the first and second conductive posts are formed by stacking a plurality of post bodies on one another, the number and cross-sectional area of loops are increased so as to increase the inductance value. A method for fabricating the inductor structure, an electronic package and a fabrication method thereof, and a method for fabricating a packaging carrier are further provided. | 2022-08-11 |
20220254870 | DIELECTRIC THIN-FILM STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME - Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a , , or <0k0> direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation. | 2022-08-11 |
20220254871 | TITANIUM LAYER AS GETTER LAYER FOR HYDROGEN IN A MIM DEVICE - In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer. | 2022-08-11 |
20220254872 | DECOUPLING CAPACITORS BASED ON DUMMY THROUGH-SILICON-VIA PLATES - Disclosed herein are IC structures with decoupling capacitors based on dummy TSV plates provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example decoupling capacitor includes first and second capacitor plates and a capacitor insulator between them. Each capacitor plate is a different blind, plate-like opening in the support structure, the openings at least partially filled with one or more conductive materials. The capacitor plate openings are referred to herein as “dummy TSV plates” because they may be fabricated while providing regular TSV openings in the support structure. Such decoupling capacitors may be better suited for high-speed microprocessor applications than conventional off-chip decoupling capacitors and may advantageously allow integrating on-chip decoupling capacitors with an ample amount of capacitive decoupling, limited or no additional processing steps on top of regular TSV processing, and in areas that may not have been used otherwise. | 2022-08-11 |
20220254873 | CAPACITOR STRUCTURE, METHOD OF FORMING THE SAME, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A capacitor structure may include a lower electrode on a substrate, a dielectric layer on the substrate, and an upper electrode on the dielectric layer. The lower electrode may include a metal nitride having a chemical formula of M | 2022-08-11 |
20220254874 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A method for forming a semiconductor structure can include the following steps. A substrate and an insulating layer that are stacked are provided, the substrate having a plurality of storage node contact structures spaced apart from each other. A grid-like upper electrode layer is formed on a surface of the insulating layer, where the upper electrode layer has a plurality of meshes penetrating the upper electrode layer, and an orthographic projection of each of the meshes on the insulating layer and an orthographic projection of a storage node contact structure on the insulating layer have an overlapping area. A dielectric layer is formed on a side wall of each mesh. The insulating layer exposed from the mesh is removed to expose the storage node contact structure. A lower electrode layer is formed inside each mesh. | 2022-08-11 |
20220254875 | SEMICONDUCTOR POWER DEVICE TERMINAL STRUCTURE - Provided are an audio data processing method and apparatus, a device and a storage medium. The method includes: acquiring audio data to be processed and a variable-speed rate of at least one audio frame in the audio data; sequentially using the at least one audio frame as a current audio frame to be processed, and converting the current audio frame to a frequency domain; determining a target phase signal of the current audio frame according to a variable-speed rate of the current audio frame and a variable-speed rate of a previous audio frame; and performing, according to the target phase signal, time domain conversion on the current audio frame converted to the frequency domain to obtain a processed current audio frame. | 2022-08-11 |
20220254876 | LDMOS HAVING MULTIPLE FIELD PLATES AND ASSOCIATED MANUFACTURING METHOD - An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. | 2022-08-11 |
20220254877 | SEMICONDUCTOR DEVICE, AND RELATED MODULE, CIRCUIT, AND PREPARATION METHOD - A semiconductor device, and a related module, circuit, and preparation method are disclosed. The device includes an N-type drift layer, a P-type base layer, N-type emitter layers, gates, a field stop layer, a P-type collector layer, and the like. The field stop layer includes a first doped region and a second doped region that are successively stacked on a surface of the N-type drift layer. A particle radius of an impurity in the first doped region is less than a particle radius of an impurity in the second doped region. Doping densities of both the first doped region and the second doped region are higher than a doping density of the N-type drift layer. According to the semiconductor device, a collector-emitter leakage current of an IGBT can be effectively reduced. | 2022-08-11 |
20220254878 | SEMICONDUCTOR DEVICE INCLUDING BARRIER LAYER BETWEEN ACTIVE REGION AND SEMICONDUCTOR LAYER AND METHOD OF FORMING THE SAME - A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region. | 2022-08-11 |
20220254879 | DEVICE COMPRISING A TRANSISTOR - A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy. | 2022-08-11 |
20220254880 | SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS - A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer. | 2022-08-11 |
20220254881 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern. | 2022-08-11 |
20220254882 | Nanosheet Devices With Hybrid Structures And Methods Of Fabricating The Same - A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer. | 2022-08-11 |
20220254883 | PROCESS FOR FABRICATING SILICON NANOSTRUCTURES - A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent. | 2022-08-11 |
20220254884 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less. | 2022-08-11 |
20220254885 | MULTI-FUNCTIONAL PCB FOR ASSEMBLING GaN-BASED POWER CONVERTER AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter. | 2022-08-11 |
20220254886 | GRADED DOPING IN POWER DEVICES - Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device. | 2022-08-11 |
20220254887 | METHOD FOR MANUFACTURING A GRID - A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n | 2022-08-11 |
20220254888 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates. | 2022-08-11 |
20220254889 | Electronic Device Including a Transistor and a Shield Electrode - An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region. | 2022-08-11 |
20220254890 | 2D-Channel Transistor Structure with Asymmetric Substrate Contacts - Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature. | 2022-08-11 |
20220254891 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features. | 2022-08-11 |
20220254892 | SEMICONDUCTOR POWER DEVICE AND METHOD OF MANUFACTURING THE SAME - The application relates to a semiconductor power device including a semiconductor body in which a transistor device is formed, the transistor device having a gate region and a channel region laterally aside the gate region, the gate region including a gate electrode for controlling a channel formation in the channel region, and a gate dielectric laterally between the channel region and the gate electrode. The gate electrode includes a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region. The gate electrode layer is made of a doped metallically conductive material. | 2022-08-11 |
20220254893 | SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES HAVING EPITAXIAL SOURCE OR DRAIN STRUCTURES - Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure. | 2022-08-11 |
20220254894 | ELECTRONIC DEVICE INCLUDING A GATE STRUCTURE AND A PROCESS OF FORMING THE SAME - An electronic device can include a gate structure. In an embodiment, the gate structure can include a gate electrode including a doped semiconductor material, a metal-containing member, a pair of conductive sidewall spacers. The first metal-containing member can overlie the gate electrode. The conductive sidewall spacers can overlie the gate electrode and along opposite sides of the first metal-containing member. In another embodiment, the gate structure can include a gate electrode, a first metal-containing member overlying the gate electrode, and a second metal-containing member overlying the first metal-containing member. The first metal-containing member can have a length that is greater than the length of the second metal-containing member and substantially the same length as the gate electrode. | 2022-08-11 |
20220254895 | SEMICONDUCTOR DEVICE WITH RESISTANCE REDUCTION ELEMENT AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide. | 2022-08-11 |
20220254896 | SEMICONDUCTOR DEVICES, TRANSISTORS, AND RELATED METHODS FOR CONTACTING METAL OXIDE SEMICONDUCTOR DEVICES - A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact includes a conductive material, such as ruthenium, to reduce the Schottky effects at the interface with the channel material. | 2022-08-11 |
20220254897 | THIN FILM TRANSISTOR INCLUDING A COMPOSITIONALLY-GRADED GATE DIELECTRIC AND METHODS FOR FORMING THE SAME - A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer. | 2022-08-11 |
20220254898 | SEMICONDUCTOR DEVICE WITH GATE SPACER AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - The present application provides a semiconductor device with an air gate spacer for reducing parasitic capacitance and a method for manufacturing the semiconductor device. The semiconductor device includes a stacking structure, a first sidewall spacer and a second sidewall spacer. The stacking structure stands on a semiconductor substrate. The first and second sidewall spacers cover a sidewall of the stacking structure. An air gap is sealed between the first and second sidewall spacers. A top end of the air gap is substantially aligned with top ends of the first and second sidewall spacers. A top portion of the air gap is tapered toward a top end of the air gap. | 2022-08-11 |
20220254899 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH GATE SPACER - The present application provides a method for preparing a semiconductor device with an air gate spacer for reducing parasitic capacitance. The method includes forming a stacking structure on a semiconductor substrate; forming a first sidewall spacer, a second sidewall spacer and a sacrificial sidewall spacer on a sidewall of the stacking structure,; and removing the sacrificial sidewall spacer to form an air gap between the first and second sidewall spacers. The sacrificial sidewall spacer is located between the first and second sidewall spacers, and the first and second sidewall spacers have an etching selectivity with respect to the sacrificial sidewall spacer | 2022-08-11 |
20220254900 | MOSFET GATE ENGINEERINNG WITH DIPOLE FILMS - A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region. | 2022-08-11 |
20220254901 | POST-FORMATION MENDS OF DIELECTRIC FEATURES - The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride. | 2022-08-11 |
20220254902 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A nitride semiconductor device includes a semiconductor layered structure including a substrate, a channel layer, and a barrier layer. The channel layer is formed above the substrate and made of a nitride semiconductor layer. The barrier layer is formed on the channel layer, has a wider band gap than the channel layer, and is made of a nitride semiconductor layer. The semiconductor layered structure includes an isolation region in which impurities are implanted. The position of an impurity concentration peak in the depth direction in the isolation region is deeper than the interface between the barrier layer and the channel layer. The concentration of the impurities at the interface between the barrier layer and the channel layer in the isolation region is lower than the concentration at the impurity concentration peak. | 2022-08-11 |
20220254903 | METHOD FOR FORMING ULTRA-SHALLOW JUNCTION - A method for forming an ultra-shallow junction includes the following operations: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, providing a dopant and implanting the dopant into the epitaxial layer and a part of the semiconductor substrate, and removing the epitaxial layer, to form the ultra-shallow junction. | 2022-08-11 |