32nd week of 2011 patent applcation highlights part 13 |
Patent application number | Title | Published |
20110193128 | METHOD OF FABRICATING VERTICAL STRUCTURE LEDS - A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out. | 2011-08-11 |
20110193129 | Light-Emitting Device and Method for Manufacturing the Same - The present invention provides an organic light-emitting element where a lower electrode, an organic compound layer and an upper electrode are laminated on a substrate, wherein the upper electrode of the organic EL element is formed by a laminate of at least a conductive first inorganic film, a conductive organic film and a conductive second inorganic film, in order to suppress the occurrence of dark spot, so that the occurrence of pinholes in the upper electrode leading to dark spots is suppressed. Here, pinholes refer to holes in the upper electrode that penetrate upper electrode from the organic compound layer underneath to the atmosphere above. | 2011-08-11 |
20110193130 | ORGANIC LIGHT EMITTING DIODE DEVICE - An organic light emitting diode device is disclosed. The organic light emitting diode device includes: a first electrode, a light emitting section disposed over the first electrode and including at least two light emitters displaying the same or different colors, a second electrode disposed over the light emitting section, and a filler layer for encapsulation disposed over the second electrode and including a light emitter displaying at least one color. | 2011-08-11 |
20110193131 | Devices, Structures, and Methods Using Self-Aligned Resistive Source Extensions - Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region. | 2011-08-11 |
20110193132 | INSULATED GATE SEMICONDUCTOR DEVICE - An insulated gate semiconductor device includes a semiconductor substrate, channel regions, floating regions, an emitter region, a body region, a hole stopper layer, and an emitter electrode. The channel regions and the floating regions are repeatedly arranged such that at least one floating region is located between adjacent channel regions. The emitter region and the body region are located in a surface portion of each channel region. The body region is deeper than the emitter region. The hole stopper layer is located in each floating region to divide the floating region into a first region and a second region. The emitter electrode is electrically connected to the emitter region and the first region. | 2011-08-11 |
20110193133 | PHOTO DETECTION DEVICE - A highly sensitive and wide spectra-range mesa type photodetector having the impurity diffusion along the mesa-sidewall is provided with. | 2011-08-11 |
20110193134 | STEP DOPING IN EXTENSIONS OF III-V FAMILY SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer. | 2011-08-11 |
20110193135 | Methods of Forming Contact Structures Including Alternating Metal and Silicon Layers and Related Devices - A method of forming a semiconductor device, the method comprising providing a semiconductor layer, and providing a first layer of a first metal on the semiconductor layer. A second layer may be provided on the first layer of the first metal. The second layer may include a layer of silicon and a layer of a second metal, and the first and second metals may be different. The first metal may be titanium and the second metal may be nickel. Related devices, structures, and other methods are also discussed. | 2011-08-11 |
20110193136 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers. | 2011-08-11 |
20110193137 | SOLID-STATE IMAGING DEVICE AND DRIVING METHOD THEREOF - A solid-state imaging device includes: a photoelectric converting section comprising a photo-diode; a charge storage section; a charge transfer section; a first control gate section provided between the photoelectric converting section and the charge storage section to control transfer of a signal charge from the photoelectric converting section to the charge storage section; and a second control gate section provided between the charge storage section and the charge transfer section to control transfer of the signal charge from the charge storage section to the charge transfer section. The charge storage section includes: a first region formed on a side near to the first control gate section; and a second region formed on a side near to the second control gate section and configured to have a channel potential increased more than that of the first region. The second region is configured to hold the signal charge in a pinning condition. | 2011-08-11 |
20110193138 | ELECTRONIC DEVICE AND MANUFACTURING METHOD - Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate | 2011-08-11 |
20110193139 | CELL MEASURING DEVICE - There is provided a cell measuring apparatus that can measure cells efficiently. In a cell measuring apparatus | 2011-08-11 |
20110193140 | Electronic component for high temperatures - A chemically sensitive field effect transistor includes a substrate, a conductor track structure situated on the substrate, and a functional layer which is contacted via the conductor track structure. To be able to form a thin, oxidation-stable and temperature-stable conductor track structure, the conductor track structure is made of a metal mixture which includes platinum and one or more metals selected from the group made up of rhodium, iridium, ruthenium, palladium, osmium, gold, scandium, yttrium, lanthanum, the lanthanides, titanium, zirconium, hafnium, niobium, tantalum, chromium, tungsten, rhenium, iron, cobalt, nickel, copper, boron, aluminum, gallium, indium, silicon, and germanium. | 2011-08-11 |
20110193141 | METHOD OF FABRICATING A FINFET DEVICE - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate. | 2011-08-11 |
20110193142 | Structure and Method for Post Oxidation Silicon Trench Bottom Shaping - A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern. | 2011-08-11 |
20110193143 | ELECTRONIC DEVICE INCLUDING DOPED REGIONS BETWEEN CHANNEL AND DRAIN REGIONS AND A PROCESS OF FORMING THE SAME - An electronic device can include a drain region of a transistor, wherein the drain region has a first conductivity type. The electronic device can also include a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type. The electronic device can further include a first doped region having the first conductivity type, wherein the first doped region extends from the drain region towards the channel region. The electronic device can still further include a second doped region having the first conductivity type, wherein the second doped region is disposed between the first doped region and the channel region. | 2011-08-11 |
20110193144 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack. | 2011-08-11 |
20110193145 | CRYSTAL PHASE STABILIZING STRUCTURE - It is possible to achieve the above interface structure stabilization by forming a structure in which a fraction of Ni atoms are substituted with Pt atoms only in the first interface layer, thereby lowering the interface energy while suppressing the variation of the characteristics of NiSi and NiSi/Si interface to the minimum extent. Therefore, it is possible to contribute to the improvement of the yield ratio of elements or the improvement of reliability through the stabilization of the crystal phase of NiSi. The NiSi is formed, for example, on the surface layer of a source drain in a transistor. | 2011-08-11 |
20110193146 | Charge Carrier Barrier for Image Sensor - A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell. | 2011-08-11 |
20110193147 | BACKSIDE ILLUMINATION CMOS IMAGE SENSORS AND METHODS OF MANUFACTURING THE SAME - Backside illumination CMOS image sensors having convex light-receiving faces and methods of manufacturing the same. A backside illumination CMOS image sensor includes a metal layer, an insulating layer and a photodiode. The insulating layer is on the metal layer. The photodiode is on the insulating layer, and a top face of the photodiode, which receives light, is curved. A method of manufacturing a backside illumination CMOS image sensor including a photodiode having a convex surface includes forming an island smaller than the photodiode on a portion of a light-receiving face of the photodiode, and annealing the island to form the photodiode having the convex light-receiving face. | 2011-08-11 |
20110193148 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 2011-08-11 |
20110193149 | SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION - A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer. | 2011-08-11 |
20110193150 | SEMICONDUCTOR DEVICE INCLUDING RESERVOIR CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor memory device includes forming a first capacitor using a metal oxide semiconductor (MOS) transistor, forming a second capacitor being a pillar type corresponding to a cell capacitor formed in a cell region, and forming a third capacitor over the first and the second capacitors | 2011-08-11 |
20110193151 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions, first active regions provided in the first region and each having a first width, second active regions provided in the second region and each having a second width greater than the first width, third active regions provided in the third region and each having a third with greater than the first width. An upper surface of an element isolation layer in the second region is higher than that of an element isolation layer in the first region. | 2011-08-11 |
20110193152 | HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE - A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region. | 2011-08-11 |
20110193153 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a semiconductor pillar and a charge storage layer. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The semiconductor pillar is buried in the stacked body, and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode films and the semiconductor pillar. The electrode films are divided into a plurality of control gate electrodes. Each of the plurality of control gate electrodes faces the semiconductor pillar and sandwiches the charge storage layer with the semiconductor pillar. | 2011-08-11 |
20110193154 | Non-volatile Memory Device - A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer. | 2011-08-11 |
20110193155 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more. | 2011-08-11 |
20110193156 | ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY AND ITS MANUFACTURING METHOD - The electrically erasable programmable memory and its manufacturing method of the present invention forms above the floating gate the polysilicon spacer regions that are extended from the central part of the source region; the insulating part between the polysilicon spacer region and the floating gate has a smaller thickness to increase the capacitance between the floating gate and the polysilicon spacer region and further increasing the voltage coupled to the floating gate. Therefore, the present invention can effectively increase the coupling capacitance at the drain terminal, and has an advantage of low cost and easy production. | 2011-08-11 |
20110193157 | CROSS-HAIR CELL BASED FLOATING BODY DEVICE - A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin. | 2011-08-11 |
20110193158 | Semiconductor Devices With Sealed, Unlined Trenches and Methods of Forming Same - A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches. | 2011-08-11 |
20110193159 | SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a silicon pillar formed substantially perpendicular to a principal surface of a silicon substrate, a first impurity diffusion layer and a second impurity diffusion layer arranged below and above the silicon pillar, respectively, a gate electrode arranged to penetrate through the silicon pillar in a horizontal direction, a gate dielectric film arranged between the gate electrode and the silicon pillar, a back-gate electrode arranged adjacent to the silicon pillar, and a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar. | 2011-08-11 |
20110193160 | ELECTRONIC DEVICE INCLUDING A BURIED INSULATING LAYER AND A VERTICAL CONDUCTIVE STRUCTURE EXTENDING THERETHROUGH AND A PROCESS OF FORMING THE SAME - An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region. | 2011-08-11 |
20110193161 | METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type. | 2011-08-11 |
20110193162 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate. | 2011-08-11 |
20110193163 | Semiconductor Devices with Improved Self-Aligned Contact Areas - A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer. | 2011-08-11 |
20110193164 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device formed on a SOI substrate which comprises a buried insulating layer and a semiconductor layer on the buried insulating layer and a method for manufacturing the same, wherein a fin of semiconductive material having two opposing sides perpendicular to a main surface of the SOI substrate is provided in the semiconductor layer, said semiconductor device comprising: a source region and a drain region provided at two ends of the fin respectively; a channel region provided at a central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, wherein the gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the SOI substrate. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor. | 2011-08-11 |
20110193165 | Floating Body Field-Effect Transistors, And Methods Of Forming Floating Body Field-Effect Transistors - In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor Si | 2011-08-11 |
20110193166 | STRUCTURE AND METHOD FOR REDUCING FLOATING BODY EFFECT OF SOI MOSFETS - The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET. | 2011-08-11 |
20110193167 | Self-Aligned Two-Step STI Formation Through Dummy Poly Removal - An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate. | 2011-08-11 |
20110193168 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer ( | 2011-08-11 |
20110193169 | Techniques for Three-Dimensional Circuit Integration - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 2011-08-11 |
20110193170 | Electro-Static Discharge (ESD) Clamping Device - An ESD clamping device comprises a plurality of fingers each comprising a source region of first conductivity type formed in a substrate of second conductivity type, a drain region of said first conductivity type formed in the substrate, and a gate formed over the substrate and between the source and drain regions. At least one of the fingers each has an ESD implantation region formed in the substrate and partially underlying the drain region of the finger, the ESD implantation region being a heavily doped region of said second conductivity type. Furthermore, at least one of the fingers has a gate extension portion projecting from the gate and demarcating an additional region in at least the drain region of the finger, the additional region of said second conductivity type being electrically connected to at least one of the gate and the substrate of each of the fingers. | 2011-08-11 |
20110193171 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region. | 2011-08-11 |
20110193172 | CROSS-HAIR CELL WORDLINE FORMATION - Disclosed are methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. In some embodiments, portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch. | 2011-08-11 |
20110193173 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed. | 2011-08-11 |
20110193174 | Multiple Silicide Integration Structure and Method - A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices. | 2011-08-11 |
20110193175 | LOWER PARASITIC CAPACITANCE FINFET - An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer. | 2011-08-11 |
20110193176 | Semiconductor Devices with Sealed, Unlined Trenches and Methods of Forming Same - A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches. | 2011-08-11 |
20110193177 | ELECTRONIC DEVICE INCLUDING A DOPED REGION DISPOSED UNDER AND HAVING A HIGHER DOPANT CONCENTRATION THAN A CHANNEL REGION AND A PROCESS OF FORMING THE SAME - An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not disposed under substantially all of a heavily doped portion of the drain region, and has a higher dopant concentration compared to the channel region. A process of forming an electronic device can include forming a drain region, a channel region, and a doped region, wherein the drain region has a conductivity type opposite that of the channel and doped region. After forming the drain, channel, and doped regions, the doped region is disposed under substantially all of the channel region, the doped region is not disposed under substantially all of a heavily doped portion of the drain region, and the drain region is laterally closer to the doped region than to the channel region. | 2011-08-11 |
20110193178 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 2011-08-11 |
20110193179 | LIGHTLY DOPED SOURCE/DRAIN LAST METHOD FOR DUAL-EPI INTEGRATION - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. | 2011-08-11 |
20110193180 | METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize. | 2011-08-11 |
20110193181 | SEMICONDUCTOR DEVICE HAVING DIFFERENT METAL GATE STRUCTURES - A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer. | 2011-08-11 |
20110193182 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured. | 2011-08-11 |
20110193183 | NANOWIRE SENSOR, NANOWIRE SENSOR ARRAY AND METHOD OF FABRICATING THE SAME - A method of fabricating a sensor comprising a nanowire on a support substrate with a first semiconductor layer arranged on the support substrate is disclosed. The method comprises forming a fin structure from the first semiconductor layer, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing at least the fin portion of the fin structure thereby forming the nanowire being surrounded by a first layer of oxide; and forming an insulating layer above the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. A nanowire sensor is also disclosed. The nanowire sensor comprises a support substrate, a semiconducting fin structure arranged on the support substrate, the fin structure comprising at least two semiconducting supporting portions and a nanowire arranged there between; and a first insulating layer on a contact surface of the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. | 2011-08-11 |
20110193184 | Micromechanical system and method for manufacturing a micromechanical system - A micromechanical system having at least one micromechanical device, in particular a sensor device and/or an actuator device, the micromechanical system having a substrate on which at least one micromechanical device is provided, the micromechanical device having at least one structured or unstructured film adhesive on at least one side. | 2011-08-11 |
20110193185 | MAGNETIC MEMORY DEVICE HAVING A RECORDING LAYER - There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge. | 2011-08-11 |
20110193186 | RADIATION DETECTOR MODULE - A radiation detector module includes a radiation detecting substrate including a plurality of semiconductor devices mounted thereon for detecting radiation, a shielding material at a position nearer to an incident side of the radiation than the radiation detecting substrate, the shielding material being capable of shielding a portion of the radiation, and a fixing member including a bottom, a first side wall extending in a normal direction to the bottom from one end of the bottom, and a second side wall extending in the normal direction to the bottom from an other end of the bottom. The first side wall and the second side wall each include a substrate supporting portion for supporting the radiation detecting substrate, and a shielding material supporting portion at a predetermined position relative to the substrate supporting portion for supporting the shielding material. | 2011-08-11 |
20110193187 | ELECTRODE MEMBER FOR SPECIFIC DETECTION OF ANALYTE USING PHOTOCURRENT - Disclosed is an electrode member for specific detection of an analyte using a photocurrent. The electrode member has at least a conductive substrate and an electron-accepting substance provided on said conductive substrate. The aforementioned electron-accepting substance consists at least of a first substance layer that is made of a semiconductor and a second substance that is made of a semiconductor of a kind different from that of the aforementioned semiconductor, a metal or a metal oxide, and is carried on the surface of said first substance layer. With the electrode member, improved detection sensitivity for the test substance and improved measurement precision can be achieved with specific detection of an analyte using a photocurrent. | 2011-08-11 |
20110193188 | IMAGE SENSOR - An image sensor comprising a black pixel region and an active pixel region is provided. The active pixel region is adjacent to the black pixel region. The black pixel region comprises a dummy black pixel region and a readout black pixel region. The readout black pixel region is surrounded by the dummy black pixel region. The dummy black pixel region comprises a photo-sensitive element, a first shielding layer, a second shielding layer and a third shielding layer. The first shielding layer, the second shielding layer and the third shielding layer are used for blocking the incident light going into the photo-sensitive element. The first shielding layer, the second shielding layer and the third shielding layer cover the photo-sensitive element, and the second shielding layer is interposed between the first shielding layer and the third shielding layer. | 2011-08-11 |
20110193189 | SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING IMAGE SENSOR - In an example embodiment, an image sensor includes a semiconductor layer and isolation regions disposed in the semiconductor layer. The isolation regions define active regions of the semiconductor layer. The image sensor further includes photoelectric converters disposed in the semiconductor layer and at least one wiring layer disposed over a top surface of the semiconductor layer. The image sensor also includes color filters disposed below a bottom surface of the semiconductor layer and lenses disposed below the color filters. Each lens is arranged to concentrate incoming light into an area spanned by a corresponding photoelectric converter. | 2011-08-11 |
20110193190 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 2011-08-11 |
20110193191 | PROTECTIVE ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor device includes at least one semiconductor element having a semiconductor stack containing a channel layer and a cap layer and a lower electrode and an upper electrode formed over a semiconductor stack, and at least one protective element having the semiconductor stack in common with the semiconductor element for protecting the semiconductor element. The protective element includes a recessed portion that penetrates the cap layer in the direction of the thickness, an insulation region formed in the semiconductor stack from the bottom of the recessed portion | 2011-08-11 |
20110193192 | Stacked-Die Electronics Package with Planar and Three-Dimensional Inductor Elements - An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component. | 2011-08-11 |
20110193193 | STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR - A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant. | 2011-08-11 |
20110193194 | THIN FILM MIM CAPACITORS AND MANUFACTURING METHOD THEREFOR - Proposed are thin film MIM capacitors with which deterioration of insulating properties and leakage current properties can be sufficiently inhibited. Also proposed is a manufacturing method for the thin film MIM capacitors. For the thin film MIM capacitor ( | 2011-08-11 |
20110193195 | Virtual substrates for epitaxial growth and methods of making the same - A virtual substrate includes a handle support and a strain-relieved single crystalline layer on the handle support. A method of making the virtual substrate includes growing a coherently-strained single crystalline layer on an initial growth substrate, removing the initial growth substrate to relieve the strain on the single crystalline layer, and applying the strain-relieved single crystalline layer on a handle support. | 2011-08-11 |
20110193196 | Indium Phosphide Substrate Manufacturing Method, Epitaxial Wafer Manufacturing Method, Indium Phosphide Substrate, and Epitaxial Wafer - Affords methods of manufacturing InP substrates, methods of manufacturing epitaxial wafers, InP substrates, and eptiaxial wafers whereby deterioration of the electrical characteristics can be kept under control, and at the same time, deterioration of the PL characteristics can be kept under control. An InP substrate manufacturing method of the present invention is provided with the following steps. An InP substrate is prepared (Steps S | 2011-08-11 |
20110193197 | STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS - A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed. | 2011-08-11 |
20110193198 | Corner Stress Release Structure Design for Increasing Circuit Routing Areas - An integrated circuit structure includes a semiconductor chip, which further includes a corner and a seal ring dispatched adjacent edges of the semiconductor chip; and a corner stress release (CSR) structure adjacent the corner and physically adjoining the seal ring. The CSR structure includes a portion in a top metallization layer. A circuit component selected from the group consisting essentially of an interconnect structure and an active circuit is directly underlying the CSR structure. | 2011-08-11 |
20110193199 | ELECTROMIGRATION IMMUNE THROUGH-SUBSTRATE VIAS - A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions. | 2011-08-11 |
20110193200 | SEMICONDUCTOR WAFER CHIP SCALE PACKAGE TEST FLOW AND DICING PROCESS - A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling. | 2011-08-11 |
20110193201 | METHOD TO FABRICATE AND TREAT A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE, ENABLING DISPLACEMENT OF DISLOCATIONS, AND CORRESPONDING STRUCTURE - The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate ( | 2011-08-11 |
20110193202 | METHODS TO ACHIEVE 22 NANOMETER AND BEYOND WITH SINGLE EXPOSURE - Apparatus and methods are disclosed herein for fabricating semiconductor device features with a half-pitch node of 22 nm and beyond using single exposure and single etch (1P1E) photolithography techniques. The method includes exposing in a single exposure a photoresist layer to the exposure source through a photolithography mask where the photolithography mask has on it an island pattern of a material having high percentage transmission. The photoresist layer is developed using a negative tone developer to form a hole pattern in the photoresist layer. The 1P1E does not require the second photo exposure of the double patterning method. Furthermore, the method circumvents the island pattern collapsing issues and the need for strong illumination associated with exiting single 1P1E processes. | 2011-08-11 |
20110193203 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained. | 2011-08-11 |
20110193204 | SEMICONDUCTOR DEVICE - A semiconductor package includes a substrate including a substrate body which has an upper surface and a lower surface facing away from the upper surface, first connection pads which are formed on the upper surface, and a second connection pad which is formed on the upper surface to be separated from the first connection pads, a semiconductor chip including first bonding pads and a second bonding pad, connection members connecting the first connection pads and the first bonding pads, and a resistor member connecting the second connection pad and the second bonding pad. | 2011-08-11 |
20110193205 | SEMICONDUCTOR DEVICE PACKAGES HAVING STACKING FUNCTIONALITY AND INCLUDING INTERPOSER - A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls. | 2011-08-11 |
20110193206 | STACKABLE SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE IN PRE-MOLDED CARRIER FRAME - Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability that are especially useful for portable and ultra-portable electronic apparatus. Other embodiments are also described. | 2011-08-11 |
20110193207 | LEAD FRAME FOR SEMICONDUCTOR DIE - A lead frame for providing electrical interconnection to a semiconductor die has a generally rectangular flag area having first and second major surfaces and four sides. The flag area is sized and shaped to receive a semiconductor die on one of the first and second major surfaces. A first row of leads is located adjacent to a first one of the four sides of the flag area and a second row of leads is located adjacent to a second one of the four sides of the flag area, where the second one of the four sides is adjacent to the first one of the four sides. The remaining two sides do not have any adjacent leads. | 2011-08-11 |
20110193208 | SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET AND ITS MANUFACTURING METHOD - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 2011-08-11 |
20110193209 | SEMICONDUCTOR PACKAGE - The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced. | 2011-08-11 |
20110193210 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad. | 2011-08-11 |
20110193211 | Surface Preparation of Die for Improved Bonding Strength - A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer. | 2011-08-11 |
20110193212 | Systems and Methods Providing Arrangements of Vias - A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values. | 2011-08-11 |
20110193213 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate. | 2011-08-11 |
20110193214 | SEMICONDUCTOR PACKAGE HAVING IMPROVED HEAT SPREADING PERFORMANCE - A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls. | 2011-08-11 |
20110193215 | SEMICONDUCTOR PACKAGE - Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased. | 2011-08-11 |
20110193216 | PACKAGE STRUCTURE - The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes an dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying with the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material. | 2011-08-11 |
20110193217 | Manufacturing of a Device Including a Semiconductor Chip - Metal particles are applied to a metal foil. A semiconductor chip is placed over the metal foil with contact elements of the semiconductor chip facing the metal particles. The metal particles are heated and the metal foil is structured after heating the metal particles. | 2011-08-11 |
20110193218 | Solder Interconnect with Non-Wettable Sidewall Pillars and Methods of Manufacture - A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall. | 2011-08-11 |
20110193219 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ASSEMBLY WITH LEAD-FREE SOLDER - A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent. | 2011-08-11 |
20110193220 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 2011-08-11 |
20110193221 | 3DIC Architecture with Interposer for Bonding Dies - A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure. | 2011-08-11 |
20110193222 | SEMICONDUCTOR MODULE, METHOD FOR FABRICATING THE SEMICONDUCTOR MODULE, AND MOBILE APPARATUS - A semiconductor module manufacturing method includes a step of bonding a semiconductor wafer, which has a plurality of semiconductor elements each of which has an element electrode formed thereon, on an expansible first insulating resin layer; a step of dicing the semiconductor wafer; a step of expanding the first insulating resin layer to widen a gap between semiconductor elements; a pressure-bonding step of pressure-bonding a metal plate whereupon an electrode is arranged and the semiconductor elements with the widened gaps in between, by having a second insulating resin layer in between, and electrically connecting the electrode and the element electrodes; a step of forming a wiring layer which corresponds to each semiconductor element by selectively removing the metal plate and forming a plurality of semiconductor modules connected by the first insulating resin layer and the second insulating resin layer; and a step of separating the semiconductor modules by cutting the first insulating resin layer and the second insulating resin layer. | 2011-08-11 |
20110193223 | SEMICONDUCTOR DEVICE, CHIP-ON-CHIP MOUNTING STRUCTURE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING THE CHIP-ON-CHIP MOUNTING STRUCTURE - A semiconductor device includes: a semiconductor chip having a semiconductor substrate; a pad electrode formed on the semiconductor substrate; a base metal layer formed on said pad electrode; and a bump electrode formed on the base metal layer, in which an exposed surface including a side surface of the base metal layer is covered with the solder bump electrode. | 2011-08-11 |
20110193224 | SEMICONDUCTOR DEVICE - In a semiconductor device, a pad electrode is disposed on a surface of a semiconductor substrate, and a surface-protective film is disposed on the surface of the semiconductor substrate and the pad electrode. The surface-protective film has an opening to expose a part of the pad electrode. A bump electrode is disposed on the part of the pad electrode exposed from the opening, and a bump is disposed on the bump electrode. The surface-protective film further has a slit at a location above the pad electrode. The slit has a frame shape surrounding a periphery of the bump electrode. The slit extends from a surface of the surface-protective film, which is opposite to the semiconductor substrate, and reaches the pad electrode. | 2011-08-11 |
20110193225 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 2011-08-11 |
20110193226 | MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer. | 2011-08-11 |
20110193227 | Methods and Apparatus for Robust Flip Chip Interconnections - Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %. | 2011-08-11 |