32nd week of 2012 patent applcation highlights part 38 |
Patent application number | Title | Published |
20120202297 | GENDER DETERMINATION METHOD - A non-invasive gender determination method and kits for accomplishing the same are disclosed herein. The present invention is based on difference in testosterone levels in the maternal body fluids of females carrying male fetuses relative to that of females carrying a female fetus. The present invention does not need specialized equipment and can quickly and rapidly detect the presence of testosterone in maternal urine or serum and thus indicate fetal gender. The kits and methods disclosed herein are useful for breeders of single-fetus mammals, veterinarians, and interested parents. | 2012-08-09 |
20120202298 | HTS Fluorescence Polarization Assay for Inhibitors of Keap1-Nrf2 Interaction - Disclosed are methods and kits for identifying modulators of the Keap1-Nrf2-ARE pathway. In particular, a high throughput fluorescent polarization assay is described that identifies small molecules that inhibit the binding of a fluorescently labeled Nrf2 peptide with the kelch domain of the Keap1 protein. Also provided are probes that can be used in the described fluorescent polarization assay. The small molecules identified using the described assay are useful for combating oxidative stress-related disorders, such as those associated with cancer, emphysema, Huntington's disease, light-induced retinal damage, and stroke. | 2012-08-09 |
20120202299 | ILLUMINATION DETECTION SYSTEM AND METHOD - An optical analysis apparatus and method in which a detector provides two different signals, based on responses to incident light absorbed within the detector over different depths. These signals are processed to discriminate between incident light of two different frequencies and thereby determine the intensity of the light of one desired frequency. | 2012-08-09 |
20120202300 | DIE BONDER INCLUDING AUTOMATIC BOND LINE THICKNESS MEASUREMENT - A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm. | 2012-08-09 |
20120202301 | METHOD OF FORMING MASK PATTERN - A disclosed method of forming a mask pattern includes forming a first resist film on a film to be etched, opening portions on the first resist film at a predetermined pitch, a first film on the first resist film so as to cover sidewalls of the first opening portions, a second resist film, second opening portions alternately arranged with the first opening portions on the second resist film, and a second film on the second resist film so as to cover sidewalls of the second opening portions, and removing a part of the second film so that the second film is left as first sidewall portions, a part of the first resist film using the first sidewall portions as a mask to form third opening portions, and a part of the first film while leaving the first film as second sidewall portions to form fourth opening portions. | 2012-08-09 |
20120202302 | SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device manufacturing system including processing devices used in processing processes, a wafer transfer device, a processing characteristic measuring unit, a device characteristic measuring unit, data server, and an analysis server. The wafer transfer device conveys the wafer to the processing devices such that a direction of the wafer differs according to each processing process. The data server stores data. The data include processing characteristic data that is the processing characteristic of the wafer for each processing process measured by the processing characteristic measuring unit, the direction of the wafer for each processing process, and device characteristic data that is the device characteristic of the wafer measured by the device characteristic measuring unit. The analysis server specifies a cause process that causes the device characteristic data to be obtained based on the correlation between the processing characteristic data and the device characteristic data. | 2012-08-09 |
20120202303 | CUSTOMIZED MANUFACTURING METHOD FOR AN OPTOELECTIRCAL DEVICE - The disclosure provides a customized manufacturing method for an optoelectrical device. The customized manufacturing method comprises the steps of providing a manufacturing flow including a front-end flow, a customized module subsequent to the front-end flow, and a pause step between the front-end flow and the customized module, processing a predetermined amount of semi-manufactured products queued at the pause step, tuning the customized module in accordance with a customer's request, and processing the semi-manufactured products by the tuned customized module to fulfill the customer's request. | 2012-08-09 |
20120202304 | III-NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD OF FABRICATING THE III- NITRIDE SEMICONDUCTOR LASER DEVICE - A method of fabricating a III-nitride semiconductor laser device includes: preparing a substrate with a semipolar primary surface, the semipolar primary surface including a hexagonal III-nitride semiconductor; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, the laser structure including a substrate and a semiconductor region, and the semiconductor region being formed on the semipolar primary surface; after forming the substrate product, forming first and second end faces; and forming first and second dielectric multilayer films for an optical cavity of the nitride semiconductor laser device on the first and second end faces, respectively. | 2012-08-09 |
20120202305 | ETCHANT FOR ETCHING DOUBLE-LAYERED COPPER STRUCTURE AND METHOD OF FORMING ARRAY SUBSTRATE HAVING DOUBLE-LAYERED COPPER STRUCTURES - An etchant for forming double-layered signal lines and electrodes of a liquid crystal display device includes hydrogen peroxide (H | 2012-08-09 |
20120202306 | Method of fabricating semiconductor substrate and method of fabricating light emitting device - The present invention provides a method of fabricating a semiconductor substrate and a method of fabricating a light emitting device. The method includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a void is formed in a first portion of the first semiconductor layer under the metallic material layer during formation of the second semiconductor layer, and separating the substrate from the second semiconductor layer by etching at least a second portion of the first semiconductor layer using a chemical solution. | 2012-08-09 |
20120202307 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first waveguide member is formed, as viewed from above, in an image pickup region and a peripheral region of a semiconductor substrate. A part of the first waveguide member, which part is disposed in the peripheral region, is removed. A flattening step is then performed to flatten a surface of the first waveguide member on the side opposite to the semiconductor substrate. | 2012-08-09 |
20120202308 | FABRICATING METHOD OF DYE-SENSITIZING SOLAR CELL - A fabricating method of a dye-sensitizing solar cell (DSSC) is provided. In the method, a working electrode and a counter electrode disposed opposite to each other is provided. The working electrode has a first patterned conductive line, and the counter electrode has a second patterned conductive line. A first gap control layer on at least an outer portion of one of the first and second patterned conductive lines is formed to surround the first and the second patterned conductive lines. Alternatively, the first gap control layer is symmetrically formed on one of the first and second patterned conductive lines. Then, a packaging material is formed on the first gap control layer. Next, the working electrode and the counter electrode are pressed to form a gap between the working electrode and the counter electrode. The packaging material is cured, and an electrolyte is filled into the gap. | 2012-08-09 |
20120202309 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SOLID-STATE IMAGE PICKUP DEVICE - The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask. | 2012-08-09 |
20120202310 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE - A method for manufacturing a solid-state image pickup device that includes a substrate including a photoelectric conversion unit and a waveguide arranged on the substrate, the waveguide corresponding to the photoelectric conversion unit and including a core and a cladding, includes a first step and a second step, in which in the first step and the second step, a member to be formed into the core is formed in an opening in the cladding by high-density plasma-enhanced chemical vapor deposition, and in which after the first step, in the second step, the member to be formed into the core is formed by the high-density plasma-enhanced chemical vapor deposition under conditions in which the ratio of a radio-frequency power on the back face side of the substrate to a radio-frequency power on the front face side of the substrate is higher than that in the first step. | 2012-08-09 |
20120202311 | METHOD OF MANUFACTURING IMAGE SENSOR - A method of manufacturing image sensor includes the following steps. A substrate having a first region and a second region is provided. A plurality of image sensing components and a periphery circuit are formed on the substrate in the first region and the second region respectively. A first conductive layer and a first dielectric layer are formed on the substrate. An etch stop layer is formed on the first dielectric layer. A second conductive layer is formed on the etch stop layer in the second region. A second dielectric layer is formed on the substrate. The second dielectric layer on the etch stop layer in the first region is etched to be removed. The etch stop layer in the first region is removed to form a space. A color filter array is disposed in the space. | 2012-08-09 |
20120202312 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An interlayer insulating film is disposed above an image pickup region and a peripheral region of the semiconductor substrate. An opening is formed in the interlayer insulating film at a position overlying a photoelectric conversion portion. A waveguide member is formed above the image pickup region and the peripheral region of the semiconductor substrate. A part of the waveguide member, which part is disposed above the peripheral region, is removed such that the interlayer insulating film is exposed. | 2012-08-09 |
20120202313 | METHOD AND APPARATUS FOR FORMING THE SEPARATING LINES OF A PHOTOVOLTAIC MODULE WITH SERIES-CONNECTED CELLS - For forming the separating lines, ( | 2012-08-09 |
20120202314 | SOLAR CELLS BASED ON POLYMER NANOWIRES - Solar cells having active layers that include poly(3-alkylthiophene) nanowires. | 2012-08-09 |
20120202315 | IN-SITU HYDROGEN PLASMA TREATMENT OF AMORPHOUS SILICON INTRINSIC LAYERS - Embodiments of the invention generally provide methods for forming amorphous silicon-based photovoltaic devices, such as solar cells, by utilizing deposition and plasma treatment steps during a plasma-enhanced chemical vapor deposition (PE-CVD) process. In one embodiments, the method includes exposing a transparent conductive oxide (TCO) layer disposed on a substrate to hydrogen plasma during pretreatment, forming a p-type α-Si film on the TCO layer, forming an α-Si intrinsic film on the p-type α-Si film during a PE-CVD process, and forming an n-type α-Si film on the α-Si intrinsic film. In some examples, the PE-CVD process includes depositing an α-Si intrinsic layer during a deposition step, treating the α-Si intrinsic layer to form a treated α-Si intrinsic layer during a plasma treatment step, and sequentially repeating the deposition step and the plasma treatment step until obtaining a desired thickness of the α-Si intrinsic film containing a plurality of treated α-Si intrinsic layers. | 2012-08-09 |
20120202316 | PLASMA TREATMENT OF TCO LAYERS FOR SILICON THIN FILM PHOTOVOLTAIC DEVICES - Embodiments of the invention generally provide methods for forming a silicon-based photovoltaic (PV) device containing a transparent conductive oxide (TCO) layer that is exposed to a very high frequency (VHF) plasma. In one embodiment, a method includes depositing a TCO layer on an underlying surface, such as a transparent substrate, and exposing the TCO layer to a VHF plasma to form a treated surface on the TCO layer during a plasma treatment process. The VHF plasma is generated by ionizing a process gas containing hydrogen (H | 2012-08-09 |
20120202317 | BIFACIAL SOLAR CELL USING ION IMPLANTATION - An improved bifacial solar cell is disclosed. In some embodiments, the front side includes an n-type field surface field, while the back side includes a p-type emitter. In other embodiments, the p-type emitter is on the front side. To maximize the diffusion of majority carriers and lower the series resistance between the contact and the substrate, the regions beneath the metal contacts are more heavily doped. Thus, regions of higher dopant concentration are created in at least one of the FSF or the emitter. These regions are created through the use of selective implants, which can be performed on one or two sides of the bifacial solar cell to improve efficiency. | 2012-08-09 |
20120202318 | METHOD FOR THE PRODUCTION OF LAYERS CONTAINING INDIUM OXIDE - The present invention relates to a liquid phase process for producing indium oxide-containing layers from nonaqueous solution, in which an anhydrous composition containing at least one indium oxo alkoxide of the generic formula M | 2012-08-09 |
20120202319 | MOLD APPARATUS AND METHOD - An apparatus and method for producing an article by molding is disclosed. In one embodiment, the method includes a mold with an upper part, a lower part and at least one mold cavity, and has a vacuum clamping ring with a least one closable vent, which is arranged between the upper part and the lower part. The mold cavity is at least partially filled with a mold material. The vent is closed, and the mold cavity is filled with a thermoplastic or thermoset material. | 2012-08-09 |
20120202320 | WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S) - Wafer-level chip scale packaging of metal-oxide-semiconductor-field-effect-transistors (MOSFET's) provides protection and good solder-ability to a die backside by fabricating a plurality of power MOSFET devices with die contacts on a wafer that can later be cut into individual die. A plurality of contact pads is included on the wafer to provide connectivity to the die contacts. A layer which includes aluminum (Al) or zinc (Zn) is electrolessly plated on a backside of the wafer to form a metalized backside. The plating tank used in this step is not contaminated. The contact pads and metalized backside are plated with a layer of electroless nickel (Ni) followed by a layer of gold (Au). Solder balls are formed on each of the contact pads after their plating with nickel (Ni) and gold (Au). The wafer is diced to yield MOSFET wafer level chip-scale packages which provide protection and good solder-ability to the die backside. | 2012-08-09 |
20120202321 | IC Device Having Low Resistance TSV Comprising Ground Connection - A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV. | 2012-08-09 |
20120202322 | ASSEMBLY JIG FOR A SEMICONDUCTOR DEVICE AND ASSEMBLY METHOD FOR A SEMICONDUCTOR DEVICE - In aspects of the assembly jig and method of the invention, when a packaging substrate is curved concaving upward at temperatures of melting solder, the gap between the assembly jig and the packaging substrate can be made smaller than the dimension of the sum of the thickness of the semiconductor chip and the thickness of the melted solder by allowing a part of the bottom surface of the chip positioning piece to become always, or substantially always, in contact with the upper surface of the packaging substrate owing to the weight of the chip positioning jig itself. As a consequence, the semiconductor chip does not slip aside out of the opening of the chip positioning piece. Therefore, the semiconductor chip can be positioned accurately on the packaging substrate. | 2012-08-09 |
20120202323 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a silicon film, in which an impurity density of a center portion is higher than that of an upper portion and a lower portion, is formed above a base layer, a mask pattern is formed above the silicon film, a recess is formed in the silicon film by selectively etching the silicon film through the mask pattern, a silicon oxide film is formed on a surface of the recess by an oxidation process of the silicon film, and the silicon film under the recess is etched through the mask pattern after the oxidation process. attern. | 2012-08-09 |
20120202324 | MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE AND PATTERN-FORMING METHOD - The present invention provides a manufacturing apparatus of a semiconductor device, having a pattern-forming apparatus using a droplet-discharging method that is suitable for a large substrate in mass production. A plurality of pattern-forming apparatuses using a droplet-discharging method and a plurality of heat-treatment chambers are provided, and each of which is connected to one transfer chamber, which is a multi-chamber system. Discharging and baking are conducted efficiently to improve productivity. A gas is blown in the same direction as the scanning direction (or a scanning direction of a discharging head) on a substrate just after a droplet is landed, by providing a blowing means in the pattern-forming apparatus, and a heater is provided in a gas-flow path for local baking. | 2012-08-09 |
20120202325 | METHOD FOR MANUFACTURING A SINGLE CRYSTAL NANO-WIRE - A method for manufacturing a single crystal nano-structure includes providing a device layer with a | 2012-08-09 |
20120202326 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure. | 2012-08-09 |
20120202327 | Compressive Polycrystalline Silicon Film and Method of Manufacture Thereof - In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C. | 2012-08-09 |
20120202328 | METHOD FOR FABRICATING MOS TRANSISTOR - The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed. | 2012-08-09 |
20120202329 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. | 2012-08-09 |
20120202330 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor. | 2012-08-09 |
20120202331 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With such an exposure mask, various light exposures can be more accurately controlled, which enables a resist to be processed into a more accurate shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps. | 2012-08-09 |
20120202332 | ROBUST SEMICONDUCTOR DEVICE - A method for producing a semiconductor component structure in a semiconductor body. In one embodiment, the method includes producing two differently doped semiconductor zones of the same conduction type, and carrying out a first implantation, implanting dopant atoms of a first conduction type into the semiconductor body via one of the sides over the whole area. A mask is produced on the one side, partly leaving free the one side. A second implantation is carried out, implanting dopant atoms of the first conduction type into the region left free by the mask proceeding from the one of the sides. | 2012-08-09 |
20120202333 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 2012-08-09 |
20120202334 | METHOD OF FABRICATION OF THE MEMRISTIVE DEVICE - Three-dimensionally spatially localized artificial filament in the active layer of the memristive device formed by means of ion implantation through the top electrode structure provide the means to achieve high repeatability and high reliability of the memristive devices, leading to significantly improved manufacturing yield. The memristive devices fabricated according to the disclosed method of fabrication can be used in data storage, signal processing and sensing applications. | 2012-08-09 |
20120202335 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 2012-08-09 |
20120202336 | METHOD OF FORMING AN ISOLATION STRUCTURE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench. | 2012-08-09 |
20120202337 | WAFER PROCESSING SHEET - Provided is a sheet for processing a wafer. The sheet can exhibit excellent heat resistance and dimensional stability, prevent breakage of a wafer in response to residual stress due to excellent stress relaxation properties, inhibit damage to or dispersion of the wafer due to application of a non-uniform pressure, and also exhibit excellent cuttability. The sheet can effectively prevent a blocking phenomenon from occurring during wafer processing. For these reasons, the sheet can be useful for processing a wafer in various wafer preparation processes such as dicing, back-grinding and picking-up. | 2012-08-09 |
20120202338 | EPITAXY OF HIGH TENSILE SILICON ALLOY FOR TENSILE STRAIN APPLICATIONS - Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×10 | 2012-08-09 |
20120202339 | Semiconductor stacking layer and fabricating method thereof - A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (α-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the α-Si layer. After that, a doped microcrystalline silicon (μc-Si) layer is formed on the treated surface of the α-Si layer, wherein interface defects existing between the α-Si layer and the doped μc-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer. | 2012-08-09 |
20120202340 | N-TYPE DOPING OF ZINC TELLURIDE - ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be performed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C. | 2012-08-09 |
20120202341 | N-TYPE DOPING OF ZINC TELLURIDE - ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C. | 2012-08-09 |
20120202342 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes depositing a wiring metal layer on a photoresist layer and a portion of a first layer of a gate lead-out electrode which is exposed via an opening, lifting-off a wiring metal layer formed on the photoresist layer forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer, selectively removing the interlayer insulation film thereby forming a contact via reaching a source region formed in a cell region, and forming a source electrode on the interlayer insulation film and electrically connecting a source electrode with the source region. | 2012-08-09 |
20120202343 | METHOD OF FORMING UNDERBUMP METALLURGY STRUCTURE EMPLOYING SPUTTER-DEPOSITED NICKEL COPPER ALLOY - A metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Cu alloy in which the weight percentage of Ni is from about 50% to about 70% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. Optionally, a wetting layer comprising Cu or Au may be deposited by sputtering. A C4 ball is applied to a surface of the underbump metallic layer comprising the Ni—Cu alloy or the wetting layer for C4 processing. The sputter deposition of the Ni—Cu alloy offers economic advantages relative to known methods in the art since the Ni—Cu alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Cu alloy is limited during C4 processing. | 2012-08-09 |
20120202344 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a technology capable of preventing corrosion of a Cu wiring and thereby improving a production yield of a semiconductor device, a manufacturing method of a semiconductor device includes the steps of: removing a portion of a Cu film other than that in a wiring trench in a semiconductor substrate by CMP using a polishing slurry, removing a portion of a barrier metal film other than that in the, wiring trench by CMP using a polishing slurry containing an anticorrosive, polishing the surface of the Cu film and the surface of the barrier metal film by CMP using pure water, thereafter cleaning the semiconductor substrate with pure water without applying an anticorrosive thereto or without cleaning it with a chemical liquid, and thereafter cleaning the semiconductor substrate with a chemical liquid without applying an anticorrosive thereto. | 2012-08-09 |
20120202345 | METHOD TO ENABLE THE PROCESS AND ENLARGE THE PROCESS WINDOW FOR SILICIDE, GERMANIDE OR GERMANOSILICIDE FORMATION IN STRUCTURES WITH EXTREMELY SMALL DIMENSIONS - Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon. | 2012-08-09 |
20120202346 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Certain embodiments provide a method for manufacturing a semiconductor device including forming first and second insulating films on first and second regions formed on a semiconductor substrate, respectively, selectively irradiating UV light to a second contact region where the second contact is to be formed in the second insulating film, forming first and second opening on the first and second insulating films by concurrently etching a first contact region in the first insulating film where the first contact is to be formed and the second contact region after having irradiated the UV light, respectively, forming first and second contacts in the first and second openings. The second insulating film differs from the first insulating film in the membrane stress, and is an insulating film with an etching rate that approaches an etching rate of the first insulating film by the UV light being irradiated. | 2012-08-09 |
20120202347 | THROUGH SILICON VIAS USING CARBON NANOTUBES - The various embodiments of the present invention provide carbon nanotube (CNT)-based TSVs and methods of making the same. The CNT-based TSVs embodiments comprise a silicon wafer having a plurality of through-vias defined therein, and a support layer comprising a CNT catalyst layer disposed beneath the silicon wafer to facilitate CNT growth through the plurality of through-vias. Once CNT arrays have grown inside and through the through-vias, the support layer and accompanying CNT catalyst layer can be removed from the silicon wafer, which will result in the CNTs remaining in the TSVs. | 2012-08-09 |
20120202348 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device according to an embodiment, includes forming a plurality of films above a substrate in a same chamber without transferring the substrate out of the chamber, forming a target film to be polished above the plurality of films, and polishing the target film by a chemical mechanical polishing (CMP) technique using a film on a front side among the plurality of films as a polishing stopper. | 2012-08-09 |
20120202349 | Photo-imageable Hardmask with Dual Tones for Microphotolithography - Disclosed is a method of making polysiloxane and polysilsesquioxane based hardmask respond to radiations with positive tone and negative tone simultaneously. Unradiated films are insoluble in developers, showing positivity tone. Radiated films are insoluble in developers as well, showing negative tone. Only half-way radiated films are soluble in developers. The dual-tone photo-imageable hardmask produces splitted patterns. Compositions of dual-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Further disclosed are processes of using photo-imageable hardmasks to create precursor structures on semiconductor substrates with or without an intermediate layer. | 2012-08-09 |
20120202350 | METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 2012-08-09 |
20120202351 | METHODS OF FORMING A PHOTO MASK - Methods of fabricating a photo mask are provided. The method includes collecting sample data, setting a preliminary mask layout, performing an optical proximity correction using the sample data and a preliminary mask layout to obtain an optimized preliminary mask layout, verifying the optimized preliminary mask layout to obtain a final mask layout, and fabricating the photo mask using the final mask layout. Verification of the optimized preliminary mask layout includes operating a verification simulator using the sample data and the optimized preliminary mask layout as input data to obtain verification image data. The verification image data includes a plurality of contours of a pattern at different vertical positions. | 2012-08-09 |
20120202352 | METHOD OF AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A vertical single wall reaction tube type batch processing furnace can reduce the generation of particles. A method of removing native oxide film by fluoride gas can enhance the efficiency of utilization of gas. A method of exciting reaction gas by a catalyst at high temperature can be applied to a batch processing. A method of exciting reaction gas by a catalyst utilizes an oxidizing agent and gas other than an oxidizing agent. The flow rate of gas in the gas injection pipe and that of gas in the exhaust pipe are made to be substantially equal to each other. The gap between two adjacent wafers is made greater than the mean free path of gas. The oxidizing agent is dissociated by a catalyst of Ir, V or Kanthal while the gas other than the oxidizing agent is dissociated by a catalyst of W. | 2012-08-09 |
20120202353 | NANOLAYER DEPOSITION USING PLASMA TREATMENT - A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps. | 2012-08-09 |
20120202354 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. | 2012-08-09 |
20120202355 | PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD - A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes. | 2012-08-09 |
20120202356 | METHODS OF FORMING RUTILE TITANIUM DIOXIDE AND ASSOCIATED METHODS OF FORMING SEMICONDUCTOR STRUCTURES - Methods of forming rutile titanium dioxide. The method comprises exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to oxygen gas (O | 2012-08-09 |
20120202357 | In Situ Vapor Phase Surface Activation Of SiO2 - Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water above the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia. | 2012-08-09 |
20120202358 | GRADED DIELECTRIC STRUCTURES - Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material. | 2012-08-09 |
20120202359 | Method of Increasing Deposition Rate of Silicon Dioxide on a Catalyst - Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about | 2012-08-09 |
20120202360 | ELECTRICAL HINGE CONNECTOR - A hinge for an aircraft power distribution system unit is provided. The unit has a housing comprising a first housing part and a second housing part. The hinge comprises a first hinge member for connection to the first housing part of the unit; and a second hinge member for connection to the second housing part of the unit, wherein the first and the second hinge members comprise an electrically conductive material and wherein the first and the second hinge members are connectable to one another to establish an electrical connection between the first and the second hinge members and to allow relative rotation between the first and the second hinge members. | 2012-08-09 |
20120202361 | Electrical connector incorporated with circuit board facilitating interconnection - An electrical connector ( | 2012-08-09 |
20120202362 | DEVICE, SYSTEM AND METHOD OF AN INTERFACE CONNECTOR - Embodiments of the invention described herein a device, method and system of connecting a first circuit board and a second circuit board using an interface connector. In one aspect, an interface connector is described that is comprised of a casing and a plurality of electrically conductive connectors insulated from one another within the casing. Each connector has a first end and a second end, wherein the first end connects to a first circuit board and the second end connects to a second circuit board. The plurality of connectors form a first row and a second row of the interface connector. The first row is comprised of evenly-numbered connectors and the second row is comprised of odd-numbered connectors. The plurality of connectors are assigned as follows: connectors | 2012-08-09 |
20120202363 | MEZZANINE CONNECTOR - A two-piece mezzanine connector for high speed, high density signals. The connector is assembled from wafers that may be formed of identical wafer halves. The halves may have interior portions that form a channel in which a lossy member may be captured for selectively configuring the connector for high frequency performance. The lossy member may be serpentine, to both provide different spacing relative to signal and ground conductors and to provide compliance to press against ground conductors when captured between wafer halves. Instead of, or in addition to, the lossy member captured between two wafer halves, the wafer halves may each have lossy material overmolded on at least one side, so that an assembled wafer may have lossy material disposed on the outside. The wafers may have dovetail projections that are secured within dovetail channels, forming structural members of the connector. | 2012-08-09 |
20120202364 | COMPLIANT CONDUCTIVE NANO-PARTICLE ELECTRICAL INTERCONNECT - An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles. | 2012-08-09 |
20120202365 | CHARGING CONNECTOR AND METHOD OF MOUNTING IT - A charging connector ( | 2012-08-09 |
20120202366 | ELECTRICAL CONNECTOR DEVICE - An electrical connection device comprises an electrical connector and a carriage. The electrical connector comprises a housing, a cage, and a plurality of terminals. The housing has a body, the terminals are provided in the body. The cage encloses the housing, and defines, together with the housing, an insertion slot, and an opening of the insertion slot corresponds to a front end of the body. The carriage can be slidably positioned in the insertion slot. The housing comprises at least a clamping slot provided close to the front end in the body, the carriage has a clamping block mating with the clamping slot, the carriage is releasably held to the electrical connector by clampingly connecting the clamping slot to the clamping block. | 2012-08-09 |
20120202367 | ELECTRICAL CONNECTION BOX - A permanent part attachment portion and an additional part attachment portion are provided to a case. A terminal portion of a permanent bus bar is disposed in the permanent part attachment portion, and a terminal portion of an additional bus bar is disposed in the additional part attachment portion by allowing the additional bus bar to be contained in the case in a removable manner. It thus becomes possible to provide an electrical connection box that is adaptable to an addition of an electrical part without changing a die used to mold the case and/or a die used to form the bus bars. | 2012-08-09 |
20120202368 | CONNECTOR - A connector (X) includes a housing ( | 2012-08-09 |
20120202369 | UNDERWATER POWER GENERATOR - A connector ( | 2012-08-09 |
20120202370 | CONNECTOR ASSEMBLIES HAVING FLEXIBLE CIRCUITS CONFIGURED TO DISSIPATE THERMAL ENERGY THEREFROM - A connector assembly that includes a communication connector comprising a base frame and a moveable side that is supported by the base frame. The moveable side has a mating array of terminals thereon and is configured to move with respect to the base frame between retracted and engaged positions to engage a communication component. The connector assembly also includes a flexible circuit including a flex interconnect that has opposite exterior surfaces. The flexible circuit is coupled to the moveable side. The connector assembly also includes a plurality of heat-dissipation elements that are attached to the flex interconnect and project away from one of the exterior surfaces. The heat-dissipation elements are configured to conduct thermal energy from the flex interconnect and transfer the thermal energy to an ambient environment. | 2012-08-09 |
20120202371 | INTEGRAL CONNECTOR FOR PROGRAMMING A HEARING DEVICE - For the connection of a programming device to a hearing device an insertable plate ( | 2012-08-09 |
20120202372 | CONNECTOR ASSEMBLY - A connector assembly includes a center contact configured to be terminated to a center conductor of a cable. A dielectric holds the center contact. A stamped and formed outer contact surrounds the dielectric and the center contact. The outer contact is configured to be terminated to a braid of the cable. A stamped and formed outer ferrule surrounds at least a portion of the outer contact such that the braid is sandwiched between the outer ferrule and the outer contact. | 2012-08-09 |
20120202373 | TEMPERATURE CONTROL ARRANGEMENT - An electrical connector includes a housing and an arrangement. The arrangement includes microelectromechanical systems (MEMS) or a piezoelectric element or a combination thereof, configured to displace a temperature controlling medium. The electrical connector also includes at least one opening in the housing for transporting the temperature controlling medium displaced by the arrangement through the opening. | 2012-08-09 |
20120202374 | PLUG CONNECTOR FOR PHOTOVOLTAIC CABLE SET - A plug-type connector has a plug part fittable with a socket part parallel to a predetermined longitudinal axis, both of the parts having a body. One of the bodies is formed with a longitudinally projecting tongue formed at a spacing from the one body with a transversely projecting barb having an angled inner face turned toward the one body, forming an acute angle of 20° to 45° with a plane perpendicular to the longitudinal axis, and forming a wedge-shaped seat with a longitudinally extending side face of the tongue. The other of the bodies is formed extending inward from the other body with a longitudinally extending passage through which the barb can pass and is formed at an inner end of the passage with an angled inner face engageable with and generally parallel to the angled inner face of the barb on fitting of the bar through the passage. | 2012-08-09 |
20120202375 | SMALL FORM FACTOR COMPUTING DEVICE WITH CONNECTOR ASSEMBLY TO INTERCONNECT SLIDING HOUSING SEGMENTS - A mobile computing device is disclosed. The mobile computing device comprises two housing segments that each contains a set of electrical components. The housing segments are slideably coupled to each other to move between a first position and a second position. The mobile computing device also comprises a cable connector that connects the sets of electrical components together. The cable connector is configured to include three connector structures that are each configured to mate with a connector. A first connector structure is configured to mate with a first connector of the first housing segment in connecting to the first set of electrical components. Similarly, a second connector structure is configured to mate with a first connector of the second housing segment in connecting to a first portion of the second set of electrical components. The third connector structure is configured to mate with a second connector of the second housing segment in connecting to a second portion of the second set of electrical components. | 2012-08-09 |
20120202376 | Mating Support Member For Electrical Connectors and Method of Mating Electrical Connectors - A mating support member that mates a first electrical connector and a second electrical connector with each other. The support member includes a support member main body having a protrusion receiving passageway, a lever disposed on an opposite side of the protrusion receiving passageway, and a cam section formed in the support member main body between the protrusion receiving passageway and the lever. The cam section includes a first receiving passageway formed at one end of the cam section, a second receiving passageway formed at another end of the cam section, and a cam groove that is formed between and continuous with the first receiving passageway and the second receiving passageway and for presses first and second connectors together. | 2012-08-09 |
20120202377 | JUMPER CABLE PLUG WITH MOISTURE RESISTANT SEAL - An electrical plug configured to be mated with a socket, the electrical plug including a substantially tubular plug housing having a front end, a rear end, a side wall between the front end and the rear end, and a housing protrusion on the side wall and configured to be inserted within a socket cutout of the socket, a groove proximate the front end of the housing, and a seal located in the groove and having a cross-section with an outer surface that is substantially similar to an outer surface of a cross-section of the side wall and the housing protrusion. | 2012-08-09 |
20120202378 | CONNECTOR HAVING A CONDUCTIVELY COATED MEMBER AND METHOD OF USE THEREOF - A connector having a conductively coated member is provided, wherein the connector comprises a connector body capable of sealing and securing a coaxial cable, and further wherein the conductively coated member, such as an 0-ring, physically seals the connector, electrically couples the connector and the coaxial cable, facilitates grounding through the connector, and renders an electromagnetic shield preventing ingress of unwanted environmental noise. | 2012-08-09 |
20120202379 | CONNECTOR WITH DEFORMABLE COMPRESSION SLEEVE - A connector for a coaxial cable that includes a connector body and a deformable sleeve. The deformable sleeve and the connector body have cooperative structure for engaging the deformable sleeve with the receiving end of the connector body for securing a cable in the connector body. The deformable sleeve has a front section connected to a rear section by a web. The deformable sleeve is movable from a first position, wherein the front end of the deformable sleeve is separably attached to the receiving end of the connector, to a second position, wherein the cable is compressively secured in the connector body. The web stretches and/or breaks when the deformable sleeve moves into the second position. | 2012-08-09 |
20120202380 | PLUG-IN CONNECTION HAVING SHIELDING - The invention relates to a plug-in connection having shielding, in particular a multi-pin, multi-row plug-in connection comprising a male multipoint connector and a female multipoint connector, the plug-in connection comprising signal contacts, which are arranged in a contact pattern of differential pairs and which form a contact group together with an L-shaped shielding element that surrounds the signal contacts, the contact groups being arranged in rows and columns and adjacent contact groups in adjacent columns being offset from each other by a specifiable length dimension in the longitudinal direction of the columns, the plug-in connection being characterized in that the specified length dimension corresponds to approximately half the distance of two adjacent contact groups in a column. | 2012-08-09 |
20120202381 | FITTING STRUCTURE FOR INNER HOLDER AND SHIELD SHELL - An inner holder through which the electric wire connected to the electronic device is passed includes a plurality of peripheral walls. A shield shell adapted to be brought into engagement with the inner holder | 2012-08-09 |
20120202382 | Piezoactuator Having Electrical Contact - A piezoactuator has multilayer construction. Piezoelectric layers and electrode layers are alternatingly disposed one over the other in a stack. A number of the electrode layers are electrically conductively connected to a contact pin. A continuation is electrically conductively disposed on the contact pin. The continuation has a contact point with the contact pin and a free end for producing an electrical connection of the piezoactuator. A straight line extending through the contact point and the free end of the continuation encloses an angle with the longitudinal axis of the contact pin that is greater than 0° and less than 180°. | 2012-08-09 |
20120202383 | FUSE CONNECTION UNIT - A fuse connection unit includes a metal core substrate that includes a metal core plate and insulation layers formed on front and back faces of the metal core plate, and a fuse block mounted on the metal core substrate. The metal core substrate has a fuse connection terminal part which is projected from an end edge of each of the insulation layers. The fuse block has a fuse connection terminal. The fuse connection terminal part and the fuse connection terminal are configured to be connected to a fuse. | 2012-08-09 |
20120202384 | SOCKET CONNECTOR WITH CONTACT TERMINAL HAVING OXIDATION-RETARDING PREPARATION ADJACENT TO SOLDER PORTION PERFECTING SOLDER JOINT - An electrical connector having a fusible element for mounting on a substrate includes an insulative housing and a contact terminal retained in the insulative housing. The contact terminal includes a resilient contacting arm extending beyond a mating face of the insulative housing and a soldering portion for mating with the fusible element. A gelatinous flux is deployed on the fusible element, and/or on the soldering portion, and/or between the fusible element and the soldering portion, and then flux is dried to immovably fix the fusible element with respect to the soldering portion. The dried flux will be re-juvenile to clean and remove an oxidized layer originally existed on the soldering portion so as to achieve robust welding quality. Besides, a method for trimming an electrical connector to have robust welding properties is also disclosed. | 2012-08-09 |
20120202385 | CONNECTOR FOR MEDICAL INSTRUMENT - A connector for a medical instrument connected to an external device for medical use is provided, and the connector for a medical instrument includes a plug portion in which electric contact point portions are placed, outer sheath cases connectively provided at the plug portion, a sub frame member interposed between the plug portion and the outer sheath cases, and having a flange portion, and a main frame member housed in the outer sheath cases and fixed to the sub frame member, wherein the plug portion and the outer sheath cases are butted against the flange portion by different fixing members respectively, and are compressed and fixed to the sub frame member. | 2012-08-09 |
20120202386 | MEZZANINE CONNECTOR - A two-piece mezzanine connector for high speed, high density signals. One piece of the connector may have conductive elements with beam-shaped mating contacts. The beams may include openings to control mechanical properties while allowing edge to edge spacing between adjacent beams to be selected to provide desired electrical properties. The openings may be teardrop shaped, with a larger width at a distal end of the beams. Beams associated with signal conductors may have openings that are shaped differently from openings of beams associated with ground conductors. For a first connector piece, mating contact regions of signal conductors may be wider than mating contact regions of ground conductors. For a second connector piece adapted to mate with the first connector piece, mating contact regions of signal conductors may be narrower than mating contact regions of ground conductors. These contact shapes may provide float while maintaining a high contact density. | 2012-08-09 |
20120202387 | MEZZANINE CONNECTOR - A footprint of an electronic assembly formed from conductive pads on a surface of a printed circuit board. One or more vias may connect each pad to a conductive structure within the printed circuit board. The footprint may be such that the vias for the pads are aligned along columns, leaving wide routing channels between the columns. The pads may have different shapes. For example, some of the pads may each have two solder attachment regions that are electrically connected to a ground plane, while other pads may each have one solder attachment region that is electrically connected to a signal trace. The solder attachment regions may be arranged in such a pattern that they align with respective contact tails of a connector assembly. A signal path may be formed between a solder attachment region and a corresponding contact tail through a solder ball attached to the contact tail. | 2012-08-09 |
20120202388 | UNIVERSAL CONNECTOR SOCKET - A universal connector socket for a surgical apparatus for the connection of different plug connectors of different surgical instruments for RF surgery. The universal connector socket has several plug contact openings for selectively connecting monopolar and bipolar surgical instruments and has several plug contact openings arranged in an overlapping manner for defining an unambiguous plug-in position of a plug connector and a shared reference plug contact opening. | 2012-08-09 |
20120202389 | SPRING ASSEMBLY WITH SPRING MEMBERS BIASING AND CAPACITIVELY COUPLING JACK CONTACTS - A spring assembly for a communications jack including a plurality of jack contacts each electrically connectable to a corresponding plug contact of a communications plug. First and second jack contacts carry a first differential signal. Fifth and sixth jack contacts carry a second differential signal. The jack contacts carrying the first differential signal are adjacent a third jack contract and the jack contacts carrying the second differential signal are adjacent a fourth jack contract. For each jack contact, the assembly has a conductive spring member electrically connected to the jack contact that biases the jack contact against a corresponding plug contact. To reduce crosstalk, the spring members connected to the first and second jack contacts are each capacitively coupled to the fourth jack contact, and the spring members connected to the fifth and sixth jack contacts are each capacitively coupled to the third jack contact. | 2012-08-09 |
20120202390 | SLIDABLE POGO PIN - There is provided a slidable pogo pin including: a first member including a first body and a first connection portion extending from the first body and integrally formed with the first body; a second member including a second body and a second connection portion extending from the second body and integrally formed with the second body; and a spring applying elastic force to the first member and the second member, with at least a part of the first member and at least a part of the second member inserted into the spring. Further, the first member and the second member are electrically connected to each other via the first connection portion and the second connection portion, and the first connection portion and the second connection portion are configured to slide with respect to each other while the first connection portion is brought into surface-to-surface contact with the second connection portion. | 2012-08-09 |
20120202391 | MULTI-CONTACT TERMINAL FITTING - A multi-contact terminal fitting (T) has a plurality of resilient contact pieces ( | 2012-08-09 |
20120202392 | TRIPLE CAM-OPERATED LINK - A high voltage link apparatus may include a link assembly that includes an insulated bushing portion; a first feed thru junction bushing portion; and a second feed thru junction bushing portion. The insulated bushing portion is electrically isolated from the first feed thru junction bushing portion and the second feed thru junction bushing portion. The first feed thru junction bushing portion is conductively coupled to the second feed thru junction bushing portion. First, second, and third bushing interfaces are provided for conductively coupling to first, second, and third power cables, respectively. Each of the first, second, and third bushing interfaces include link receiving portions configured to receive the link assembly therein. The link assembly is installable in the first, second, and third bushing interfaces in first and second, reversible orientations. | 2012-08-09 |
20120202393 | ARRANGEMENT WITH A CLAMP OF METAL CONSTRUCTED AS A PIPE PIECE - An arrangement for fastening an electrical conductor has a clamp ( | 2012-08-09 |
20120202394 | TERMINAL FITTING AND A METHOD FOR FORMING A FLUID-PROOF TERMINATED WIRE ASSEMBLY - A terminal fitting ( | 2012-08-09 |
20120202395 | CONNECTOR HAVING IMPROVED CONTACTS - An electrical connector for connecting a conductor of a daughter card connector wafer with a blade in the housing of a backplane connector. The daughter card conductor has a body with two elongated beams extending outward from the body. The two elongated beams each have an outer edge and an inner edge, whereby an opening is defined between the inner edges. The backplane conductor has a body with a narrowed tab portion extending outward from said second conductor body. The narrowed tab portion having outer opposite edges and is sized so that the narrowed tab portion fits between at least a portion of the outer edges of the two elongated beams, and in some cases between at least a portion of the inner edges of the two elongated beams. | 2012-08-09 |
20120202396 | INFLATABLE WET SUIT - Wet suits used by water sports enthusiasts (e.g., surfers) are provided with the ability to be inflated during emergency situations to provide life-saving buoyancy and floatation aid. The inflatable wet suit will preferably include a torso section having a back pocket and a bladder assembly having an inflatable bladder bag and an inflator valve adapted for operative connection with a compressed gas canister positioned within the back pocket. A rip cord has one of its ends connected to the inflator valve and extends over a shoulder region of the torso section so that the other end thereof is graspably positioned adjacent a front portion of the torso section. A canister pouch within the back pocket of the torso section is provided for receiving the gas canister therein. The canister pouch includes a front wall attached to the torso section along side and bottom edges thereof with a top edge being unattached to the torso section so as to define a pouch space with an open upper end. The front wall also preferably includes at least one cut-out region to allow manual manipulation of the gas canister positioned in the pouch space. A deflation assembly allows the bladder bag to be deflated after use. | 2012-08-09 |