| 32nd week of 2013 patent applcation highlights part 29 |
| Patent application number | Title | Published |
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| 20130201723 | LIGHT GUIDE DEVICE - A light guide device for illumination, lighting and display purposes that exhibits an output light having a predetermined, and preferably uniform, angular luminance profile is described. The device comprises a light guide ( | 2013-08-08 |
| 20130201724 | LIGHT GUIDE PLATE HAVING DUAL MICRO STRUCTURES - A light guide plate includes a light incident surface, a light exit surface; and a bottom surface opposite the light exit surface. The light incident surface includes many first micro structures and many second micro structures. Each second micro structure cover some of the first micro structures. | 2013-08-08 |
| 20130201725 | RESONANT CIRCUIT AND RESONANT DC/DC CONVERTER - The present disclsure relates to a resonant circuit ( | 2013-08-08 |
| 20130201726 | RESONANT POWER CONVERTER HAVING SWITCHED SERIES TRANSFORMER - A multi-transformer LLC (resonant) power converter having at least two transformers including a first T | 2013-08-08 |
| 20130201727 | METHOD TO MINIMIZE INPUT CURRENT HARMONICS OF POWER SYSTEMS SUCH AS ESP POWER SYSTEMS - Disclosed is a method for the improvement of the line quality in a system, in which a common feeding ( | 2013-08-08 |
| 20130201728 | FORWARD CONVERTER WITH MAGNETIC COMPONENT - A forward converter comprises a magnetic component with a transformer and a filter output inductor. Also disclosed is a method for assembly of a forward converter. A first and a second U/UR core are arranged to form an O-core. Windings of the transformer are arranged on the O-core. A bobbin-less U/UR core is arranged to abut the O-core, and windings of a filter output inductor are arranged directly on a body section of the bobbin-less U/UR core. Alternatively, windings of the transformer are arranged on a first section of an E/ER core, and windings of the filter output inductor are arranged directly on a second, bobbin-less section of the E/ER core. | 2013-08-08 |
| 20130201729 | LOW-VOLUME PROGRAMMABLE-OUTPUT PFC RECTIFIER WITH DYNAMIC EFFICIENCY AND TRANSIENT RESPONSE OPTIMIZATION - The present invention is a system, apparatus and method of a PFC rectifier having a programmable output voltage that does not incur a drastic penalty in the overall size or volume of the device, or a significant degradation in efficiency. The PFC rectifier of the present invention may incorporate a two-stage solution for output voltage regulation. The present invention provides a topology of a small-size/volume PFC rectifier with a variable (i.e. programmable) output voltage and a complementary control method. The two-stage system of the present invention incorporates a smaller and lower cost capacitor than the bulky size and costly energy storage capacitors required in conventional prior art. The present invention also achieves tight output regulation. The two-stage topology of the present invention further achieves on-line efficiency optimization and significantly reduces the volume of the downstream stage over the prior art examples through dynamic adjustment of the downstream stage supply voltage. | 2013-08-08 |
| 20130201730 | Alternating Parallel Fly Back Converter with Alternated Master-Slave Branch Circuits - An alternating parallel flyback converter with alternated master and slave circuit branches is provided. The flyback converter includes a master flyback circuit branch, a slave flyback circuit branch connected with the master flyback circuit branch in parallel, and a controller. The controller controls the operation of each of the flyback circuit branches based on the current and the voltage at the output terminal of the flyback converter. The master flyback circuit branch operates continuously while the slave flyback circuit branch only operates when the output power of the flyback converter is higher than a threshold. The master flyback circuit branch and the slave flyback circuit branch are periodically alternated, and in particular, through zero crossing of the power. With the flyback converter of the present invention, the reliability and the service life of the converter can be improved. | 2013-08-08 |
| 20130201731 | POWER FACTOR CORRECTION DEVICE, AND CONTROLLER AND THD ATTENUATOR USED BY SAME - A power factor correction device, and a controller and a total harmonic distortion (THD) attenuator used by same. The power factor correction device comprises a converter and a controller ( | 2013-08-08 |
| 20130201732 | VARIABLE SPEED DRIVE PROVIDED WITH A SUPERCAPACITOR MODULE - A variable-speed drive including: a DC power supply bus including a positive line and a negative line; a bus capacitor connected between the positive line and the negative line of the DC power supply bus; an inverter module supplied with power by the DC power supply bus and controlled to provide a variable voltage to an electrical load; a first switching branch connected between the positive line and the negative line of the bus and including at least one first electronic switch; and a first module including a braking resistor, or a second module including a mechanism for storing and regenerating electrical energy generated during braking of the electrical load, wherein the first module and the second module are removable and interchangeable. | 2013-08-08 |
| 20130201733 | ISOLATED DYNAMIC CURRENT CONVERTERS - Isolated Dynamic-Current (“Dyna-C”) converters are converters that convert incoming 3-phase AC or DC power to a mix of DC and AC power via an isolation link. In various embodiments, the isolation link is a high-frequency isolation transformer. Isolated Dyna-C converters may provide a high-frequency galvanic isolation and are able to convert three-phase AC power to three-phase AC power, or three-phase AC power to DC and vice versa. The topology is minimal and the costs are low. Isolated Dyna-C converters provide fast current responses and keep the losses low by using a simplified two-stage conversion and providing a magnetizing current that is dynamically controllable and tailored to the load. An isolated Dyna-C converter may synthesize currents at its input or output ports with an arbitrary phase that is relative to the grid or load voltages, thereby enabling a full independent control over the active and reactive power at its ports. | 2013-08-08 |
| 20130201734 | DEVICE FOR SUPPRESSING HIGH-FREQUENCY CURRENTS IN INFEED LINES OF AN INVERTER - A device for suppressing high-frequency currents in infeed lines to an inverter having a common-mode impedance. A magnetic core is configured for inductively coupling the infeed lines, wherein the current load on the common-mode impedance is minimized. A snubber impedance unit is inductively coupled to the common-mode impedance and has a frequency-dependent impedance. | 2013-08-08 |
| 20130201735 | AC-DC CONVERTER WITH ADAPTIVE CURRENT SUPPLY MINIMISING POWER CONSUMPTION - A circuit arrangement with standby mode minimising power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low. | 2013-08-08 |
| 20130201736 | SOLAR INVERTER SYSTEM AND CONTROL METHOD THEREOF - A solar inverter system includes a first inverter, a second inverter, and a controller. The first inverter has a first input terminal, and a first output terminal. The first input terminal is coupled to a solar panel. The second inverter has a second input terminal, and a second output terminal. The second input terminal is coupled to the solar panel. The first output terminal and the second output terminal are parallel with a utility grid. The controller is coupled to the first inverter and the second inverter for controlling the first inverter and the second inverter to output total output power in turn, or controlling the first inverter and the second inverter to output the total output power simultaneously. | 2013-08-08 |
| 20130201737 | OFF-GRID MASTER-SLAVE SOLAR INVERTER SYSTEM AND METHOD THEREOF - A control method of an off-grid master-slave solar inverter system includes powering on the off-grid master-slave solar inverter system; a controller controlling a first inverter and a second inverter to prepare to output pulses corresponding to a first series number and pulses corresponding to a second series number, respectively; only the first inverter outputting a pulse corresponding to a first number of the first series number; and the controller controlling the first inverter to output a first alternating current voltage and the second inverter to output a second alternating current voltage with a frequency of the first alternating current voltage after a first predetermined time. | 2013-08-08 |
| 20130201738 | POWER FACTOR CONTROL OF A CYCLO-CONVERTER - A three-phase resonant cyclo-converter comprising a power control module, wherein the power control module is arranged to develop a plurality of repeating switching periods within a cycle, the power control module further arranged to: control the length of a first switching period in the cycle to adjust the power flow, and control the relative length of two or more further switching periods in the cycle to adjust the power factor, wherein the relative length is controlled based on a cross-product of voltage and current values associated with the further switching periods. | 2013-08-08 |
| 20130201739 | MAGNETIC FLUX CONVERSION DEVICE - Embodiments provide a magnetic flux conversion device (MFCD) that may produce a regulated output signal with a target value (e.g., target voltage and/or target current) from a source signal on a power line. The MFCD may include a secondary stage configured to be inductively coupled with the power line. The source signal may cause a secondary electrical signal to flow in the secondary stage. A regulator module may be coupled to the secondary stage and configured to produce the output signal with the target value across output nodes by sensing the output signal and shunting the secondary stage if a value of the output signal is above the target value. | 2013-08-08 |
| 20130201740 | MAXIMUM POWER POINT TRACKER, POWER CONVERSION CONTROLLER, POWER CONVERSION DEVICE HAVING INSULATING STRUCTURE, AND METHOD FOR TRACKING MAXIMUM POWER POINT THEREOF - Disclosed are a maximum power point tracker, a power conversion controller, a power conversion device having an insulating structure, and a method for tracking maximum power point. The power conversion device includes: a DC/AC converter including a primary DC chopper unit having a primary switch, a transformer, and an AC/AC conversion unit including a secondary switch; a current detector detecting current from an input stage of the DC/AC converter and providing a detected current value; a voltage detector detecting a system voltage from an output stage of the DC/AC converter; and a power conversion controller generating a primary PWM signal to be provided to the primary DC chopper unit and secondary first and second PWM signals, having the mutually opposing phases, to be provided to the AC/AC conversion unit by using the detected current value and the system voltage. | 2013-08-08 |
| 20130201741 | POWER MODULE FOR CONVERTING DC TO AC - A power module for converting direct current to alternating current comprising a semiconductor switching circuit device, a substrate onto which the switching circuit device is physically and electrically coupled without wirebonds, a plurality of leadframe terminals physically and electrically coupled to the substrate, and a cover including an opening exposing a bottom side of the substrate and including a wall portion oriented generally orthogonally relative to the substrate with at least some of the leadframe terminals projecting outwardly from the wall portion. The leadframe terminals projecting outwardly from the wall portion may include an affixed portion coupled to the substrate and an extending segment lying in a plane above the affixed portion with the extending segment projecting outwardly from the wall portion and the cover encapsulating the affixed portion whereby the extending segment is spaced from a plane defined by the bottom side of the substrate. | 2013-08-08 |
| 20130201742 | VOLTAGE CONVERTING CIRCUIT AND ELECTRONIC DEVICE - A voltage converting circuit includes a plurality of first capacitors that are charged by a power source, a second capacitor, connected in parallel to the plurality of first capacitors, which is able to be charged to a voltage that is supplied to a load circuit, and a plurality of switching circuits, provided in such a way as to correspond to the plurality of first capacitors, each of which switches states of connection between its corresponding first capacitor and the second capacitor. The first capacitors are sequentially connected to the second capacitor through the corresponding switching circuits as charging voltages of the first capacitors reach a predetermined connection voltage that is higher than a charging voltage of the second capacitor so that the first capacitors are not short-circuited with each other. | 2013-08-08 |
| 20130201743 | Three-Dimensional Memory Comprising an Integrated Intermediate-Circuit Die - The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (V | 2013-08-08 |
| 20130201744 | DMA ARCHITECTURE FOR NAND-TYPE FLASH MEMORY - A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits. | 2013-08-08 |
| 20130201745 | Circuit and System of a Low Density One-Time Programmable Memory - A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2 | 2013-08-08 |
| 20130201746 | CIRCUIT AND SYSTEM FOR TESTING A ONE-TIME PROGRAMMABLE (OTP) MEMORY - Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array. | 2013-08-08 |
| 20130201747 | PERMANENT SOLID STATE MEMORY USING CARBON-BASED OR METALLIC FUSES - A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The material is made of a carbon allotrope such that when current is passed through the carbon allotrope, the carbon is quickly oxidized (burned) leaving a complete gap (void) where the fuse once was. One of the advantages of this method is that the fuse material is fully oxidized in the particular “neck region of the bowtie”, such that there is no material left over from which dendrites can grow. In other embodiments, the data layer is a metal or metal oxide selected from the following metals: Tungsten (W), Rhenium (Rh), Osmium (Os), Iridium (Ir), Molybdenum (Mo), Ruthenium (Ru), Rhodium (Rh), Chromium (Cr), and Manganese (Mn). | 2013-08-08 |
| 20130201748 | Circuit and System of Protective Mechanisms for Programmable Resistive Memories - Programmable resistive memory using at least one diodes as program selectors can be data protected by programming protection bits in a non-volatile protection bit register. The data stored in the protection bit register can be used to enable or disable reading or writing in part or the whole programmable resistive memory. The data stored in the protection bit register can also be used to enable or enable scrambling the addresses to allow accessing the programmable resistive memory array. Similarly, the data stored in the protection bit register can be used to scramble data when writing into and descramble data when reading from the programmable resistive memory. Keys can be provided for address or data scrambling. The non-volatile protection bit register can be built with the kind of cells as the main array and/or integrated with the main array in the programmable resistive memory. | 2013-08-08 |
| 20130201749 | Circuit and System for Using Junction Diode as Program Selector for One-Time Programmable Devices - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. | 2013-08-08 |
| 20130201750 | VARIABLE RESISTANCE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A variable resistance memory device comprises a variable resistance memory cells and a read/write circuit configured to provide a program voltage to the variable resistance memory cell, and further configured to adjust a compliance current flowing through the variable resistance memory cell in successive loops of a program operation. | 2013-08-08 |
| 20130201751 | MULTI-PORT MEMORY BASED ON DRAM CORE - A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports. | 2013-08-08 |
| 20130201752 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device in which stored data can be retained even when power is not supplied, and there is no limitation on the number of write cycles. The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, a memory cell connected between the source line and the bit line, a first driver circuit electrically connected to the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line and the source line. The first transistor is formed using a semiconductor material other than an oxide semiconductor. The second transistor is formed using an oxide semiconductor material. | 2013-08-08 |
| 20130201753 | IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM - A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The circuit includes a write disable function to prevent discharge of a global bit line during a write operation. The write disable function disables a NAND gate driving a global pull down device during the write operation preventing the global pull down device from discharging the global bit line. | 2013-08-08 |
| 20130201754 | MRAM WITH CURRENT-BASED SELF-REFERENCED READ OPERATIONS - A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element. | 2013-08-08 |
| 20130201755 | MTJ CELL FOR AN MRAM DEVICE AND A MANUFACTURING METHOD THEREOF - An MTJ cell includes a first metal layer elongated in the X-direction; a second metal layer separated from the first metal layer and elongated in the Y-direction; a magnetic tunnel junction (MTJ) interposed between the overlapping parts of the first and second metal layers and having extended parts not covered by the second metal layer, the MTJ including a pinned layer, a barrier layer, and a storage layer sequentially laminated; and a yoke spanning across the second metal layer, with both ends in the X-direction contacting the top surface of the extended parts of the storage layer not covered by the second metal layer, either directly or through an insulator. The planar shapes of the MTJ and the yoke possess a quantum easy axis in the X-direction and Y-direction, respectively. The storage layer at its extended parts possesses a relaxed coupling with the yoke that essentially achieves continuity of flux return directly or indirectly through a nonmagnetic insulating layer, while maintaining a quantum easy axis orthogonal to that of the yoke. The YZ cross-sectional area of the yoke is greater than the YZ cross-sectional area of the storage layer. | 2013-08-08 |
| 20130201756 | Self-Referenced MRAM Element with Linear Sensing Signal - The present disclosure concerns a self-referenced MRAM element, comprising a magnetic tunnel junction having a magnetoresistance, comprising: a storage layer having a storage magnetization that is pinned along a first direction when the magnetic tunnel junction is at a low temperature threshold; a sense layer having a sense magnetization; and a tunnel barrier layer included between the storage layer and the sense layer; and an aligning device arranged for providing the sense magnetization with a magnetic anisotropy along a second direction that is substantially perpendicular to the first direction such that the sense magnetization is adjusted about the second direction; the aligning device being further arranged such that, when a first read magnetic field is provided, a resistance variation range of the magnetic tunnel junction is at least about 20% of the magnetoresistance. The self-referenced MRAM cell can be read with an increased reliability and has reducing power consumption. | 2013-08-08 |
| 20130201757 | MULTI-FREE LAYER MTJ AND MULTI-TERMINAL READ CIRCUIT WITH CONCURRENT AND DIFFERENTIAL SENSING - A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer. | 2013-08-08 |
| 20130201758 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings. | 2013-08-08 |
| 20130201759 | COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 2013-08-08 |
| 20130201760 | Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling. | 2013-08-08 |
| 20130201761 | SENSE AMPLIFIER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled. | 2013-08-08 |
| 20130201762 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program voltage, to a first group of nonselective word lines adjacent to a selective word line. The control circuit is further configured to apply a second write pass voltage, which is higher than the first write pass voltage, to a second group of second nonselective word lines, the second group not including the word lines of the first group. | 2013-08-08 |
| 20130201763 | METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY - A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. | 2013-08-08 |
| 20130201764 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described. | 2013-08-08 |
| 20130201765 | POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal. | 2013-08-08 |
| 20130201766 | Volatile Memory with a Decreased Consumption and an Improved Storage Capacity - A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines. | 2013-08-08 |
| 20130201767 | SEMICONDUCTOR MEMORY APPARATUS, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME - A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled. | 2013-08-08 |
| 20130201768 | INTERNAL VOLTAGE GENERATING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF GENERATING INTERNAL VOLTAGE - An internal voltage generating circuit and a semiconductor memory device including the internal voltage generating circuit are disclosed. The internal voltage generating circuit includes a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit. The first voltage generating circuit stabilizes a first external supply voltage to generate a first internal voltage. The second voltage generating circuit stabilizes the first external supply voltage and a second external supply voltage to generate a second internal voltage having a voltage level higher than the first internal voltage. The third voltage generating circuit stabilizes the second internal voltage to generate a third internal voltage having a voltage level lower than the second internal voltage. Accordingly, the semiconductor memory device may be insensitive to a change in an external supply voltage and have small power consumption. | 2013-08-08 |
| 20130201769 | NONVOLATILE MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME - A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller. | 2013-08-08 |
| 20130201770 | MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION - Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. | 2013-08-08 |
| 20130201771 | Volatile Memory with a Decreased Consumption - A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation. | 2013-08-08 |
| 20130201772 | LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD - A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier ( | 2013-08-08 |
| 20130201773 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes an operation control unit, a reference voltage generating unit, and a sensing unit. The operation control unit is configured to select a unit cell from unit cells to perform reading and writing operations. The reference voltage generating unit is configured to voltage-divide a read voltage using series-connected resistors and generate a reference voltage based on the voltage-divided read voltage. The sensing unit is configured to compare a size of a voltage through an e-fuse of the selected unit cell based on the read voltage with the reference voltage, and sense data of the e-fuse of the selected unit cell. The nonvolatile memory device also includes a read current supply unit configured to output the read voltage to the unit cells during a reading operation of the nonvolatile memory device. | 2013-08-08 |
| 20130201774 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM - A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data. | 2013-08-08 |
| 20130201775 | SINGLE-STROBE OPERATION OF MEMORY DEVICES - An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation. | 2013-08-08 |
| 20130201776 | BUILT-IN TEST CIRCUIT AND METHOD - A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type. | 2013-08-08 |
| 20130201777 | REFRESH CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address. | 2013-08-08 |
| 20130201778 | SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS - A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device. | 2013-08-08 |
| 20130201779 | ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM - The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal. | 2013-08-08 |
| 20130201780 | CENTRIFUGAL CONCRETE MIXER - A centrifugal concrete mixer includes a base frame, a mixing drum provided on the base frame, a transmission means and two stirring pieces. The transmission means has a power device driving a transmission shaft to rotate at a speed of 60 rpm to 600 rpm. One end of the transmission shaft penetrates into the mixing drum. A waterproof unit is provided between the transmission shaft and the mixing drum. The stirring pieces are assembled on the transmission shaft in the mixing drum. The stirring piece is formed into a plate. An outer surface of each stirring piece relative to its rotating direction is formed into an inclined surface. The outer end of each stirring piece is provided with an auxiliary stirring portion to face the inner surface of the mixing drum. The rotation of the stirring piece generates a centrifugal force to stir the concrete containing gravels. | 2013-08-08 |
| 20130201781 | Acoustic Acceleration of Fluid Mixing in Porous Materials - Apparatus and methods are disclosed for uniformly mixing fluid phases entrained in a porous material. A mixer may have a vessel and at least one porous material held by the vessel. At least one actuator may be acoustically coupled with at least one wall of the vessel for generating a wave. The wave effects mixing of at least two fluids in the porous material. The actuator may be a linear motor actuated with a control signal of predetermined frequency. The actuator may have a number of actuator pairs each including respective first and second actuators at respective first and second sides of the vessel. The actuators may be hinged for reciprocal movement. The actuators may be actuated to form a compression expansion wave to effect fluid motion in the porous material. | 2013-08-08 |
| 20130201782 | Method and Apparatus for Aerating Liquid - A liquid aeration apparatus is a vessel with a neck and an opening that is interconnected to a body. The opening receives a quantity of liquid that is thinned as the liquid is transferred from the neck to the body. The liquid is then collected in the body of the vessel. The body includes at least one tripping mechanism that induces turbulence to the liquid. | 2013-08-08 |
| 20130201783 | DRESSING SHAKER - A dressing shaker includes a container body having a spout. An internal mixing element is carried on an axle for sliding motion up and down the length of the rod, within the container. By shaking or inverting the container, the mixing element travels back and forth along the rod, mixing the dressing. | 2013-08-08 |
| 20130201784 | BATTER SHAKER - A batter shaker includes a container body having a spout. An internal mixing element is carried on an axle or rod for sliding motion up and down the length of the rod, within the container. By shaking or inverting the container, the mixing element travels back and forth along the rod, mixing the batter | 2013-08-08 |
| 20130201785 | EMULSIFICATION DEVICE FOR CONTINUOUSLY PRODUCING EMULSIONS AND/OR DISPERSIONS - The invention relates to an emulsification device for continuously producing emulsions, nano-emulsions, and/or dispersions having a liquid crystalline structure, comprising a) at least one mixing system, b) at least one drive for the stirring element, and c) at least one delivery unit for each component or each component mixture. | 2013-08-08 |
| 20130201786 | Energy-Saving Static Stirring Apparatus For Automatically Stirring A Fluid - An energy-saving static stirring apparatus for automatically stirring a fluid includes a deflector adapted for stationary placement in a container that holds a fluid for boiling. The deflector may include at least one friction contact point for frictionally engaging the container to prevent movement of the deflector. An inner portion of the deflector may be configured for placement proximate to a center of the container. An outer portion of the deflector may be configured for placement proximate to a side of the container. One or more deflector ramps define one or more vent openings to impart lateral movement to heated fluid currents and/or vapor bubbles moving upwardly away from a heat source below the container and to redirect the fluid currents and/or vapor bubbles into a swirling motion that stirs the fluid without movement of the deflector. | 2013-08-08 |
| 20130201787 | Methods, Systems and Devices for Near-Well Fracture Monitoring Using Tomographic Fracture Imaging Techniques - Described herein are various embodiments of methods and corresponding hardware and software configured to permit the vicinity around and/or near a well to be imaged, where the well is being subjected to, or has been subjected to, fracking operations. The methods and corresponding hardware and software permit the generation of images of near-well fractures or faults resulting from the fracking. | 2013-08-08 |
| 20130201788 | METHOD OF SEISMIC SOURCE INDEPENDENT OPERATION - A method of controlling seismic data acquisition may include sending a first message to place a plurality of energy sources into an operating mode; sending a second message to place at least one of plurality of energy sources into a non-operating mode; and sending a third message from at least one energy source to a controller. | 2013-08-08 |
| 20130201789 | METHOD OF SEISMIC VIBRATORY LIMITS CONTROL AT LOW FREQUENCIES - A method of performing a seismic sweep determining a user-defined force at a frequency using user defined inputs; determining a maximum force at the frequency using sweep parameters; and using the maximum force to drive a seismic source if the user-defined force is greater than the maximum force. | 2013-08-08 |
| 20130201790 | METHOD OF DEPLOYMENT, METHOD AND DEVICE FOR SEISMIC PROSPECTING IN AN AQUATIC MEDIUM - A method for seismic prospecting in an aquatic medium using a device having at least one seismic cable provided with sensors and at least one moving seismic source. The method includes the following steps: 1) moving the cable in the water using two drones each placed at one end of the cable and which maintain tension in the cable, the movement of the cable minimizing the deviation of the cable with respect to a desired route in the terrestrial reference frame where the movement of the cable is also being restricted by a maximum track curvature value in the water, and, at the same time; and 2) moving the seismic source in a reference frame connected to the cable, emitting waves via the seismic source, and sensing reflections of the waves by the cable. | 2013-08-08 |
| 20130201791 | METHOD AND SYSTEM FOR DETERMINING SOURCE SIGNATURES AFTER SOURCE GHOST REMOVAL - Seismic data are acquired using a seismic source comprising a plurality of seismic sub-sources disposed in a body of water at a plurality of depths and activated with different time delays. Far-field signatures are determined for the plurality of seismic sub-sources at each of the plurality of depths. A composite ghost-free far-field signature of the seismic source is determined from the far-field signatures for the plurality of seismic sub-sources at each of the plurality of depths and different time delays. A source response is removed from the seismic data using the far-field signatures of the seismic source | 2013-08-08 |
| 20130201792 | METHOD AND APPARATUS FOR PROCESSING SEISMIC DATA - Methods, apparatuses, and systems are disclosed for processing seismic data. In some embodiments, a set of vectorial measurements and a set of corresponding scalar measurements of a seismic wavefield may be obtained at a seismic receiver. An angle of incidence of the seismic wavefield at a first instance of time may be determined by calculating an incidence vector of the seismic wavefield at the seismic receiver at the first instance of time, with the incidence vector derived from a measure of correlation of at least one of the vectorial measurements. A component of a vectorial measurement may be corrected with the determined angle of incidence of the seismic wavefield at the first instance of time, and the corrected component may be combined with a scalar measurement that corresponds to the first instance of time. | 2013-08-08 |
| 20130201793 | Vibrator source system for improved seismic imaging - A system for modeling the output signal emanating from a seismic vibrator based on a superposed collection of damped harmonic oscillators, whose critical parameters are determined from signals from accelerometers on the baseplate and reaction mass portions of the vibrator together with the input force (pilot sweep). This modeled output signal is a more accurate representation of the seismic signal that propagates into the earth and may be used in the cross-correlation process to significantly enhance the accuracy of the recorded seismic data. Additionally, by modeling the output signal on a shot by shot basis, any changes in the ground's surface can be monitored and/or documented, and, if required, the sweep parameters can be varied shot by shot for optimum performance. | 2013-08-08 |
| 20130201794 | SYSTEM, METHOD, AND COMPUTER-READABLE MEDIUM FOR INTERACTIVE IDENTIFICATION OF SUBSURFACE REGIONS - A computer-implemented method, apparatus, and system for interactive identification of subsurface regions that represent lithology and/or fluid anomalies that indicate the presence of hydrocarbons may be provided. Since the introduction of AvO classes, AvO interpretation has largely been quantitatively driven through polygonal selection of non-background trend values from cross plots of seismic and/or derived seismic attributes such as intercept and slope. Embodiments of the invention may provide a system and/or method which allows qualitative and quantitative, interactive, visual observation of AvO and petrophysical classes and projections simultaneously, through, for example, co-blending based an intuitive parameterization of gradational color tables with varying opaqueness along axes representing respectively background trend and anomaly, or petrophysical variables. | 2013-08-08 |
| 20130201795 | FRACTURE IDENTIFICATION FROM AZIMUTHAL MIGRATED SEISMIC DATA - A method is described for identifying anisotropic regions in unconventional hydrocarbon reservoirs, such as in shale formations. Anisotropy can be indicative of a zone of fracturing, which may represent a “sweet spot” for drilling a productive well. Seismic amplitude data from receivers is recorded along two orthogonal lines radiating from a seismic source. After time-migration, the equations for each orthogonal direction may be summed to obtain values for A and (B | 2013-08-08 |
| 20130201796 | ELECTRONIC APPARATUS - An electronic apparatus includes a substrate and an oscillation device ( | 2013-08-08 |
| 20130201797 | kF. - The invention disclosed herein relates to methods and means for locating entities, places and/or things. Various embodiments of the methods and means of the invention may be performed by and/or implemented in hardware, in software, by one or more entities, and/or by some combination of hardware, software and/or one or more entities. | 2013-08-08 |
| 20130201798 | IMAGING TRANSDUCER ARRAY - An imaging transducer ( | 2013-08-08 |
| 20130201799 | SWEEP DESIGN FOR SEISMIC SOURCES - A system and method are described herein for generating a frequency sweep signal set for use in seismic data gathering. Low frequency sweep rate modifications are combined to compensate for vibrator limitations and vibrator far-field responses with high frequency sweep rate modifications to compensate for absorption, and then the frequency sweep signal set is generated based on the combination of high and low frequency sweep rate modifications. | 2013-08-08 |
| 20130201800 | CONTROLLING MOBILE DEVICE BASED ON SOUND IDENTIFICATION - A method and apparatus for performing a function in a mobile device are disclosed. A media sound from a sound output device external to the mobile device is captured and a sound feature is extracted from the captured media sound. A function to be performed in the mobile device is determined by identifying at least one reference sound feature in a set of reference sound features based on the extracted sound feature, each reference sound feature in the set of reference sound features being associated with at least one of a plurality of media sounds and at least one of a plurality of functions. Further, the determined function is performed in the mobile device. | 2013-08-08 |
| 20130201801 | TWO-DIRECTIONAL DATE CORRECTOR MECHANISM FOR A DATE MECHANISM, DATE MECHANISM, TIMEPIECE - A two-directional date corrector mechanism controlled by a pull-out piece for a date mechanism. The mechanism includes a 24 hour wheel, a date updating finger pivoting integrally therewith, a date driving star-wheel, and a corrector star-wheel meshing therewith and located between the date driving star-wheel and the finger and configured to be uncouplable from the finger under action of an uncoupling mechanism controlled by the pull-out piece, the uncoupling mechanism having a coupling position where the corrector star-wheel meshes with the finger, and an uncoupling position where it is released from the finger to allow the date to be corrected. A date mechanism can include such a date corrector mechanism and a timepiece can include such a date corrector mechanism. | 2013-08-08 |
| 20130201802 | DEVICE FOR DETECTING AND SYNCHRONISING THE POSITION OF A WHEEL OF A TIMEPIECE MECHANISM - Device for detecting and synchronising the position of at least one first wheel ( | 2013-08-08 |
| 20130201803 | WATCH WITH TACTILE ZONES OF CAPACITIVE TYPE COMPRISING A BATTERY HATCH CLOSED BY AN ELECTRICALLY CONDUCTING COVER - A wristwatch with capacitive touch zones including a case made of a non electrically conductive material, the case including a housing in which a battery is housed and which is closed by an electrically conductive battery cover. The electrically conductive battery cover is mounted on the watch case with interposition of an electrically conductive sealing gasket between the battery cover and the battery. | 2013-08-08 |
| 20130201804 | WATCH CASE WITH ORIENTABLE AND INDEXED BEZEL - A watch case ( | 2013-08-08 |
| 20130201805 | Active Media for Heat Assisted Magnetic Recording (HAMR) - An apparatus includes a magnetic recording layer and a thermally active material adjacent to and/or embedded in the magnetic recording layer, wherein the thermally active material has a thermal property that changes when the temperature of the thermally active material changes, or undergoes a phase transition in a predetermined temperature range, to reduce a peak temperature or increase a thermal gradient of a heated portion of the magnetic recording layer. | 2013-08-08 |
| 20130201806 | INFORMATION RECORDING MEDIUM, INFORMATION RECORDING APPARATUS AND METHOD, AND INFORMATION REPRODUCING APPARATUS AND METHOD - An information recording medium adopting a zone CAV method is provided with: a guide layer in which tracks are formed in advance; and a plurality of recording layers laminated on the guide layer. On the tracks, a plurality of guide areas, each of which has a physical structure for carrying guide information for guidance, are arranged discretely at arrangement intervals of predetermined distance or less which is set in advance in a track direction and are shifted between a plurality of tracks throughout the plurality of tracks which are adjacent to each other in a radial direction. On the tracks, moreover, a plurality of specific areas, each of which has a predetermined pattern, are respectively arranged in a same phase from an inner circumference to an outer circumference in the radial direction such that the predetermined pattern can be detected in a state in which tracking servo is open. | 2013-08-08 |
| 20130201807 | METHOD AND DEVICE TO IMPROVE START-UP PERFORMANCE OF A MULTI-LAYER OPTICAL DISC - A method comprising recording data related to a start-up procedure on at least one of a plurality of recording layers disposed on an optical record carrier for reading back the recorded data during subsequent start-ups, the selection of the at least one recording layer based on properties of the at least one recording layer is disclosed. The technique reduces the optical record carrier start-up time and is useful for DVD, HD-DVD and BD recorders and/or players. | 2013-08-08 |
| 20130201808 | OPTICAL INFORMATION RECORDING/REPRODUCING APPARATUS, OPTICAL INFORMATION REPRODUCING APPARATUS, OPTICAL INFORMATION RECORDING/REPRODUCING METHOD AND OPTICAL INFORMATION REPRODUCING METHOD - An optical-information reproducing apparatus for reproducing information from an optical-information storage medium where an interference pattern between a signal beam and a reference beam is recorded as page data by being angle-multiplexed, the optical-information reproducing apparatus, including a light-source for emitting a light beam, an optical element for splitting the light beam into the reference beam and the signal beam, an angle-controlling element for controlling the reference beam into a direction which is perpendicular to the angle-multiplexed direction, the reference beam being guided to enter the optical-information storage medium, an optical detector for detecting a reproduced image which is reproduced by the reference beam, and a position-controlling circuit for controlling position relationship between the reference beam and the optical-information storage medium. | 2013-08-08 |
| 20130201809 | RECORDING/REPRODUCING SYSTEM AND SERVER - If a fault, or deterioration in read-out quality, is detected during recording processing with respect to a first recording face, a duplication is made, with respect to the recorded data on the second recording face of the same recording medium, on a separate recording medium. | 2013-08-08 |
| 20130201810 | LIBRARY DEVICE - (JA) The present invention makes it possible, in a library device capable of containing magazines in a two-tier manner, to simultaneously eject two magazines by a simple mechanism with a reduced number of constituent parts. | 2013-08-08 |
| 20130201811 | SPINDLE MOTOR HAVING MAGNETIC CIRCUIT FOR STATOR AND ROTOR MAGNET, AND STORAGE DISK DRIVE HAVING THE SAME - A spindle motor includes a base portion; a stator arranged above the base portion; a rotor hub including a cover portion positioned above the stator, and a side wall portion arranged to extend downward from an outer edge of the cover portion; a rotor magnet positioned radially outward of the stator, and fixed to an inner circumferential surface of the side wall portion of the rotor hub; and a bearing mechanism arranged to support the rotor hub and the rotor magnet to be rotatable. A height of the rotor magnet as measured in an axial direction is preferably in a range of about 2 mm to about 3 mm (both inclusive), and a height of a stator core of the stator as measured in the axial direction is preferably in a range of about 50% to about 75% (both inclusive) of the height of the rotor magnet. | 2013-08-08 |
| 20130201812 | SPINDLE MOTOR AND DISK DRIVE APPARATUS - A spindle motor includes a flat stator, a rotor magnet arranged above the stator, and a magnetic portion made of a ferromagnetic material. The magnetic portion is positioned lower than the stator and the magnetic portion are axially overlapped with coils. A magnetic attraction force is generated between the magnetic portion and the rotor magnet. Since the magnetic portion is positioned lower than the stator, it is possible to cause magnetic fluxes to efficiently flow between the rotor magnet and the stator. Further, the stator includes a protrusion protruded radially outward beyond an outer circumferential portion of a rotor hub. Accordingly, in a plan view, the stator is positioned radially outward of the rotor hub. | 2013-08-08 |
| 20130201813 | RECORDABLE OPTICAL DISC, RECORDING DEVICE, AND RECORDING METHOD - The present invention is to realize a proper inner zone layout in a quadruple-layer disk. | 2013-08-08 |
| 20130201814 | Methods and Apparatus for Signal Conditioning in OFDMA Systems - Methods and systems for conditioning an orthogonal frequency division multiplex (OFDM) signal are disclosed. The OFDM signal may be conditioned prior to transmission by a transmitter in an orthogonal frequency division multiple access (OFDMA) system operating on a channel with a plurality of subcarriers grouped into subchannels. The OFDM signal may be clipped based on a desired peak-to-average-power ratio (PAPR) to produce a clipped-off portion of the OFDM signal. The clipped-off portion of the OFDM signal may be transformed into the frequency domain to produce a frequency-domain signal. An in-band spectral shaping mask may be applied to subcarriers or subchannels of the frequency-domain signal within the channel to control the levels of distortion on the individual subcarriers or subchannels. The shaped frequency-domain signal is transformed into the time domain to produce a time-domain signal. A conditioned signal is produced for transmission by subtracting the time-domain signal from the OFDM signal. | 2013-08-08 |
| 20130201815 | BUFFER SPACE ALLOCATION METHOD AND DEVICE - Disclosed are a buffer space allocation method and a device. The solution of the present invention enables the division of the buffer space in the buffer resource of a terminal equipment according to the currently configured carrier aggregation mode of the terminal equipment, so that the number of buffer spaces in the buffer can be adjusted according to the number of aggregated carriers, thereby improving the utilization rate of the buffer resource. The method is simple, easy to implement, and applicable to both FDD and TDD systems. | 2013-08-08 |
| 20130201816 | METHOD AND APPARATUS FOR E-TFC SELECTION FOR UPLINK MIMO COMMUNICATION - One or more scheduling grants may be received from a Node B related to a plurality of uplink MIMO streams. A determination may be made as to a primary transport power and a primary transport block size for a primary stream. A secondary transmit power and a secondary transport block size for a secondary stream may also be determined. | 2013-08-08 |
| 20130201817 | FAULT DETECTION AND MITIGATION FOR IN-VEHICLE LAN NETWORK MANAGEMENT - A method of detecting and mitigating an unintended active state of an in-vehicle communication network. The in-vehicle communication network includes a plurality of electronic control units (ECUs) communicating over a controller area network bus system. Each ECU includes both transmitting and receiving capabilities, and is configured with a communication protocol that provides guidelines for exchanging messages with other ECUs within the communication system. Each ECU enters a communication kernel active state for communicating on the bus. Virtual networks within the communication system are identified. Each virtual network includes a collection of signals involving respective ECUs whose transmission and reception are started and stopped collectively as a unit. Each respective virtual network that is active by fault is detected. Each faulty active virtual network is deactivated. | 2013-08-08 |
| 20130201818 | METHOD FOR MANAGING A DEGRADED MODE OF A CELL IN A RADIOCOMMUNICATION NETWORK - A method for managing a degraded mode of a cell of a cellular network including a site controller for controlling, via a packet network, transmitters distributed over various sites of the cell such that transmitters implementing the same pair of frequencies over different sites form a channel which, in dynamic mode, is allocated dynamically to any communication between terminals of the cell, the channel including a master transmitter selected by the controller. The method includes, in each master transmitter on detection of a failure of the controller: switching in degraded mode of the master transmitter, by associating with the channel a predefined communication known to the terminals, and transmission from the master transmitter, via the network, of a control message informing a control console connected to the packet network of the implementation of the degraded mode so that the console participates in a communication underway in the channel. | 2013-08-08 |
| 20130201819 | SWITCH REDUNDANCY IN SYSTEMS WITH DUAL-STAR BACKPLANES - Backplane redundancy is provided for a system including multiple nodes that communicate packets through first and second switches. Assuming that the first switch is initially assigned to an active state and the second switch to a standby state, the nodes communicate the data packets through physically enabled first backplane links to the first switch. The nodes physically enable second backplane links that are in a condition to communicate the data packets to the second switch. A messageless failover process is initiated by temporarily disabling, at the first switch, the first backplane links between the first switch and the nodes. In response to the nodes detecting the disabled first backplane links to the first switch, the nodes reconfigure themselves to communicate the data packets through the second backplane links to the second switch and to stop communicating the packets through the first backplane links to the first switch. | 2013-08-08 |
| 20130201820 | TRIGGERING A REDUNDANT ROUTER MASTER/BACKUP STATUS CHANGE BASED ON SWITCH CONNECTIVITY - Systems and methods according to the exemplary embodiments enable improved switch or link failure handling. A redundant router master/backup status change may be triggered based on switch connectivity. According to an exemplary embodiment, a method is provided. The method includes monitoring a connectivity of a network, detecting a failure, and based on the detected failure, changing the redundant router master/backup status of both a first router and at least a second of router. | 2013-08-08 |
| 20130201821 | COMMUNICATION SYSTEM, CONTROL DEVICE, NODE, PROCESSING RULE SETTING METHOD AND PROGRAM - A communication system includes a plurality of nodes and a control device. Each node includes a packet processor that processes a packet in accordance with a processing rule when the packet is received. The processing rule correlates the processing applied to the packet with a matching rule that identifies the packet the processing is to be applied to. The control device calculates a packet forwarding path in response to a request for setting processing rules from any node, sets processing rules that implement the packet forwarding path on the node on the packet forwarding path and records the processing rules in a manner coordinated with one another. The control device inquires at the node on the packet forwarding path about state of setting of processing rule and, upon detecting failure in the processing rule set in at least one node, executes rollback operation on the correlated processing rules set in other node. | 2013-08-08 |
| 20130201822 | COMPUTER NETWORK METHOD AND DEVICE USING LINK AGGREGATION - A method and device of link aggregation in computer networking, wherein data originally scheduled for forwarding by a scheduled data port are diverted for forwarding by a backup data port assigned to the scheduled data port upon detection that the scheduled data port is connected to a data link which is not capable of data traffic even though the data port is still a selected port. | 2013-08-08 |
