| 32nd week of 2013 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20130200422 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate, an organic light emitting diode provided on the substrate and including a first electrode, an organic emission layer, and a second electrode, a packed layer on the organic light emitting diode, and a protective layer on the packed layer, the protective layer including at least one of a graphene oxide and a graphene nitride. | 2013-08-08 |
| 20130200423 | OPTOELECTRONIC SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF - The present application provides an optoelectronic semiconductor device, comprising: a substrate; an optoelectronic system on the substrate; a barrier layer on the optoelectronic system, wherein the barrier layer thickness is not smaller than 10 angstroms; and an electrode on the barrier layer. | 2013-08-08 |
| 20130200424 | COMPOUND SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - According to the present invention, a method for manufacturing a compound semiconductor comprises: forming a graphene-derived material layer on either a first selected substrate or a first selected compound semiconductor layer; forming a second compound semiconductor layer of at least one layer on at least said graphene-derived material layer, and changing the graphene-derived material layer so as to separate said second compound semiconductor layer of at least one layer. | 2013-08-08 |
| 20130200425 | PHOSPHOR-CONTAINING ADHESIVE SILICONE COMPOSITION SHEET, AND METHOD OF PRODUCING LIGHT-EMITTING DEVICE USING SAME - An adhesive silicone composition sheet, in which a phosphor is dispersed uniformly and in which the dispersion state of the phosphor is stable over time, which is a solid or semisolid in an uncured state at room temperature and is therefore easy to handle, and which can easily form a silicone resin layer on the surface of an LED chip using conventional assembly apparatus. The adhesive silicone composition sheet is formed from a heat-curable silicone resin composition, which comprises: (1) an organopolysiloxane in which at least 90% of the organic groups bonded to silicon atoms are methyl groups, (2) a curing agent, and (3) a phosphor, and which exists in a plastic solid or semisolid state at normal temperature. | 2013-08-08 |
| 20130200426 | HYBRID SILICONE COMPOSITION FOR LIGHT EMITTING DEVICE - A silicon-based curable composition providing improved transparency, mechanical strength and resistance against heat and photo-degradation comprises at least one organopolysiloxane represented by the composition formula (1): | 2013-08-08 |
| 20130200427 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution. | 2013-08-08 |
| 20130200428 | PROGRAMMABLE SCR FOR ESD PROTECTION - A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal ( | 2013-08-08 |
| 20130200429 | EPITAXY LEVEL PACKAGING - A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate. | 2013-08-08 |
| 20130200430 | ELECTRONIC DEVICE WITH MIRCOFILM ANTENNA AND RELATED METHODS - An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and the electrically conductive feed line, a second substrate on the insulating layer, and an antenna on the second substrate and having nanofilm layers stacked on the second substrate. The antenna is coupled to the feed line through an aperture. | 2013-08-08 |
| 20130200431 | Selective Area Growth of Germanium and Silicon-Germanium in Silicon Waveguides for On-chip Optical Interconnect Applications - A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a spacer layer which covers the sidewalls. Undesirable exposure of the top corners of the growth windows is prevented by undercutting the growth window prior to deposition of the dielectric spacer layer. The effectiveness of this process has been demonstrated by selective-area growth of Ge and Ge/SiGe quantum wells on a silicon substrate. Integration of active optoelectronic devices with waveguide layers via end-coupling through the dielectric spacer layer can be reliably accomplished in this manner. | 2013-08-08 |
| 20130200432 | SEMICONDUCTOR COMPONENT, SUBSTRATE AND METHOD FOR PRODUCING A SEMICONDUCTOR LAYER SEQUENCE - A semiconductor component includes a semiconductor body based on a nitride compound semiconductor material, and a substrate on which the semiconductor body is arranged, wherein impurities are formed in the substrate in a targeted manner. | 2013-08-08 |
| 20130200433 | STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES - A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device. | 2013-08-08 |
| 20130200434 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 2013-08-08 |
| 20130200435 | SEMICONDUCTOR DEVICES WITH FIELD PLATES - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer. | 2013-08-08 |
| 20130200436 | Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends - A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES. | 2013-08-08 |
| 20130200437 | METHOD OF FORMING NANOGAP PATTERN, BIOSENSOR HAVING THE NANOGAP PATTERN, AND METHOD OF MANUFACTURING THE BIOSENSOR - Provided is a method of forming a nanogap pattern of a biosensor. First, an oxide layer is formed on a substrate and a first nitride layer is formed on the oxide layer. The first nitride layer is partially etched to form a first nitride layer pattern having a first gap that gradually narrows from a top portion to a bottom portion thereof and exposes the oxide layer. A second nitride layer is formed along the first nitride layer and along sidewalls and a bottom surface of the first gap. The second nitride layer is etched to form a second nitride layer pattern having a second gap narrower than the first gap on the sidewalls of the first gap. The oxide layer is etched by using the second nitride layer pattern as an etching mask to form an oxide layer pattern having a third gap, and thus, the nanogap pattern is completed. | 2013-08-08 |
| 20130200438 | SYSTEMS AND METHODS FOR SIGNAL AMPLIFICATION WITH A DUAL-GATE BIO FIELD EFFECT TRANSISTOR - The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. An amplification factor of the BioFET device may be provided by a difference in capacitances associated with the gate structure on the first surface and with the interface layer formed on the second surface. | 2013-08-08 |
| 20130200439 | MICRO-ELECTROMECHANICAL SEMICONDUCTOR COMPONENT - A micro-electromechanical semiconductor component is provided with a semiconductor substrate, a reversibly deformable bending element made of semiconductor material, and at least one transistor that is sensitive to mechanical stresses. The transistor is designed as an integrated component in the bending element. | 2013-08-08 |
| 20130200440 | HIGH-K HETEROSTRUCTURE - A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al | 2013-08-08 |
| 20130200441 | INTEGRATED CIRCUIT CONTACT STRUCTURE AND METHOD - An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact. | 2013-08-08 |
| 20130200442 | SALICIDE FORMATION USING A CAP LAYER - A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack. | 2013-08-08 |
| 20130200443 | Interface Engineering to Optimize Metal-III-V Contacts - Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact. | 2013-08-08 |
| 20130200444 | SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR WITH CARBON-CONTAINING INSULATION LAYER AND METHOD FOR FABRICATING THE SAME - A Schottky barrier field effect transistor with a carbon-containing insulation layer and a method for fabricating the same are provided. The Schottky barrier field effect transistor comprises: a substrate; a gate stack formed on the substrate; a metal source and a metal drain formed in the substrate on both sides of the gate stack respectively; and the carbon-containing insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively, in which a material of the carbon-containing insulation layer is organic molecular chains containing an alkyl group. | 2013-08-08 |
| 20130200445 | HVMOS TRANSISTOR STRUCTURE HAVING OFFSET DISTANCE AND METHOD FOR FABRICATING THE SAME - An HVMOS transistor structure includes: a first ion well of a first conductivity type and a second ion well of a second conductivity type different from the first conductivity type formed over a substrate, wherein the first ion well and the second ion well have a junction at their interface; a gate overlying the first ion well and the second ion well; a drain region of the first conductivity type, in the first ion well, spaced apart from a first sidewall of the gate by an offset distance; and a source region of the first conductivity type in the second ion well. In addition, a method for fabricating the HVMOS transistor structure described above is also provided. | 2013-08-08 |
| 20130200446 | SPIN-BASED DEVICE - A spin-based device comprises a channel, first and second electrodes configured, in response to a bias configuration, to generate an electric field along the channel, and a spin injector arranged to inject spin into the channel at a point between the first and second electrodes. The device may further comprise a spin current detector and/or a spin accumulation detector arranged at different points(s) along the channel. | 2013-08-08 |
| 20130200447 | Adjustable Meander Line Resistor - An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor formed on a second doped region of the transistor and a connector coupled between the first resistor and the second resistor. A control circuit is employed to control the on and off of the transistor so as to achieve the adjustable meander line resistor. | 2013-08-08 |
| 20130200448 | Meander Line Resistor Structure - A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor. | 2013-08-08 |
| 20130200449 | FINFET STRUCTURE WITH NOVEL EDGE FINS - A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor. | 2013-08-08 |
| 20130200450 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction. | 2013-08-08 |
| 20130200451 | NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT - A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region. | 2013-08-08 |
| 20130200452 | LATERAL DOUBLE-DIFFUSED MOSFET - A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. | 2013-08-08 |
| 20130200453 | SEMICONDUCTOR DEVICES INCLUDING BIPOLAR TRANSISTORS, CMOS TRANSISTORS AND DMOS TRANSISTORS, AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices having a bipolar transistor, a CMOS transistor, a drain extension MOS transistor and a double diffused MOS transistor are provided. The semiconductor device includes a semiconductor substrate including a logic region in which a logic device is formed and a high voltage region in which a high power device is formed, trenches in the semiconductor substrate, isolation layers in respective ones of the trenches, and at least one field insulation layer disposed at a surface of the semiconductor substrate in the high voltage region. Related methods are also provided. | 2013-08-08 |
| 20130200454 | REPLACEMENT-GATE FINFET STRUCTURE AND PROCESS - A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region. | 2013-08-08 |
| 20130200455 | DISLOCATION SMT FOR FINFET DEVICE - A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer. | 2013-08-08 |
| 20130200456 | Semiconductor Substrate, Integrated Circuit Having the Semiconductor Substrate, and Methods of Manufacturing the Same - The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed. | 2013-08-08 |
| 20130200457 | STRONGLY CORRELATED OXIDE FIELD EFFECT ELEMENT - Provided is a strongly correlated oxide field effect element demonstrating a phase transition and a switching function induced by electrical means. The strongly correlated oxide field effect element is a strongly correlated oxide field effect element | 2013-08-08 |
| 20130200458 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes. | 2013-08-08 |
| 20130200459 | STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES - A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device. | 2013-08-08 |
| 20130200460 | ESD Protection Circuit - An electrostatic discharge (ESD) protection circuit is provided. A first NMOS transistor is coupled to a power line. A second NMOS transistor is coupled between the first transistor and a ground. A detection unit provides a detection signal when an ESD event occurs at the power line. A trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors. | 2013-08-08 |
| 20130200461 | Semiconductor Device and Method of Forming the Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL. | 2013-08-08 |
| 20130200462 | Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level - A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES. | 2013-08-08 |
| 20130200463 | Cross-Coupled Transistor Circuit Defined on Two Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 2013-08-08 |
| 20130200464 | Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 2013-08-08 |
| 20130200465 | Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with At Least Two Non-Inner Positioned Gate Contacts - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes two conductive contacting structures at a location not over an inner non-diffusion region. | 2013-08-08 |
| 20130200466 | INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR - A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor. | 2013-08-08 |
| 20130200467 | DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE METAL DEVICES - A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors. | 2013-08-08 |
| 20130200468 | Integration of SMT in Replacement Gate FINFET Process Flow - A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region. | 2013-08-08 |
| 20130200469 | Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks With Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 2013-08-08 |
| 20130200470 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures. | 2013-08-08 |
| 20130200471 | ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD - An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region. | 2013-08-08 |
| 20130200472 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire. | 2013-08-08 |
| 20130200473 | MICROMECHANICAL COMPONENT AND METHOD FOR THE MANUFACTURE OF SAME - A method for manufacturing a micromechanical component is described in which a trench etching process and a sacrificial layer etching process are carried out to form a mass situated movably on a substrate. The movable mass has electrically isolated and mechanically coupled subsections of a functional layer. A micromechanical component having a mass situated movably on a substrate is also described. | 2013-08-08 |
| 20130200474 | Low Frequency CMUT with Vent Holes - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. | 2013-08-08 |
| 20130200475 | MRAM Device and Fabrication Method Thereof - A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device. | 2013-08-08 |
| 20130200476 | Memory Cell with Phonon-Blocking Insulating Layer - An apparatus and associated method for a non-volatile memory cell with a phonon-blocking insulating layer. In accordance with various embodiments, a magnetic stack has a tunnel junction, ferromagnetic free layer, pinned layer, and an insulating layer that is constructed of an electrically and thermally insulative material that blocks phonons while allowing electrical transmission through at least one conductive feature. | 2013-08-08 |
| 20130200477 | SEMICONDUCTOR PHOTOMULTIPLIER DEVICE - According to embodiments of the present invention, a semiconductor photomultiplier device is provided. The semiconductor photomultiplier device includes a substrate having a front side and a back side, a common electrode of a first conductivity type adjacent to the back side, and a cell including an active region of a second conductivity type adjacent to the front side, and a contact region of the second conductivity type adjacent to the front side, the contact region being spaced apart from the active region by a separation region. | 2013-08-08 |
| 20130200478 | SOLID-STATE IMAGING APPARATUS AND MANUFACTURING METHOD THEREOF - A solid-state imaging apparatus and a manufacturing method of a solid-state imaging apparatus are provided. Metal wirings | 2013-08-08 |
| 20130200479 | SOLID-STATE IMAGING DEVICE, METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - There is provided a solid-state imaging device including a pixel array portion in which multiple unit pixels are arranged on a semiconductor substrate, the multiple unit pixels each including a photoelectric conversion portion generating and accumulating a light charge based on a quantity of received light and a charge accumulation portion accumulating the light charge, wherein at least part of an electrode closer to an incidence side on which light enters the unit pixel of the charge accumulation portion, is formed with a metal film functioning as a light blocking film. | 2013-08-08 |
| 20130200480 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes a first structure part, a second structure part, and a third structure part. The first structure part includes a first insulating body and a first photoelectric conversion part. The first photoelectric conversion part is periodically disposed in the first insulating body and selectively absorbs light in the first wavelength band. The second structure part includes a second insulating body and a second photoelectric conversion part. The second photoelectric conversion part is periodically disposed in the second insulating body and selectively absorbs light in the second wavelength band. The third structure part includes a third photoelectric conversion part. The third photoelectric conversion part absorbs light in a third wavelength band. When viewed in the light incidence direction, the first photoelectric conversion part, the second photoelectric conversion part, and the third photoelectric conversion part are disposed in this order. | 2013-08-08 |
| 20130200481 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 2013-08-08 |
| 20130200482 | SHALLOW TRENCH ISOLATION FOR DEVICE INCLUDING DEEP TRENCH CAPACITORS - A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less. | 2013-08-08 |
| 20130200483 | FIN STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a fin structure is provided. The method includes forming a hard mask material layer on a substrate, and then patterning the hard mask material layer to form a first hard mask layer. Thereafter, a portion of the substrate is removed to form two trenches, wherein a remaining substrate forms a fin between the trenches. Afterwards, an insulating layer is formed in each trench, wherein the insulating layers expose an upper portion of the fin. Further, the upper portion of the fin is trimmed, so that the trimmed upper portion is narrower than a lower portion of the fin, and a fin structure having an inverse T shape is formed. | 2013-08-08 |
| 20130200484 | PROCESS FOR MANUFACTURING A WAFER BY ANNEALING OF BURIED CHANNELS - A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures. | 2013-08-08 |
| 20130200485 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer. | 2013-08-08 |
| 20130200486 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER - Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess. | 2013-08-08 |
| 20130200487 | PATTERN STRUCTURE AND METHOD OF FORMING THE SAME - A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern. | 2013-08-08 |
| 20130200488 | STRUCTURES AND TECHNIQUES FOR USING MESH-STRUCTURE DIODES FOR ELECTRO-STATIC DISCHARGE (ESD) PROTECTION - An Electro-Static Discharge (ESD) protection using at least one I/O pad with at least one mesh structure of diodes provided on a semiconductor body is disclosed. The mesh structure has a plurality of cells. At least one cell can have a first type of implant surrounded by at least one cell with a second type of implant in at least one side of the cell, and at least cell can have a second type of implant surrounded by at least one cell with a first type of implant in at least one side of the cell. The two types of implant regions can be separated with a gap. A silicide block layer (SBL) can cover the gap and overlap into the both implant regions to construct P/N junctions on the polysilicon or active-region body on an insulated substrate. Alternatively, the two types of implant regions can be isolated by LOCOS, STI, dummy gate, or SBL on silicon substrate. The regions with the first and the second type of implants can be coupled to serve as the first and second terminal of a diode, respectively. The mesh structure can have a first terminal coupled to the I/O pad and a first terminal coupled to a first supply voltage. | 2013-08-08 |
| 20130200489 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors. | 2013-08-08 |
| 20130200490 | Capacitor Structure and Method of Forming the Same - Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N | 2013-08-08 |
| 20130200491 | METHOD OF MANUFACTURING CAPACITOR, CAPACITOR AND METHOD OF FORMING DIELECTRIC FILM FOR USE IN CAPACITOR - Provided are a method of manufacturing a capacitor capable of achieving a high dielectric constant property and a low leakage current, a capacitor, and a method of forming a dielectric film used in the capacitor. The capacitor is fabricated by forming a lower electrode layer on a substrate; forming a first TiO | 2013-08-08 |
| 20130200492 | OPTO-ELECTRONIC DEVICE - The present invention provides a current blocking structure for electronic devices, preferably optoelectronic devices. The current blocking structure comprises a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer and a first p-type semiconductor material layer wherein the n-type Ru—InP layer is less than 0.6 μm thick. The semiconductor material arrangement and p-type semiconductor material layer form a current blocking p-n junction. The current blocking structure may further comprise other n-type layers and/or multiple n-type Ru—InP layers and/or intrinsic/undoped layers wherein the n-type Ru—InP layers may be thicker than 0.6 μm. | 2013-08-08 |
| 20130200493 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP. | 2013-08-08 |
| 20130200494 | VARIABLE CAPACITANCE CHAMBER COMPONENT INCORPORATING A SEMICONDUCTOR JUNCTION AND METHODS OF MANUFACTURING AND USING THEREOF - A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction. | 2013-08-08 |
| 20130200495 | BUFFER LAYER STRUCTURES SUITED FOR III-NITRIDE DEVICES WITH FOREIGN SUBSTRATES - Embodiments of the present disclosure include a buffer structure suited for III-N device having a foreign substrate. The buffer structure can include a first buffer layer having a first aluminum composition and a second buffer layer formed on the first buffer layer, the second buffer layer having a second aluminum composition. The buffer structure further includes a third buffer layer formed on the second buffer layer at a second interface, the third buffer layer having a third aluminum composition. The first aluminum composition decreases in the first buffer layer towards the interface and the second aluminum composition throughout the second buffer layer is greater than the first aluminum composition at the interface. | 2013-08-08 |
| 20130200496 | MULTI-LAYER METAL SUPPORT - The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 100 and 600 ° C. | 2013-08-08 |
| 20130200497 | MULTI-LAYER METAL SUPPORT - The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 500 and 1050° C. | 2013-08-08 |
| 20130200498 | METHODS AND APPARATUS FOR LITHOGRAPHY USING A RESIST ARRAY - Methods, apparatus, and systems are provided for forming a resist array on a material to be patterned. The resist array may include an arrangement of two different materials that are adapted to react to activation energy differently relative to each other to enable selective removal of only one of the materials (e.g., one is reactive and the other is not reactive; one is slightly reactive and the other is very reactive; one is reactive in one domain and the other in an opposite domain). The first material may be disposed as isolated nodes between the second material. A subset of nodes may be selected from among the nodes in the array and the selected nodes may be exposed to activation energy to activate the nodes and create a mask from the resist array. Numerous additional aspects are disclosed. | 2013-08-08 |
| 20130200499 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device which includes the following components. A substrate with a first conductivity type has a cell region and a peripheral region thereon, wherein the peripheral region surrounds the cell region. An epitaxial layer having the first conductivity type is disposed on the substrate. A first spiral-shaped region having a second conductivity type is embedded in the epitaxial layer within the peripheral region and encircles the cell region. | 2013-08-08 |
| 20130200500 | RESIST PATTERN THICKENING MATERIAL, METHOD FOR FORMING RESIST PATTERN, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern to be thickened, e.g., in form of lines and spaces pattern, can thicken the resist pattern to be thickened regardless of the size of the resist pattern to be thickened; and which is suited for forming a fine space pattern or the like, exceeding exposure limits. The present invention also provides a process for forming a resist pattern and a process for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized. | 2013-08-08 |
| 20130200501 | IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING - Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material. | 2013-08-08 |
| 20130200502 | Semiconductor Device and Method of Manufacturing Thereof - A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier. | 2013-08-08 |
| 20130200503 | PROTECTIVE LAYERS IN SEMICONDUCTOR PACKAGING - A semiconductor package includes a semiconductor die having an upper surface with bond pads thereon. A plurality of leads surround sides of the semiconductor die. Bonding wires couple each of the bond pads to a corresponding one of the plurality of leads. An encapsulant covers the upper surface and the sides of the semiconductor die and the bonding wires. The encapsulant also covers a portion of a top of each of the plurality of leads and sides of the plurality of leads that are nearest the semiconductor die. A bottom of each of the plurality of leads and the sides of the plurality of leads that are farthest from the semiconductor die are exposed outside the encapsulant. A protective film covers a lower surface of the semiconductor die and has a bottom that is substantially coextensive with the bottom of each of the plurality of leads. | 2013-08-08 |
| 20130200504 | ELECTRONIC COMPONENT MODULE AND METHOD FOR PRODUCING SAME - An electronic component module includes a double-sided mounting board having a front surface and a back surface; components mounted on the front surface and the back surface of the double-sided mounting board; an insulating resin sealing the components mounted on the front surface and the back surface; and a lead frame bonded to the back surface of the double-sided mounting board. The back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin, and the thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to the thickness of the lead frame. | 2013-08-08 |
| 20130200505 | PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads. | 2013-08-08 |
| 20130200506 | METHOD OF PREVENTING EPOXY BLEED OUT OF LEAD FRAME AND LEAD FRAME MANUFACTURED BY USING THE SAME - The epoxy bleed out prevention method including: providing a lead frame that is manufactured through a shaping process which forms a die pad and a plurality of leads by using a conductive raw material, a pre-plating process performed on the shaped conductive raw material, and a tape attaching process; and performing a bleed out prevention process which prevents an epoxy bleed out of a die bonding epoxy-based resin applied on the die pad after the tape attaching process. | 2013-08-08 |
| 20130200507 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 2013-08-08 |
| 20130200508 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques. | 2013-08-08 |
| 20130200509 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part. | 2013-08-08 |
| 20130200510 | SEMICONDUCTOR DEVICE, HEAT RADIATION MEMBER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device has a substrate having a front surface, and a rear surface including a fin forming region and a peripheral region surrounding the fin forming region. An insulating substrate is disposed on the front surface of the substrate. A semiconductor chip is disposed on the insulating substrate. A plurality of fins is formed in the fin forming region, and a reinforcing member is formed on the substrate through a bonding member, so as to overlap the peripheral region. | 2013-08-08 |
| 20130200511 | REDUCING STRESS IN MULTI-DIE INTEGRATED CIRCUIT STRUCTURES - An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer. | 2013-08-08 |
| 20130200512 | PACKAGE WITH INTERPOSER FRAME AND METHOD OF MAKING THE SAME - Embodiments of mechanisms of utilizing an interposer frame to form a package using package on package (PoP) technology are provided in this disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has through substrate holes (TSHs) lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improves mechanical strength of the PoP package. | 2013-08-08 |
| 20130200513 | NO-FLOW UNDERFILL FOR PACKAGE WITH INTERPOSER FRAME - Mechanisms of forming a package on package (PoP) package by using an interposer and an no-reflow underfill (NUF) layer are provided. The interposer frame improves the form factor of the package, enables the reduction in the pitch of the bonding structures. The NUF layer enables a semiconductor die and an interposer frame be bonded to a substrate by utilizing the heat on the connectors of the semiconductor die and on the connectors of the interposer frame for bonding. The heat provided by the semiconductor die and the interposer frame also transforms the NUF layer into an underfill. PoP structures formed by using the interposer frame and the NUF layer improve yield and have better reliability performance. | 2013-08-08 |
| 20130200514 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor package comprises a board including a board pad, a plurality of semiconductor chips mounted on the board, the semiconductor chips including chip pads. Bumps are disposed on the chip pads, respectively, and a wire is disposed between the chip pads and the bumps. The wire electrically connects the chip pads of the plurality of semiconductor chips and the board pad to each other. | 2013-08-08 |
| 20130200515 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal. | 2013-08-08 |
| 20130200516 | HYBRID SUBSTRATE, PRODUCTION METHOD THEREFOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE - A hybrid substrate according to the present invention comprises a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least comprises a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other. | 2013-08-08 |
| 20130200517 | INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME - The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package. | 2013-08-08 |
| 20130200518 | Devices Including Metal-Silicon Contacts Using Indium Arsenide Films and Apparatus and Methods - Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide. | 2013-08-08 |
| 20130200519 | Through silicon via structure and method of fabricating the same - The present invention relates to a method of fabricating a through silicon via (TSV) structure, in which, a dielectric layer is disposed to cover surface of each of a device region of a substrate and a sidewall and a bottom of a via hole in a TSV region of the substrate, and the via hole having the dielectric layer covering the sidewall and the bottom is filled with a conductive material. The present invention also relates to a TSV structure, in which, a dielectric layer disposed in the device region of a substrate extends to the via hole in a TSV region of the substrate to cover surface of the sidewall of the via hole to serve as a dielectric liner, and a conductive material is filled into the via hole having the dielectric layer covering the sidewall. | 2013-08-08 |
| 20130200520 | THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING - At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces. | 2013-08-08 |
| 20130200521 | INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL - Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal. | 2013-08-08 |
