| 32nd week of 2009 patent applcation highlights part 54 |
| Patent application number | Title | Published |
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| 20090198867 | METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE - A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry. | 2009-08-06 |
| 20090198868 | METHOD OF ACCESSING VIRTUAL STORAGE DEVICE THROUGH VIRTUAL DATA ROUTER - A method of accessing a virtual storage device through a virtual data router (VD router) is described. A virtual disk device on a controller may be accessed from various controllers through different paths based on asynchrony of data sending/receiving of a VD router. Moreover, the method is advantageous in having high access efficiency and consistency of data access via different paths at the same time. | 2009-08-06 |
| 20090198869 | ERASE COUNT RECOVERY - An erase count of a flash memory block which is lost, e.g., due to power failure is updated or replaced by using known erase counts of other blocks of the flash memory. A flash management algorithm assigns a new erase count value instead of the lost one based on either a maximum value, an average value or a value combining the maximum value of the known erase counts and some tolerance value. The known values may be obtained from wear leveling data or from a stored erase history. | 2009-08-06 |
| 20090198870 | Methods and Media for Writing Data to Flash Memory - A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory. | 2009-08-06 |
| 20090198871 | EXPANSION SLOTS FOR FLASH MEMORY BASED MEMORY SUBSYSTEM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 2009-08-06 |
| 20090198872 | HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 2009-08-06 |
| 20090198873 | PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 2009-08-06 |
| 20090198874 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 2009-08-06 |
| 20090198875 | DATA WRITING METHOD FOR FLASH MEMORY, AND CONTROLLER AND SYSTEM USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented. | 2009-08-06 |
| 20090198876 | Programmable Command Sequencer - An embedded subsystem IC which provides simple procedures for an external CPU IC to invoke one or more functions provided by modules of the subsystem is disclosed. The embedded subsystem comprises at least one module to perform at least one function, a first memory, and a sequence controller. Each module is controlled by values stored in local registers of the module. The first memory stores at least one predefined sequence of instructions. Each instruction sequence controls a module to perform a function. The sequence controller comprises a second memory to store a vector table and a state machine. In response to receiving a command the CPU, the sequence controller obtains a start address in the first memory of an instruction sequence corresponding with the command. The state machine programs one or more registers of a module that performs the function identified by the command according to the instruction sequence that begins with the start address. | 2009-08-06 |
| 20090198877 | SYSTEM, CONTROLLER, AND METHOD FOR DATA STORAGE - A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified. | 2009-08-06 |
| 20090198878 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD - The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs. While an instruction has been contained in the second program, the instruction instructs that the plurality of first programs are transferred from the first storage device to the second storage device, contents of the plurality of first programs transferred to the second storage devices are compared with each other; and if the contents of the plurality of first programs are not made coincident with each other, then a normal program is judged from the plurality of first programs based upon a majority decision. The CPU executes the first program judged as the normal program so as to initially initiate the information processing system. | 2009-08-06 |
| 20090198879 | MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME - A memory system has a memory unit composed of a plurality of memory cells, a memory controller for controlling to read out and write data from and to the memory unit, and a host processor connected to the memory controller for reading out and writing data from and to the memory unit through the memory controller. The memory controller has a refresh controller for rewriting the data stored in the memory unit. The host processor has a determination unit for determining whether or not a refresh operation can be executed to the memory unit and a permission signal transmission unit for transmitting a refresh permission signal when it is determined that the refresh operation can be executed to the memory unit by the determination unit. The refresh controller controls the start of the refresh operation to the memory unit based on the refresh permission signal transmitted from the host processor. | 2009-08-06 |
| 20090198880 | READ STROBE FEEDBACK IN A MEMORY SYSTEM - A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus. | 2009-08-06 |
| 20090198881 | MEMORY SYSTEM - A memory system including: a memory device; an ECC system installed in the memory device so as to generate a warning signal in case there are uncorrectable errors; an address generating circuit for generating internal addresses in place of bad area addresses in accordance with the waning signal, the progressing of the internal addresses being selected as to avoid address collision with the address progressing of the memory device at least at the beginning; and a CAM for storing the internal addresses as substitutive area addresses, the CAM being referred to at an access time of the memory device so as to generate the substitutive area addresses in place of the bad area addresses in accordance with the warning signal. | 2009-08-06 |
| 20090198882 | METHOD OF WEAR LEVELING FOR NON-VOLATILE MEMORY AND APPARATUS USING THE SAME - A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap. | 2009-08-06 |
| 20090198883 | DATA COPY MANAGEMENT FOR FASTER READS - Multiple copy sets of data are maintained on one or more storage devices. Each copy set includes at least some of the same data units as other sets. Different sets optionally have data units stored in different orders on the storage device(s). A particular one of the sets of data is selected as the set to be accessed in response to detecting a particular scenario. | 2009-08-06 |
| 20090198884 | REDUCED HARD-DRIVE-CAPACITY DETECTION DEVICE - The present disclosure relates to a device for detecting accessible capacity in an external hard drive. The disclosed device may detect reduced accessible capacity in an external hard drive due to an modification or deletion of either the Host-Protected Area or the Device Configuration Overlay table. | 2009-08-06 |
| 20090198885 | SYSTEM AND METHODS FOR HOST SOFTWARE STRIPE MANAGEMENT IN A STRIPED STORAGE SUBSYSTEM - Systems and methods for coalescing host generated write requests in a RAID software driver module to generate full stripe write I/O operations to storage devices. Where RAID management is implemented exclusively in software features and aspects hereof improve performance by using full stripe write operations instead of slower read-modify-write operations. The features and aspects may be implemented for example within a software RAID driver module coupled to a plurality of storage devices in a storage system devoid of RAID specific hardware and circuits. | 2009-08-06 |
| 20090198886 | Power Conservation in a Composite Array of Data Storage Devices - Operating a composite array of data storage devices, such as hard disk drives, to conserve power includes storing data in block-level stripes with parity on a composite array including a controller and at least three data storage devices. The composite array includes a hot spare distributed across the data storage devices. The method further comprises placing one of the data storage devices in a standby state, operating the rest of the data storage devices in an active state, and controlling logical operations of the controller and the read and write operations of the active data storage devices to substitute for read and write operations on the standby device. For example, the controller can read redundant data on the active drives and compute data identical to the data on the standby drive to substitute for reading the standby drive. Furthermore, the controller can write a modified version of data on the standby drive to a spare block to substitute for writing to the standby drive. | 2009-08-06 |
| 20090198887 | STORAGE SYSTEM - A storage group configured by a plurality of storage devices is configured by a plurality of storage sub-groups, and the respective storage sub-groups are configured from two or more storage devices. A sub-group storage area, which is the storage area of the respective storage sub-groups, is configured by a plurality of rows of sub-storage areas. A data set, which is configured by a plurality of data elements configuring a data unit, and a second redundancy code created on the basis of this data unit, is written to a row of sub-storage areas, a compressed redundancy code is created on the basis of two or more first redundancy codes respectively created based on two or more data units of two or more storage sub-groups, and this compressed redundancy code is written to a nonvolatile storage area that differs from the above-mentioned two or more storage sub-groups. | 2009-08-06 |
| 20090198888 | Disk Array System - Provided is a disk array system which is connected to a computer and which data is transmitted by the computer, including: a plurality of disk drives for storing user data transmitted by the computer; a cache memory for temporarily storing data sent/received among the computer and the plurality of disk drives; and a control unit for controlling input/output of the data to/from the cache memory, in which the control unit stores user data identification information that is capable of judging whether the user data is stored in a sector of the disk drive. The disk array system according to this invention allows the identification of user data of a disk drive. | 2009-08-06 |
| 20090198889 | RECORDING APPARATUS, RECORDING METHOD, PROGRAM FOR RECORDING METHOD, AND STORAGE MEDIUM THAT STORES PROGRAM FOR RECORDING METHOD - A recording apparatus includes: a type detecting section that detects a type of storage medium; an erase-block size detecting section that detects an erase-block size of the storage medium; a recording section that records desired data to a data area in the storage medium and records management information of the data area to a management area in the storage medium; and a control section that controls the recording section by issuing a command to the recording section, on the basis of results of the detection. Each time a certain amount of data is recorded to the data area, the control section updates the management information in accordance with the recording, and when the storage medium is a storage medium in which recorded data is updated for each erase-block size, the control section increases the certain amount of data according to an increase in the erase-block size. | 2009-08-06 |
| 20090198890 | METHOD OF SEARCHING NEIGHBORING CELL ADDRESS IN SAME RESOLUTION OCTREE STRUCTURE - Disclosed is a method of searing an address in the octree structure having the same resolution. The method of searching address values of the neighboring cells in the octree structure having the same resolution can include performing address encoding of octree cells by giving an inherent address value that is increased according to a depth level of octree to each cell in the octree structure such that address difference values of neighboring cells in the octree structure has a sequential rule; and searching an address value of a neighboring cell that is in contact by a surface with the selected octree cell by using the sequential rule of the address-encoded address difference value of each octree cell. In accordance with an embodiment of the present invention, it is possible to efficiently search address values of neighboring cells that are in contact with an octree cell. | 2009-08-06 |
| 20090198891 | Issuing Global Shared Memory Operations Via Direct Cache Injection to a Host Fabric Interface - A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping. | 2009-08-06 |
| 20090198892 | RAPID CACHING AND DATA DELIVERY SYSTEM AND METHOD - The initial systems analysis of a new data source fully defines each data element and also designs, tests and encodes complete data integration instructions for each data element. A metadata cache stores the data element definition and data element integration instructions. The metadata cache enables a comprehensive view of data elements in an enterprise data architecture. When data is requested that includes data elements defined in a metadata cache, the metadata cache and associated software modules automatically generate database elements to fully integrate the requested data elements into existing databases. | 2009-08-06 |
| 20090198893 | Microprocessor systems - A memory management arrangement includes a memory management unit | 2009-08-06 |
| 20090198894 | Method Of Updating IC Instruction And Data Cache - A method of updating a cache in an integrated circuit is provided. The integrated circuit incorporates the cache, memory and a memory interface connected to the cache and memory. Following a cache miss, the method fetches, using the memory interface, first data associated with the cache miss and second data from the memory, where the second data is stored in the memory adjacent the first data, and updates the cache with the fetched first and second data via the memory interface. The cache includes instruction and data cache, the method performing arbitration between instruction cache misses and data cache misses such that the fetching and updating are performed for data cache misses before instruction cache misses. | 2009-08-06 |
| 20090198895 | CONTROL METHOD, MEMORY, AND PROCESSING SYSTEM UTILIZING THE SAME - A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output. | 2009-08-06 |
| 20090198896 | DUAL WRITING DEVICE AND ITS CONTROL METHOD - A first storage system sets a storage area of a first disk drive as a first volume, and misrepresents an identifier of the storage system and an identifier of the first volume. A second storage system sets a storage area of a second disk drive as a second volume, and misrepresents an identifier of the storage system and an identifier of the second volume. The first storage system copies data of the first volume in the second volume. The second storage system copies data of the second volume in the first volume. A management computer determines whether there is a match between the data of the first volume and the data of the second volume. When it is determined that there is not match, the host computer accesses only one of the first volume and the second volume that stores the latest data. | 2009-08-06 |
| 20090198897 | CACHE MANAGEMENT DURING ASYNCHRONOUS MEMORY MOVE OPERATIONS - A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed. | 2009-08-06 |
| 20090198898 | PARALLEL DATA PROCESSING APPARATUS - A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays. | 2009-08-06 |
| 20090198899 | SYSTEM AND METHOD FOR TRANSACTIONAL CACHE - A computer-implemented method and system to support transactional caching service comprises configuring a transactional cache that are associated with one or more transactions and one or more work spaces; maintaining an internal mapping between the one or more transactions and the one or more work spaces in a transactional decorator; getting a transaction with one or more operations; using the internal mapping in the transactional decorator to find a work space for the transaction; and applying the one or more operations of the transaction to the workspace associated with the transaction. | 2009-08-06 |
| 20090198900 | Microprocessor Having a Power-Saving Instruction Cache Way Predictor and Instruction Replacement Scheme - Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter provides a signal to the way predictor that determines whether the way predictor operates in a first mode or a second mode. Following a cache miss, the cache refill circuit selects a way of the cache and compares a layer number associated with a dataram field of the way to a way set layer number. The cache refill circuit writes a block of data to the field if the layer number is not equal to the way set layer number. If the layer number is equal to the way set layer number, the cache refill circuit repeats the above steps for additional ways until the block of memory is written to the cache. | 2009-08-06 |
| 20090198901 | COMPUTER SYSTEM AND METHOD FOR CONTROLLING THE SAME - A computer system includes a main memory for storing a large amount of data, a cache memory that can be accessed at a higher speed than the main memory, a memory replacement controller for controlling the replacement of data between the main memory and the cache memory, and a memory controller capable of allocating one or more divided portions of the cache memory to each process unit. The memory replacement controller stores priority information for each process unit, and replaces lines of the cache memory based on a replacement algorithm taking the priority information into consideration, wherein the divided portions of the cache memory are allocated so that the storage area is partially shared between process units, after which the allocated amounts of cache memory are changed automatically. | 2009-08-06 |
| 20090198902 | MEMORY MAPPING TECHNIQUES - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations. | 2009-08-06 |
| 20090198903 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT VARY AN AMOUNT OF DATA RETRIEVED FROM MEMORY BASED UPON A HINT - In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction. | 2009-08-06 |
| 20090198904 | Techniques for Data Prefetching Using Indirect Addressing with Offset - A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction. | 2009-08-06 |
| 20090198905 | Techniques for Prediction-Based Indirect Data Prefetching - A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table. | 2009-08-06 |
| 20090198906 | Techniques for Multi-Level Indirect Data Prefetching - A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of a memory) at the first memory address is then fetched. A second memory address is then determined based on the content at the first memory address. Content that is included in a second data block (e.g., a second cache line) at the second memory address is then fetched (e.g., from the memory or another memory). A third memory address is then determined based on the content at the second memory address. Finally, a third data block (e.g., a third cache line) that includes another pointer or data at the third memory address is fetched (e.g., from the memory or the another memory). | 2009-08-06 |
| 20090198907 | Dynamic Adjustment of Prefetch Stream Priority - A method, processor, and data processing system for dynamically adjusting a prefetch stream priority based on the consumption rate of the data by the processor. The method includes a prefetch engine issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem. The first prefetch stream has a first assigned priority that determines a relative order for scheduling prefetch requests of the first prefetch stream relative to other prefetch requests of other prefetch streams. Based on the receipt of a processor demand for the data before the data returns to the cache or return of the data along time before the receiving the processor demand, logic of the prefetch engine dynamically changes the first assigned priority to a second higher or lower priority, which priority is subsequently utilized to schedule and issue a next prefetch request of the first prefetch stream. | 2009-08-06 |
| 20090198908 | METHOD FOR ENABLING DIRECT PREFETCHING OF DATA DURING ASYCHRONOUS MEMORY MOVE OPERATION - While an AMM operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers a cache injection by the AMM mover (or memory controller) of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache. The memory controller also forwards the next cache lines in the sequence of data to the L2 cache and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller does not overrun the upper caches, by placing moved data into only a subset of the available cache lines of the upper level cache. | 2009-08-06 |
| 20090198909 | Jump Starting Prefetch Streams Across Page Boundaries - A method, processor, and data processing system for enabling utilization of a single prefetch stream to access data across a memory page boundary. A prefetch engine includes an active streams table in which information for one or more scheduled prefetch streams are stored. The prefetch engine also includes a victim table for storing a previously active stream whose next prefetch crosses a memory page boundary. The scheduling logic issues a prefetch request with a real address to fetch data from the lower level memory. Then, responsive to detecting that the real address of the stream's next sequential prefetch crosses the memory page boundary, the prefetch engine determines when the first prefetch stream can continue across the page boundary of the first memory page (via an effective address comparison). The PE automatically reinserts the first prefetch stream into the active stream table to jump start prefetching across the page boundary. | 2009-08-06 |
| 20090198910 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA - According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that requests a copy of only the target granule for subsequent query access. In response to a combined response to the partial touch request indicating success, the combined response representing a system-wide response to the partial touch request, the processing unit receives the target granule of the target cache line and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the cache line. | 2009-08-06 |
| 20090198911 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR CLAIMING COHERENCY OWNERSHIP OF A PARTIAL CACHE LINE OF DATA - According to method of data processing in a multiprocessor data processing system, in response to a processor request to modify a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a data-claim-partial request that requests permission to promote only the target granule of the target cache line to a unique copy with an intent to modify the target granule. In response to a combined response to the data-claim-partial request indicating success (the combined response representing a system-wide response to the data-claim-partial-request), the processing unit promotes only the target granule of the target cache line to a unique copy by updating a coherency state of the target granule and retaining a coherency state of at least one other granule of the target cache line. | 2009-08-06 |
| 20090198912 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR IMPLEMENTING CACHE MANAGEMENT FOR PARTIAL CACHE LINE OPERATIONS - A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field. | 2009-08-06 |
| 20090198913 | Two-Hop Source Snoop Based Messaging Protocol - A messaging protocol that facilitates a distributed cache coherency conflict resolution in a multi-node system that resolves conflicts at a home node. The protocol may perform a method including supporting at least three protocol classes for the messaging protocol, via at least three virtual channels provided by a link layer of a network fabric coupled to the caching agents, wherein the virtual channels include a first virtual channel to support a probe message class, a second virtual channel to support an acknowledgment message class, and a third virtual channel to support a response message class. | 2009-08-06 |
| 20090198914 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD IN WHICH AN INTERCONNECT OPERATION INDICATES ACCEPTABILITY OF PARTIAL DATA DELIVERY - According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request. | 2009-08-06 |
| 20090198915 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT DYNAMICALLY SELECT A MEMORY ACCESS SIZE - A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data. | 2009-08-06 |
| 20090198916 | Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System - A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is ignored. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed. | 2009-08-06 |
| 20090198917 | SPECIALIZED MEMORY MOVE BARRIER OPERATIONS - An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC. | 2009-08-06 |
| 20090198918 | Host Fabric Interface (HFI) to Perform Global Shared Memory (GSM) Operations - A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping. | 2009-08-06 |
| 20090198919 | A Non-Volatile Memory Device, and Method of Accessing a Non-Volatile Memory Device - A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power. | 2009-08-06 |
| 20090198920 | Processing Units Within a Multiprocessor System Adapted to Support Memory Locks - A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing unit within a multiprocessor system. The requesting processing unit can relinquish the access request once the timer countdown has reached a timeout period. | 2009-08-06 |
| 20090198921 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING REDUCED ALIASING IN BRANCH LOGIC - In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data. | 2009-08-06 |
| 20090198922 | FILE-COPYING APPARATUS OF PORTABLE STORAGE MEDIA - The present invention provides a portable file-copying apparatus which includes a first connecting unit, a second connecting unit, and a control unit. The first connecting unit can receive a first portable storage media which includes an original file. The second connecting unit can receive a second portable storage media. Furthermore, the control unit is connected to the first connecting unit, the second connecting unit, and a memory. The control unit is applied for storing the original file in the memory, and copying the file to the second portable storage media in accordance with a control signal. | 2009-08-06 |
| 20090198923 | APPARATUS FOR PREDICTING MEMORY ACCESS AND METHOD THEREOF - A method for predicting memory access, where each data processing procedure is performed in a plurality of stages with segment processing, and the plurality of stages include at least a first stage and a second stage, includes: dividing a memory into a plurality of memory blocks, generating a predicting value of a second position information according to a correct value of a first position information at the first stage, accessing the memory blocks of the corresponding position in the memory according to the predicting value of the second position information, and identifying whether the predicting value of the second position information is correct or not for determining whether the memory is re-accessed, where the first stage occurs before the second stage in a same data processing procedure. | 2009-08-06 |
| 20090198924 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 2009-08-06 |
| 20090198925 | APPARATUS AND METHOD FOR MEMORY MIGRATION IN A DISTRIBUTED MEMORY MULTIPROCESSOR SYSTEM - A distributed memory multiprocessor system including a plurality of cells interconnected via an inter-cell network, each of the plurality of cells including at least one cache, a memory, a memory controller, and a directory managing a status of data stored in the memory, the distributed memory multiprocessor system includes a directory information updating unit of a first cell that updates the directory of the first cell, and a directory information transmitting unit of a second cell that transmits the directory information contained in the directory of the second cell. | 2009-08-06 |
| 20090198926 | METHOD AND DEVICE FOR SWITCHING DATA - A method, the method includes providing data; retrieving interleaving command information from a two dimensional array of interleaving command information; wherein the two dimensional array includes multiple interleaving command information rows, each row includes interleaving commands associated with multiple TDM time slots; and determining, in response to the retrieved interleaving command information, whether to provide data from a first data source or from a second data source. | 2009-08-06 |
| 20090198927 | METHODS FOR IMPLEMENTATION OF WORM MODE ON A REMOVABLE DISK DRIVE STORAGE SYSTEM - Embodiments provide systems and methods for maintaining immutable data in an archiving system using random access memory. To ensure data is immutable, novel pointers are maintained in the hardware/firmware of the drive ports and on the removable disk drives. For example, a hardware/firmware in a modular drive bay maintains a pointer to a memory address in the removable disk drive memory that cannot write to a memory block that precedes the pointer. Data may only be stored after the pointer in the removable disk drive. As such, once data is written to the removable disk drive, the data cannot be overwritten although the removable disk drive employs random access memory. | 2009-08-06 |
| 20090198928 | METHOD AND SYSTEM FOR PROVIDING DATA BACKUP TO MULTIPLE STORAGE MEDIA - A method and system for providing automatic data backup to multiple storage media is disclosed herein. An archive pack is used as a data backup and the archive pack comprises: plurality of storage media arranged as pairs, the storage media in the pair are configured to function independently and only one storage medium in the pair is configured to be visible to a user at any time; and a coordinator configured to co-ordinate the storage media in the pair such that data is stored to each storage medium in the pair substantially simultaneously, but separately. | 2009-08-06 |
| 20090198929 | STORAGE CONTROL DEVICE AND METHOD FOR MANAGING SNAPSHOT - An erasure declaration-related write request is received. In cases where, in response to the erasure declaration-related write request, erasure-corresponding data elements which are data elements corresponding to an erasure target and which are stored in a storage area A in the first logical volume are overwritten with erasure data elements which are data elements signifying erasure at or after the snapshot acquisition time point, the storage area A is associated with a storage area B in which encrypted data elements corresponding to the erasure-corresponding data elements stored in storage area A are stored. | 2009-08-06 |
| 20090198930 | INFORMATION BACKUP SYSTEM FOR HANDHELD DEVICES - An information backup system [ | 2009-08-06 |
| 20090198931 | INFORMATION PROCESSING APPARATUS AND DATA BACKUP METHOD - An information processing apparatus includes a battery for providing the interior of the information processing apparatus with power; a volatile memory for storing data; a nonvolatile memory for backupping the data stored in the volatile memory; a controller for controlling backup of the data in accordance with a process comprising the steps of: saving the data into the nonvolatile memory; upon recovery of the power from the external power source, writing back the data into the volatile memory; and deleting the data saved in the nonvolatile memory; wherein when the power from an external power source to the information processing apparatus is stopped during deleting data in the nonvolatile memory, the controller selectively writes back deleted data from the volatile memory into the nonvolatile memory. | 2009-08-06 |
| 20090198932 | Secure direct platter access - Bulk data transfers by directly accessing a persistent and secured area on the data storage device, e.g., a disk drive having a magnetic storage medium, without relying on the system operating system to execute its read/write operations. For a disk drive, the Protected Area Run Time Interface Extension (PARTIES) technology is applied to create and organize a secured sub-area within a secured storage area. The secured sub-area is a data buffer to and from which large data file transfers can be made with data authenticity and confidentiality. Since this new secured sub-area is not organized and protected by the operating system, it is inherently protected from attack by viruses or Trojan horse software whose effectiveness depends on their ability to maliciously direct the operating system. In addition, the read/write operations bypass command payload limits while reducing data and command validation costs. | 2009-08-06 |
| 20090198933 | Method and Apparatus for Handling Multiple Memory Requests Within a Multiprocessor System - A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed. | 2009-08-06 |
| 20090198934 | FULLY ASYNCHRONOUS MEMORY MOVER - A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation. | 2009-08-06 |
| 20090198935 | METHOD AND SYSTEM FOR PERFORMING AN ASYNCHRONOUS MEMORY MOVE (AMM) VIA EXECUTION OF AMM STORE INSTRUCTION WITHIN INSTRUCTION SET ARCHITECTURE - A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM ST instruction moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location. When the move is completed in the virtual address space, the AMM operation performs the physical move of the data to the second memory location outside the processor core, without processor involvement. | 2009-08-06 |
| 20090198936 | REPORTING OF PARTIALLY PERFORMED MEMORY MOVE - A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for completion of the physical movement of data from a first memory location to a second memory location. The processor executes a second operation, which checks a status of the completion of the data move and returns a notification indicating the status. The notification indicates a status, which includes one of: data move in progress; data move totally done; data move partially done; data move cannot be performed; and occurrence of a translation look-aside buffer invalidate entry (TLBIE) operation. The processor initiates one or more actions in response to the notification received. | 2009-08-06 |
| 20090198937 | MECHANISMS FOR COMMUNICATING WITH AN ASYNCHRONOUS MEMORY MOVER TO PERFORM AMM OPERATIONS - A data processing system includes a set of architected registers within which the processor places state and other information to communicate with the asynchronous memory mover in order to initiate and control an AMM operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation in response to receiving a set of parameters within the architected registers, which parameters are associated with an AMM store instruction executed by the processor to initiates a move of data in virtual space before placing the information in the architected registers. The architected registers are processor architected registers, defined on a per thread basis by a compiler, or memory mapped architected registers allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application. The architected registers are also utilized to store state information to enable a restore to a point before execution of the AMM operation. | 2009-08-06 |
| 20090198938 | HANDLING OF ADDRESS CONFLICTS DURING ASYNCHRONOUS MEMORY MOVE OPERATIONS - A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source to a destination memory location, independent of the processor. The memory mover sets a flag bit to indicate that the asynchronous memory mover is currently performing an AMM operation at the memory. When the processor receives a memory access operation, the processor checks the value of the flag bit before issuing the new memory access operation, and checks the associated address of the AMM operation to determine possible address conflicts. The processor then evaluates and responds to address conflicts to prevent corruption of data during an AMM operation. | 2009-08-06 |
| 20090198939 | LAUNCHING MULTIPLE CONCURRENT MEMORY MOVES VIA A FULLY ASYNCHRONOOUS MEMORY MOVER - A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers from the processor. The processor forwards the parameters after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address. The memory mover responds to receiving the first set of parameters by generating and launching a first asynchronous memory move (AMM) operation. When the memory mover receives a second set of parameters in a second set of registers before the first AMM operation completes, the memory mover generates and launches a second AMM operation concurrently with the first AMM operation if no address conflicts exist. | 2009-08-06 |
| 20090198940 | APPARATUS, SYSTEM, AND METHOD FOR RELOCATING LOGICAL ARRAY HOT SPOTS - An apparatus, system, and method are disclosed for relocating logical array hot spots. An organization module organizes a plurality of logical arrays. Each logical array comprises a plurality of logical segments from a plurality of storage devices and configured to store data. An identification module identifies a hot spot on a first logical array if accesses to the first logical array exceed an access threshold. A migration module dynamically migrates a first logical segment from the first logical array to a second logical segment of a second logical array, wherein the migration is transparent to a host and data of the first logical segment is continuously available to the host. | 2009-08-06 |
| 20090198941 | Computer system with addressable storage medium - A computer system with an addressable medium is disclosed. The computer system comprises an addressable medium subsystem, a microprocessor and at least one input/output device. The addressable medium subsystem includes: a control logic which has a control circuit with an address table for storing a plurality of addresses, and an access logic with a storage medium layer and an electromagnetic induction circuit. The electromagnetic induction circuit includes a plurality of coils and a plurality of rods. Each rod is surrounded by one of the coils and corresponds to one of a plurality of regions on the storage medium layer. The access logic controls the coils to access the data stored on the regions for the control logic. Each region corresponds to one of the addresses on the address table. The microprocessor and the input/output device electrically couple with the control logic. Both the microprocessor accesses instructions for executing and the input/output device accesses data via the control logic. | 2009-08-06 |
| 20090198942 | STORAGE SYSTEM PROVIDED WITH A PLURALITY OF CONTROLLER MODULES - A plurality of global LDEV managed by a plurality of controller modules are provided above local LDEV under the control of each controller module. Each global LDEV is correlated to any of the plurality of local LDEV. The controller modules judge whether or not a local LDEV correlated to a global LDEV specified by an I/O request received from a host device or a first other controller module is a management target itself, and if the result of that judgment is affirmative, the controller modules access the local LDEV correlated to the specified global LDEV, while if the result of the judgment is negative, the controller modules transfer the received I/O request to a second other controller module. | 2009-08-06 |
| 20090198943 | Semiconductor Exposure Apparatus, Control Method, and Computer-Readable Storage Medium - A semiconductor exposure apparatus which executes a plurality of jobs each including at least one application program is provided. The apparatus includes a memory configured to be used to execute the application program, an application program execution management unit configured to manage execution of the application program included in the job; and a memory access management unit configured to manage a memory area to be allocated to the application program using a table in which the job including the application program, the application program, and memory area information to specify the allocated memory area are registered in association with each other, wherein the memory access management unit deletes, from the table, the memory area information of the application program included in the job registered in the table when the job is completed. | 2009-08-06 |
| 20090198944 | SEMICONDUCTOR MEMORY DEVICE - An adaptive semiconductor memory device is used for being inserted into a host for storage. The semiconductor memory device comprises a non-volatile memory and a switch. The switch can be a logical switch or a physical switch that controls the semiconductor memory device to be in compliance with either a first specification version or a second specification version of the semiconductor memory device. The second specification version in comparison with the first specification version is used for higher capacity applications. | 2009-08-06 |
| 20090198945 | System and Method For Configuring Storage Resources For Database Storage - A system and method for configuring storage resources for database storage are disclosed. A method may include mapping at least one first tablespace having a first block size to at least one first logical unit. The method may also include mapping the at least one first tablespace and the at least one first logical unit to a first cache having a size equal to the first block size. In addition, the method may include mapping at least one second tablespace having a second block size to at least one second logical unit. The method may further include mapping the at least one second tablespace and the at least one second logical unit to a second cache having a size equal to the second block size. | 2009-08-06 |
| 20090198946 | Computer system and garbage collection method of disk space - A processor of a management computer acquires the free disk space amount of a disk pool, acquires the invalid disk space amount from a plurality of host computers, determines a host computer to which the instruction for the physical disk space collection is issued on the basis of the invalid disk space amount, and judges that the free disk space amount is smaller than a predetermined threshold value before transmitting a GC control request to the determined host computer; another processor generates and transmits invalid disk space position information indicating the position of the invalid disk space in a virtual volume in cases where a host investigation request is received; and the other processor collects the physical disk space of a physical disk allocated to the storage disk space of the virtual volume in the disk pool. | 2009-08-06 |
| 20090198947 | Memory Mapping Restore and Garbage Collection Operations - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations. | 2009-08-06 |
| 20090198948 | Techniques for Data Prefetching Using Indirect Addressing - A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory address. Finally, a data block (e.g., a cache line) including data at the second memory address is fetched (e.g., from the memory or another memory). | 2009-08-06 |
| 20090198949 | HYPERVOLUME DATA STORAGE OBJECT AND METHOD OF DATA STORAGE - The present disclosure relates to a data storage device having a hypervolume accessible by a plurality of servers operating on two or more data storage systems, a first physical volume, associated with the hypervolume, located at a first data storage system, and a second physical volume, associated with the hypervolume, located at a second storage system. The hypervolume directs input/output (I/O) from the servers to a primary physical volume comprising either the first or second physical volume, and the primary physical volume may be changed, transparently to the servers, to the other of the first or second physical volume. The present disclosure, in another embodiment, relates to a method for moving operation of a storage device from one data storage location to a second data storage location. A hypervolume is used to redirect input/output (I/O) from the a plurality of servers from the one physical volume to another. | 2009-08-06 |
| 20090198950 | Techniques for Indirect Data Prefetching - A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address. | 2009-08-06 |
| 20090198951 | Full Virtualization of Resources Across an IP Interconnect - An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network. | 2009-08-06 |
| 20090198952 | Memory Mapping Architecture - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations. | 2009-08-06 |
| 20090198953 | Full Virtualization of Resources Across an IP Interconnect Using Page Frame Table - An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network. | 2009-08-06 |
| 20090198954 | Method and system for generating location codes - The present disclosure provides a method for generating a standardized location code is provided that comprises extracting an address component from an input location data record, parsing the address component into one or more address words, and processing the address words by validating the address words one by one using one or more validation rules specific to the input location data record. The method also includes constructing the standardized location code by assembling the processed address words and producing an updated location data file to be shared with a plurality of subscribing applications. | 2009-08-06 |
| 20090198955 | ASYNCHRONOUS MEMORY MOVE ACROSS PHYSICAL NODES (DUAL-SIDED COMMUNICATION FOR MEMORY MOVE) - A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor. | 2009-08-06 |
| 20090198956 | System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture - A system and method are provided for implementing a two-tier full-graph interconnect architecture. In order to implement a two-tier full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the two-tier full-graph interconnect architecture. Data is then transmitted from one processor to another within the two-tier full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor chip identifier associated with a target processor to which the data is to be transmitted. | 2009-08-06 |
| 20090198957 | System and Method for Performing Dynamic Request Routing Based on Broadcast Queue Depths - A system and method for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data. | 2009-08-06 |
| 20090198958 | System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information - A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data. | 2009-08-06 |
| 20090198959 | SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIVE OPERATIONS - A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry. | 2009-08-06 |
| 20090198960 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT PARTIAL CACHE LINE READS - According to a method of data processing in a multiprocessor data processing system, in response to a processor request to read a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial read request that requests permission to read only the target granule of the target cache line. In response to a combined response to the partial read request indicating success, the combined response representing a system-wide response to the partial read request, the processing unit receives the target granule of the target cache line, supplies the target granule to a requesting processor core, and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the target cache line. | 2009-08-06 |
| 20090198961 | Cross-Thread Interrupt Controller for a Multi-thread Processor - An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, the interrupt controller has, for a second thread, an interrupt request register accessible to the first thread, an interrupt count accessible to the first thread, and an interrupt acknowledge accessible to the second thread. Each interrupt controller separately has a counter for each request which increments upon assertion of a request and decrements upon assertion of an acknowledgement. | 2009-08-06 |
| 20090198962 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE INCLUDING ADDRESS TYPE TAG BIT - In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address. | 2009-08-06 |
| 20090198963 | COMPLETION OF ASYNCHRONOUS MEMORY MOVE IN THE PRESENCE OF A BARRIER OPERATION - A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation. | 2009-08-06 |
| 20090198964 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR OUT OF ORDER INSTRUCTION ADDRESS STRIDE PREFETCH PERFORMANCE VERIFICATION - A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides. | 2009-08-06 |
| 20090198965 | METHOD AND SYSTEM FOR SOURCING DIFFERING AMOUNTS OF PREFETCH DATA IN RESPONSE TO DATA PREFETCH REQUESTS - According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core. | 2009-08-06 |
| 20090198966 | Multi-Addressable Register File - A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file. | 2009-08-06 |
