32nd week of 2009 patent applcation highlights part 39 |
Patent application number | Title | Published |
20090197362 | Array substrate for liquid crystal display device and method of manufacturing the same - A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad and a gate electrode on a substrate through a first mask process, forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the substrate including the gate line, the gate pad and the gate electrode through a second mask process, wherein the data line crosses the gate line to define a pixel region, the source electrode is extended from the data line, the drain electrode is spaced apart from the source electrode, and the active layer is disposed between the gate electrode and the source and drain electrodes, forming a passivation layer on an entire surface of the substrate including the data line, the source electrode and the drain electrode through a third mask process, the passivation layer being etched to expose the substrate in the pixel region, a part of the drain electrode, the gate pad and the data pad, and forming a pixel electrode, a gate pad terminal and a data pad terminal by depositing a transparent conductive material on an entire surface of the substrate including the passivation layer, the pixel electrode directly contacting the exposed part of the drain electrode, the gate pad terminal directly contacting the gate pad, and the data pad terminal directly contacting the data pad. | 2009-08-06 |
20090197363 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A method for manufacturing a semiconductor optical device comprises forming a groove on a first semiconductor layer; forming a second semiconductor layer containing aluminum in the groove; forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; forming an insulating layer on the third semiconductor layer covering the region opposite the second semiconductor layer; forming a stripe-shaped structure by etching the first semiconductor layer and the third semiconductor layer without exposing the second semiconductor layers using the insulating layer as a mask; and burying the stripe-shaped structure with burying layers. | 2009-08-06 |
20090197364 | METHOD OF FABRICATING SUBSTRATE - A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel. | 2009-08-06 |
20090197365 | Treatment method for surface of substrate, method of fabricating image sensor by using the treatment method, and image sensor fabricated by the same - Provided may be a treatment method to remove defects created on the surface of a substrate, a method of fabricating an image sensor by using the treatment method, and an image sensor fabricated by the same. The treatment method may include providing a semiconductor substrate including a surface defect, providing a chemical solution to a surface of the semiconductor substrate, and removing the surface defect by consuming the surface of the semiconductor substrate and forming a chemical oxide layer on the semiconductor substrate. | 2009-08-06 |
20090197366 | SOLID-STATE IMAGE SENSOR, MANUFACTURING METHOD FOR SOLID-STATE IMAGE SENSOR, AND CAMERA - A solid-state image sensor includes a plurality of light-receiving elements arranged in a light-receiving area, and a plurality of micro-lenses corresponding to the light-receiving elements, and has a flattening film formed on the plurality of the micro-lenses. At a center of the light-receiving area, the micro-lenses are placed in positions directly above corresponding photodiodes, and placed in positions which are progressively offset from positions directly above the corresponding photodiodes, towards a center of the light receiving area, as micro-lenses are located farther from the center of the light-receiving area. | 2009-08-06 |
20090197367 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 2009-08-06 |
20090197368 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 2009-08-06 |
20090197369 | Multilayer substrate manufacturing method - A method for producing a multilayer substrate includes stacking a first substrate, the first substrate having a circuit pattern; stacking a connector, the connector coupling onto said first substrate, the connector having a ring structure, the ring structure having a plurality of holes separated a predetermined distance from one another; and stacking a second substrate, the second substrate coupling onto said first substrate by inserting said connector, the second substrate having a circuit pattern, the circuit pattern being electrically connected to a circuit pattern formed on said first substrate, the circuit pattern being electrically connected using the plurality of holes formed on said connector. The method of producing a multilayer substrate can shield the EMI generated by a high-speed switching element. | 2009-08-06 |
20090197370 | Method and apparatus for manufacturing semiconductor device - There is provided a method and an apparatus for manufacturing a semiconductor device having a lidless and highly reliable flip-chip structure. The method for manufacturing a semiconductor device wherein an underfill resin is filled in a space between a substrate and a semiconductor chip includes injecting a first underfill resin in said space under a first injecting condition; specifying a location where the fillet height of the underfill resin formed on the side of said semiconductor chip does not meet a prescribed standard; and injecting a second underfill resin in a location where the fillet height does not meet the prescribed standard under a second injecting condition. Since the fillet heights can uniformly meet the prescribed standard, the concentration of stress can be avoided, and a semiconductor device having a lidless and highly reliable flip-chip structure can be manufactured. | 2009-08-06 |
20090197371 | Integrated Circuit Packaging Using Electrochemically Fabricated Structures - Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material, or conductive material containing passages that allow the flow of fluid to maintain desired thermal properties of the packaged electronic components. | 2009-08-06 |
20090197372 | METHOD FOR MANUFACTURING STACK PACKAGE USING THROUGH-ELECTRODES - Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level. | 2009-08-06 |
20090197373 | Semiconductor Device Singulation Method - The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S | 2009-08-06 |
20090197374 | METHOD OF FABRICATING CHIP PACKAGE STRUCTURE - A chip package structure includes a chip, a lead frame, first and second bonding wires, an upper encapsulant, a first lower encapsulant, and a second lower encapsulant. The chip has an active surface, a back surface, and chip bonding pads disposed on the active surface. The lead frame having an upper surface and a lower surface includes a die pad, leads, and at least a bus bar. The back surface of the chip is adhered to the die pad. The leads surround the die pad. The bus bar is disposed between the die pad and the leads. The first bonding wires are connected to the chip bonding pads and the bus bar. The second bonding wires are connected to the bus bar and the leads. The upper encapsulant encapsulates the upper surface of the lead frame, the chip, the first bonding wires, and the second bonding wires. | 2009-08-06 |
20090197375 | Metal-resin-boned structured body and resin-encapsulated semiconductor device, and fabrication method for them - A fabrication method for a metal-base/polymer-resin bonded structured body according to the present invention includes the steps of: (1) applying, to a surface of the metal base, a solution containing an organometallic compound decomposable at 350° C. or lower; (2) baking the applied solution in an oxidizing atmosphere to form, on the surface of the metal base, a coating containing an oxide of the metal of the organometallic compound; (3) providing the polymer resin on the coating; and (4) hardening the polymer resin to provide the metal-base/polymer-resin bonded structured body. | 2009-08-06 |
20090197376 | PLASMA CVD METHOD, METHOD FOR FORMING SILICON NITRIDE FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas. | 2009-08-06 |
20090197377 | ESD POWER CLAMP WITH STABLE POWER START UP FUNCTION - A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps. | 2009-08-06 |
20090197378 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region. | 2009-08-06 |
20090197379 | SELECTIVE EPITAXY VERTICAL INTEGRATED CIRCUIT COMPONENTS AND METHODS - Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. | 2009-08-06 |
20090197380 | METHOD FOR MANUFACTURING A RECESSED GATE TRANSISTOR - A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate. | 2009-08-06 |
20090197381 | METHOD FOR SELECTIVELY FORMING STRAIN IN A TRANSISTOR BY A STRESS MEMORIZATION TECHNIQUE WITHOUT ADDING ADDITIONAL LITHOGRAPHY STEPS - A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps. | 2009-08-06 |
20090197382 | MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES - Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased). | 2009-08-06 |
20090197383 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths. | 2009-08-06 |
20090197384 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower electrode, and an upper electrode on the dielectric portion. The inner portion is provided with a lower part and an upper part upwardly extending from the lower part. The insulator laterally holds the lower part. The outer portion is arranged on the insulator and is electrically connected with the upper part. | 2009-08-06 |
20090197385 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention discloses a semiconductor device and a method of manufacture thereof. The present invention prevents from leaning or collapsing in the subsequent dip-out process by making the bottom plate of adjacent capacitors to be connected each other and supported each other in patterning the conductive layer for the bottom plate of capacitor. | 2009-08-06 |
20090197386 | Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM, And Methods Of Forming DRAM Memory Cells - The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated. | 2009-08-06 |
20090197387 | METHOD OF FORMING A GATE STACK STRUCTURE - A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness. | 2009-08-06 |
20090197388 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including at leasty one of the following steps: sequentially forming a first oxide layer, a nitride layer, a second oxide layer, a bottom anti-reflect coating and a photo-resist pattern over a semiconductor substrate; exposing the uppermost surface of the semiconductor substrate by performing a first reactive ion etch process; and then forming a trench in the uppermost surface of the semiconductor substrate by performing a second reactive ion etch process. | 2009-08-06 |
20090197389 | Method for manufacturing semiconductor device - The present invention provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate having a quartz support substrate and a silicon layer, forming a base or substrate silicon oxide film over the entire upper surface of the silicon layer, forming a silicon nitride film over the entire upper surface of the substrate silicon oxide film by a plasma CVD method, patterning the silicon nitride film thereby to form a mask pattern having a circumferential exposure portion that exposes the substrate silicon oxide film in a circumferential area, a first opening pattern that exposes the substrate silicon oxide film in an element isolation area, and a second opening pattern that exposes the substrate silicon oxide film within a peripheral area, and thermally oxidizing the substrate using the mask pattern as a mask thereby to form an element isolation structure portion in the element isolation area. | 2009-08-06 |
20090197390 | LOCK AND KEY STRUCTURE FOR THREE-DIMENTIONAL CHIP CONNECTION AND PROCESS THEREOF - A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL). | 2009-08-06 |
20090197391 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A method for manufacturing an SOI substrate is provided in which adhesiveness between a single crystal semiconductor substrate and a semiconductor substrate is improved; bonding defects are reduced; and sufficient bonding strength is provided in a bonding step and also in a process of manufacturing a semiconductor device. An insulating film including halogen is formed on a single crystal semiconductor substrate side in which an embrittlement layer is formed. The insulating film including halogen undergoes a plasma treatment. The insulating film including halogen and a face of a semiconductor substrate are bonded so as to face each other. A thermal treatment is performed to split the single crystal semiconductor substrate along the embrittlement layer, thereby separating the single crystal semiconductor substrate into a single crystal semiconductor substrate and the semiconductor substrate to which a single crystal semiconductor layer is bonded. The single crystal semiconductor layer bonded to the semiconductor substrate undergoes a planarization treatment. | 2009-08-06 |
20090197392 | MANUFACTURING METHOD OF SOI SUBSTRATE - An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate. | 2009-08-06 |
20090197393 | Method for dividing semiconductor wafer and manufacturing method for semiconductor devices - In a semiconductor wafer including a plurality of imaginary-divided-regions which are partitioned by imaginary-dividing-lines that are respectively arranged in a grid-like arrangement on the semiconductor wafer and a circumferential line that is the outer periphery outline of the semiconductor wafer, a mask is placed so as to expose an entirety of surfaces of the wafer corresponding to respective removal-regions, the removal-regions being regions in approximately triangular form partitioned by the circumferential line of the wafer and the imaginary-dividing-lines and being some of the imaginary-divided-regions, and then plasma etching is performed on a mask placement-side surface, by which the semiconductor wafer is divided into the individual semiconductor devices along dividing lines while portions correspond to the removal-regions in the wafer are removed. | 2009-08-06 |
20090197394 | WAFER PROCESSING - Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular depth in rows and columns. The method further includes forming a passivation layer on side walls of the number of trenches. The method also includes cutting a second side of the semiconductor wafer in rows and columns aligned with the number of trenches such that the semiconductor wafer singulates into a number of dice. | 2009-08-06 |
20090197395 | METHOD OF MANUFACTURING DEVICE - A method of manufacturing a device includes: a laser beam-machined groove forming step of irradiating a wafer with a laser beam from the back side of the wafer along planned dividing lines so as to form laser beam-machined grooves along the planned dividing lines; an etching step of etching a back-side surface of the wafer having been subjected to the laser beam-machined groove forming step, so as to remove denatured layers formed at processed surfaces of the laser beam-machined grooves; an adhesive film attaching step of attaching an adhesive film to the back-side surface of the wafer having been subjected to the etching step, and adhering the adhesive film side of the wafer to a surface of a dicing tape; and an adhesive film rupturing step of expanding the dicing tape so as to rupture the adhesive film along individual devices. | 2009-08-06 |
20090197396 | Method for Producing Silicon Wafer - The present invention provides a method for producing a silicon wafer at least including a step of performing RTA heat treatment with respect to a silicon wafer in an atmospheric gas, wherein nitrogen gas is used as the atmospheric gas, which is mixed with oxygen at a concentration of less than 100 ppm so as to perform the heat treatment. Hereby a method for producing a high-quality wafer can be provided, where the RTA heat treatment subject to the silicon wafer can be performed at a low temperature or over a short period of time, so that generation of slip dislocation of the silicon wafer can be suppressed, and at the same time vacancies can be implanted inside the silicon wafer without using NH | 2009-08-06 |
20090197397 | Method of Manufacturing Semiconductor Device - The present invention discloses a method of manufacturing a semiconductor device including a plurality of semiconductor layers grown on a substrate and removing the substrate from the plurality of semiconductor layers. The method of manufacturing the semiconductor device comprises a first step for growing a III-nitride compound semiconductor layer between the substrate and the plurality of semiconductor layers, and a second step for removing the substrate by etching the III-nitride compound semiconductor layer. | 2009-08-06 |
20090197398 | III Nitride Single Crystal and Method of Manufacturing Semiconductor Device Incorporating the III Nitride Single Crystal - A III nitride single-crystal manufacturing method in which a liquid layer ( | 2009-08-06 |
20090197399 | METHOD OF GROWING GROUP III-V COMPOUND SEMICONDUCTOR, AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE AND ELECTRON DEVICE - Provided are a method of growing a group III-V compound semiconductor, and method of manufacturing a light-emitting device and an electron device, in which risks are reduced and nitrogen can be efficiently supplied at low temperatures. | 2009-08-06 |
20090197400 | METHOD FOR RECYCLING OF ION IMPLANTATION MONITOR WAFERS - A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape. | 2009-08-06 |
20090197401 | Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces - Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction. | 2009-08-06 |
20090197402 | SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PROCESS TUBE - In a substrate processing apparatus, a process vessel is configured to accommodate and process a substrate held at a horizontal position. A gas introduction port is installed at a periphery of a first side of the process vessel and configured to introduce gas into the process vessel from a lateral direction of the substrate. A gas exhaust port is installed at a second side of the process vessel which is opposite to the first side, and is configured to exhaust gas inside the process vessel from a lateral direction of the substrate. A slope part is installed between the gas introduction port and the gas exhaust port inside the process vessel, and is configured to guide a flow path of the gas introduced into the process vessel. | 2009-08-06 |
20090197403 | METHOD FOR FORMING INSULATING FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for forming an insulating film includes forming a silicon nitride film on a silicon surface by subjecting a target substrate wherein silicon is exposed in the surface to a treatment for nitriding the silicon, forming a silicon oxynitride film by heating the target substrate provided with the silicon nitride film in an N | 2009-08-06 |
20090197404 | High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability - The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated. By performing further damascene process steps over the various damascene interconnect features formed by using the present invention, various interconnect systems such as a single damascene planar via, a single damascene embedded via, and various dual damascene interconnect system having either a planar via or an embedded via can be fabricated. | 2009-08-06 |
20090197405 | METHOD OF FORMING A LAYER OVER A SURFACE OF A FIRST MATERIAL EMBEDDED IN A SECOND MATERIAL IN A STRUCTURE FOR A SEMICONDUCTOR DEVICE - There is described a method of forming a barrier layer ( | 2009-08-06 |
20090197406 | SEQUENTIAL DEPOSITION OF TANTALUM NITRIDE USING A TANTALUM-CONTAINING PRECURSOR AND A NITROGEN-CONTAINING PRECURSOR - Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process. | 2009-08-06 |
20090197407 | Process for Manufacturing Rounded Polysilicon Electrodes on Semiconductor Components - A polysilicon layer provided for a polysilicon electrode ( | 2009-08-06 |
20090197408 | INCREASING ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE OF A SEMICONDUCTOR DEVICE BY FORMING AN ALLOY - By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents. | 2009-08-06 |
20090197409 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus. The substrate processing apparatus comprises a reaction tube; a heating device configured to heat the reaction tube; and a manifold installed outward as compared with the heating device and made of a nonmetallic material. A first thickness of the manifold defined in a direction perpendicular to a center axis of the reaction tube is greater than a second thickness of the manifold defined at a position adjacent to the reaction tube in a direction parallel to the center axis of the reaction tube. The manifold comprises a protrusion part of which at least a portion protrudes inward more than an inner wall of the reaction tube, and a gas supply unit disposed at at least the protrusion part for supplying gas to an inside of the reaction tube. | 2009-08-06 |
20090197410 | METHOD OF FORMING TASIN FILM - A substrate is disposed in a processing chamber. An organic Ta compound gas having Ta═N bond, a Si-containing gas and a N-containing gas are introduced into the processing chamber to form a TaSiN film on the substrate by CVD. In this film formation, at least one of a partial pressure of the Si-containing gas in the processing chamber, a total pressure in the processing chamber, a film forming temperature and a partial pressure of the N-containing gas in the processing chamber is controlled to thereby regulate Si concentration in the film. Particularly, when SiH | 2009-08-06 |
20090197411 | NEW METAL PRECURSORS CONTAINING BETA-DIKETIMINATO LIGANDS - Methods and compositions for depositing a metal containing thin film on a substrate comprises introducing a vapor phase metal-organic precursor into a reaction chamber containing one or more substrates. The precursor has at least one β-diketiminato ligand, and has the general formula: | 2009-08-06 |
20090197412 | Chemical mechanical polishing composition and process - To provide a polishing slurry composition which effectively reduces the occurrence of scratches, and a method of polishing which reduces the occurrence of scratches while realizing an economical polishing step. The aforementioned object is attained by using a polishing slurry composition for polishing a semiconductor substrate containing a metal oxide particle, at least one water-soluble organic polymer and water, said slurry composition characterized in that, when a test substrate having a metal film, a shallow trench isolation film or dielectric film is polished by varying a rate of a polishing pad equipped in a polishing apparatus under a constant polishing pressure to achieve a maximum polishing rate. | 2009-08-06 |
20090197413 | Polishing Composition and Polishing Method Using The Same - The present invention provides a polishing composition that can be suitably used in polishing of polysilicon, and a polishing method using the polishing composition. The polishing composition contains abrasive grains and an anionic surfactant having a monooxyethylene group or a polyoxyethylene group and has a pH of 9 to 12. If the anionic surfactant contained in the polishing composition has a polyoxyethylene group, the number of repeating oxyethylene units in the polyoxyethylene group is preferably 2 to 8. The anionic surfactant contained in the polishing composition can be an anionic surfactant that has a phosphate group, a carboxy group, or a sulfo group as well as a monooxyethylene group or a polyoxyethylene group. The content of the anionic surfactant in the polishing composition is preferably 20 to 500 ppm. | 2009-08-06 |
20090197414 | Polishing Composition and Polishing Method Using The Same - The present invention provides a polishing composition that can be suitably used in polishing of polysilicon, and a polishing method using the polishing composition. The polishing composition contains a nitrogen-containing nonionic surfactant and abrasive grains and has a pH of 9 to 12. The content of the nitrogen-containing nonionic surfactant in the polishing composition is preferably 20 to 500 ppm. The abrasive grains contained in the polishing composition are preferably colloidal silica. The average primary particle diameter of the abrasive grains contained in the polishing composition is preferably 10 to 90 nm. The content of the abrasive grains in the polishing composition is preferably 1.0 to 5.0% by mass. | 2009-08-06 |
20090197415 | POLISHING FLUID COMPOSITION - To provide a polishing composition capable of increasing polishing rate and reducing surface roughness, without causing surface defects on a surface of an object to be polished; and a polishing process for a substrate to be polished. [1] a polishing composition comprising water, an abrasive, an intermediate alumina, and a polycarboxylic acid having 4 or more carbon atoms with no OH groups or a salt thereof, wherein a content of the intermediate alumina is from 1 to 90 parts by weight, based on 100 parts by weight of the abrasive; and [2] a polishing process for a substrate to be polished, comprising polishing a substrate to be polished under conditions that a composition of a polishing liquid during polishing is the composition as defined in item [1] above. | 2009-08-06 |
20090197416 | SILICON NANO WIRE HAVING A SILICON-NITRIDE SHELL AND MTHOD OF MANUFACTURING THE SAME - Silicon nano wires having silicon nitride shells and a method of manufacturing the same are provided. Each silicon nano wire has a core portion formed of silicon, and a shell portion formed of silicon nitride surrounding the core portion. The method includes removing silicon oxide formed on the shell of the silicon nano wire and forming a silicon nitride shell. | 2009-08-06 |
20090197417 | METHOD FOR FORMING SPACERS OF DIFFERENT SIZES - A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall. | 2009-08-06 |
20090197418 | SUBSTRATE PROCESSING APPARATUS - A method of using a heat exchanger efficiently and uniformly to cool or heats portions to be controlled to a prescribed temperature, and then continuously carry out stable processing. The heat exchanger is constructed by arranging partition walls between two plates to form a fluid channel and a fin parallel with the channel or inclined by a prescribed angle on each of the two plates insides the channel so that the plate or a member in contact with the plate is cooled or heated with the fluid flowing through the channel. | 2009-08-06 |
20090197419 | PROCESS FOR REMOVING HIGH STRESSED FILM USING LF OR HF BIAS POWER AND CAPACITIVELY COUPLED VHF SOURCE POWER WITH ENHANCED RESIDUE CAPTURE - A method of fabricating multilayer interconnect structures on a semiconductor wafer uses an interior surface of a metal lid that has been roughed to a surface roughness in excess of RA 2000 with a reentrant surface profile. The metal lid is installed as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling. | 2009-08-06 |
20090197420 | METHOD FOR ETCHING A SILICON-CONTAINING ARC LAYER TO REDUCE ROUGHNESS AND CD - A method of dry developing a multi-layer mask having a silicon-containing anti-reflective coating (ARC) layer on a substrate is described. The method comprises forming the multi-layer mask on the substrate, wherein the multi-layer mask comprises a lithographic layer overlying the silicon-containing ARC layer. A feature pattern is then formed in the lithographic layer using a lithographic process, wherein the feature pattern comprises a first critical dimension (CD). Thereafter, the feature pattern is transferred from the lithographic layer to the silicon-containing ARC layer using a dry plasma etching process, wherein the first CD in the lithographic layer is reduced to a second CD in the silicon-containing layer and a first edge roughness is reduced to a second edge roughness in the silicon-containing ARC layer. | 2009-08-06 |
20090197421 | CHEMISTRY AND COMPOSITIONS FOR MANUFACTURING INTEGRATED CIRCUITS - Methods of removing metal-containing materials during the manufacture of integrated circuits are disclosed. Generally, the methods include providing a substrate assembly that includes a metal-containing material, contacting the metal-containing material with a reactive composition that includes a chlorocarbon material under conditions effective to form a reaction product, and removing the reaction product. | 2009-08-06 |
20090197422 | REDUCING DAMAGE TO LOW-K MATERIALS DURING PHOTORESIST STRIPPING - A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer. | 2009-08-06 |
20090197423 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method that can eliminate unevenness in the distribution of plasma. The method is for a substrate processing apparatus that has a processing chamber in which a substrate is housed, a mounting stage that is disposed in the processing chamber and on which the substrate is mounted, and an electrode plate that is disposed in the processing chamber such as to face the mounting stage, the electrode plate being made of silicon and connected to a radio-frequency power source, and carries out plasma processing on the substrate. In the plasma processing, the temperature of the electrode plate is measured, and based on the measured temperature, the temperature of the electrode plate is maintained lower than a critical temperature at which the specific resistance value of the silicon starts changing. | 2009-08-06 |
20090197424 | Substrate processing apparatus and method for manufacturing semiconductor device - A substrate processing apparatus according to the present invention promotes supplying gases to spaces between adjacent substrates without reducing the number of substrates which can be collectively processed. The substrate processing apparatus includes: a processing chamber for storing and processing substrates stacked in multiple stages in horizontal posture; at least one processing gas supply nozzle which extends running along an inner wall of the processing chamber in the stacking direction of the substrates and supplies a processing gas to the inside of the processing chamber; a pair of inactive gas supply nozzles which are provided so as to extend running along the inner wall of the processing chamber in the stacking direction of the substrates and so as to sandwich the processing gas supply nozzle from both sides thereof along the circumferential direction of the substrates and which supply the inactive gas to the inside of the processing chamber; and an exhaust line for exhausting the inside of the processing chamber. | 2009-08-06 |
20090197425 | SUBSTRATE PROCESSING APPARATUS - An ALD apparatus comprises: a process chamber ( | 2009-08-06 |
20090197426 | Process for Preparing a Dielectric Interlayer Film Containing Silicon Beta Zeolite - A process for forming a zeolite beta dielectric layer onto a substrate such as a silicon wafer has been developed. The zeolite beta is characterized in that it has an aluminum concentration from about 0.1 to about 2.0 wt. %, and has crystallites from about 5 to about 40 nanometers. The process involves first dealuminating a starting zeolite beta, then preparing a slurry of the dealuminated zeolite beta followed by coating a substrate, e.g. silicon wafer with the slurry, heating to form a zeolite beta film and treating the zeolite beta with a silylating agent. | 2009-08-06 |
20090197427 | IMPURITY-ACTIVATING THERMAL PROCESS METHOD AND THERMAL PROCESS APPARTUS - A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T | 2009-08-06 |
20090197428 | IMPURITY-ACTIVATING THERMAL PROCESS METHOD AND THERMAL PROCESS APPARATUS - An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process. | 2009-08-06 |
20090197429 | ROTATING PLUG ADAPTER WITH INTEGRAL TWO BLADE RECEPTACLE - A rotating two blade plug adapter includes a housing including a top and bottom coupled to freely rotate about a rotary cap disposed between the housing top and bottom. Right and left electrical spades extend from the rotary cap and a receptacle integral to the periphery of the housing accepts a two blade plug that may be oriented at a wall receptacle by rotating the adapter housing and receptacle to a desired orientation. Internal flanges define grooves in which rotary electrical contacts are maintained through rotation of the housing and integral receptacle. | 2009-08-06 |
20090197430 | CONNECTOR - The invention discloses a connector including a housing, a terminal, a circuit board, and a light-emitting device. The housing has an accommodation space. The terminal is disposed in the accommodation space for being coupled with a plug. The circuit board is disposed in the accommodation space and includes a first surface toward to the terminal and a second surface opposite to the first surface. The light-emitting device is disposed to the first surface. | 2009-08-06 |
20090197431 | Electrical connector for receiving an electrical card assembly - An electrical connector ( | 2009-08-06 |
20090197432 | Connector - A connector includes a grounding terminal, a signal terminal and an insulating casing. The grounding terminal has an annular body and two grounding portions extending from the bottom of the annular body. The signal terminal has a substrate. One end of the substrate is provided with a soldering portion, and the other end of the substrate is bent to form a hollow cylindrical contacting portion. The contacting portion is disposed in the annular body of the grounding terminal. A wings is formed respectively by means of extending horizontally and outwards from two sides the end of the substrate having the contacting portion. The insulating body covers the grounding terminal and the signal terminal. The grounding portion of the grounding terminal and the soldering portion of the signal terminal extend outside the insulating casing respectively. | 2009-08-06 |
20090197433 | CONNECTOR FOR HIGHBANDWIDTH CONNECTION AND ELECTRONIC CARD EQUIPPED WITH SAME - Connector for high-speed two-wire link, able to be mounted directly on a printed circuit. The connector comprises two parallel pins, an insulating insert in which the pins are mounted, a metal casing associated with mounting means for the fixing thereof onto a printed circuit and two shielded linking cables, each linked to a pin. | 2009-08-06 |
20090197434 | Radio Frequency Connector - An RF connector includes an RF connector block including a body portion having a plurality of dividers projecting from a surface thereof with each of the dividers having a first surface configured to mate with an RF circuit board and having a second sloped surface. The RF connector block also includes a plurality of signal contacts disposed between each of the plurality of dividers with a first portion of each of the plurality of signal contacts disposed to mate with the RF circuit board and a second portion of each of the signal contacts disposed through an opposite side of the RF connector block. A plurality of RF connector receptacles are configured to mate with the second portion of a corresponding one of said plurality of signal connectors. Such an arrangement results in an RF connector having signal contacts highly isolated from each other. | 2009-08-06 |
20090197435 | PRINTED CIRCUIT BOARD DIRECT CONNECTION AND METHOD OF FORMING THE SAME - A system for directly connecting multiple printed circuit boards (PCB) circuits without the need for peripheral connectors. Multiple PCBs are electrically and mechanically interfaced with one or more plated holes or tabs on at least one first PCB and one or more plated tabs or holes on at least one second PCB. The plated tab(s)/hole(s) from said second PCB mate with the corresponding plated tab(s)/hole(s) from said first PCB to form a mechanical and electrical interconnect. | 2009-08-06 |
20090197436 | NON-INTRUSIVE INTERPOSER FOR ACCESSING INTEGRATED CIRCUIT PACKAGE SIGNALS - Disclosed is an interposer for accessing one or more signals from an Integrated Circuit (IC) package. The interposer is disposed between the IC package and a socket body. The interposer comprises a plurality of clearance holes and at least one connecting element. The plurality of clearance holes allows an array of contacts on a first surface of the socket body to pass through the interposer and make electrical contact with a first set of contacts of a plurality of contacts of the IC package. The at least one connecting element is configured to make electrical contact with a second set of contacts of the plurality of contacts of the IC package. The electrical contact between the at least one connecting element and the second set of contacts of the plurality of contacts of the IC package provides access to the one or more signals from the IC package. | 2009-08-06 |
20090197437 | SOCKET, METHOD FOR MANUFACTURING SOCKET, AND SEMICONDUCTOR DEVICE - A socket includes an insulating elastomeric sheet having a penetration hole, metal circuits formed on at least one of the front and rear surfaces of the elastomeric sheet, and a through-hole having a metal film formed on an inner wall of the penetration hole. The metal circuit on the front surface of the elastomeric sheet is electrically connected to the metal circuit on the rear surface of the elastomeric sheet via the through-hole. With such a configuration of the socket, it is possible to provide a socket contact terminal and a semiconductor device having the same, which is suitable for low-resistance, large-current, and high-speed configurations. | 2009-08-06 |
20090197438 | Cable assembly with an organizer for adjusting the cable outlet - A cable assembly comprises an insulative housing defining a main body portion with a front face, an upper and a lower tongue portion respectively extending forwardly from a top and bottom side of the front face, and the main body portion defining a base section and an organizer angled with the base section, and the insulative housing defined by an upper cover and a lower cover engaged with the upper cover; a printed circuit board disposed in the insulative housing and defining a mating portion extending forwardly from the front face of the insulative housing and disposed between the upper and lower tongue portion and a rear portion opposite to the mating portion thereof; and a cable terminated to the rear portion of the printed circuit board and extending out of the insulative housing along the organizer of the insulative housing. | 2009-08-06 |
20090197439 | ELECTRICAL PRESS-IN CONTACT - The present invention relates to an electrical press-in contact, particularly press-in pin con-tact, for transmitting electric current and/or electrical signals, comprising a press-in section and a mounting section which are mechanically coupled with each other via a relief section, and the relief section comprises a compensating portion and a stop portion, wherein the compensating portion allows a coupled relative movement of the press-in section and the mounting section, and the stop portion blocks a movement of press-in section and mounting section towards each other. | 2009-08-06 |
20090197440 | Board to Board Connector - A board mounted connector for a board to board connector system is disclosed which can be smaller, provide a more robust connection to a conductive circuit on a printed circuit board while allowing for a high degree of circuit design freedom on the board circuit due to the terminal insertion from the mating side of the housing where the terminals are generally above a bottom portion ( | 2009-08-06 |
20090197441 | CONNECTOR - A connector which is capable of preventing degradation of transmission, and achieving downsizing. Contact portions of first and second signal contacts, and contact portions of ground contacts are arranged in a row in a contact arranging direction. Contact portions of contacts for non-high-speed transmission are arranged in a row in the contact arranging direction. The row formed by the contact portions of the first and second signal contacts, and the contact portions of the ground contacts, and the rows formed by the contact portions of the contacts for non-high-speed transmission are parallel. The contact portions of each pair of first and second signal contacts are disposed between the contact portions of adjacent ones of the ground contacts in the contact arranging direction. | 2009-08-06 |
20090197442 | Electronic assembly with foldable connector - An electronic assembly ( | 2009-08-06 |
20090197443 | Electronic assembly with foldable connector - An electronic assembly ( | 2009-08-06 |
20090197444 | Protection Cap and Combination of a Connector and a Protection Cap - The invention relates to a protection cap for protecting at least a portion of leads of a connector. The comprises a top surface (T) and a bottom surface (B) and side walls (S) joining said top surface and bottom surface. The to surface has a first series of openings elongated in a first direction (I) and the bottom surface has a second series of openings elongated in a second direction (II). The opening of the second series are each arranged to receive at least portions of one or more of said leads when said cap is positioned over said leads. The first direction of said first series of openings makes an angle with said second direction of said second series of openings. The invention further relates to a combination of a protection cap and a connector and to a method for mounting a connector on a substrate. | 2009-08-06 |
20090197445 | Card Connector - A card connector for inserting a card therein is disclosed. The card connector includes a housing body having a contact, a cover covering the housing body, a slider being movable between a card ejected position and a card attached position. The slider includes a slider body and a leaf spring part attached to the slider body for elastically locking to the card. The card connector includes an excess bending preventing part configured to prevent permanent deformation of the leaf spring part by the card being inserted into the card connector in an irregular manner. | 2009-08-06 |
20090197446 | HIGH DENSITY COAXIAL JACK - A coaxial switching jack with a pair of coaxial assemblies mounted within a housing having a pair of front cable connection locations is disclosed. The coaxial assemblies each include a center conductor and an outer shield conductor. The center conductors are connected by a first spring and the shell conductors are connected by a second spring. Insertion of a coaxial cable connector within one of the front cable connection locations deflects the springs from the corresponding coaxial assembly and disconnects the center and shell conductors of the two assemblies. The jack may also be configured to provide an electrical connection between the center and shell conductors of the second coaxial assembly if a coaxial cable connector is inserted within the first coaxial assembly. The connection between the center and shell conductors of the second coaxial assembly may be through a resistor assembly allowing for selection of a desired electrical impedance. | 2009-08-06 |
20090197447 | CONNECTOR ARRANGEMENT WITH PENETRATOR IN A SUBMERSIBLE ELECTRICAL ASSEMBLY - A connector arrangement in a submersible electrical assembly including an electric equipment or electrical power consumer housed in an enclosure filled with conductive fluid. Power is supplied to the power consumer in a connecting area defined through a dielectric containment located inside the enclosure, and to a penetrator comprising power cable termination components enclosed in a penetrator housing extending from a rear end to a forward end of the penetrator. The rear end is arranged to seal about a power cable receivable in the housing from the rear end. The forward end exposes a connector arranged for electrically connecting the power consumer to the penetrator. The penetrator housing in the forward end is extended beyond the connector through a housing section projecting into the power consumer enclosure and terminated in a forward end by an end wall. The end wall has a passage sealable about a power consumer conductor mateable with the connector of the penetrator in a connecting mode. | 2009-08-06 |
20090197448 | COMBINED-TYPE CONNECTOR - The present invention provides a combined-type connector that can enhance the ability to receive an end of each of terminal metal fittings and can prevent reduction in the contact margin between terminal metal fittings to thereby improve the performance of the combined-type connector. | 2009-08-06 |
20090197449 | Electrical connector - An electrical connector for a flat conductive member include a housing; a first terminal including a first fixing arm portion, a first movable arm portion, and a first connecting portion; a second terminal including a second fixing arm portion, a second movable arm portion, and a second connecting portion; and a pressing member for pressing a first pressure receiving portion and a second pressure receiving portion so that the first pressing portion and the second pressing portion press the flat conductive member. The pressing member includes a cam portion having a small radius cam portion and a large radius cam portion. The small radius cam portion contacts with the first pressure receiving portion when the pressing member is situated at the open position. The large radius cam portion presses the first pressure receiving portion and the second pressure receiving portion when the pressing member is situated at the closed position. | 2009-08-06 |
20090197450 | CONNECTOR - The present invention provides a connector having a seal member for sealing around an electrical wire. The connector includes a connector housing, the seal member, and a rear holder. The connector housing has a layer-by-layer arrangement of plate-shaped housings which each have terminal receiving channels to receive terminals. The seal member has a seal main body surrounding the electrical wire and a tube portion projecting from the seal main body in the lengthwise direction of the electrical wire. The rear holder includes a plurality of holders to pinch the tube portion of the seal member. Each holder has a groove to pinch the tube portion of the seal member and the groove compresses an inner diameter of the tube portion when the holders pinch the tube portions therebetween. | 2009-08-06 |
20090197451 | CAP FOR TELECOMMUNICATIONS CROSS CONNECT BLOCK - An electrical connector assembly for terminating first and second electrical wires, the electrical connector assembly comprising a housing including a compartment for receiving first and second IDC elements and a cap movably mounted to the housing to cover the compartment. The cap is movable between an open position and a closed position. The cap includes a general body portion, a wire retention portion, and a latching mechanism. The wire retention portion includes first and second wire holders to retain and align the respective electrical wires within the housing for engagement with a gripping portion of the respective IDC element when the cap is placed in a closed position. The gripping force of the wire holders is less than a gripping force of the IDC elements. The latching mechanism can releasably fasten the cap to the housing when the cap is placed in a closed position. When the cap is returned to an open position after the cap was placed in the closed position, the first and second wires are retained by the first and second IDC elements and the first and second wire holders disengage the first and second wires from the cap. | 2009-08-06 |
20090197452 | Electrical Connector - An electrical connector for accepting an edge of a circuit board having a notch and a plurality of circuit board electrical contacts disposed on the edge is disclosed. The electrical connector has an insulative housing that accepts the edge of the circuit board. A positioning protrusion is formed on the insulative housing and is at least partially receivable within the notch of the edge of the circuit board. A plurality of contacts are carried by the insulative housing and contact the circuit board electrical contacts. The positioning protrusion has a lower portion that is less than or the same thickness as a width of the notch, an upper portion that is thicker than the width of the notch, and a middle portion connecting the upper portion and lower portion, where the middle portion having a thickness that changes symmetrically. | 2009-08-06 |
20090197453 | CONNECTOR FOR CARD - A connector for a card includes first contact terminals that come in contact with first outer connection parts of a card to be fitted, and second contact terminals that come in contact with second outer connection parts of the card. Contact parts of the first contact terminals that come in contact with the first outer connection parts, and contact parts of the second contact terminals that come in contact with the second outer connection parts are formed to face directions orthogonal to each other. | 2009-08-06 |
20090197454 | Electrical connector having a pair of load levers - An electrical connector mounted to a printed circuit board for receiving an IC package is provided that includes an insulative housing ( | 2009-08-06 |
20090197455 | Device for electrical connection of discontinuous conductors - A device for electrical connection of discontinuous conductors, extending in a longitudinal direction, comprising a body made of insulating material inside which is disposed a conductor element provided with means adapted to come into contact with the conducting part of at least one respective discontinuous conductor, said body having guides for sliding of a respective slider provided with at least one relative seat extending parallel to said longitudinal direction and adapted to contain a portion of the relative discontinuous conductor, said slider being movable from a first position of extraction from the body to a second position of insertion inside said body. | 2009-08-06 |
20090197456 | SERVICE PLUG - A service plug includes: a base member in which a circuit terminal adapted to be connected to an electric circuit is provided and an open hole is formed in such a manner as to face the circuit terminal; a plug body comprising a short-circuit terminal adapted to be inserted into the circuit terminal; and a restricting member provided in the vicinity of the open hole of the base member for restricting movement of the plug body in a direction which intersects an inserting direction of the short-circuit terminal. | 2009-08-06 |
20090197457 | Key coded power adapter connectors - A key coded power connector and a system and method for making key coded power connections are disclosed. A power connector such as a power adapter connector is configured with either a visual keying system, a physical keying system, or both. The physical keying system prevents a user from connecting a host device to a connector of the power source which does not support that host device. The visual keying system provides the user with an early indication that the particular device is not supported by a power source. The user can visually compare a marking key on the host device with the making key on the power connector and determine whether or not the power source is capable of outputting sufficient power to operate the device. The visual and physical keying systems prevents a user from improperly connecting a host device to a power source which does not support that device. | 2009-08-06 |
20090197458 | Method and Apparatus for Patch Panel Patch Cord Documentation and Revision - A method and apparatus are provided for monitoring and reporting cable connectivity such as patch panel port-level connectivity on a real-time basis. For patch panel systems, the approach is based upon a distributed architecture that may be modularly scalable and may reduce, if not eliminate, the need for a centralized signal processor and complex cabling between patch panels and the centralized signal processor. Each patch panel may determine port level connectivity independently. Polling delays and polling-related overhead processing may be reduced or eliminated by supporting real-time monitoring of port connectivity at the port level. The approach provides improved real-time reporting of patch panel connectivity with reduced cabling complexity, increased reliability, and decreased maintenance costs. In addition, the approach is compatible with (i.e., may communicate with and be controlled by) a multipurpose network management system (NMS). In addition, a compatible revision system is provided. | 2009-08-06 |
20090197459 | Cable connector assembly having wire management members with low profile - A cable connector assembly ( | 2009-08-06 |
20090197460 | MALE MEDICAL DEVICE ELECTRICAL CONNECTOR WITH ENGINEERED FRICTION FIT - A male connector, including: a body having a proximal end and a distal end; and an elastomeric member disposed around an outer surface of the distal end of the body, wherein the distal end of the body is configured to be received into a female connector interface in a medical device, and wherein the proximal end of the body is configured to receive an electronic block connector therein. | 2009-08-06 |
20090197461 | Plug Tail Lighting Switch and Control System - The present invention is directed to an electrical wiring system for use in an AC electrical power distribution circuit including at least one first AC power conductor disposed between an upstream AC power element and a device box and at least one second AC power conductor disposed between the device box and a downstream AC power element. The at least one first AC power conductor and the at least one second AC power conductor are routed into an interior portion of the device box and accessible via a front open face of the device box. The system includes a connector device including a connector housing having a plurality of connector contacts disposed therein. | 2009-08-06 |