| 31st week of 2010 patent applcation highlights part 68 |
| Patent application number | Title | Published |
|---|
| 20100198984 | Method and System for Transparent TCP Offload with Best Effort Direct Placement of Incoming Traffic - Certain aspects of a method and system for transparent transmission control protocol (TCP) offload with best effort direct placement of incoming traffic are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) processor without transferring state information to a host processor every time a TCP segment is received. When an event occurs that terminates the collection of TCP segments, the NIC processor may generate a new aggregated TCP segment based on the collected TCP segments. If a placement sequence number corresponding to the generated new TCP segment for the particular network flow is received before the TCP segment is received, the generated new TCP segment may be transferred directly from the memory to the user buffer instead of transferring the data to a kernel buffer, which would require further copy by the host stack from kernel buffer to user buffer. | 2010-08-05 |
| 20100198985 | AUTOMATIC NETWORK CLUSTER PATH MANAGEMENT - Automatic network configuration of cluster paths to access data within a cluster is described. Each node of the cluster presents to clients an image of the cluster as a single system. Each node also stores information regarding what node has particular data, as well as information about network addresses and corresponding network capabilities for the various network addresses for each node. When a node receives a request for data, the node determines a node where the request data can be accessed, determines network addresses and network capabilities for each network address of the node, and selects a path to access the node based on the determined information. The receiving node may select the path based on network type and capability, as well as load and performance of the network. | 2010-08-05 |
| 20100198986 | NETWORK STORAGE DEVICE COLLECTOR - Embodiments of the invention relate to systems, methods, and computer program products for remotely collecting data stored by a user in one or more network storage areas residing on a network. For example, embodiments of the method involve utilizing a mapping tool to identify at least one network storage area associated with the user, utilizing a collection tool to access at least one network storage area via a network, copying the data stored on the at least one network storage area, and transmitting the data from the at least one network storage area to a collection server. | 2010-08-05 |
| 20100198987 | STORAGE SYSTEM, PATH MANAGEMENT METHOD AND PATH MANAGEMENT DEVICE - Proposed are a storage system, a path management method and a path management device capable of ensuring the processing performance demanded by a user while seeking to improve the access performance from a host system to a storage apparatus. Path switching control for dynamically switching the path to be used by the host system according to the loaded condition of the respective paths between the host system and the storage apparatus is executed; and a path is selected as needed according to a policy containing path switching rules created by a user, and path switching control for excluding the selected path from the target and dynamically switching the path to be used by the host system is executed. | 2010-08-05 |
| 20100198988 | METHODS FOR USING THE ADDRESSING, PROTOCOLS AND THE INFRASTRUCTURE OF EMAIL TO SUPPORT NEAR REAL-TIME COMMUNICATION - A method of implementing late binding of time-based media that can be rendered in near real-time by a recipient when transmitted over a communication network. The method involves addressing a message to a recipient using an address associated with the recipient and progressively creating time-based media associated with the message. When the address of the recipient is defined, the method uses the address to define an active delivery route for the delivery of time-based media associated with the message in near real-time to the recipient. When the active delivery route is discovered and is available, the method further involves progressively and simultaneously transmitting to the recipient the created time-based media associated with the message as the time-based media is being created. | 2010-08-05 |
| 20100198989 | ASSIGNING PRIORITY TO NETWORK TRAFFIC AT CUSTOMER PREMISES - A device may receive a message from a client device and determine whether the message includes particular data. The device may identify an address within a particular address group when the message includes the particular data. The traffic associated with addresses within the particular address group are assigned priority over traffic associated with addresses outside the particular address group. The device may provide the identified address to the client device so that traffic associated with the client device receives priority over other traffic | 2010-08-05 |
| 20100198990 | MULTI-POINT CONNECTION DEVICE, SIGNAL ANALYSIS AND DEVICE, METHOD, AND PROGRAM - Provided is a multi-point connection device including: a first signal receiving unit which receives a first signal containing a plurality of constituent elements and first analysis information expressing the relationship between the constituent elements contained in the first signal; a second signal receiving unit which receives a second signal containing a plurality of constituent elements and second analysis information expressing the relationship between the constituent elements contained in the second signal; a signal mixing unit which mixes the first signal and the second signal; and an analysis information mixing unit which mixes the first analysis information and the second analysis information. | 2010-08-05 |
| 20100198991 | DUPLEXED FIELD CONTROLLER - There is provided a duplexed field controller. The duplexed field controller includes: first and second control units between which a control authority is switchable; a first application clock that is updated based on a reference clock so as to define a timing of an application operation of the first control unit; a second application clock that is updated based on the reference clock so as to define a timing of an application operation of the second control unit; and an update control unit that bypasses the first update of the second application clock after switching of the control authority, if the first application clock is ahead of the second application clock when the control authority is switched from the first control unit to the second control unit. | 2010-08-05 |
| 20100198992 | Synchronization of audio and video signals from remote sources over the internet - The present invention is an architecture and technology for a method for synchronizing multiple streams of time-based digital audio and video content from separate and distinct remote sources, so that when the streams are joined, they are perceived to be in unison. | 2010-08-05 |
| 20100198993 | TERMINAL DEVICE, PERIPHERAL DEVICE, AND WRITE PROGRAM - A terminal device | 2010-08-05 |
| 20100198994 | System and method for virtualizing the peripherals in a terminal device to enable remote management via removable portable media with processing capability - Systems and methods for virtualizing the peripherals in a wireless device to enable remote management via removable portable media with processing capability are described. One aspect may include a system for virtualizing a peripheral device of a wireless device from a media device, the system comprising a media device, including a first memory; a processor coupled to said first memory; and a virtualization device controller interface remote layer adapted to run on said processor and first memory, wherein said virtualization device controller interface remote layer is adapted to communicate with a peripheral device of the wireless device. | 2010-08-05 |
| 20100198995 | HOST APPARATUS AND INFORMATION PROCESSING SYSTEM USING THE SAME - In an information processing system, a host apparatus and a device are communicatively connected such that the host apparatus serves as a master and the device serves as a slave. The device is configured to establish a power-saving mode, when any command is not received from the host apparatus for a prescribed time period. A device driver is provided in the host apparatus. The device driver is configured to transit from a normal state to a suspended state when an operation command for operating the device is not received from an application running in the host apparatus for a prescribed time period, and to transmit a dummy response to the application, when an inquiry command is received from the application while the device driver is placed in the suspended state, without notifying the inquiry command to the device. | 2010-08-05 |
| 20100198996 | MANAGEMENT DEVICE AND COMPUTER READABLE MEDIUM - A management device for managing a device has: a control unit including: a status acquiring unit that acquires a status of the device; and a notifying unit that, if the device is in a specific status, notifies information about the specific status to another device; and a first management screen supply unit supplying first management screen data to a display unit, wherein the control unit determines whether a notifying function of the notifying unit is valid or invalid, if the notifying function is valid, the control unit controls the status acquiring unit to periodically acquire the status of the device regardless of whether the first management screen supply unit starts up, and if the notifying function is invalid, the control unit controls the status acquiring unit to acquire the status of the device when the first management screen supply unit starts up in response to an instruction from a user. | 2010-08-05 |
| 20100198997 | Direct Memory Access In A Hybrid Computing Environment - Direct memory access (‘DMA’) in a hybrid computing environment that includes a host computer, an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where DMA includes identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol; segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments; pinning, by the system level message passing module, the memory segments against paging; and asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator. | 2010-08-05 |
| 20100198998 | I/O CONTROLLER AND DESCRIPTOR TRANSFER METHOD - An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit. | 2010-08-05 |
| 20100198999 | METHOD AND SYSTEM FOR WIRELESS USB TRANSFER OF ISOCHRONOUS DATA USING BULK DATA TRANSFER TYPE - A method and system for transferring data in a wireless USB system having a first USB enabled device and a second USB enabled device are provided. The method includes providing a first data having a first data transfer type, converting the first data to a second data having a second data transfer type, wirelessly transferring the second data from the first USB enabled device to the second USB enabled device using the second data transfer type, and converting the wirelessly transferred second data to a third data having the first data transfer type. | 2010-08-05 |
| 20100199000 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A data storage device including a main body and a storage element is provided. The main body has a first connecting part and a second connecting part, suitable for being connected to a first electronic device and a second electronic device, respectively. The storage element is disposed at the main body and is electrically connected to the first connecting part and the second connecting part, wherein the data storage device is suitable for receiving data from the first electronic device, and the data is stored in the storage element, or is transmitted to the second electronic device, or the data is stored in the storage element and is transmitted to the second electronic device. In addition, an operating method of the data storage device is also provided. | 2010-08-05 |
| 20100199001 | SUBSTRATE PROCESSING SYSTEM - Provided is a substrate processing system configured to provide proper data. The substrate processing system comprises a substrate processing apparatus comprising a plurality of components, a controller configured to control the substrate processing apparatus by setting a sequence prescribing time and components, and a collection unit configured to collect data from the components. The collection unit is configured to match data collected from the components via the controller with data collected directly from the components. | 2010-08-05 |
| 20100199002 | INDUSTRIAL CONTROLLER - This invention realizes a synchronization control function without providing a bus dedicated for synchronization control by using a bus (system bus) used to transmit and receive data between units from the prior art. When a timer interruption occurs during the execution of a process performed in a normal cyclic, a CPU unit interrupts the process and transmits synchronization data by collective addressing using the system bus to other synchronization units performing the synchronization control. The synchronization unit executes a synchronization cycle upon the reception of the synchronization data by collective addressing as a trigger, acquires the received synchronization data with the start of the synchronization cycle, and performs a refresh process of the synchronization data of IN data after executing an input/output process. The CPU unit performs the refresh process of the synchronization data of the IN data, and obtains the synchronization data to be transmitted next by a synchronization interrupt task process. The synchronization unit constantly acquires the most recent synchronization data and simultaneously operates. | 2010-08-05 |
| 20100199003 | FIELD CONTROL SYSTEM - The field control system includes: a field device; a field controller which is connected to a control network and which executes a computation processing for controlling the field device according to a given control cycle while executing a data communication between the field controller and the field device, the field controller including a communication unit configured to execute the data communication with the field device, and a control computation unit configured to execute the computation processing independently from the communication unit; and an operation monitor which is connected to the control network and which operates and monitors the field device, the operation monitor including a network clock which provides a common network time to the control network. The control computation unit and the communication unit execute the computation processing and the data communication in synchronism with each other in accordance with a timer clock based on the network time. | 2010-08-05 |
| 20100199004 | COMMUNICATION METHOD IN A MRI SYSTEM - In a method of communication on a multidrop bus of a magnetic resonance system, an adaptive protocol script for telegrams on the multidrop bus is used, that implements adaptive protocol matching using telegram start characters, addresses and frame-type binding. For this purpose, a telegram frame is divided into a link layer and a service layer, the link layer being device-based and being responsible for differentiating addresses and frame types, and enabling devices that use different communication protocols to be simultaneously present on the bus. The service layer represents the load of the link layer, and its service script is operation-based, and the service layer provides, for the exterior, interfaces that are independent of the communication protocols used by the devices. | 2010-08-05 |
| 20100199005 | COMMUNICATION INTERFACE CIRCUIT, ELECTRONIC DEVICE, AND COMMUNICATION METHOD - According to one embodiment, an interface comprises establishing a connection to a communicatee device, transmitting a connection maintenance signal to the communicatee device, and decreasing a maximum amplitude of the connection maintenance signal from a first amplitude, establishing a connection to the communicatee device again when communication is disabled, and transmitting the connection maintenance signal to the communicatee device, and setting the maximum amplitude of the connection maintenance signal to a second amplitude which is larger than the maximum value of the connection maintenance signal obtained when the communication is disabled by a predetermined value. | 2010-08-05 |
| 20100199006 | DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A master (LSI | 2010-08-05 |
| 20100199007 | Direct Slave-to-Slave Data Transfer on a Master-Slave Bus - A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a source for a read operation, configure the second slave device as a target for a write operation, provide a clock signal to both the first slave device and the second slave device, and initiate a read operation of the first slave device. Initiation of the read operation causes the first slave device to provide data onto the peripheral bus. Responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device. The master device is configured to ignore the data provided on the peripheral bus by the first slave device. | 2010-08-05 |
| 20100199008 | System and method for implementing a remote input device using virtualization techniques for wireless device - Systems and methods for implementing a remote input device using virtualization techniques for wireless devices are described. In one aspect, the system may comprise a wireless device that includes a processor, a memory, input hardware, and a protocol slave adapted to communicate with the input hardware; and a removable media device that includes a memory, a processor, and a protocol master adapted to communicate with the protocol slave of the wireless device. In another embodiment, the method may comprise emulating a hardware interface on a removable media device; mapping input hardware of a wireless device to the interface; mapping a processor of the media device to the input hardware; wrapping and sending input hardware commands from a protocol master of the media device to a protocol slave of the wireless device; and executing the commands on the input device. | 2010-08-05 |
| 20100199009 | SERIAL DATA COMMUNICATION SYSTEM AND SERIAL DATA COMMUNICATION METHOD - When transmitting serial data from a master device to a slave device, it is possible to promptly detect a communication error if any occurs. Serial data transmitted from the master device to the slave device has two or more continuous bytes of dummy data having an identical structure. When the slave device recognizes the dummy data, communication error processing is executed. Assume that the serial data is shifted by an affect of a noise. In this case, “a text end control code (ETX)” is also shifted and the serial data cannot be recognized and no data reception end process is executed. However, during a period after this, a part of the first dummy data and a part of the second dummy data are received and one dummy data is recognized. Thus, the slave device can promptly execute the communication error processing. | 2010-08-05 |
| 20100199010 | DEVICE HAVING PRIORITY UPGRADE MECHANISM CAPABILITIES AND A METHOD FOR UPDATING PRIORITIES - A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests. | 2010-08-05 |
| 20100199011 | Adaptable Hardware-Programmable Transmission Interface for Industrial PCs - An adaptable hardware-programmable transmission interface for an industrial PC is characterized by a module switch provided on a motherboard of the industrial PC, and a plurality of riser cards, each of which is connectable to a connecting end of the motherboard and formed with one or a plurality of slots having a variety of specifications, allowing the motherboard to be significantly downsized. In addition, the same motherboard can be connected with a selected one of the different riser cards to provide lane interfaces that meet various dynamic changing needs. | 2010-08-05 |
| 20100199012 | System for connecting an external device to a serial flexray data bus - A system for connecting an external device to a serial FlexRay data bus using which data are transmitted over two data lines as a voltage difference signal, the external device being decoupled from the serial FlexRay data bus by an active star circuit to preserve the signal integrity of the voltage difference signal. | 2010-08-05 |
| 20100199013 | System and Method for Coupling a LTH HH Tape Device with a Serial Attached SCSI Connection to a SAS-Cable - A method, system and apparatus for efficiency coupling a LTO HH tape drive device having a Serial Attached SCSI connector to a SAS-Cable. The method for coupling a LTO HH tape drive device having a Serial Attached SCSI connector to a SAS-Cable includes employing an adapter having a structure featuring an offset between the centerlines of the LTO side and the SAS-Cable side. The method also includes reducing the overmold structure of the adapter on the SAS Cable Side of the adapter to prevent interference from excess structure contained on the connector during the insertion of the SAS Cable as well as enhancing the overmold structure of the adapter on the LTO drive side of the adapter to facilitate a secure grip on the adapter. The method further includes offsetting the centerlines of the LTO side and the SAS-Cable side to enhance the applicability of the adapter to a wide range of SAS-Cables and guiding the insertion of the adapter into a LTO drive via insertion guide pins to prevent the damage to the adapter pins on the LTO drive side of the adapter. | 2010-08-05 |
| 20100199014 | Microcontroller Peripheral Event Distribution Bus - A method and apparatus for distributing events. In one embodiment, the method includes a bus concurrently transmitting a first event-signal and a first event-identification (event-ID); wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur. The first event-ID corresponds to the first event-signal. | 2010-08-05 |
| 20100199015 | SYSTEM AND METHOD FOR IDENTIFYING DATA STREAMS ASSOCIATED WITH MEDICAL EQUIPMENT - A system and method for uniquely identifying data streams associated with medical equipment are described. The system may be implemented in a variety of ways, including as a combination of a medical device, a data stream identifier, and a medical device identifier. The medical device generates a plurality of data streams. The data streams are uninterrupted transmissions of data from the medical device. The data streams include information regarding the operation of the medical device. The data stream identifier attaches a unique data tag to the data streams. The medical device identifier is configured to generate a medical device tag. The 10 medical device tag includes information to uniquely identify the medical device and is accessible from an external computer. The data stream identifier and the medical device identifier are secured to the medical device. | 2010-08-05 |
| 20100199016 | DEVICE FOR WIRLESS TRANSMISSION OF DIGITAL INFORMATION - Disclosed is to a USB device for receiving data from other data transmitting devices. The inventive USB device comprises a printed circuit board having a microprocessor and memory, a USB controller connected to the microprocessor, a USB connector connected to the printed circuit board, and wireless receiving means connected to the printer circuit board for receiving external data to be stored in the memory. The data stored in the memory include, but are not limited to, unique identifiers from external devices. The inventive USB device may further comprise means for transmitting data from the device to external devices. The inventive USB has a power source to provide power for it to work for an extended period of time. The above inventive USB device may further provide means for a user to initiate the device to transmit the ID to other receiving devices within the proximity. | 2010-08-05 |
| 20100199017 | Data Encoding Using Spare Channels in a Memory System - Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI. | 2010-08-05 |
| 20100199018 | DATA TRANSFER SYSTEM, DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, AND DATA TRANSFER METHOD - A data transfer system transmitting and receiving data through a first transmission path and a second transmission path, the data transferring system includes a first apparatus that transmits data through the first transmission path and a second apparatus that receives the data from the first apparatus through the first transmission path, the second apparatus transmits error bit information about the bit position of an error, wherein when the first apparatus receives the error bit information from the second apparatus, the first apparatus transmits switching bit information concerning the bit position which is identified by the error bit information and the transmission path of which is switched to the second transmission path and the data on the bit position identified by the error bit information to the second apparatus through the second transmission path, and the second apparatus receives the data on the bit position identified by the switching bit information. | 2010-08-05 |
| 20100199019 | LOGICAL MEMORY BLOCKS - The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T. | 2010-08-05 |
| 20100199020 | NON-VOLATILE MEMORY SUBSYSTEM AND A MEMORY CONTROLLER THEREFOR - In the present invention a non-volatile memory subsystem comprises a non-volatile memory device and a memory controller. The memory controller controls the operation of the non-volatile memory device with the memory controller having a processor for executing computer program instructions for partitioning the non-volatile memory device into a plurality of partitions, with each partition having adjustable parameters for wear level and data retention. The memory subsystem also comprises a clock for supplying timing signals to the memory controller. | 2010-08-05 |
| 20100199021 | Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down. | 2010-08-05 |
| 20100199022 | INFORMATION ACCESS METHOD WITH SHARING MECHANISM AND COMPUTER SYSTEM - An information access method and a computer system are provided. The computer system includes a system management bus (SMBus), a non-volatile memory, a plurality of hardware devices, a chipset, and a CPU. The hardware devices have a plurality of specific recognition information. The CPU performs a configuration process on the hardware devices through the chipset according to the standard for a SMBus protocol, so as to distribute a plurality of memory spaces in the non-volatile memory to the hardware devices. The hardware devices share the SMBus for accessing the plurality of specific recognition information in the memory spaces. | 2010-08-05 |
| 20100199023 | APPARATUS AND METHOD FOR MANAGING MEMORY - A memory management method and apparatus are disclosed. The memory management apparatus may compute a remaining storage capacity of a flash memory based on a number of bad blocks in a flash memory or a number of block-erases of each of a plurality of blocks, and may display the computed remaining storage capacity of the flash memory. | 2010-08-05 |
| 20100199024 | METHOD AND APPARATUS FOR MANAGING DATA OF FLASH MEMORY VIA ADDRESS MAPPING - A method of managing data of a flash memory is provided. The method comprises: assigning a logical area of the flash memory as a user block area in which user storage data is stored, and a free block area in which the user storage data is temporarily stored when changing the user storage data; and, when a first data unit of user storage data received from a host is different from a second data unit used while mapping a physical address and a logical address of the flash memory where the user storage data is stored, assigning a predetermined logical area of the flash memory as a cache block area in which the user storage data received from the host is temporarily stored. | 2010-08-05 |
| 20100199025 | MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM - A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit. | 2010-08-05 |
| 20100199026 | Flash File System and Driving Method Thereof - The present invention discloses a flash file system and drive method thereof, characterized in that, after reception of an access function, it verifies the parameters in the access function and analyzes the file name of the file to be accessed included therein, then queries the starting position of the file to be accessed, and finally controls a physical driver module to access data from the flash according to the starting position and such parameters. The flash file system according to the present invention does not require FAT (File Allocation Table) file system and block interface, thereby simplifying the complexity of file system and enhancing system performance. | 2010-08-05 |
| 20100199027 | SYSTEM AND METHOD OF MANAGING INDEXATION OF FLASH MEMORY - The invention is a system of managing indexation of memory. Said system has a microprocessor, and a flash memory. Said flash memory has an indexed area comprising indexed items, and an index that is structured in a plurality of index areas comprising a plurality of entries. Said flash memory comprises an index summary comprising a plurality of elements. Each index summary element is linked to an index area of said index. Each index summary element is built from all entries belonging to said linked index area and is built using k hash functions, with 1≦k. | 2010-08-05 |
| 20100199028 | Non-volatile storage device with forgery-proof permanent storage option - The invention is related to non-volatile storage devices. | 2010-08-05 |
| 20100199029 | Storage device, computer system, and data writing method - A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data. | 2010-08-05 |
| 20100199030 | METHOD OF MANAGING FLASH MEMORY ALLOCATION IN AN ELECTRONI TOKEN - The invention is a method of managing flash memory-allocation in an electronic token. Said token has a memory comprising a list area and a managed area. Said managed area comprises allocated spaces and at least one free memory chunk. Said list area comprises at least one valid entry referencing a free memory chunk. Said valid entry comprises a state field. Said method comprises the step of selecting a free memory chunk further to an allocation request where said free memory chunk is referenced by an old entry, and the step of identifying a new allocated space in the selected free memory chunk. The state field of said valid entry is preset with a virgin state. Said method comprises the step of invalidating the old entry referencing the selected free memory chunk. | 2010-08-05 |
| 20100199031 | SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE OF AN ELECTRONIC DEVICE - The invention relates to a system and method for controlling implementation of a command to a NAND memory device. The method comprises: monitoring an input/output (I/O) bus connected to the NAND memory device for an assertion of a write command for the NAND memory device. Upon detection of the write command, the method evaluates a destination address associated with the write command. If the destination address is not a restricted address for the NAND memory device, then the method allows the write command to modify the contents; and if the destination address is a restricted address for the NAND memory device, then the method prevents assertion of the write command on the contents. | 2010-08-05 |
| 20100199032 | ENHANCED DATA COMMUNICATION BY A NON-VOLATILE MEMORY CARD - A method of transmitting a stream of data bits from a memory card to a host device includes determining, at the memory card, a first number of data lines between the memory card and the host device, from one to a plurality of data lines. If the first number of data lines is determined to be a plurality of data lines, the method includes switching, at the memory card, the data stream between one of the first number of data lines and another of the first number of data lines after each occurrence of a second number of one or more bits of the data stream having passed toward the host device. The method also includes, if the first number of data lines is determined to be one data line, transmitting, from the memory card, the stream of data bits over the one data line to the host device. | 2010-08-05 |
| 20100199033 | SOLID-STATE DRIVE COMMAND GROUPING - A method and other embodiments associated with solid-state drive command grouping are described. In one embodiment, a first command and a second command are grouped into a command pack, where the first command and the second command do not share a common channel for execution. A solid-state drive is controlled to execute the command pack on the solid-state drive, where executing the command pack causes the first command and the second command to execute concurrently on separate channels. | 2010-08-05 |
| 20100199034 | METHOD AND APPARATUS FOR ADDRESS FIFO FOR HIGH BANDWIDTH COMMAND/ADDRESS BUSSES IN DIGITAL STORAGE SYSTEM - A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a pointer location of a read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available. | 2010-08-05 |
| 20100199035 | File server and file management method - A file server achieving sufficient power-saving effect is provided. The file server is capable of operating an on-line storage medium (in a state in which reading/writing can be started immediately in response to a file read/write request) and an off-line storage medium (which has to be started up upon receiving a read/write request). Upon reception of a stream file write request, the file server's processing unit acquires bit rate information from the stream file, calculates the file's splitting position from the bit rate information and startup time of the off-line storage medium, and stores a first part (up to the splitting position) in the on-line storage medium while storing the remaining second part in the off-line storage medium. Upon reception of a stream file read request, the processing unit reads out the first part while starting up the off-line storage medium and reading out the second part. | 2010-08-05 |
| 20100199036 | SYSTEMS AND METHODS FOR BLOCK-LEVEL MANAGEMENT OF TIERED STORAGE - Acceleration of I/O access to data stored on large storage systems is achieved through multiple tiers of data storage. An array of first storage devices with relatively slow data access rates, such as hard disk drives, is provided along with a smaller number of second storage devices having relatively fast data access rates, such as solid state disks. Data is moved from the first storage devices to the second storage devices to improve data access time based on applications accessing the data and data access patterns. | 2010-08-05 |
| 20100199037 | Methods and Systems for Providing Translations of Data Retrieved From a Storage System in a Cloud Computing Environment - A method for providing translations of data retrieved from a storage system in a cloud computing environment includes receiving, by an interface object executing on a first physical computing device, a request for provisioning of a virtual storage resource by a storage system. The interface object requests, from a storage system interface object, provisioning of the virtual storage resource. The interface object receives, from the storage system interface object, an identification of the provisioned virtual storage resource. The interface object translates the identification of the provisioned virtual storage resource from a proprietary format implemented by the storage system interface object into a standardized format by accessing an interface translation file mapping each of a plurality of proprietary formats with the standardized format. The interface object responds to the request received from the second physical computing device, with a translation of the received identification. | 2010-08-05 |
| 20100199038 | REMOTE COPY METHOD AND REMOTE COPY SYSTEM - In a configuration in which it is necessary to transfer data from a first storage system to a third storage system through a storage system between the storage systems, there is a problem that it is inevitable to give an excess logical volume to a second storage system between the storage systems. A remote copy system includes first storage system that sends and receives data to and from an information processing apparatus, a second storage system, and a third storage system. The second storage system virtually has a second storage area in which the data should be written and has a third storage area in which the data written in the second storage area and update information concerning the data are written. Data sent from the first storage system is not written in the second storage area but is written in the third storage area as data and update information. The data and the update information written in the third storage area are read out from the third storage system. | 2010-08-05 |
| 20100199039 | Systems and Methods for Optimizing Host Reads and Cache Destages in a Raid System - In one aspect, a method of a storage adapter controlling a redundant array of independent disks (RAID) may be provided. The method may include examining performance curves of a storage adapter with a write cache, determining if an amount of data entering the write cache of the storage adapter has exceeded a threshold, and implementing a strategy based on the determining operation. The strategy may include one of coupling Read-XOR/Write operations and providing priority reordering of Read operations over the Read-XOR/Write operations in order to minimize host read response time if data entering the write cache is less than the threshold, and allowing all Read operations and Read-XOR/Write operations to be queued at the device using simple tags in order to achieve maximum throughput if data entering the write cache is greater than the threshold. Additional aspects are described. | 2010-08-05 |
| 20100199040 | Storage Subsystem And Storage System Architecture Performing Storage Virtualization And Method Thereof - A method for generating a virtual volume (VV) in a storage system architecture. The architecture comprises a host and one or more disk array subsystems. Each subsystem comprises a storage controller. One or more of the subsystems comprises a physical storage device (PSD) array. The method comprises the following steps: mapping the PSD array into a plurality of media extents (MEs), each of the MEs comprises a plurality of sections; providing a virtual pool (VP) to implement a section cross-referencing function, wherein a section index (SI) of each of the sections contained in the VP is defined by the VP to cross-reference VP sections to physical ME locations; providing a conversion method or procedure or function for mapping VP capacity into to a VV; and presenting the VV to the host. A storage subsystem and a storage system architecture performing the method are also provided. | 2010-08-05 |
| 20100199041 | Storage Subsystem And Storage System Architecture Performing Storage Virtualization And Method Thereof - Method for accessing data in a storage system architecture, the architecture comprises at least one disk array subsystem, comprising the following steps. Provide a SAS for managing a first and a second media extent (ME) the at least one subsystem. Obtain a location index corresponding to a host LBA via a BAT. Obtain a location information of a physical section located in the first ME corresponding to the location index via a physical section to virtual section cross-referencing functionality. Update the cross-reference in the cross-referencing functionality so that the location information obtained from the cross-referencing functionality corresponding to the location index is the location information of the second physical section. A host IO request addressing the host LBA accesses data in the second physical section utilizing the location information of the second physical section. | 2010-08-05 |
| 20100199042 | SYSTEM AND METHOD FOR SECURE AND RELIABLE MULTI-CLOUD DATA REPLICATION - A multi-cloud data replication method includes providing a data replication cluster comprising at least a first host node and at least a first online storage cloud. The first host node is connected to the first online storage cloud via a network and comprises a server, a cloud array application and a local cache. The local cache comprises a buffer and a first storage volume comprising data cached in one or more buffer blocks of the local cache's buffer. Next, requesting authorization to perform cache flush of the cached first storage volume data to the first online storage cloud. Upon receiving approval of the authorization, encrypting the cached first storage volume data in each of the one or more buffer blocks with a data private key. Next, assigning metadata comprising at lest a unique identifier to each of the one or more buffer blocks and then encrypting the metadata with a metadata private key. Next, transmitting the one or more buffer blocks with the encrypted first storage volume data to the first online cloud storage. Next, creating a sequence of updates of the metadata, encrypting the sequence with the metadata private key and then transmitting the sequence of metadata updates to the first online storage cloud. | 2010-08-05 |
| 20100199043 | METHODS AND MECHANISMS FOR PROACTIVE MEMORY MANAGEMENT - A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed. The system includes mechanisms directed towards historical memory usage monitoring, memory usage analysis, refreshing memory with highly-valued (e.g., highly utilized) pages, I/O pre-fetching efficiency, and aggressive disk management. Based on the memory usage information, pages are prioritized with relative values, and mechanisms work to pre-fetch and/or maintain the more valuable pages in memory. Pages are pre-fetched and maintained in a prioritized standby page set that includes a number of subsets, by which more valuable pages remain in memory over less valuable pages. Valuable data that is paged out may be automatically brought back, in a resilient manner. Benefits include significantly reducing or even eliminating disk I/O due to memory page faults. | 2010-08-05 |
| 20100199044 | INTERFACE APPARATUS, CALCULATION PROCESSING APPARATUS, INTERFACE GENERATION APPARATUS, AND CIRCUIT GENERATION APPARATUS - There is provided is an interface apparatus including: a stream converter receiving write-addresses and write-data, storing the received data in a buffer, and sorting the stored write-data in the order of the write-addresses to output the write-data as stream-data; a cache memory storing received stream-data if a load-signal indicates that the stream-data are necessarily loaded and outputting data stored in a storage device corresponding to an input cache-address as cache-data; a controller determining whether or not data allocated with a read-address have already been loaded, outputting the load-signal instructing the loading on the cache memory if not loaded, and outputting a load-address indicating a load-completed-address of the cache memory; and at least one address converter calculating which one of the storage devices the allocated data are stored in, by using the load-address, outputting the calculated value as the cache-address to the cache memory, and outputting the cache-data as read-data. | 2010-08-05 |
| 20100199045 | STORE-TO-LOAD FORWARDING MECHANISM FOR PROCESSOR RUNAHEAD MODE OPERATION - A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode. | 2010-08-05 |
| 20100199046 | METHOD AND DEVICE FOR CONTROLLING A MEMORY ACCESS IN A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS - A method and device for controlling memory access in a computer system having at least two execution units, a buffer area, in particular a cache memory area being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein in the performance mode each execution unit accesses the buffer area assigned to it and in the compare mode both execution units access one buffer area that can be predefined, the buffer areas being configurable. | 2010-08-05 |
| 20100199047 | EXPIRING VIRTUAL CONTENT FROM A CACHE IN A VIRTUAL UNINERSE - An invention that expires cached virtual content in a virtual universe is provided. In one embodiment, there is an expiration tool, including an identification component configured to identify virtual content associated with an avatar in the virtual universe; an analysis component configured to analyze a behavior of the avatar in a region of the virtual universe; and an expiration component configured to expire cached virtual content associated with the avatar based on the behavior of the avatar in the region of the virtual universe. | 2010-08-05 |
| 20100199048 | SPECULATIVE WRITESTREAM TRANSACTION - Embodiments of the present invention provide a system that performs a speculative writestream transaction. The system starts by receiving, at a home node, a writestream ordered (WSO) request to start a WSO transaction from a processing subsystem. The WSO request identifies a cache line to be written during the WSO transaction. The system then sends an acknowledge signal to the processing subsystem to enable the processing subsystem to proceed with the WSO transaction. During the WSO transaction, the system receives a second WSO request to start a WSO transaction. The second WSO request identifies the same cache line as to be written during the subsequent WSO transaction. In response to receiving the second WSO request, the system sends an abort signal to cause the processing subsystem to abort the WSO transaction. | 2010-08-05 |
| 20100199049 | PARAMETER COPYING METHOD AND PARAMETER COPYING DEVICE - A parameter copying method is applied to a duplex system in which MPU and a main memory are duplicated and duplex operations on a hot standby system are performed. The parameter copying method includes cache reading data in the main memory corresponding to one MPU, cache writing the data read in the cache reading step on an as-is basis, and writing the data into the main memory corresponding to the one MPU by a block write that is produced by a cache replace caused due to the cache writing step, and also writing the same data into the main memory corresponding to the other MPU by the block write on a basis of a mirrored write. | 2010-08-05 |
| 20100199050 | PROACTIVE TECHNIQUE FOR REDUCING OCCURRENCE OF LONG WRITE SERVICE TIME FOR A STORAGE DEVICE WITH A WRITE CACHE - Provided are techniques for introducing a delay in responding to host write requests. A percentage of fullness of a write cache is determined. Based on the determined percentage of fullness of the write cache (f), a low cache threshold (L), alpha (α), and k, an amount of delay to introduce into responding to a host write request is determined. Techniques wait the amount of the delay before responding to the host write request although the host write request processing has completed. | 2010-08-05 |
| 20100199051 | CACHE COHERENCY IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM - A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories. | 2010-08-05 |
| 20100199052 | INFORMATION PROCESSING APPARATUS, EXECUTION ENVIRONMENT TRANSFERRING METHOD AND PROGRAM THEREOF - Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory. | 2010-08-05 |
| 20100199053 | METHOD AND APPARATUS FOR LOGICAL VOLUME MANAGEMENT - Systems and methods for consistent logical volume management of the storage subsystem. The present invention guarantees permanent identification data consistency while migrating, mirroring, creating, deleting LU and so on. It prevents the administrator from the change of management. | 2010-08-05 |
| 20100199054 | System and Method for Improving Memory Transfer - System and method for performing a high-bandwidth memory copy. Memory transfer instructions allow for copying of data from a first memory location to a second memory location without the use of load and store word instructions thereby achieving a high-bandwidth copy. In one embodiment, the method includes the steps of (1) decoding a destination address from a first memory transfer instruction, (2) storing the destination address in a register in the bus interface unit, (3) decoding a source address from a second memory transfer instruction, and (4) copying the contents of a memory location specified by the source memory address to a memory location specified by the contents of the register. Other methods and a microprocessor system are also presented. | 2010-08-05 |
| 20100199055 | INFORMATION PROCESSING SYSTEM AND MANAGEMENT DEVICE FOR MANAGING RELOCATION OF DATA BASED ON A CHANGE IN THE CHARACTERISTICS OF THE DATA OVER TIME - In an information processing system including a computer device, and a storage device storing data used by the computer device, the region in which the data is held is managed in association with a change, over the passage of time in the performance and availability required of the data holding region. The computer device includes a storage device managing unit for managing the storage device which stores data used by the computer device. The storage device managing unit periodically monitors temporal characteristics information, and moves data, if the storage region having functional characteristics corresponding to the temporal characteristics information is different from the storage region to which the data is currently assigned. | 2010-08-05 |
| 20100199056 | FRACTURED ERASE SYSTEM AND METHOD - Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background. | 2010-08-05 |
| 20100199057 | INDEPENDENT LINK AND BANK SELECTION - Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller. | 2010-08-05 |
| 20100199058 | Data Set Size Tracking and Management - Specified data sets may be tracked from creation to end-of-life (e.g., deletion). Between creation and end-of-life, data set storage changes may be recorded (i.e., when additional storage is allocated or when some storage is released). During a subsequent allocation cycle, this information may be used in conjunction with user-specified allocation rules to manage or control the data set's initial allocation. | 2010-08-05 |
| 20100199059 | MOBILE COMMUNICATION DEVICE AND METHOD FOR DEFRAGGING MIFARE MEMORY - A mobile communication device ( | 2010-08-05 |
| 20100199060 | MEMORY CONTROLLER, NONVOLATILE MEMORY MODULE, ACCESS MODULE, AND NONVOLATILE MEMORY SYSTEM - An address management part | 2010-08-05 |
| 20100199061 | System and Method for Distributed Partitioned Library Mapping - A system and method of media library access that utilizes distributed mapping of media library partitions. A first controller can be connected to a data transport element of a media library and a second controller can be connected to a media changer of the media library. The first controller can maintain a media library partition representing a portion of the media library, receive a command from a host application based on the media library partition and forward the command to the second controller. The first controller can further translate logical addresses referenced in the command to physical addresses before forwarding the command to the second controller. The second controller can receive the command from the first controller and forward the command to the media changer. The second controller can also prioritize the command on using a FIFO or other prioritization scheme. | 2010-08-05 |
| 20100199062 | MANAGING REQUESTS OF OPERATING SYSTEMS EXECUTING IN VIRTUAL MACHINES - A coordinator in a computer system receives a request from one of a plurality of operating systems (that coexist in the computer system) to invoke a service of a management routine in the computer system. The plurality of operating systems execute in respective virtual machines of the computer system. The coordinator processes the received request to invoke the service of the management routine to prevent a conflict from occurring with respect to at least another one of the plurality of operating systems. | 2010-08-05 |
| 20100199063 | METHODS AND MECHANISMS FOR PROACTIVE MEMORY MANAGEMENT - A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed. The system includes mechanisms directed towards historical memory usage monitoring, memory usage analysis, refreshing memory with highly-valued (e.g., highly utilized) pages, I/O pre-fetching efficiency, and aggressive disk management. Based on the memory usage information, pages are prioritized with relative values, and mechanisms work to pre-fetch and/or maintain the more valuable pages in memory. Pages are pre-fetched and maintained in a prioritized standby page set that includes a number of subsets, by which more valuable pages remain in memory over less valuable pages. Valuable data that is paged out may be automatically brought back, in a resilient manner. Benefits include significantly reducing or even eliminating disk I/O due to memory page faults. | 2010-08-05 |
| 20100199064 | Fast Address Translation for Linear and Circular Modes - The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address in series. This invention generates the physical address and virtual address simultaneously. A bitwise operation on the base address, the offset address and each stored virtual address determines whether the base address and offset address sum equals the virtual address without requiring a carry propagate. Circular addressing is implemented in the match determination by masking bits corresponding to the circular address limit. | 2010-08-05 |
| 20100199065 | METHODS AND APPARATUS FOR PERFORMING EFFICIENT DATA DEDUPLICATION BY METADATA GROUPING - The system is composed of: identifier generation program or logic, identifier confirm program or logic, plural identifier table and metadata mapping table. Data streams or data blocks, files are stored in the data storage system with metadata. The metadata includes additional information of the data and files. For example application, creator, timestamp, OS type, and the like. Data storage system or backup appliance with this invention can have plural groups which are related to the metadata. Each group has an identifier table so that eliminating duplicated data is executed within the group. | 2010-08-05 |
| 20100199066 | GENERATING A LOG-LOG HASH-BASED HIERARCHICAL DATA STRUCTURE ASSOCIATED WITH A PLURALITY OF KNOWN ARBITRARY-LENGTH BIT STRINGS USED FOR DETECTING WHETHER AN ARBITRARY-LENGTH BIT STRING INPUT MATCHES ONE OF A PLURALITY OF KNOWN ARBITRARY-LENGTH BIT STRINGS - Generating and using a high-speed, scalable and easily updateable data structures are described. The proposed data structure provides minimal perfect hashing functionality while intrinsically supporting low-cost set-membership queries. In other words, in some embodiments, it provides at most one match candidate in a set of known arbitrary-length bit strings that is used to match the query. | 2010-08-05 |
| 20100199067 | Split Vector Loads and Stores with Stride Separated Words - A method, system and computer program product are presented for causing a parallel load/store of stride-separated words from a data vector using different memory chips in a computer. | 2010-08-05 |
| 20100199068 | RECONFIGURABLE PROCESSOR FOR REDUCED POWER CONSUMPTION AND METHOD THEREOF - Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a distributed configuration memory, a no-operation (NOP) register, and a controller. The NOP register stores information which represents whether or not a NOP operation is performed at each clock cycle. The controller controls to deactivate the distributed configuration memory at a clock cycle at which a NOP operation is performed. | 2010-08-05 |
| 20100199069 | SCHEDULER OF RECONFIGURABLE ARRAY, METHOD OF SCHEDULING COMMANDS, AND COMPUTING APPARATUS - A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources. | 2010-08-05 |
| 20100199070 | PROGRAMMABLE FILTER PROCESSOR - A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit. | 2010-08-05 |
| 20100199071 | DATA PROCESSING APPARATUS AND IMAGE PROCESSING APPARATUS - A data processing apparatus in which pipeline processing is performed comprises a control unit that controls a data processing sequence, a first processing unit that begins first data processing by inputting data on the basis of a start signal, outputs data subjected to the first data processing, and outputs a completion signal to the control unit after completing the first data processing, and a second processing unit that begins second data processing by inputting the data subjected to the first data processing on the basis of a start signal, outputs data subjected to the second data processing, and outputs a completion signal to the control unit after completing the second data processing. The control unit outputs a following start signal to the first processing unit and the second processing unit upon reception of the completion signal of the first data processing and the second data processing respectively. | 2010-08-05 |
| 20100199072 | Register file - A register file comprising a plurality of register entries for storing data values for use in the execution of data processing instructions is provided, and comprises at least one write port and at least one read port, and circuitry responsive to a write request received at said at least one write port to update one of said plurality of register entries identified by an address specified by said write request with a data value specified by said write request. The register file also comprises further circuitry responsive to a received control signal to set at least a portion of a predetermined register entry to a predetermined value. In this way, certain register file updating instructions can be executed in parallel with other instructions without the need for additional full write-ports as would be required for typical dual-issue, thereby reducing area and routing complexity and cost compared with the use of an additional write-port due to the lower gate count required by the proposed further circuitry. | 2010-08-05 |
| 20100199073 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 2010-08-05 |
| 20100199074 | INSTRUCTION SET ARCHITECTURE WITH DECOMPOSING OPERANDS - Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor. | 2010-08-05 |
| 20100199075 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 2010-08-05 |
| 20100199076 | COMPUTING APPARATUS AND METHOD OF HANDLING INTERRUPT - A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor. | 2010-08-05 |
| 20100199077 | AUTHENTICATED DEBUG ACCESS FOR FIELD RETURNS - Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party. | 2010-08-05 |
| 20100199078 | METHOD OF SAFE AND RECOVERABLE FIRMWARE UPDATE AND DEVICE USING THE SAME - A safe and recoverable firmware update method which for a remote embedded electronic device and the device thereof. The method includes reading an update status in a flash memory, and determining the update status. If the update status is “DEFAULT”, a default firmware is executed. If the update status is not “DEFAULT”, the update status is further determined if it is “UPDATED”. If the update status is “UPDATED”, a configuration area is set as “BOOTING” and a new firmware is executed. If the update status is not “UPDATED”, the update status is determined if it is “RUNNEW”. If the update status is “RUNNEW”, a new firmware and an update validation method are executed. If the update validation method gets an update completion validation message, the update status is set as “RUNNEW”. If the update status is not “RUNNEW”, a default firmware is executed. | 2010-08-05 |
| 20100199079 | ROUTER DEVICE - The router device is able to use either battery power or a commercial power supply, and when using battery power detects battery voltage and indicates the level of battery voltage with an LED. When the router device is using battery power, writing of the firmware is disabled. Further, writing of settings information write is disabled when battery voltage goes below a second threshold value; and supply of power to the CPU is subsequently interrupted when battery voltage goes below a first threshold value. In this way the router device of the invention avoids problems occurring due to a drop in battery voltage when using battery power. | 2010-08-05 |
| 20100199080 | Method and System for Diagnosing and Programming Industrial Vehicles - A method and system for diagnosing and programming industrial vehicles, especially lift trucks, is provided. The method and system utilizes a computer that is connected to an area network having at least one server, e.g. the internet. The computer is also connected through an electronic interface to a lift truck's data bus. | 2010-08-05 |
| 20100199081 | APPARATUS AND METHOD FOR DOWNLOADING CONTENTS USING AN INTERIOR MASS STORAGE IN A PORTABLE TERMINAL - A method and apparatus for downloading content to a large-capacity internal memory in a portable terminal are provided. The method includes performing a booting process of the portable terminal at the occurrence of a booting event, examining whether a Universal Serial Bus (USB) port is enabled during the booting process, if the USB port is enabled, receiving data through the USB port before driver loading, and storing the received data into the large-capacity internal memory and performing the booting process. | 2010-08-05 |
| 20100199082 | MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory. | 2010-08-05 |
| 20100199083 | ONBOARD ACCESS CONTROL SYSTEM FOR COMMUNICATION FROM THE OPEN DOMAIN TO THE AVIONICS DOMAIN - An onboard access control system to an information system onboard an aircraft, for communication from the open domain to the avionics domain, the open end avionics domains being connected to each other through a single-directional link from the avionics domain to the open domain. The system includes: a security device including: access switches controlling access to the avionics and open domains, a controller, a module for acquisition putting data into buffer memory and transmission to the avionics domain, a data control module, an acquisition module from the open domain and putting into buffer memory, and an operator's authentication mechanism. | 2010-08-05 |
