31st week of 2010 patent applcation highlights part 49 |
Patent application number | Title | Published |
20100197076 | METHODS FOR MANUFACTURING A PHASE-CHANGE MEMORY DEVICE - In a method of forming a chalcogenide compound target, a first powder including germanium carbide or germanium is prepared, and a second powder including antimony carbide or antimony is prepared. A third powder including tellurium carbide or tellurium is prepared. A powder mixture is formed by mixing the first to the third powders. After a shaped is formed body by molding the powder mixture. The chalcogenide compound target is obtained by sintering the powder mixture. The chalcogenide compound target may include a chalcogenide compound that contains carbon and metal, or carbon, metal and nitrogen considering contents of carbon, metal and nitrogen, so that a phase-change material layer formed using the chalcogenide compound target may stable phase transition, enhanced crystallized temperature and increased resistance. A phase-change memory device including the phase-change material layer may have reduced set resistance and driving current while improving durability and sensing margin. | 2010-08-05 |
20100197077 | SEMICONDUCTOR PACKAGE ADAPTED FOR HIGH-SPEED DATA PROCESSING AND DAMAGE PREVENTION OF CHIPS PACKAGED THEREIN AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the to first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball. | 2010-08-05 |
20100197078 | DICING FILM HAVING SHRINKAGE RELEASE FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME. - The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same. | 2010-08-05 |
20100197079 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate-such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder. | 2010-08-05 |
20100197080 | ADHESIVE SHEET FOR MANUFACTURING SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SHEET, AND SEMICONDUCTOR DEVICE OBTAINED BY THE METHOD - The adhesive sheet for manufacturing a semiconductor device is an adhesive sheet for manufacturing a semiconductor device used when a semiconductor element is adhered to an adherend and the semiconductor element is wire-bonded, and is a peelable adhesive sheet in which the 180 degree peeling adhesive strength against a silicon wafer is 5 (N/25 mm width) or less. | 2010-08-05 |
20100197081 | MICROELECTRONIC PACKAGE WITH THERMAL ACCESS - A method of forming a microelectronic package including the steps of providing a three-layer metal plate, having a first layer, a second layer and a third layer. A plurality of conductive elements is formed from the first layer of the metal plate. A dielectric sheet is attached to the first layer of the metal plate, such that the dielectric sheet is remote from the third layer. A plurality of conductive features is then formed from the third layer of the metal plate which are also remote from the dielectric sheet. A microelectronic element is next electrically conducted to the conductive elements and a heat spreader is thermally connected the microelectronic element. | 2010-08-05 |
20100197082 | Implantable Microelectronic Device and Method of Manufacture - An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder. | 2010-08-05 |
20100197083 | FABRICATION METHODS OF THIN FILM TRANSISTOR SUBSTRATES - Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost. | 2010-08-05 |
20100197084 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises forming an insulating layer on a polymer substrate, growing a germanium layer on the insulating layer, forming a gate pattern on the germanium layer, forming a metal layer on the germanium layer including the gate pattern, annealing the metal layer to form a compound layer mixed with the metal layer and the germanium layer, and forming a contact by etching the metal layer. | 2010-08-05 |
20100197085 | Method of manufacturing an organic thin film transistor - An organic thin film transistor that has good adhesiveness and good contact resistance as well as allows ohmic contact between an organic semiconductor layer and a source electrode and a drain electrode, and its manufacturing method. There is also provided a flat panel display device using the organic thin film transistor. The organic thin film transistor includes a source electrode, a drain electrode, an organic semiconductor layer, a gate insulating layer, and a gate electrode formed on a substrate, and a carrier relay layer including conductive polymer material formed at least between the organic semiconductor layer and the source electrode or the organic semiconductor layer and the drain electrode. | 2010-08-05 |
20100197086 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME AND MASK FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE - A thin film transistor substrate, wherein the moving area of electrons between source and drain electrodes of a thin film transistor (TFT) is minimized, the moving distance of electrons is increased, and the sizes of capacitors defined by a gate electrode together with the respective source and drain electrodes are identical to each other so that an off current generated when the TFT is off can be minimized; a method of manufacturing the thin film transistor substrate; and a mask for manufacturing the thin film transistor substrate. Accordingly, it is possible to minimize an off current induced due to a phenomenon of electron trapping by light. | 2010-08-05 |
20100197087 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device having a raised source and drain structure, in forming a raised region by etching, etching of an island-like semiconductor film which is an active layer is inhibited. In a method for manufacturing a semiconductor device, an insulating film is formed by oxidizing or nitriding the surface of an island-like semiconductor film, a semiconductor film is formed on a region which is a part of the insulating film, a gate electrode is formed over the insulating film, an impurity element imparting one conductivity type is added to the island-like semiconductor film and the semiconductor film using the gate electrode as a mask, the impurity element is activated by heating the island-like semiconductor film and the semiconductor film, and the part of the insulating film between the island-like semiconductor film and the semiconductor film disappears by heating the island-like semiconductor film and the semiconductor film. | 2010-08-05 |
20100197088 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: forming a first-conductivity-type semiconductor region on a semiconductor layer; forming a mask member on the first-conductivity-type semiconductor region; selectively forming an opening in the mask member; etching the first-conductivity-type semiconductor region exposed to the opening to form a trench having a larger diameter than the opening and an eaves-like mask projected above the trench and made of the mask member; and forming a second-conductivity-type semiconductor region in the trench below the eaves-like mask by epitaxial growth to form a structure section in which the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region are alternately repeated in a direction generally parallel to a major surface of the semiconductor layer. | 2010-08-05 |
20100197089 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH METAL-SEMICONDUCTOR COMPOUND SOURCE/DRAIN CONTACT REGIONS - Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer. | 2010-08-05 |
20100197090 | Method of fabricating semiconductor device having transistor - Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode. | 2010-08-05 |
20100197091 | GATE DIELECTRIC/ISOLATION STRUCTURE FORMATION IN HIGH/LOW VOLTAGE REGIONS OF SEMICONDUCTOR DEVICE - A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr | 2010-08-05 |
20100197092 | Method of Manufacturing Semiconductor Device Having Stress Creating Layer - Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively. | 2010-08-05 |
20100197093 | STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING - A method of manufacturing dual embedded epitaxially grown semiconductor transistors is provided, the method including depositing a first elongated oxide spacer over first and second transistors of different types, depositing a first elongated nitride spacer on the first oxide spacer, depositing a first photoresist block on the nitride spacer above the first transistor, etching the first nitride spacer above the second transistor, implanting a first halo around the second transistor, etching a first recess in an outer portion of the first halo, stripping the first photoresist above the first transistor, forming a first epitaxially grown semiconductor material in the first recess, implanting a first extension in a top portion of the first material, depositing an elongated blocking oxide over the first and second transistors and first extension, depositing a second photoresist block on the blocking oxide above the second transistor and first extension, etching the blocking oxide and first nitride spacer above the first transistor, implanting a second halo around the first transistor, etching a second recess in an outer portion of the second halo, stripping the second photoresist above the second transistor, forming a second epitaxially grown semiconductor material in the second recess, implanting a second extension in a top portion of the second material, etching the blocking oxide above the second transistor, etching nitride caps from the first and second transistors, depositing a second elongated oxide spacer on the first and second transistors, depositing a second elongated nitride spacer on the second oxide spacer, etching the second nitride spacer to leave nitride sidewalls around gates of the first and second transistors, and implanting deep sources and drains in the first and second transistors. | 2010-08-05 |
20100197094 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 2010-08-05 |
20100197095 | Methods Of Forming Memory Cells - Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric material over a semiconductor substrate. The construction may be placed within a chamber. While the construction is within the chamber, a plurality of charge-trapping centers may be dispersed over the tunnel dielectric material. The charge-trapping centers may be nanoclusters formed by sputter-depositing metallic nanoparticles into an aggregation chamber, and then aggregating groups of the nanoparticles into the nanoclusters. Also while the construction is within the chamber, electrically insulative material may be formed over and between the charge-trapping centers. Control gate material may then be formed over the electrically insulative material. | 2010-08-05 |
20100197096 | METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS - Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously. | 2010-08-05 |
20100197097 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor. | 2010-08-05 |
20100197098 | METHOD OF FABRICATING A HIGH PERFORMANCE POWER MOS - A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode. | 2010-08-05 |
20100197099 | SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF - A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies. | 2010-08-05 |
20100197100 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material. | 2010-08-05 |
20100197101 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED METHOD - Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film. | 2010-08-05 |
20100197102 | FILM DEPOSITION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A film deposition method includes the steps of: coating a solution containing a polysilane compound on a substrate to form a coating film and then carrying out a first thermal treatment in an inert atmosphere, thereby forming the coating film into a silicon film; forming a coating film containing a polysilane compound on the silicon film and then carrying out a second thermal treatment in an inert atmosphere or a reducing atmosphere, thereby forming the coating film into a silicon oxide precursor film; and carrying out a third thermal treatment in an oxidizing atmosphere, thereby forming the silicon oxide precursor film into a silicon oxide film and simultaneously densifying the silicon film. | 2010-08-05 |
20100197103 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device can include forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region, forming an offset spacer of a first material on the gate structure, performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, forming a material layer of a second material on the semiconductor substrate and the gate structures, forming a material layer of a third material, which has an etch selectivity with respect to the second material, on the material layer made of the second material, etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantation mask, and removing the material layer of the third material. | 2010-08-05 |
20100197104 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 2010-08-05 |
20100197105 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 2010-08-05 |
20100197106 | SEMICONDUCTOR EMBEDDED RESISTOR GENERATION - A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.; etching the silicon layer to yield a polyconductor (PC) disposed substantially above the STI region; oxidizing the PC; depositing at least one of an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the at least one oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer disposed substantially above the STI region; patterning a transistor gate with a photo-resist mask disposed on another portion of the silicon layer disposed substantially away from the STI region; and etching the silicon layer to yield at least one transistor structure disposed substantially away from the STI region and at least one resistor structure disposed substantially above the STI region. | 2010-08-05 |
20100197107 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first film on a processed film, patterning the first film into a pattern with smaller width and a space with larger width, forming a second film along upper and side surfaces of first film and an upper surface of second film, etching the second film thereby to expose upper surfaces of first film and processed film while part of second film remains along the side surface of first film, etching the first film under the condition that the first film has higher etch selectivity than the second film, etching an upper part of second film under the condition that the second film has a higher etch selectivity than the processed film, after the first film has been etched, and etching the processed film with the second film serving as mask after the upper part of second film has been etched. | 2010-08-05 |
20100197108 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STRUCTURE - A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density. | 2010-08-05 |
20100197109 | METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE - Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed. | 2010-08-05 |
20100197110 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved. | 2010-08-05 |
20100197111 | METHOD OF MANUFACTURING MEMORY DEVICE AND METHOD OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE USING THE SAME - A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer. | 2010-08-05 |
20100197112 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 2010-08-05 |
20100197113 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a thin semiconductor device having flexibility. A groove is formed in one surface of a substrate; an element layer including an element is formed, the element being disposed within the groove; the substrate is thinned from the other surface of the substrate until one surface of the element layer is exposed, to form a layer which is to be transposed, having the element; and the layer to be transposed is transposed onto the film. | 2010-08-05 |
20100197114 | Methods of die sawing - A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced. | 2010-08-05 |
20100197115 | METHOD OF SEGMENTING SEMICONDUCTOR WAFER - To provide a method of segmenting a semiconductor wafer, which is capable of preventing chippings. | 2010-08-05 |
20100197116 | LASER-BASED MATERIAL PROCESSING METHODS AND SYSTEMS - Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. In at least one embodiment, an ultrashort pulse laser system may include at least one of a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may also include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond and/or picosecond pulses, and in some embodiments with pulse widths up to a few nanoseconds. | 2010-08-05 |
20100197117 | MIXED-SCALE ELECTRONIC INTERFACES - Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state. Other embodiments of the present invention are directed to a nanowire structure including a mixed-scale interface. | 2010-08-05 |
20100197118 | MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES - A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices. | 2010-08-05 |
20100197119 | Resistor Random Access Memory Cell Device - A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film. | 2010-08-05 |
20100197120 | Forming Phase Change Memory Cell With Microtrenches - A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area. | 2010-08-05 |
20100197121 | Methods of manufacturing semiconductor devices - A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure. | 2010-08-05 |
20100197122 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed. Further, a second growing operation for selectively growing the second polycrystalline semiconductor layer and the third polycrystalline semiconductor layer on the exposed portion of the p-type polycrystalline semiconductor film exposed in the lower surface of the visor section without contacting the silicon nitride film, while growing the second semiconductor layer and the third semiconductor layer, so that the third semiconductor layer is in contact with the third polycrystalline semiconductor layer. | 2010-08-05 |
20100197123 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a device isolation structure formed on a semiconductor substrate to define an active region. A first Si-based epitaxial pattern is formed over the active region corresponding to a bit line contact region and a portion of a gate region at both sides adjacent to the bit line contact region. A second Si-based epitaxial layer is formed over the semiconductor substrate which is stepped up on the first Si-based epitaxial pattern. A stepped gate pattern is formed over the stepped second Si-based epitaxial layer. | 2010-08-05 |
20100197124 | Methods of Forming Semiconductor Devices Using Plasma Dehydrogenation and Devices Formed Thereby - A semiconductor integrated circuit device with enhanced reliability is provided. The semiconductor integrated circuit device includes a semiconductor substrate; a gate insulation film that is provided on the semiconductor substrate; a gate electrode that is provided on the gate insulation film; and a sidewall spacer that is provided on side walls of the gate insulation film and the gate electrode and includes, wherein the sidewall spacer has a first sidewall spacer in contact with the gate electrode and a second sidewall spacer formed on the side walls of the first sidewall spacer, and a ratio of an Si—OH area to an Si—O area in at least one of the first and second sidewall spacers is 0.05 or less, as measured by Fourier Transform InfraRed (FTIR). | 2010-08-05 |
20100197125 | TECHNIQUE FOR PROCESSING A SUBSTRATE - An improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for processing a substrate. The method may comprise ion implanting a substrate disposed downstream of the ion source with ions generated in an ion source; and disposing a first portion of a mask in front of the substrate to expose the first portion of the mask to the ions, the mask being supported by the first and second mask holders, the mask further comprising a second portion wound in the first mask holder. | 2010-08-05 |
20100197126 | USE OF CHAINED IMPLANTS IN SOLAR CELL - The manufacture of solar cells is simplified and cost reduced through by performing successive ion implants, without an intervening thermal cycle. In addition to reducing process time, the use of chained ion implantations may also improve the performance of the solar cell. In another embodiment, two different species are successively implanted without breaking vacuum. In another embodiment, the substrate is implanted, then flipped such that it can be and implanted on both sides before being annealed. In yet another embodiment, one or more different masks are applied and successive implantations are performed without breaking the vacuum condition, thereby reducing the process time. | 2010-08-05 |
20100197127 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed, wherein a plating layer is formed on a first surface side of a semiconductor substrate stably and at a low cost, while preventing the plating liquid from being contaminated and avoiding deposition of uneven plating layer on a second surface side. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied on the electrode on the second surface and a film is stuck on the curing resin, and the curing resin is then cured. After that, a plating process is conducted on the first surface. The film and the curing resin are then peeled off. | 2010-08-05 |
20100197128 | CMOS Integration with Metal Gate and Doped High-K Oxides - A method and apparatus are described for fabricating single metal gate electrodes ( | 2010-08-05 |
20100197129 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a stacked body of a dielectric layer including a silicon oxide and a conductive layer including silicon above a substrate; and forming a hole penetrating through the dielectric layer and the conductive layer in the stacked body, the forming the hole including: forming a first mask layer including a silicon oxide above the stacked body; etching the conductive layer while using the first mask layer as a mask; and forming a second mask layer having more silicon content than the dielectric layer above the first mask layer to etch the dielectric layer while using the second mask layer as a mask. | 2010-08-05 |
20100197130 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film. | 2010-08-05 |
20100197131 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 2010-08-05 |
20100197132 | Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow - A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor. | 2010-08-05 |
20100197133 | METHOD OF FORMING A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE BY USING A HARD MASK FOR DEFINING THE VIA SIZE - In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches. | 2010-08-05 |
20100197134 | COAXIAL THROUGH CHIP CONNECTION - An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another. | 2010-08-05 |
20100197135 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH METAL-CONTAINING CAP LAYERS - A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, forming a patterned mask layer on the patterned substrate, where the patterned mask layer contains openings that expose the Cu metal surfaces. The method further includes depositing a metal-containing layer on the Cu metal surfaces, depositing an additional metal-containing layer on the patterned mask layer, and removing the patterned mask layer and the additional metal-containing layer from the patterned substrate to selectively form metal-containing cap layers on the Cu metal surfaces. | 2010-08-05 |
20100197136 | COMPOSITION FOR CLEANING AND RUST PREVENTION AND PROCESS FOR PRODUCING SEMICONDUCTOR ELEMENT OR DISPLAY ELEMENT - A composition for cleaning and corrosion inhibition which is used in a step of manufacturing a semiconductor device or a display device having a copper-containing metallic wiring is provided, wherein the corrosion inhibitor component is any one of pyrazole, a pyrazole derivative such as 3,5-dimethylpyrazole, a triazole derivative such as 1,2,4-triazole, an aminocarboxylic acid such as iminodiacetic acid or ethylenediaminedipropionic acid hydrochloride, or a disulfide compound such as diisopropyl disulfide or diethyl disulfide; and the cleaning agent component is any one of ammonium fluoride, tetramethylammonium fluoride, ammonium acetate, acetic acid, glyoxylic acid, oxalic acid, ascorbic acid, 1,2-diaminopropane or dimethylacetamide. Also, a method for manufacturing a semiconductor device or the like using the composition for cleaning and corrosion inhibition is provided. | 2010-08-05 |
20100197137 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber. | 2010-08-05 |
20100197138 | METHOD AND APPARATUS FOR ETCHING - Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a backside process gas between a substrate and a substrate support assembly, and cyclically etching a layer on the substrate. | 2010-08-05 |
20100197139 | METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME - A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask. | 2010-08-05 |
20100197140 | ANGLED-WEDGE CHROME-FACE WALL FOR INTENSITY BALANCE OF ALTERNATING PHASE SHIFT MASK - A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees with the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist. | 2010-08-05 |
20100197141 | NOVEL SELF-ALIGNED STATIC RANDOM ACCESS MEMORY (SRAM) ON METAL GATE - A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions. | 2010-08-05 |
20100197142 | HIGH SELECTIVITY, LOW DAMAGE ELECTRON-BEAM DELINEATION ETCH - A method and apparatus for selective etching a substrate using a focused beam. For example, multiple gases may be used that are involved in competing beam-induced and spontaneous reactions, with the result depending on the materials on the substrate. The gases may include, for example, an etchant gas and an auxiliary gas that inhibits etching. | 2010-08-05 |
20100197143 | DRY ETCHING METHOD FOR SILICON NITRIDE FILM - A dry etching method for a silicon nitride film capable of improving throughput is provided. A dry etching method for dry-etching a silicon nitride film | 2010-08-05 |
20100197144 | METHODS FOR DAMAGE ETCH AND TEXTURING OF SILICON SINGLE CRYSTAL SUBSTRATES - Methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Damage etch with a TMAH solution followed by texturing using solution of KOH or NaOH mixed with IPA is particularly advantageous. The substitution of some of the IPA with ethylene glycol further improves results. Also disclosed is a process that combines both damage etch and texturing etch into a single step. | 2010-08-05 |
20100197145 | SILICON NITRIDE PASSIVATION FOR A SOLAR CELL - A silicon nitride layer may be formed with a suitable refractive index, mass density, and hydrogen concentration so that the layer may serve as an ARC/passivation layer on a solar cell substrate. The silicon nitride layer may be formed on a solar cell substrate by adding a hydrogen gas diluent to a conventional precursor gas mixture during the deposition process. Alternatively, the silicon nitride layer may be formed on a solar cell substrate by using a precursor gas mixture consisting essentially of silane and nitrogen. To improve deposition chamber throughput, the silicon nitride layer may be a dual stack film that includes a low-hydrogen interface layer and a thicker bulk silicon nitride layer. Placing a plurality of solar cell substrates on a substrate carrier and transferring the substrate carrier into the deposition chamber may further enhance deposition chamber throughput. | 2010-08-05 |
20100197146 | Method of heat treating silicon wafer - In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer. | 2010-08-05 |
20100197147 | SINGLE-SHOT SEMICONDUCTOR PROCESSING SYSTEM AND METHOD HAVING VARIOUS IRRADIATION PATTERNS - High throughput systems and processes for recrystallizing thin film semiconductors that have been deposited at low temperatures on a substrate are provided. A thin film semiconductor workpiece is irradiated with a laser beam to melt and recrystallize target areas of the surface exposed to the laser beam. The laser beam is shaped into one or more beamlets using patterning masks. The mask patterns have suitable dimensions and orientations to pattern the laser beam radiation so that the areas targeted by the beamlets have dimensions and orientations that are conducive to semiconductor recrystallization. The workpiece is mechanically translated along linear paths relative to the laser beam to process the entire surface of the work piece at high speeds. Position sensitive triggering of a laser can be used generate laser beam pulses to melt and recrystallize semiconductor material at precise locations on the surface of the workpiece while it is translated on a motorized stage. | 2010-08-05 |
20100197148 | FLEXIBLE MAGNETIC INTERCONNECTS - A flexible magnetic interconnect is disclosed. In one embodiment, an apparatus includes a module having a recess therein. A magnetic structure is moveable within the recess and a flexible circuit cooperates with the module to retain the magnetic structure within the recess. Movement of the magnetic structure is caused by magnetic attraction between the magnetic structure and an external magnetic structure. The flexible circuit includes a compliant contact, which changes shape by movement of the magnetic structure. | 2010-08-05 |
20100197149 | HIGH DENSITY CONNECTOR ASSEMBLY - A connector assembly includes an array of signal contacts having mating portions configured for mating engagement with corresponding signal contacts of a mating connector assembly. The assembly also includes a housing holding the array of signal contacts in rows and columns. The signal contacts are arranged along axes of the rows and columns, and the mating portions of the signal contacts are oriented at a non-orthogonal angle relative to the axes of the rows and columns. | 2010-08-05 |
20100197150 | PRINTED CIRCUIT ASSEMBLY - A printed circuit assembly includes a base printed circuit having a printed circuit receiving area and a plurality of electrical contacts provided on the printed circuit receiving area. The printed circuit assembly also includes a secondary printed circuit having a secondary substrate including a mating edge and a plurality of secondary contacts provided along the mating edge. The secondary printed circuit is mounted on the base printed circuit such that the mating edge of the secondary printed circuit is directly engaged with the base printed circuit at the printed circuit receiving area. Each of the secondary contacts is electrically connected to a corresponding one of the electrical contacts of the base printed circuit. | 2010-08-05 |
20100197151 | SOCKET PACKAGE INCLUDING INTEGRATAED CAPACITORS - A socket package is provided to be positioned between a circuit package and a printed circuit board (PCB). The socket package includes a plurality of interconnects, to connect portions of the circuit package to portions of the PCB. Additionally, a plurality of capacitors are included with the socket package. The capacitors connect the interconnects provided to the socket package, and may be provided in lieu of capacitors in a circuit package, thus decreasing the complexity and build cost of the circuit package. | 2010-08-05 |
20100197152 | SOCKET FOR CONNECTING BALL-GRID-ARRAY INTEGRATED CIRCUIT DEVICE TO TEST CIRCUIT - A simple structure socket | 2010-08-05 |
20100197153 | CONNECTOR ASSEMBLY HAVING ELECTRONIC COMPONENTS MOUNTED THERETO - A connector assembly configured to be mounted to a device substrate is provided. She connector assembly includes a connector substrate, an electronic component. contacts, and conductive wires. The connector substrate has a mounting side and an opposite supporting side interconnected by an edge. The mounting side is used to mount the connector substrate to the device substrate. The electronic component is disposed on the supporting side of the connector substrate. The contacts are provided on the mounting side of the connector substrate and are used to electrically couple the electronic component with the device substrate. The wires are joined to the electronic component and to the contacts. The wires extend along the supporting and mounting sides and wrap around the edge of the connector substrate. The conductive wires are separated from one another by a separation gap along the supporting side and the mounting side of the connector substrate. | 2010-08-05 |
20100197154 | FIXING STRUCTURE OF RELAY CONNECTOR - A fixing structure of a relay connector includes: a guide block fixed to a lower portion of the relay connector; a movable support shaft movable in a first direction perpendicular to a second direction which is parallel to an axial direction of the coaxial connector; lock plates provided at both ends of the movable support shaft; a fixing operating lever provided inside the guide block so as to swing around a lever support shaft and provided with a cam part; and a rail member provided with a pair of slide parts, the guide block inserted between the slide parts. When the fixing operating lever is swung to be tilted to one side, the upper and lower surfaces of the slide parts are clamped and fixed between the side parts of the lower portion of the relay connector and the lock plates. When the fixing operating lever is swung to be tilted to the other side, the relay connector can move in the second direction. | 2010-08-05 |
20100197155 | PUSH-PUSH MECHANISM, PARTICULARLY FOR A CARD READER - The invention concerns a push-push mechanism, particularly for a card reader with a control cam and a control pin, which engages with the control cam and is operatively connected with a slider, during which the transition of the control pin from the initial position to the reading position takes place by a first push and the transition from the reading position back into the initial position by a second push on the control pin and thus the slider, whereby the control pin is flexibly deflected during its actuation along the control cam. | 2010-08-05 |
20100197156 | LATCHABLE POWER OUTLET - A latchable power outlet with greater ease is disclosed, comprising: a base; at least two electrically conductive plates on the base, wherein the at least two electrically conductive plates are employed for making connection with a power supply and electrically conductive tongs; a two-stage self-locking switch structure on the base; a movable frame connected to the two-stage self-locking switch structure, pressing the two-stage self-locking switch structure after being directly or indirectly pressed by the plug; and at least two electrically conductive tongs; wherein the at least two electrically conductive tongs are connected to the at least two electrically conductive plates and clamp the contact prongs of the plug while being pressed by the movable frame, and wherein the at least two electrically conductive tongs release the contact prongs of the plug and are disconnected from the at least two electrically conductive plates while returning to original position. | 2010-08-05 |
20100197157 | Socket, plug, and adaptor combination with waterproof arrangement - A socket, plug, and adaptor combination includes a housing having a forward sliding door; an inverted L-shaped circuit assembly in the housing having a conductor mounting section in the vertical part; a transformer being concealed in the horizontal part of the circuit assembly in a waterproof way and adapted to electrically connect to a power cord; two electrical connection assemblies each disposed in the conductor mounting section and having a prong; a conductive assembly comprising two separate fuses disposed in the conductor mounting section, each fuse being electrically interconnected between the prong and the transformer; a cover releasably secured onto the circuit assembly and having two sockets distal the prongs; and a covering plate disposed between the transformer and the cover. The combination is applicable to be used as a charger for outdoor LED type Christmas light strings. | 2010-08-05 |
20100197158 | CABLE CONNECTOR - A cable connector includes a housing and a first contact provided in the housing. The first contact includes a first engaging and pivoting unit opposed to a back surface of the cable. The cable connector also includes a second contact which is provided in the housing and which includes a second engaging and pivoting unit opposed to the back surface of the cable. The second engaging and pivoting unit has a root which is thicker than that of the first engaging and pivoting unit. The cable connector also includes a cover. The cover includes a first through hole into which the first engaging and pivoting unit is inserted, a first cam unit engaged with the first engaging and pivoting unit, a second through hole into which the second engaging and pivoting unit is inserted, and a second cam unit engaged with the second engaging and pivoting unit. | 2010-08-05 |
20100197159 | AIRCRAFT ELECTRICAL CONNECTOR WITH DIFFERENTIAL ENGAGEMENT AND OPERATIONAL RETENTION FORCES - An aircraft powering system is provided which includes an aircraft electrical connector is provided with features to allow facile engagement with an aircraft and strong retention forces. The aircraft powering system may include the aircraft electrical connector having a unique biasing mechanism and modular construction, wherein the biasing mechanism is configured to place differential forces onto mating electrical connectors from an aircraft. The biasing mechanism may be operatively coupled to a handle or trigger, which may be easily engageable by an operator. | 2010-08-05 |
20100197160 | ELECTRICAL CONNECTOR - An electrical connector for transmitting data signals between the insulated conductors of a first data cable and corresponding insulated conductors of a second data cable, including a socket shaped to at least partially receive a plug of said first data cable; a plurality of insulation displacement contact slots shaped to receive end sections of the conductors of the second data cable; a plurality of electrically conductive contacts including resiliently compressible spring finger contacts extending into the socket for electrical connection with corresponding conductors of the first cable; insulation displacement contacts seated in corresponding insulation displacement contact slots for effecting electrical connection with corresponding conductors of the second data cable; and mid sections extending therebetween; and a plurality of capacitive plates coupled to respective ones of said mid sections of the contacts by electrically conductive stems, wherein the capacitive plates are arranged side by side and extend in a substantially common direction. | 2010-08-05 |
20100197161 | POWER OUTLET - A power outlet for effecting an electrical connection between an electric device and insulated conductors of an electric power cable, including a socket having apertures including electrically conductive socket contacts seated therein for effecting electrical connection to corresponding electrically conductive contacts of a plug of the electric device; a plurality of primary channels shaped to at least partially receive, and seat therein, respective lengthwise sections of the insulated conductors of the power cable; a plurality of insulation displacement contacts for making separate electrical connections to said insulated conductors, when received in said primary channels, under relative movement between the insulation displacement contacts and the insulated conductors; a connector, relatively movable with respect to the primary channels, for effecting said relative movement, wherein the insulation displacement contacts are electrically coupled to respective ones of said socket contacts; and said primary channels extend transversely to a lengthwise direction of extent of the power outlet. | 2010-08-05 |
20100197162 | METHOD AND SYSTEM FOR IMPROVING CROSSTALK ATTENUATION WITHIN A PLUG/JACK CONNECTION AND BETWEEN NEARBY PLUG/JACK COMBINATIONS - This application describes a jack for improving crosstalk attenuation. The jack has a housing, a foil at least partially surrounding the housing, a printed circuit board, and at least one pair of insulation displacement contacts and vias. Each pair of insulation contacts and vias are associated with a differential signal. A conductive trace stub is routed on the printed circuit board near the edge of the board in order to at least partially balance the coupling from one of the insulation displacement contacts and vias of a pair to the foil with the other insulation displacement contact and via of the pair. | 2010-08-05 |
20100197163 | Insulation Displacement Contact With Separation Point and Contact Arrangement With Insulation Displacement Contact - The invention relates to an insulation displacement contact for contacting an electrical conductor and to a contact arrangement with at least one insulation displacement contact. In order to limit contacting forces in such a way that the contact arrangement undergoes no substantial deformation, the insulation displacement contact includes at least one insulation displacement arm having a separation point, which limits movements of a free end of the at least one insulation displacement arm, which is brought about by the contacting process. | 2010-08-05 |
20100197164 | CONNECTION STRUCTURE OF CONNECTING TERMINAL AND METHOD OF CONNECTING THE SAME - An objective is to provide a connection structure of a connecting terminal by which it becomes able to perform a connection of any of pieces for piercing as assuredly without being bended that is piercing through an electrically conductive flat square body, and to provide a method of connecting such the terminal. A unit for connecting a pierced terminal ( | 2010-08-05 |
20100197165 | Information Handling System with Integral Cable - An information handling system disposed within a housing may include a cable coupled to the information handling system. The cable may be configured to move from a retracted position substantially within the housing to an extended position wherein a portion of the cable is external to the housing. Further, a connector end of the cable may be configured to communicatively couple the information handling system to a portable device. | 2010-08-05 |
20100197166 | ELECTRICAL CONNECTOR HAVING POWER CONTACTS - An electrical power connector is provided that is configured to mate with a complementary electrical connector. The electrical power connector includes a connector housing that retains both electrical signal contacts and electrical power contacts. The electrical power connector includes an engagement assembly that includes 1) at least one polarization member configured to mate with a polarization member of the complementary electrical connector only when the electrical power connector is in a desired orientation relative to the complementary electrical connector, and 2) a securement member configured to releasably engage a securement member of the complementary electrical connector. | 2010-08-05 |
20100197167 | Cable connecting device and connecting apparatus with cable connecting devices of this kind - The invention relates to a cable connecting device for a connecting apparatus for the variable connection of cables, having a connecting module which has cable connecting elements for detachably connecting two cables, and having a module carrier which can be detachably connected to the connecting module and can be detachably fixed to a holding device of the connecting apparatus. The invention also relates to a connecting apparatus with a cable connecting device of this kind. In order to develop the connecting apparatus and the cable connecting device in such a way that mounting of said devices is simplified, with the connecting module being reliably held on the module carrier, it is proposed according to the invention that the connecting module can be inserted into a receiving passage in the module carrier in a mounting direction and can be latched to the module carrier in a latching position. | 2010-08-05 |
20100197168 | Multi-Position Coaxial Connector System - Systems for connecting RF coaxial cables are disclosed. In some embodiments, the systems include the following: a plug including a D-sub housing having two rows of eight RF coaxial contacts and a plurality of protrusions extending therefrom; a receptacle including a D-sub housing having two rows of eight openings and a plurality of indentations that are sized and positioned so as to mate with the protrusions extending from the plug, the receptacle including a rear unibody joined with the D-sub housing and a transition body positioned between and joining the D-sub housing and the rear unibody. The plug and receptacle are configured to provide about a 50-Ohm impedance across the system and the plug and receptacle are configured to operate under a ground-first condition. | 2010-08-05 |
20100197169 | CONNECTOR WITH SHORT LENGTH COMPLIANT PIN - An electrical connector having a plurality of connector units each having a pair of columns of edge coupled differential signal pairs separated by a ground shield terminal. The ground shield terminals each face a different signal pair of terminals in an adjacent column. Notwithstanding the different size and configurations of the ground and signal terminals, the terminals have mounting tail portions that are disposed in a uniform array different from the arrangement of the body portions of the terminals of the connector unit. The mounting tail portions are of a reduced length which benefit the electrical performance of the connector where it meets its supporting circuit board. | 2010-08-05 |
20100197170 | COMMUNICATION SYSTEM WITH SHORT LENGTH COMPLIANT PIN - An electrical connector having a plurality of connector units each having a pair of columns of edge coupled differential signal pairs separated by a ground shield terminal. The ground shield terminals each face a different signal pair of terminals in an adjacent column. Notwithstanding the different size and configurations of the ground and signal terminals, the terminals have mounting tail portions that are disposed in a uniform array different from the arrangement of the body portions of the terminals of the connector unit. The mounting tail portions are of a reduced length which benefit the electrical performance of the connector where it meets its supporting circuit board. | 2010-08-05 |
20100197171 | CONNECTOR - A connector | 2010-08-05 |
20100197172 | Multiconductor Jack And Multiconductor Plug - A multiconductor plug ( | 2010-08-05 |
20100197173 | RIGHT ANGLE TYPE SPRING CONNECTOR - To provide a right angle type spring connector in which a caulking work is not necessary, the number of components is small, and electric connection is reliably maintained. | 2010-08-05 |
20100197174 | CONNECTOR ASSEMBLY FOR CONNECTING A LEAD AND AN IMPLANTABLE MEDICAL DEVICE - A connector assembly for detachably connecting a lead to an implantable medical device and an implantable medical device capable of being detachably connected to a lead that include one or more deflectable connector clip and a housing. The connector clip includes a first arm, a second arm, and a top portion extending between the first arm and the second arm, and is capable of being deflected from a first position, corresponding to a first relative position of the first arm and the second arm, to a second position corresponding to a second relative position of the first arm and the second arm. The housing includes a first member and a second member, the first member formed to be fixedly engaged with the second member to enclose the connector clip within the housing with the one or more connector clip being positioned within one of the first member and the second member. | 2010-08-05 |
20100197175 | ELECTRICAL APPARATUS - The subject matter of the invention is an electrical apparatus ( | 2010-08-05 |