| 31st week of 2010 patent applcation highlights part 32 |
| Patent application number | Title | Published |
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| 20100195372 | RESISTANCE-CHANGING MEMORY DEVICE - A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data. | 2010-08-05 |
| 20100195373 | Method of Operating a Memory Circuit using Memory Cells with Independent-Gate Controlled Access Devices - A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OFF” while the double-gate pull-down devices are configured to operate in a double gate mode. During a WRITE operation, the first and second access devices are configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON.” | 2010-08-05 |
| 20100195374 | Eight Transistor Soft Error Robust Storage Cell - A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell. | 2010-08-05 |
| 20100195375 | FULL CMOS SRAM - A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors. | 2010-08-05 |
| 20100195376 | BIT LINE VOLTAGE CONTROL IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM. | 2010-08-05 |
| 20100195377 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME - A semiconductor memory apparatus includes a sense amplifier coupled to a plurality of bit lines, a switching unit configured to cause the plurality of bit lines to be coupled to a first node in response to a switching signal, a mode selecting unit configured to selectively couple the first node to a pad or a ground terminal in response to a mode selection signal and a testing unit configured to supply current to the pad during a test mode. | 2010-08-05 |
| 20100195378 | Phase Change Memory With Dual Word Lines and Source Lines and Method of Operating Same - A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines. | 2010-08-05 |
| 20100195379 | System and Method of Pulse Generation - In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold. | 2010-08-05 |
| 20100195380 | Non-Volatile Memory Cell with Precessional Switching - A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified. | 2010-08-05 |
| 20100195381 | SWITCHABLE ELEMENT - A switchable element. The element includes a source electrode, a drain electrode, a conducting channel between the source electrode and the drain electrode, and a gate with multiferroic material being switchable, by application of an electrical signal to the gate, between a first switching state with a first spontaneous polarization direction and a second switching state with a second spontaneous polarization direction. The conducting channel is magnetoresistive, and a magnetic field strength at the conducting channel in the first switching state is different than a magnetic field strength in the second switching state, whereby a current-voltage characteristic of the conducting channel is dependent on the switching state of the multiferroic material. | 2010-08-05 |
| 20100195382 | THIN FILM MAGNETIC MEMORY DEVICE CAPABLE OF CONDUCTING STABLE DATA READ AND WRITE OPERATIONS - A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element. | 2010-08-05 |
| 20100195383 | Isolated P-well Architecture for a Memory Device - A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source. | 2010-08-05 |
| 20100195384 | SYSTEM AND METHOD TO READ DATA SUBJECT TO A DISTURB CONDITION - Systems and methods for reading data are disclosed. In a particular embodiment, a method includes measuring characteristics of a plurality of cells at a memory. The characteristics correspond to a plurality of values including a first value stored at a particular cell and a second value stored at a second cell of the memory. The method includes testing whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the particular cell, and providing a data value corresponding to the particular cell. The data value is determined at least in part based on a result of the testing. | 2010-08-05 |
| 20100195385 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of sequentially performing a LSB program operation and an MSB program operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises multi-level memory cells each configured to store two pieces of bit information and page buffers each coupled to a bit line coupled with the memory cells and configured to comprise a first latch coupled to first and second nodes and a second latch coupled to third and fourth nodes, the method including inputting data of MSBs to the second and fourth nodes and setting data of the second and fourth nodes according to a state of data of LSBs stored in the memory cells, and precharging the bit line according to a combination of data stored in the first and second latches and performing the MSB program operation according to a state of a LSB program operation stored in the memory cells. | 2010-08-05 |
| 20100195386 | PAGE BUFFER CIRCUIT AND NONVOLATILE MEMORY DEVICE - A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node. | 2010-08-05 |
| 20100195387 | NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD - A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition. | 2010-08-05 |
| 20100195388 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes sequentially programming first to (n−1) | 2010-08-05 |
| 20100195389 | FLASH MEMORY DEVICE AND METHODS PROGRAMMING/READING FLASH MEMORY DEVICE - Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states. | 2010-08-05 |
| 20100195390 | MEMORY DEVICE WITH NEGATIVE THRESHOLDS - A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read reference levels is negative. After storing the data, second storage values are read from the cells using the read reference levels, so as to reconstruct the stored data. In another disclosed method, data is stored in the memory by mapping the data to first storage values selected from a set of the nominal storage values, and writing the first storage values to the cells. The set of nominal storage values is defined such that at least one of the nominal storage values is negative. | 2010-08-05 |
| 20100195391 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M| 2010-08-05 | |
| 20100195392 | CAPACITOR STRUCTURE HAVING IMPROVED AREA EFFICIENCY, A MEMORY DEVICE INCLUDING THE SAME, AND A METHOD OF FORMING THE SAME - Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed. | 2010-08-05 |
| 20100195393 | Data storage system with refresh in place - A data storage system for refreshing in place data stored in a non-volatile re-writeable memory is disclosed. Data from a location memory can be read into a temporary storage location; the data at the memory location can be erased; the read data error corrected if necessary; and then the read data can be programmed and rewritten back to the same memory location it was read from. One or more layers of the non-volatile re-writeable memory can be fabricated BEOL as two-terminal cross-point memory arrays that are fabricated over a substrate including active circuitry fabricated FEOL. A portion of the active circuitry can be electrically coupled with the one or more layers of two-terminal cross-point memory arrays to perform data operations on the arrays, such as refresh in place operations or a read operation that triggers a refresh in place operation. The arrays can include a plurality of two-terminal memory cells. | 2010-08-05 |
| 20100195394 | NONVOLATILE MEMORY DEVICE - A page buffer of a nonvolatile memory device according to the present disclosure comprises a first data latch unit configured to store data for program or program inhibition, a second data latch unit configured to store data for setting threshold voltage states of cells to be programmed, and a 1-bit pass determination unit configured to determine whether a cell to be programmed has been programmed to exceed a verification voltage by grounding or making floating a first verification signal output terminal in response to data set to a first node of the first data latch unit and data applied to a sense node. | 2010-08-05 |
| 20100195395 | Non-volatile memory device having vertical structure and method of operating the same - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 2010-08-05 |
| 20100195396 | SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME - A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the buffer unit includes a volatile memory, a self-test interface includes a data input/output pin, and a controller which controls the main memory and the buffer unit. The controller at least stores data in the buffer from the self-test interface via the data input/output pin. | 2010-08-05 |
| 20100195397 | Controlled Boosting In Non-Volatile Memory Soft Programming - A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process. | 2010-08-05 |
| 20100195398 | APPLYING DIFFERENT BODY BIAS TO DIFFERENT SUBSTRATE PORTIONS FOR NON-VOLATILE STORAGE - Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage. | 2010-08-05 |
| 20100195399 | MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE - Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are read at substantially the same time by coupling a selected memory segment, and at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines. Other methods, devices, and systems are also provided. | 2010-08-05 |
| 20100195400 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number. | 2010-08-05 |
| 20100195401 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data. | 2010-08-05 |
| 20100195402 | PAGE BUFFER CIRCUIT - A page buffer circuit comprises a first sensing unit configured to sense a voltage of a bit line and change a voltage of a first sense node, a data conversion unit configured to sense a voltage level of the first sense node and change a voltage level of a second sense node or to couple the second sense node and the first sense node, and first and second latch units coupled in common to the second sense node. | 2010-08-05 |
| 20100195403 | ERASE VERIFY IN MEMORY DEVICES - In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a sample are not erased, either directly or indirectly. The number of unerased cells in the sample can be compared to a threshold. An erase operation can be performed on the memory block responsive to the comparison until the number of unerased cells is less than the threshold. | 2010-08-05 |
| 20100195404 | Method and apparatus for management of over-erasure in NAND-based NOR-type Flash Memory - A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and erasing, erase verifying, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state. Other block sections are iteratively selected and erased, erased verified, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level. | 2010-08-05 |
| 20100195405 | SEGMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING - A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed. | 2010-08-05 |
| 20100195406 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including precharging a sense node to thereby precharge a bit line coupled to the cell string for a program or data read operation; and simultaneously resetting a cell channel in a state in which the drain select transistor is turned off, the source select transistor is turned on, and the memory cells are turned on by applying a first voltage to a number of word lines coupled to the memory cells during a first time period, wherein the first time period is less than a bit line precharge time period. | 2010-08-05 |
| 20100195407 | READ OPERATION METHOD OF MEMORY DEVICE - A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell during a second read operation, and applying the second voltage to the first memory cell and the first voltage to the second memory cell during a third read operation. | 2010-08-05 |
| 20100195408 | Non-Body Contacted Sense Amplifier with Negligible History Effect - In a method of mitigating hysteresis effect in a sense amplifier circuit, a data value is sensed from a data source with the sense amplifier during a first period. The data value is stored in a latch. The data valued stored in the latch is inverted, thereby generating an inverted data value. The data source is isolated from the sense amplifier and the inverted data value is read with the sense amplifier during a second period immediately following the first period. | 2010-08-05 |
| 20100195409 | Fuse elemetns based on two-terminal re-writeable non-volatile memory - A margin restore fuse element is described, including a latch configured to store data, a first memory element coupled to the latch and configured to store a first resistive value, a second memory element coupled to the latch and configured to store a second resistive value, a restore circuit coupled to the latch, the first memory element, and the second memory element, the restore circuit being configured to perform a restore data operation to substantially restore the first and second memory elements to the first and second resistive values, respectively. The latch, restore circuit, and other circuitry can be formed FEOL on a substrate (e.g., a semiconductor wafer) as part of a microelectronics fabrication process and the fuse element and memory elements can be formed BEOL over the substrate as part of another microelectronics fabrication process. The fuse and memory elements can be included in a two-terminal non-volatile memory cell. | 2010-08-05 |
| 20100195410 | Semiconductor memory device having shift registers - A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop. | 2010-08-05 |
| 20100195411 | SEMICONDUCTOR MEMORY DEVICE AND FAIL BIT DETECTION METHOD IN SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a plurality of pages. Each page of the plurality of pages is divided into a plurality of segments, and one segment is constituted of a plurality of bytes. A fail detection circuit receives signals of the plurality of fail bit detection signal lines, and the fail detection circuit collectively detects presence/absence of a fail bit in the memory cell array in units of segments. | 2010-08-05 |
| 20100195412 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized(FIG. | 2010-08-05 |
| 20100195413 | SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit. | 2010-08-05 |
| 20100195414 | LEVEL DETECTOR, INTERNAL VOLTAGE GENERATOR INCLUDING LEVEL DETECTOR, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING INTERNAL VOLTAGE GENERATOR - A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage. | 2010-08-05 |
| 20100195415 | Semiconductor memory device and reading method therefor - A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a reference bit line, to thereby charge the bit line and the reference bit line to an initial voltage. After the charge, a selected memory cell is connected to the bit line, the reference bit line is connected to a reference voltage generating circuit, and a voltage differential type sense amplifier amplifies a difference voltage between a voltage of the bit line decreased by discharge of the selected memory cell and a voltage of the reference bit line generated by the reference voltage generating circuit, to thereby read out memory cell data. | 2010-08-05 |
| 20100195416 | Anti-fuse circuit and semiconductor memory device - An anti-fuse circuit uses first to fifth power supplies which have first to fifth power supply voltages, respectively, in the order of highest to lowest during writing. The anti-fuse circuit includes: a first level shift circuit which is connected to the second to fourth power supplies and which converts a first logic signal that changes between the third and fourth power supply voltages into a second logic signal that changes between the second and fourth power supply voltages; a second level shift circuit which is connected to the first, second, and fourth power supplies and which converts the second logic signal into a third logic signal that changes between the first and fourth power supply voltages; a transistor having a source connected to the first power supply and a gate connected to the third logic signal; and an anti-fuse element having one end connected to the drain of the transistor and the other end connected to the fifth power supply. | 2010-08-05 |
| 20100195417 | SEMICONDUCTOR DEVICE, CIRCUIT OF CONTROLLING SIGNAL LINES AND METHOD OF CONTROLLING SIGNAL LINES - A semiconductor device includes first and second lines, and a switch between the first and second lines. The switch temporary and electrically connects the first and second lines to each other, when the first signal line is transitioned from a first level to a second level while the second signal line is transitioned from the second level to the first level. | 2010-08-05 |
| 20100195418 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - Provided is a semiconductor memory device. The semiconductor memory device includes first and second memory chips and a control logic configured to execute an interleave program between the first and second memory chips. The control logic receives write data to be written into first and second memory blocks of the first memory chip. If the first and second memory blocks are normal blocks, the control logic simultaneously performs a program operation for the first and second memory blocks. If one memory block of the first and second memory blocks is a bad block, the control logic writes the received write data corresponding to the one memory block into a storage circuit. | 2010-08-05 |
| 20100195419 | Configurable Write Policy in a Memory System - A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used. | 2010-08-05 |
| 20100195420 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - A semiconductor memory system includes a memory controller and a memory. The memory controller includes a control signal converting unit converting a control signal into a converted control signal including n sequential clock pulses and a target clock pulse activated after a time period has elapsed from a start point of the n sequential clock pulses, and output the converted clock signal, and a controller transmitting unit converting the converted control signal into an optical signal, and transmitting the optical signal to the memory. The memory includes a memory receiving unit converting the optical signal into an electrical signal, and a control signal re-converting unit detecting the time period from the electrical signal, and converting the control signal into a control signal corresponding to the time period. | 2010-08-05 |
| 20100195421 | STACKED-DIE MEMORY SYSTEMS AND METHODS FOR TRAINING STACKED-DIE MEMORY SYSTEMS - Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault. | 2010-08-05 |
| 20100195422 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A semiconductor integrated circuit includes: a current difference sense type of a sense amplifier including: an input line connected to memory cells as a target to be read, a reference line connected to reference cells, and a first pre-charge circuit configured to pre-charge the input line and the reference line; a second pre-charge circuit configured to perform pre-charging of the input line and pre-charging of the reference line; and a control circuit configured to control the second pre-charge circuit so that the second pre-charge circuit may perform both the pre-charging of the input line and the pre-charging of the reference line independently of each other, and start both the pre-charging of the input line and the pre-charging of the reference line earlier than pre-charging by the first pre-charge circuit. | 2010-08-05 |
| 20100195423 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit. | 2010-08-05 |
| 20100195424 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device | 2010-08-05 |
| 20100195425 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND MEMORY REPAIR METHOD - A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being detected by the BIST circuit, and a repair register configured to store data for the address of the defective bit. The semiconductor device also includes an address controller configured to, based on the address retained in the eFuse macro, perform control to use the repair register during writing or reading of data to or from the address of the defective bit. | 2010-08-05 |
| 20100195426 | Semiconductor memory device and method of testing the same - A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal. | 2010-08-05 |
| 20100195427 | 1-TRANSISTOR TYPE DRAM CELL, DRAM DEVICE AND DRAM COMPRISING THEREOF AND DRIVING METHOD THEREOF AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device, and more precisely to an 1-transisotr type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process allowing a write current to be flowed from the bit line to a floating body by rasing the bit line to the second constant voltage level and raising the sensing line to the half second constant voltage level, while maintaining the bias of the word line at the second constant voltage level. | 2010-08-05 |
| 20100195428 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal operation mode, and converts serial data applied to a particular terminal, which is one of the plurality of terminals, to parallel data, and outputs the parallel data to which the serial data applied to the particular terminal is converted to the plurality of drive units in a test mode. | 2010-08-05 |
| 20100195429 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memory device further includes a clock phase adjusting unit that generates a delay to a clock, where the delay is same or longer than the time taken from when the external access request is issued until when a critical path is passed, and the delay is also shorter than one cycle. Then a flip-flop retrieves the request from the command decoder at the clock timing from the clock phase adjusting unit to supply it to the memory cell array. | 2010-08-05 |
| 20100195430 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 2010-08-05 |
| 20100195431 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed. | 2010-08-05 |
| 20100195432 | POURING AND MIXING LID FOR CYLINDRICAL CONTAINERS - A cover for blending one or more materials in an open topped container. The cover is adapted to close the open top during blending. The cover may have a central hole for passing the shaft of a powered blender and a peripheral opening for pouring materials from the container or into a container, and to view the progress of the mixing. Optionally, the cover may have a third opening and as a further option, a fourth opening, the third and fourth openings adapted to connect to a commercial vacuum device for evacuating dust from the container during blending. The third and fourth openings may be formed as prescored removable portions of the cover. In a further option, the third and fourth openings may be provided with close fitting removable resilient plugs. The upper surface of the cover may be inclined so that liquids flow towards the peripheral opening and into the container. | 2010-08-05 |
| 20100195433 | APPARATUS FOR PROCESSING MATERIAL, SUCH AS A BIOMASS OR FEED FOR CATTLE - An apparatus for processing material, such as a biomass or fodder for cattle, comprises a container having a bottom and an upright wall, and at least one mixing element comprising an upright column and a mixing blade attached to the column. A front edge of the mixing element at least substantially joins the bottom of the container. The mixing element with its column is rotatably mounted in the container and can be coupled to a drive unit. The mixing blade comprises an element which is rotatably supported on a carrier that is fixed to the column. A part of the circumferential edge of the rotatable element may form the front edge and the part of the outer edge of the mixing blade that joins said front edge. | 2010-08-05 |
| 20100195434 | Heterodyned Seismic Source - The invention relates to an apparatus for generating heterodyned seismic signals as well as methods of using the heterodyned signals and a system for generating the heterodyned seismic signals. The heterodyned signals can be used near sensitive marine animals because the source frequencies are ultrasonic and the heterodyned seismic signal is generated in a narrow beam. | 2010-08-05 |
| 20100195435 | Protective socket for a sensor node - The present invention relates to a seismic cable ( | 2010-08-05 |
| 20100195436 | METHODS AND SYSTEMS FOR DEPLOYING SEISMIC DEVICES - Methods and systems for acoustically determining reservoir parameters of subterranean formations. A tool comprising at least one seismic source or seismic receiver mounted thereon; a conveyance configured for movement of the acoustic tool in a borehole traversing the subterranean formations; and a source retainer configured or designed for permanent deployment in the borehole to removably retain the acoustic tool in the borehole. The source retainer when deployed provides acoustic coupling with the borehole and removably retains the acoustic tool in the borehole so that, over multiple deployments, the acoustic tool is repeatedly deployed at the same predetermined location and orientation relative to the subterranean formation, and with the same acoustic coupling to the borehole. | 2010-08-05 |
| 20100195437 | VELOCITY MODEL FOR WELL TIME-DEPTH CONVERSION - Systems and methods create a velocity model for well time-depth conversion. In one implementation, a system optimizes a time-depth relationship applied to data points from a single well to estimate coefficients for a velocity function that models the data points. The system optimizes by reducing the influence of outlier data points, for example, by weighting each data point to decrease the influence of those far from the velocity function. The system also reduces the influence of top and bottom horizons of geological layers by applying data driven techniques that estimate the velocity function without undue dependence on the boundary conditions. The system can optimize estimation of a rate of increase in velocity to enable the velocity function to go through a data point on each top horizon. The system may also estimate each base horizon from trends in the data points and adjust the velocity function to go through a data point on each base horizon. | 2010-08-05 |
| 20100195438 | DERIVING TILT-CORRECTED SEISMIC DATA IN A MULTI-AXIS SEISMIC SENSOR MODULE - A seismic sensor module includes sensing elements arranged in a plurality of axes to detect seismic signals in a plurality of respective directions, and a processor to receive data from the sensing elements and to determine inclinations of the axes with respect to a particular orientation. The determined inclinations are used to combine the data received from the sensing elements to derive tilt-corrected seismic data for the particular orientation. | 2010-08-05 |
| 20100195439 | SEISMIC ACQUISITION SYSTEM AND TECHNIQUE - An apparatus includes an array of seismic sensor units that are adapted to acquire measurements in connection with a land surface-based seismic survey. Each seismic sensor unit includes a particle motion sensor and a rotation sensor. | 2010-08-05 |
| 20100195440 | CORRECTION OF VELOCITY CUBES FOR SEISMIC DEPTH MODELING - Systems and methods perform correction of velocity cubes for seismic depth modeling. An example system receives a velocity model defined in the time domain for seismic modeling of a subsurface earth volume and receives well depth data associated with the subsurface earth volume. The system updates an average velocity cube associated with the velocity model to correct depth-converted time horizons to accord with known well markers, thereby increasing the accuracy and correctness of the velocity model. | 2010-08-05 |
| 20100195441 | PARALLEL-PATH ACOUSTIC TELEMETRY ISOLATION SYSTEM AND METHOD - An acoustic telemetry isolation system and method for use with tubular assemblies such as drillpipe and production tubing includes an acoustic wave transmitter and an acoustic isolator. A “down” wave propagated toward the isolator is reflected back substantially in phase with an “up” wave propagated from the acoustic wave source away from the isolator. Furthermore, the acoustic isolator is similarly effective in reflecting “up” propagating waves originating from below the isolator, hence further protecting the acoustic wave source from possible deleterious interference. The construction of the isolator utilizes a specified combination of waves traveling in parallel in materials whose properties aid the beneficial combination of reflected and transmitted waves. The design of the isolator is to generally provide a bandstop filter function, thereby aiding the frequency isolation of an acoustic transmitter over a passband that may be constrained by the geometry of drill pipe or components of production tubing. It causes substantially all of the emitted wave energy to travel in a chosen direction along the drill pipe, thus aiding the efficiency of acoustic telemetry in the pipe. | 2010-08-05 |
| 20100195442 | MUD PULSE TELEMETRY DATA MODULATION TECHNIQUE - A technique for communicating data within a wellbore is provided. In one embodiment, a method includes receiving digital data and encoding the digital data into symbols each representative of one or more data bits of the digital data In this embodiment, the method also includes modulating the phase of an acoustic wave within the wellbore to represent the plurality of symbols, wherein modulating the phase of an acoustic wave includes changing the phase of the acoustic wave such that the acoustic wave includes smooth phase transitions between successive phases representative of the plurality of symbols. Various additional methods, systems, and devices are also provided. | 2010-08-05 |
| 20100195443 | Transducer Array Arrangement and Operation for Sodar Application - An array of transducers for a sodar system, and the operation of the array in a monostatic sodar system. The array is made up of a number of individual sound transducers. Each transducer emits sound into the atmosphere and senses emitted sound that has been reflected by the atmosphere. The transducers have a generally circular cross-sectional shape. The transducers are arranged in a generally planar, generally hexagonal grid packing arrangement. | 2010-08-05 |
| 20100195444 | LOUDSPEAKER POSITION ESTIMATION - The invention relates to an automated estimation of the position (co-ordinates) of a set of loudspeakers in a room Based on measured impulse responses the distances between each pair of loudspeakers are estimated, thereby forming a distance matrix, and the resultant distance matrix is used by a multidimensional scaling (MDS) algorithm to estimate the co-ordinates of each individual loudspeaker An improved co-ordinate estimation can, if desired, be derived by utilising the stress values provided by the MDS algorithm. | 2010-08-05 |
| 20100195445 | Systems And Methods With Improved Three-Dimensional Source Location Processing Including Constraint Of Location Solutions To A Two-Dimensional Plane - Systems and methods are disclosed associated with processing origin/location information of a source or event. In one exemplary implementation, there is provided a method of performing improved three-dimensional source location processing including constraint of location solutions to a two-dimensional plane. Moreover, the method includes obtaining a plane of constraint characterized as a plane in which the source is likely to occur, providing one or more virtual sensing elements each characterized as being located on a first side of the plane of constraint in a mirror image/symmetrical position across from a corresponding actual sensing element on an opposite side of the plane, and constraining possible origin locations to be located in the plane of constraint. Other exemplary implementations may include determining the origin location as a function of positions of the sensing elements and the virtual sensing elements as well as time-of-arrival and/or angle-of-arrival information. | 2010-08-05 |
| 20100195446 | DETERMINING ENCLOSURE BREACH ULTRASONICALLY - A structure intrusion may be determined. For example, a signal may be received corresponding to a wave propagating in the structure. Next, the received signal may be analyzed. Based on the analysis in a “passive mode”, a breach may be determined to have occurred in the structure when the received signal indicates that at least one aspect of the received signal crosses a predetermined threshold. Furthermore, based on the analysis in an “active mode”, a breach may be determined to have occurred in the structure when comparing the received signal to a baseline waveform indicates that at least one aspect of the received signal varies from the baseline waveform by a predetermined amount. The wave propagating in the structure may comprise an elastic wave and may be in an acoustic frequency range or in an ultrasonic frequency range. | 2010-08-05 |
| 20100195447 | Alarm clock and a system and a method to wake a user - An alarm clock, a system and a method wake a user. The alarm clock may have a transmitter which sends a signal to an ear piece which may be worn in and/or on an ear of a user. The earpiece may emit an alert in response to the wireless signal to alert the user to a specified time without disturbing other individuals. The earpiece may have a vibrating module which may emit vibrations into the ear after receiving the signal. The earpiece may have a speaker which may emit an audible alert. | 2010-08-05 |
| 20100195448 | Wireless Clock System and Method - A wireless clock system includes a master clock or other master time source, and a plurality of slave clocks or repeater devices. Each slave clock can both wirelessly receive and wirelessly transmit time signals including current time data. To avoid conflicts among the slave clocks, each slave clock transmits time signals in a frequency-hopping manner over pseudo-randomized frequencies and at pseudo-randomized transmission start times. In another embodiment, power consumption at the slave clocks is minimized by activating and deactivating receivers within the slave clocks at predetermined times and at predetermined intervals, each interval being longer than the previous interval, until valid time signals are received from either the master clock or another slave clock. Calibration of the slave clock's time base is also performed. | 2010-08-05 |
| 20100195449 | CLOCK WORK MOVEMENT FOR A WRISTWATCH - Clockwork movement for a wristwatch, comprising a kinematic chain including at least one belt ( | 2010-08-05 |
| 20100195450 | MAGNETIC DISK DRIVE - A magnetic disk drive, comprising: a slider, which is provided at a position facing to a disk surface; an arm, which is configured to conduct rocking motion around a pivot; a base, which is configured to support a motor thereon, which rotates the disk; a semiconductor laser module, which is configured to be fixed on the arm and stores a semiconductor laser element therein; a light irradiation portion upon the disk surface; and a wave guide, which is configured to build up an optical path between the light irradiation portion and the semiconductor laser module, wherein the semiconductor laser module and a portion of the base are connected therebetween by a flexible heat-conductive member having a predetermined curvature. | 2010-08-05 |
| 20100195451 | OPTICAL DISK PLAYBACK DEVICE - An optical disk playback device includes a first control means for holding difference information which the first control means generates by, during playback of an optical disk | 2010-08-05 |
| 20100195452 | CONTENTS DATA REPRODUCTION APPARATUS AND CONTENTS DATA REPRODUCTION METHOD - The present invention facilitates operations of updating, altering and/or otherwise recomposing the reproduction list of contents data prepared according to the frequency of reproduction, the priority of reproduction, the preference of the user and so on. There is provided a contents data reproduction apparatus for reproducing contents data, which includes a detecting section that detects the external force, a weighting information generating section that generates weighting information, a memory section that stores the weighting information, a reproduction control section that composes a reproduction list of the contents data, a reproduction section that reads out the contents data and reproducing them, and a display section that visibly displays the reproduction list, the reproduction control section recomposing the reproduction list of the contents data, referring to the weighting information, according to the outcome of detection of the detecting section and visibly displaying the reproduction list on the display section. | 2010-08-05 |
| 20100195453 | OPTICAL DISC DEVICE AND FOCUS CONTROL METHOD - Disclosed is an optical disc device that is able to increase accuracy in reproducing information from an optical disc. The optical disc device | 2010-08-05 |
| 20100195454 | Optical disc recording apparatus - An optical pickup is disposed which irradiates a laser beam onto an optical disc where a guide groove having characteristics of thermal interference (heat discoloration) is spirally formed. The optical pickup irradiates the laser beam along the guide groove to conduct one of data recording in which pits indicating a data length are formed, and visible-image formation in which a part of the optical disc is discolored. The laser beam irradiation position is controlled so that the data recording is conducted with starting from the inner peripheral side of the optical disc, and the visible-image formation is conducted with starting from the outer peripheral side of the optical disc. | 2010-08-05 |
| 20100195455 | OPTICAL DISC APPARATUS, FOCUS ERROR SIGNAL ADJUSTMENT METHOD, PROGRAM, AND INTEGRATED CIRCUIT - To adjust the symmetry of a focus error signal, the symmetry of the focus error signal needs to be measured during upward and downward driving of an objective lens, which is performed at every varying setting of a signal correction gain value of the focus error signal, and such adjustment takes a long time. An optical disc device ( | 2010-08-05 |
| 20100195456 | OPTICAL DISC CONTROL DEVICE - There is provided an optical disc control device which can perform stable repetitive control without deteriorating the followability of a target value when performing jumping, retry, and long seek. The optical disc control device comprises an adder which receives a compensation target signal having a periodic frequency component, which is read out from an optical disc; a filter which outputs a signal component included in an arbitrarily determined learning frequency band in the output signal of the adder; a memory which successively updates and stores the output signal of the filter; a gain element which multiplies signal information outputted from the memory by a gain which is not less than 0 and not larger than 1, and inputs the product to the adder; a rotation speed detector which detects the rotation speed of the optical disc; a disc position detector which detects the position of the pickup on the optical disc; a circumferential direction move amount calculator which calculates the move amount of the pickup in the circumferential direction on the optical disc; and a memory controller which control the addresses for reading out the signal information stored in the memory on the basis of the circumferential direction move amount which is calculated by the circumferential direction move amount calculator. | 2010-08-05 |
| 20100195457 | OPTICAL DISC SIGNAL PROCESSING DEVICE, OPTICAL DISC SIGNAL PROCESSING METHOD, OPTICAL DISC REPRODUCTION AND RECORDING DEVICE, AND OPTICAL DISC REPRODUCTION AND RECORDING METHOD - An optimum method for adjusting the physical position or angle of an optical pickup (a | 2010-08-05 |
| 20100195458 | INFORMATION RECORDING MEDIUM, RECORDING APPARATUS, REPRODUCING APPARATUS AND REPRODUCING METHOD - An information recording medium, comprising N number (N is an integer fulfilling N≧3) of information layers on which information is recordable, and allowing information to be recorded on each of the information layers and allowing information recorded on each of the information layers to be reproduced by being irradiated with laser light. The N number of information layers include an N′th information layer, an (N−1)th information layer, an (N−2)th information layer, . . . a second information layer and a first information layer sequentially located from a laser light incidence side. A reflectance of the N′th information layer is R | 2010-08-05 |
| 20100195459 | Adjustment Method Of Optimum Write Power And Optical Write/Retrieval Device - A power adjustment method in which a modulation index is calculated from reproduced signals of patterns recorded by irradiating light onto an optical information recording medium with a recording power varied and an optimum power of irradiation light is set up using the modulation index. The power adjustment method includes calculating an optimum value PcO of a predetermined correction term Pc using a relation of a value obtained by subtracting the predetermined correction term Pc from the recording power and the modulation index, finding a value Pth of the recording power at which the modulation index becomes substantially zero in the relation of the value obtained by subtracting the optimum value PcO from the recording power and the modulation index, and setting up a value obtained by multiplying the value of Pth by a predetermined constant as a recording power of each of the recording patterns. | 2010-08-05 |
| 20100195460 | OPTICAL WRITING APPARATUS, IMAGE FORMING APPARATUS AND DATA WRITING METHOD - An optical writing apparatus includes: a light source section having a plurality of light emitting elements arrayed in a main scanning direction; an optical section having a plurality of imaging lenses that condense irradiated light from the light emitting elements to form an image on an exposure surface; and a storage section. The storage section stores: first correction data including light amount correction values for correcting amounts of light of the respective light emitting elements; and second correction data. The second correction data includes: local correction target position information in an array direction of the light emitting elements that is calculated based on optical characteristics data specific to the imaging lenses; and a correction reference value for correcting one or more of the light amount correction values of one or more of the light emitting elements arrayed at local positions indicated by the correction target position information. | 2010-08-05 |
| 20100195461 | Multi-Session Pre-Recorded Storage Medium - Apparatus characterized as a multi-session data storage medium such as an optical disc, and method for formatting the same. In accordance with various embodiments, a first session is recorded onto the medium with a first set of user data. A second session is subsequently recorded onto the medium with a second set of user data. The second session contactingly abuts the first session without the use of an intervening linking area therebetween. This enhances the data storage capacity of the medium irrespective of the total number of sessions applied thereto. In some embodiments, the first session is described by a first file system and the second session is described by a different, second file system independent of the first file system. The respective file systems may be accessed by different readback systems, such a personal computer (PC) and a gaming system. | 2010-08-05 |
| 20100195462 | METHOD OF EVALUATING REPRODUCE SIGNAL AND OPTICAL DISC DRIVE - A highly efficient and reliable reproduced signal evaluation method and an optical disc drive using that method in which assuming that the number of 2T's appearing successively in a predetermined evaluation bitstream is i, the evaluation bitstream is divided into a main bitstream (5+2i) long and sub bitstreams at the ends of the main bitstream. The check process to determine whether a predetermined evaluation bitstream is included in the binarized bitstreams is replaced with a main bitstream agreement check. This can prevent an increase in the circuit size. At the same time, by separately summing up for each main bitstream the calculated results of Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bitstream, the size of an evaluation summing circuit can be reduced. | 2010-08-05 |
| 20100195463 | STORAGE DEVICE AND INFORMATION PROCESSING APPARATUS - According to one embodiment, a power management module of a storage device executes a process of stopping rotation of a disk storage medium by selectively using one of a first mode of stopping the rotation of the disk storage medium on condition that a media access command is not received during a predetermined time from last reception of a media access command, and a second mode of stopping the rotation of the disk storage medium on condition that a media access command which causes access to the disk storage medium is not received during a predetermined time from last reception of a media access command which causes access to the disk storage medium. In addition, the power management module executes a process of starting the rotation of the disk storage medium by selectively using one of a third mode and a fourth mode. | 2010-08-05 |
| 20100195464 | INTEGRATED CIRCUIT, OPTICAL DISC SYSTEM AND TRACKING ERROR SIGNAL GENERATION METHOD - A first comparator ( | 2010-08-05 |
| 20100195465 | METHOD OF RECORDING INFORMATION TO AND REPRODUCING INFORMATION FROM AN OPTICAL INFORMATION STORAGE MEDIUM - A method of recording information to a read-only optical information storage medium comprising a plurality of areas, including: recording data in at least one of the plurality of areas in the form of pits in a first pit pattern; and recording data in others of the plurality of areas in the form of pits in a second pit pattern different from the first. | 2010-08-05 |
| 20100195466 | ELECTRONIC DEVICE, DATA RECORDING METHOD AND DATA RECORDING SYSTEM - Data to be recorded onto a recording medium | 2010-08-05 |
| 20100195467 | OPTICAL DISC RECORDING/REPRODUCING APPARATUS - There is provided an optical disc recording/reproducing apparatus which can reduce the chip size using the high-miniaturization process and can enhance the detection accuracy. A signal which is obtained by amplitude-adjusting a header region in a reproduced signal detected by an optical pickup ( | 2010-08-05 |
| 20100195468 | OPTICAL DATA STORAGE MEDIA CONTAINING METAL AND METAL OXIDE DARK LAYER STRUCTURE - Optical data storage media containing a “dark” layer structure are disclosed. Layered metals and metal oxides provide a dark background that enhances detection of changes in the data layer of the storage media. Combinations such as chromium metal and chromium oxide, and molybdenum metal and molybdenum oxide are offered as examples of suitable materials. | 2010-08-05 |
| 20100195469 | Media Pre-Write With Track-Aligned Write Beam Deflection and Write Frequency Adjustment - Method and apparatus for formatting a data storage medium, such as a magnetic or optical disc. In accordance with various embodiments, a data storage medium is rotated while a write beam is used to write data to the rotating medium. The data are written in the form of a plurality of concentric data tracks. A deflection angle of the write beam is continuously adjusted in an axial direction along each track. In some embodiments, the axial deflection of the write beam imparts a desired angular offset between a beginning point of a first track and a beginning point of an immediately adjacent second track. This allows a first translation geometry, such as a linear translation path of a linear actuator, to emulate a different second translation geometry, such as a rotary translation path of a rotary actuator. | 2010-08-05 |
| 20100195470 | Optical Disk Recording/Reproducing Apparatus And Alternation Process Method Thereof - A disk recording/reproducing apparatus includes a disk rotator which rotates an optical disk, an optical pickup, a slide motor which moves the optical pickup into a radial direction of the optical disk, and a controller which controls at least the disk rotator and the slide motor in accordance with a signal obtained from the optical pickup. The controller determines an alternation destination for recording data at an alternation origin therein or during the alternation process depending on a position of the alternation origin on the optical disk and a reference position on the optical disk, when the optical disk has an alternation area on an innermost periphery and an outermost periphery, and the recording/reproducing apparatus conducts the alternation process upon detection of a defect block within a user data recording area on the optical disk, thereby conducting the alternation process thereon. | 2010-08-05 |
| 20100195471 | Optical storage medium, optical read/write apparatus, and optical read/write method - An optical read/write apparatus causes a read/write light beam from illuminating means to strike only one side of an optical storage medium including stacked data storage layers each of which is readable/writeable separately from the other layers. In this case, the optical read/write apparatus operates so that data is read/written from/into a second data storage layer after fully recording a recordable area of a first data storage layer. Thus, light can be shone with uniform intensity across the substantially entire recordable area of the second data storage layer without using a complex read/write system even under such conditions that the transmittance to light of the first data storage layer in the recordable area may vary depending on whether any data is recorded in the recordable area. | 2010-08-05 |
