| 31st week of 2010 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20100193771 | QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS - Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well. | 2010-08-05 |
| 20100193772 | Thin film transistor and display device - Provided is a thin film transistor capable of improving reliability in the thin film transistor including an oxide semiconductor layer. A thin film transistor including: a gate electrode; a gate insulating film formed on the gate electrode; an oxide semiconductor layer forming a channel region corresponding to the gate electrode on the gate insulating film; a channel protective film formed at least in a region corresponding to the channel region on the oxide semiconductor layer; and a source/drain electrode. A top face and a side face of the oxide semiconductor layer are covered with the source/drain electrode and the channel protective layer on the gate insulating film. | 2010-08-05 |
| 20100193773 | Nitrogen-containing heterocycle derivative and organic electroluminescent element using the same - A novel derivative of heterocyclic compound having nitrogen atom with a structure made by bonding special groups to benzimidazole, a material for an organic electroluminescence (EL) device comprising the derivative of heterocyclic compound having nitrogen atom and an organic electroluminescence device comprising at least one organic compound layer containing a light emitting layer sandwiched between a pair of electrodes, wherein the device contains the derivative of heterocyclic compound having nitrogen atom. An organic EL device achieving elevation of luminance and of efficiency in light emission even under low driving voltage is obtainable by an employment of the derivative of heterocyclic compound having nitrogen atom for at least one layer composing organic compound layers of the EL device. | 2010-08-05 |
| 20100193774 | Quinoid Compounds and Their Use in Semiconducting Matrix Materials, Electronic and Optoelectronic Structural Elements - The invention relates to quinoid compounds and their use in semiconductive matrix materials, electronic and optoelectronic structural elements. | 2010-08-05 |
| 20100193775 | ORGANIC TRANSISTOR, ORGANIC TRANSISTOR ARRAY, AND DISPLAY DEVICE - An organic transistor includes a substrate; a gate electrode and a gate insulating film sequentially formed on the substrate in the stated order; and a source electrode, a drain electrode, and an organic semiconductor layer formed on at least the gate insulating film. Ultraviolet light is radiated to the substrate from a side without the gate electrode, transmitted through the substrate and the gate insulating film, reflected at the gate electrode, and absorbed at the organic semiconductor layer. Conductivity of the organic semiconductor layer that has absorbed the ultraviolet light is lower than that of the organic semiconductor layer that has not absorbed the ultraviolet light. | 2010-08-05 |
| 20100193776 | ORGANIC ELECTROLUMINESCENT DEVICE - An organic electroluminescent device | 2010-08-05 |
| 20100193777 | METHOD OF PRODUCING A DESUBSTITUTED COMPOUND, ORGANIC SEMICONDUCTOR FILM AND METHOD OF PRODUCING THE SAME - A method of producing a desubstituted compound, including: applying an external stimulation to a compound A-(B) | 2010-08-05 |
| 20100193778 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode display with first and second substrates, and a method of manufacturing the organic light emitting diode display. The first substrate has a plurality of first organic light emitting diodes each having a first emissive area and a first non-emissive area, and a first driving circuit unit for driving the first organic light emitting diodes. The second substrate has a plurality of second organic light emitting diodes each having a second emissive area and a second non-emissive area, and a second driving circuit unit for driving the second organic light emitting diodes. The first emissive areas of the first organic light emitting diodes face the second non-emissive areas of the second organic light emitting diodes, respectively, and the second emissive areas of the second organic light emitting diodes face the first nonemissive area of the first organic light emitting diodes, respectively. | 2010-08-05 |
| 20100193779 | BOTTOM GATE THIN FILM TRANSISTOR, FLAT PANEL DISPLAY HAVING THE SAME AND METHOD OF FABRICATING THE SAME - A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes. | 2010-08-05 |
| 20100193780 | METHOD OF FORMING MEMORY CELL USING GAS CLUSTER ION BEAMS - A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes. | 2010-08-05 |
| 20100193781 | MICROMECHANICAL STRUCTURE AND A METHOD OF FABRICATING A MICROMECHANICAL STRUCTURE - A micromechanical structure and a method of fabricating a micromechanical structure are provided. The micromechanical structure comprises a silicon (Si) based substrate; a micromechanical element formed directly on the substrate; and an undercut formed underneath a released portion of the micromechanical element; wherein the undercut is in the form of a recess formed in the Si based substrate. | 2010-08-05 |
| 20100193782 | TRANSISTOR AND METHOD FOR MANUFACTURING THE TRANSISTOR - It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer. | 2010-08-05 |
| 20100193783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In forming a thin film transistor, an oxide semiconductor layer is used and a cluster containing a titanium compound whose electrical conductance is higher than that of the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer. | 2010-08-05 |
| 20100193784 | THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A thin-film transistor includes: a gate electrode formed on a substrate; an oxide semiconductor layer forming a channel region corresponding to the gate electrode; a first gate insulating film formed on the substrate and the gate electrode, and including a silicon nitride film; a second gate insulating film selectively formed to contact with the oxide semiconductor layer in a region, on the first gate insulating film, corresponding to the oxide semiconductor layer, and including one of a silicon oxide film and a silicon oxynitride film; a source/drain electrode; and a protecting film. An upper surface and a side surface of the oxide semiconductor layer and a side surface of the second gate insulating film are covered, on the first gate insulating film, by the source/drain electrode and the protecting film. | 2010-08-05 |
| 20100193785 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor. | 2010-08-05 |
| 20100193786 | Structures for measuring misalignment of patterns - A structure for measuring misalignment of patterns may include a first wiring and a second wiring. The first wiring may include a first lower pattern and a first upper pattern. The first upper pattern may extend in a y-direction, and a first end portion of the first upper pattern that is relatively further toward (proximal to) a negative y-direction may contact the first lower pattern. The second wiring may include a second lower pattern and a second upper pattern. The second upper pattern may extend in the y-direction, a second end portion of the second upper pattern that is relatively further toward (proximal to) a positive y-direction may contact the second lower pattern. The second wiring may be spaced apart from the first wiring along the negative y-direction. | 2010-08-05 |
| 20100193787 | Semiconductor device - A semiconductor device, includes a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor element installed in the first surface of the package substrate. The package substrate includes a plurality of first land pads disposed in the first surface, second land pads disposed in the second surface and a second testing-dedicated pad disposed in the second surface. The semiconductor element is electrically coupled to the first land pads, an inter-pad distance for the second land pads is larger than an inter-pad distance for the first land pads, the first land pad contains a first testing-dedicated pad electrically coupled to the semiconductor element, the first testing-dedicated pad and the second testing-dedicated pad each include a dedicated terminal, which is essential for applying a specified electrical signal from an LSI tester, when an LSI testing is conducted for a semiconductor wafer and the first testing-dedicated pad is electrically coupled to only the second testing-dedicated pad through a wiring. | 2010-08-05 |
| 20100193788 | AREA SENSOR AND DISPLAY APPARATUS PROVIDED WITH AN AREA SENSOR - An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light. | 2010-08-05 |
| 20100193789 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit. | 2010-08-05 |
| 20100193790 | FLAT PANEL DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A flat panel display apparatus that can be manufactured with less patterning operations using a mask, and a method of manufacturing the same, the flat panel display apparatus including a substrate; an active layer of a thin film transistor (TFT); a first bottom electrode and a first top electrode of a capacitor; a first insulation layer formed on the substrate; a gate bottom electrode and a gate top electrode corresponding to the channel region; a second bottom electrode and a second top electrode of the capacitor; a pixel bottom electrode and a pixel top electrode; a second insulation layer formed on the gate electrode, the second electrode of the capacitor, and the pixel top electrode; and a source electrode and a drain electrode formed on the second insulation layer. | 2010-08-05 |
| 20100193791 | Organic light emitting diode display device and method of fabricating the same - An OLED display device includes a substrate, a TFT on the substrate, the TFT including a semiconductor layer, a gate electrode, and source and drain electrodes, a first electrode electrically connected to one of the source and drain electrodes, a pixel defining layer on the substrate, the pixel defining layer exposing the first electrode and having a reversed trapezoidal shape, an emitting layer on the exposed first electrode, and a second electrode on the emitting layer. | 2010-08-05 |
| 20100193792 | LAMINATED FILM MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A production method for a semiconductor film according to the present invention includes: step (a) of forming a first film | 2010-08-05 |
| 20100193793 | CIRCUIT BOARD AND DISPLAY DEVICE - The present invention provides a circuit board having a reduced wiring area in a circuit portion and therefore suitably used for reduction in a display region of a display device, and further provides a display device including such a circuit board. The present invention is a circuit board including:
| 2010-08-05 |
| 20100193794 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device (OLED) including: a substrate including a plurality of pixel units; first electrodes disposed in the pixel units; first subsidiary electrodes completely covering the top surfaces of corresponding ones of the first electrodes; first electrode protection units disposed on edges of the first electrodes on which the first subsidiary electrodes are not disposed; a pixel defining layer disposed on the substrate, having holes to expose the first electrodes; a light emission layer; and a second electrode disposed on the light emission layer. The light emission layer includes organic emission layers (EMLs) disposed on the first electrodes. The light emission layer may include subsidiary hole injection layers disposed on selected ones of the first electrodes, to vary a distance between the first electrodes and portions of the second electrode. | 2010-08-05 |
| 20100193795 | LARGE-GRAIN CRYSTALLINE THIN-FILM STRUCTURES AND DEVICES AND METHODS FOR FORMING THE SAME - Methods for forming semiconductor devices include providing a crystalline template having an initial grain size, annealing the crystalline template, the annealed template having a final grain size larger than the initial grain size, forming a buffer layer over the annealed template, and forming a semiconductor layer over the buffer layer. | 2010-08-05 |
| 20100193796 | Semiconductor device - The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer. | 2010-08-05 |
| 20100193797 | Stacked transistors and electronic devices including the same - Stacked transistors and electronic devices including the stacked transistors. An electronic device includes a substrate, a first transistor on the substrate and including a first active layer, a first gate, and a first gate insulating layer between the first active layer and the first gate, a first metal line spaced apart from the first gate on the substrate, a first insulating layer covering the first transistor and the first metal line, and a second transistor on the first insulating layer between the first transistor and the first metal line, and including a second active layer, a second gate, and a second gate insulating layer between the second active layer and the second gate. | 2010-08-05 |
| 20100193798 | SOURCE FOLLOWER CIRCUIT OR BOOTSTRAP CIRCUIT, DRIVER CIRCUIT COMPRISING SUCH CIRCUIT, AND DISPLAY DEVICE COMPRISING SUCH DRIVER CIRCUIT - In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized. | 2010-08-05 |
| 20100193799 | Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film. | 2010-08-05 |
| 20100193800 | SEMICONDUCTOR DEVICE - A semiconductor device is fabricated on an off-cut semiconductor substrate | 2010-08-05 |
| 20100193801 | SOLDER MATERIAL, METHOD FOR MANUFACTURING THE SAME, JOINED BODY, METHOD FOR MANUFACTURING THE SAME, POWER SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING THE SAME - A zinc based solder material | 2010-08-05 |
| 20100193802 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device is provided. The method includes steps of forming a semiconductor element layer on a first substrate; bonding a second substrate to the semiconductor element layer; and replacing the first substrate with a combining substrate, wherein the combining substrate has a thermal conductivity larger than that of the first substrate. | 2010-08-05 |
| 20100193803 | Stacked Micro Optocouplers and Methods of Making the Same - Disclosed are packages for optocouplers and methods of making the same. An exemplary optocoupler comprises a substrate having a first surface and a second surface, a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's first surface, and a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's second surface. The substrate may comprise a pre-molded leadframe, and electrical connections between optoelectronic dice on opposite surfaces of the substrate may be made via one or more leads of the leadframe. | 2010-08-05 |
| 20100193804 | PHOTODETECTOR AND DISPLAY DEVICE PROVIDED WITH THE SAME - Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate ( | 2010-08-05 |
| 20100193805 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a semiconductor light-emitting element including a first multilayer reflector, an active layer having a light-emitting region, and a second multilayer reflector in the stated order; a semiconductor light-detecting element disposed opposite the first multilayer reflector in relation to the semiconductor light-emitting element and including a light-absorbing layer configured to absorb light emitted from the light-emitting region; and an insulating oxidized layer disposed between the semiconductor light-emitting element and the semiconductor light-detecting element. | 2010-08-05 |
| 20100193806 | Light Emitting Diode Unit, Display Apparatus Having the Same and Manufacturing Method of the Same - Disclosed are a light emitting diode unit, a display apparatus having the same, and a method of manufacturing the same. The light emitting diode unit includes at least one light emitting diode, a quantum dot layer, and a buffer layer. The light emitting diode emits first light. The quantum dot layer is provided on the light emitting diode and includes a plurality of quantum dots that absorb the first light to emit second light having a wavelength different from a wavelength of the first light. The buffer layer is interposed between the light emitting diode and the quantum dot layer and separates the light emitting diode from the quantum dot layer. The buffer layer includes a scattering agent which is dispersed in resin to diffuse the light emitted from the light emitting diode. | 2010-08-05 |
| 20100193807 | LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device comprises a substrate, a first lead frame and a second lead frame on the substrate, a first light emitting diode, a heat conductor on the substrate, and a heat transfer pad. The first light emitting diode on the first lead frame is electrically connected to the first lead frame and the second lead frame. The heat conductor is electrically separated from the first lead frame. The heat transfer pad contacts the first lead frame and the heat conductor thermally to connect the first lead frame to the heat conductor. | 2010-08-05 |
| 20100193808 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF LIGHT EMITTING CELLS AND PACKAGE MOUNTING THE SAME - Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type semiconductor layer located on a portion of the N-type semiconductor layer. The plurality of light emitting cells are bonded to a submount substrate. Accordingly, heat generated from the light emitting cells can be easily dissipated, so that a thermal load on the light emitting device can be reduced. Meanwhile, since the plurality of light emitting cells are electrically connected using connection electrodes or electrode layers formed on the submount substrate, it is possible to provide light emitting cell arrays connected to each other in series. Further, it is possible to provide a light emitting device capable of being directly driven by an AC power source by connecting the serially connected light emitting cell arrays in reverse parallel to each other. | 2010-08-05 |
| 20100193809 | LIGHT EMITTING DIODE STRUCTURE, LED PACKAGING STRUCTURE USING THE SAME AND METHOD OF FORMING THE SAME - A light emitting diode (LED) structure, a LED packaging structure, and a method of forming LED structure are disclosed. The LED structure includes a sub-mount, a stacked structure, an electrode, an isolation layer and a conductive thin film layer. The sub-mount has a first surface and a second surface opposite the first surface. The stacked structure has a first semiconductor layer, an active layer and a second semiconductor layer that are laminated on the first surface. The electrode is disposed apart from the stacked structure on the first surface. The isolation layer is disposed on the first surface to surround the stacked structure as well as cover the lateral sides of the active layer. The conductive thin film layer connects the electrode to the stacked structure and covers the stacked structure. | 2010-08-05 |
| 20100193810 | Optical Device and the Forming Method Thereof - An optical device is provided which includes a first electrode; a substrate disposed on the first electrode; a plurality of multi-layer film structures disposed on the substrate, and the multi-layer film structure consisted of at least two insulated layer with different reflection index formed alternately; a first semiconductor conductive layer disposed on the substrate to cover the multi-layer film structure; an active layer disposed on the first semiconductor conductive layer; a second semiconductor conductive layer disposed on the active layer; a transparent conductive layer disposed on the second semiconductor conductive layer; and a second electrode disposed on the transparent conductive layer, thereby, the multi-layer structure can increase the light reflective effect or anti-reflective effect within the optical device to improve the light emitting effective. | 2010-08-05 |
| 20100193811 | LIGHT EMITTING DIODE - The invention discloses a light-emitting diode including a substrate, a main stack structure, a plurality of secondary pillars, a transparent insulating material, a transparent conducting layer, a first electrode and a second electrode. The pillars are formed on the substrate and surrounding the main stack structure. The main stack structure and each of the pillars has a first conducting-type semiconductor layer, a luminescing layer, and a second conducting-type semiconductor layer formed on the substrate in sequence. The transparent insulating material fills the gaps between the pillars and is as high as the pillars. The transparent conducting layer is coated on the main stack, the pillars and the transparent insulating material. The first electrode is formed on the transparent conducting layer and second electrode is formed on the first conducting-type semiconductor layer. | 2010-08-05 |
| 20100193812 | LIGHT-EMITTING DIODE - The invention discloses a light-emitting diode which comprises a substrate, a first conducting-type semiconductor layer, plural pillars, a transparent insulating material, an illuminating layer, a second conducting-type semiconductor layer, a first transparent conducting layer and a second transparent conducting layer. The first conducting-type semiconductor layer is formed on the substrate, and the top surface of the first conducting-type semiconductor layer comprises a first region and a second region surrounded by the first region. The pillars are formed on the first region. The transparent insulating material is filled in the gaps between the pillars to be as high as the pillars. The illuminating layer is formed on the second region, and the second conducting-type semiconductor layer is formed on the illuminating layer. The first transparent conducting layer is formed on the second conducting-type semiconductor layer, and the second transparent conducting layer is formed on a top surface of the pillars and the transparent insulating material. | 2010-08-05 |
| 20100193813 | LIGHT-EMITTING DIODE - The invention discloses a light-emitting diode comprising a substrate, a primary stack structure, a secondary stack structure, a transparent insulating material and a transparent conducting layer in an embodiment. Each of the primary and the secondary stack structure has a first conducting-type semiconductor layer, an illuminating layer, and a second conducting-type semiconductor layer sequentially formed on the substrate, wherein plural pillar-like holes are formed at the top surface of the second conducting-type semiconductor layer of the secondary stack structure and protrude into the first conducting-type semiconductor layer of the secondary stack structure. The transparent insulating material is filled into the holes. The transparent conducting layer is coated on the primary stack structure, the transparent insulating material, and the top surface of the second conducting-type semiconductor layer of the secondary stack structure. | 2010-08-05 |
| 20100193814 | LIGHT-EMITTING DIODE - The invention discloses a light-emitting diode which includes a substrate on which a first conducting-type semiconductor layer, an illuminating layer and a second conducting-type semiconductor layer are formed sequentially, a transparent insulating material, a first transparent conducting layer, and a second transparent conducting layer. The top surface of the first conducting-type semiconductor layer includes a first region and a second region surrounded by the first region. Plural pillar-like holes are formed at the first region and protrude into the first conducting-type semiconductor layer. The transparent insulating material fills up the holes. The first transparent conducting layer is formed on the second conducting-type semiconductor layer, and the second transparent conducting layer is formed on the top surface of the transparent insulating material and on the first region. | 2010-08-05 |
| 20100193815 | Method for the Manufacture of an Optoelectronic Component and an Optoelectronic Component - A method is disclosed for the manufacture of an optoelectronic component. A substrate has a first primary face and a second primary face that lies opposite the first primary face. A semiconductor body that is capable of emitting electromagnetic radiation from a front side is attached to the first primary face of the substrate. A covering that is transparent to the radiation from the optoelectronic semiconductor body is applied to at least the front side of the semiconductor body. The covering is given the form of an optical element by using a closed cavity that is shaped with the contour of the optical element. | 2010-08-05 |
| 20100193816 | LIGHT EMITTING DIODE PACKAGE AND FABRICATION METHOD THEREOF - A light emitting diode package and a fabrication method thereof are provided. The light emitting diode package comprises a lead frame, having a frame body and a conductive layer covering the frame body. A reflector has a first portion and a second portion sandwiching the lead frame, wherein the first portion has a depression to expose the lead frame, and a light emitting diode chip is disposed on the lead frame in the depression. The fabrication method comprises forming a frame body and forming a conductive layer covering the frame body to form a lead frame. A first portion and a second portion of a reflector are formed to sandwich the lead frame, wherein the first portion has a depression to expose the lead frame. A light emitting diode chip is disposed on the lead frame in the depression. | 2010-08-05 |
| 20100193817 | ORGANIC ELECTROLUMINESCENT ELEMENT AND METHOD FOR MANUFACTURING THE SAME - The present invention provides an organic electroluminescence (EL) element that suppresses leakage current flowing between an upper electrode and an under electrode through an organic layer. The organic EL element ( | 2010-08-05 |
| 20100193818 | Radiation-Emitting Device - A radiation-emitting device has a radiation-emitting component with a layer stack with an active region that is formed for the emission of electromagnetic radiation. A microstructure layer is mechanically coupled to the layer stack and has elevations that extend away from the layer stack. A protective layer has a planar side facing away from the microstructure layer and is arranged on a side of the microstructure layer facing away from the layer stack. | 2010-08-05 |
| 20100193819 | LIGHT-EMITTING SURFACE ELEMENT AND METHOD FOR PRODUCING A LIGHT-EMITTING SURFACE ELEMENT - A light-emitting surface element includes a connection device, a light-generating element having at least two electrical connections electrically conductively connected to assigned connection lines on the connection device, and at least one planar light-guiding element formed by injection-molding in a manner at least partly embedding an arrangement composed of connection device and light-generating element in the planar light-guiding element. | 2010-08-05 |
| 20100193820 | ORGANIC ELECTROLUMINESCENCE DEVICE AND LUMINESCENCE APPARATUS - The invention provides an organic EL device including an anode, a cathode, and a luminescent portion positioned between the anode and cathode, the luminescent portion including two or more luminescent layers, each of the luminescent layers including plural primary luminescent layers that emit light of different colors, and each of the primary luminescent layers having a thickness of 5 nm or less. | 2010-08-05 |
| 20100193821 | OPTICAL ELEMENT PACKAGE AND METHOD OF MANUFACTURING THE SAME - An optical element package includes: an optical element in a form of a chip, and a lens resin having a convex lens surface covering an optical functional surface of the optical element. The convex lens surface is formed as a rough surface having a plurality of minute convex curved surfaces having a vertex in a direction perpendicular to a plane in contact with each part of the convex lens surface. | 2010-08-05 |
| 20100193822 | LIGHT EMITTING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - The light emitting device has a substrate, metallization including silver established on the surface of the substrate, a light emitting element mounted on the substrate, conducting wire that electrically connects the metallization and the light emitting element, light reflective resin provided on the substrate to reflect light from the light emitting element, and insulating material that covers at least part of the metallization surfaces. The insulating material is established to come in contact with the side of the light emitting element. This arrangement can suppress the leakage of light emitting element light from the substrate, and can achieve a light emitting device with high light extraction efficiency. | 2010-08-05 |
| 20100193823 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a method of manufacturing a nitride semiconductor light emitting device and the nitride semiconductor light emitting device manufactured by the method, the method including: forming a light emitting structure by sequentially growing a first conductivity nitride layer, an active layer and a second conductivity type nitride layer on a preliminary substrate for nitride single crystal growth; separating the light emitting structure in accordance with a size of final light emitting device; forming a conductive substrate on the light emitting structure; polishing a bottom surface of the preliminary substrate to reduce a thickness of the preliminary substrate; forming uneven surface structures by machining the preliminary substrate; selectively removing the preliminary substrate to expose portions of the first conductivity type nitride layer; and forming electrodes on the portions of the first conductivity type nitride layer exposed by selectively removing the preliminary substrate. | 2010-08-05 |
| 20100193824 | 2-TERMINAL SEMICONDUCTOR DEVICE USING ABRUPT METAL-INSULATOR TRANSITION SEMICONDUCTOR MATERIAL - Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2 eV and holes in a hole level disposed on the first electrode layer, and a second electrode layer disposed on the abrupt MIT semiconductor organic or inorganic material layer. An abrupt MIT is generated in the abrupt MIT semiconductor material layer by a field applied between the first electrode layer and the second electrode layer. | 2010-08-05 |
| 20100193825 | LIGHT-EMITTING DIODE PACKAGE AND METHOD FOR FABRICATING THE SAME - A light-emitting diode (LED) package is disclosed. The LED package includes a metal substrate, a first insulating polymer layer disposed on the metal substrate, an upper metal layer disposed on surface of the first insulating polymer layer, and at least a LED chip. The first insulating polymer layer includes a cavity and first insulating polymer layer surrounding the cavity includes a reflecting slope, and the LED chip is disposed in the cavity of the first insulating polymer layer and electrically connected to the upper metal layer. | 2010-08-05 |
| 20100193826 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer, and an electrode layer comprising a conductive polymer on the second conductive semiconductor layer. | 2010-08-05 |
| 20100193827 | Pixel Structure and Method for Fabricating the Same - A pixel structure includes a first patterned metal layer, a gate insulating layer, a semiconductor channel layer, a second patterned metal layer, a passivation layer, and a conducting layer. A gate line of the second patterned metal layer is electrically connected by the conducting layer to a gate extension electrode of the first patterned metal layer. A source electrode of the second patterned metal layer is electrically connected by the conducting layer to a second data line segment of the first patterned metal layer. A method for fabricating a pixel structure is also disclosed herein. | 2010-08-05 |
| 20100193828 | LIGHT EMITTING DEVICE AND PACKAGE HAVING THE SAME - There is provided a light emitting device that can minimize reflection or absorption of emitted light, maximize luminous efficiency with the maximum light emitting area, enable uniform current spreading with a small area electrode, and enable mass production at low cost with high reliability and high quality. A light emitting device according to an aspect of the invention includes a light emitting lamination including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer, and a conductive substrate at one surface thereof. Here, the light emitting device includes a barrier unit separating the light emitting lamination into a plurality of light emitting regions, a first electrode structure, and a second electrode structure. The first electrode structure includes a bonding unit, contact holes, and a wiring unit connecting the bonding unit to the contact holes. | 2010-08-05 |
| 20100193829 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE USING THE SAME - There is provided a semiconductor light emitting device, a method of manufacturing the same, and a semiconductor light emitting device package using the same. A semiconductor light emitting device having a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a second electrode layer, and insulating layer, a first electrode layer, and a conductive substrate sequentially laminated, wherein the second electrode layer has an exposed area at the interface between the second electrode layer and the second conductivity type semiconductor layer, and the first electrode layer comprises at least one contact hole electrically connected to the first conductivity type semiconductor layer, electrically insulated from the second conductivity type semiconductor layer and the active layer, and extending from one surface of the first electrode layer to at least part of the first conductivity type semiconductor layer. | 2010-08-05 |
| 20100193830 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE HEAT SPREADER AND DUAL ADHESIVES - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly from the base through an opening in the first adhesive, and the base extends laterally from the post. The first adhesive extends between the base and the conductive trace and the second adhesive extends between the post and the conductive trace. The conductive trace provides signal routing between a pad and a terminal. | 2010-08-05 |
| 20100193831 | EPOXY RESIN COMPOSITION, CURED OBJECT OBTAINED THEREFROM, AND LIGHT-EMITTING DIODE - Provided are an epoxy resin composition including acid anhydrides (A) and epoxy resins (B), in which: (a) cyclohexane-1,2,4-tricarboxylic acid-1,2-anhydride accounts for 50 to 90 mass % of the acid anhydrides (A); (b) an alicyclic epoxy resin compound accounts for 30 to 90 mass % of the epoxy resins (B) and an epoxy resin compound represented by the following general formula (1) accounts for 10 to 50 mass % of the epoxy resins (B); and (c) contents of the acid anhydrides (A) and the epoxy resins (B) are such that a blending equivalent ratio between the acid anhydrides and the epoxy resins ranges from 0.4 to 0.7, a cured product of the composition, and a light-emitting diode. The epoxy resin composition has the following characteristics. That is, (1) the composition has a low viscosity after the mixing, a low degree of viscosity increase in standing at room temperature, and excellent workability, (2) the composition has satisfactory curability even when no curing accelerator is added, and (3) a cured product is colorless and transparent, has crack resistance, and changes its color to a small extent with long-term light irradiation and heating. The composition is suitable for an encapsulant for a photoelectric conversion element such as a blue LED or white LED. (In the formula, R's each independently represent a hydrogen atom or a methyl group, m represents an integer of 1 to 3, and n represents an integer of 2 to 8.) | 2010-08-05 |
| 20100193832 | LIGHT EMITTING DEVICE - A light emitting device is provided that includes a substrate, a light emitting unit formed on the substrate, and an encapsulation unit. The encapsulation unit may include a first region corresponding to the light emitting unit and a second region coalesced with the substrate. The encapsulation unit of the first region or a part of the encapsulation unit of the first region may have a positive curvature. | 2010-08-05 |
| 20100193833 | Nitride-Based Semiconductor Device, Light Apparatus, and Method of Manufacturing Nitride-Based Semiconductor Device - A nitride-based semiconductor device includes a substrate made of a nitride-based semiconductor, a device layer formed on the substrate, and an electrode formed on a surface of the substrate opposite to the device layer. The substrate includes a first surface having a nonpolar plane or a semipolar plane, a second surface opposite to the first surface, a defect concentration region extending in a direction inclined with respect to a normal direction of the first surface from the first surface toward the second surface and penetrating to the second surface and a current path region separated from other region of the substrate by the defect concentration region employed as a boundary, the defect concentration region is not exposed on the first surface, and the electrode is formed on the second surface in the current path region. | 2010-08-05 |
| 20100193834 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light emitting device having a light emitting structure including at least one first conductive GaN based semiconductor layer, an active layer above the at least one first conductive GaN based semiconductor layer, and at least one second conductive GaN based semiconductor layer above the active layer, a plurality of patterns disposed from the at least one second conductive GaN based semiconductor layer through a portion of the at least one first conductive GaN based semiconductor layer, and an insulating member on the plurality of patterns. The plurality of patterns include a lower part contacting with the light emitting structure and a upper part contacting with the light emitting structure. A first base angle of the lower part is different from the second base angle of the upper part. | 2010-08-05 |
| 20100193835 | Trench insulated gate bipolar transistor (GBT) with improved emitter-base contacts and metal schemes - A trench insulation gate bipolar transistor (IGBT) power device includes a plurality of trench gates surrounded by emitter regions of a first conductivity type near a top surface of a semiconductor substrate encompassed in base regions of a second conductivity type and a collector layer disposed at a bottom surface of the semiconductor substrate. The trench IGBT power device further includes an insulation layer covering over the top surface over the trench gate and the emitter regions having emitter-base contact trenches opened therethrough between the trench gates and extending to the base regions and an emitter-base contact dopant region disposed in the base region of the second conductivity type surrounding a lower region of the contact trenches. The emitter-base contact dopant region is disposed at a distance away from a channel near the trench gates for reducing an emitter-base resistance without increasing a gate-emitter threshold voltage. | 2010-08-05 |
| 20100193836 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate. | 2010-08-05 |
| 20100193837 | Semiconductor Device - Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device ( | 2010-08-05 |
| 20100193838 | EPITAXIAL SEMICONDUCTOR LAYER AND METHOD - A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface. | 2010-08-05 |
| 20100193839 | III-V-Group compound semiconductor device - A III-V-group compound semiconductor device includes a substrate, a channel layer provided over the substrate, a barrier layer provided on the channel layer so as to form a hetero-interface, a plurality of electrodes provided on the barrier layer, an insulator layer provided to cover an entire upper surface of the barrier layer except for at least partial regions of the electrodes, and a hydrogen-absorbing layer stacked on the insulator layer or an integrated layer in which an hydrogen-absorbing layer is integrated with the insulator layer. | 2010-08-05 |
| 20100193840 | SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES - A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin. | 2010-08-05 |
| 20100193841 | METHOD FOR FORMING RESIST PATTERN AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The resist material contains a photo-acid generator having an absorption peak to exposure light having a wavelength of less than 300 nm, and a second photo-acid generator having an absorption peak to exposure light having a wavelength of 300 nm or more. The method for forming a resist pattern comprises a step for selectively exposing which exposes a coating film of the resist material to an exposure light having a wavelength of less than 300 nm, and a step for selectively exposing by using an exposure light having a wavelength of 300 nm or more. The semiconductor device comprises a pattern formed by the resist pattern. The method for forming a semiconductor device comprises a step for forming a resist pattern on an underlying layer by the aforementioned manufacturing method, and a step for patterning the underlying layer by etching using the resist pattern as a mask. | 2010-08-05 |
| 20100193842 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device | 2010-08-05 |
| 20100193843 | MANUFACTURE METHOD OF MULTILAYER STRUCTURE HAVING NON-POLAR A-PLANE III-NITRIDE LAYER - A manufacture method of a multilayer structure having a non-polar a-plane {11-22} III-nitride layer includes forming a nucleation layer on a r-plane substrate, wherein the nucleation layer is composed of multiple nitride layers; and forming a non-polar a-plane {11-20} III-nitride layer on the nucleation layer. The nucleation layer features reduced stress, reduced phase difference of lattice, blocked elongation of dislocation, and reduced density of dislocation. Thus, the non-polar a-plane {11-20} III-nitride layer with flat surface can be formed. | 2010-08-05 |
| 20100193844 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - A solid-state imaging device including: light-receiving units which are formed in rows and columns; a transfer channel formed in each column; first and second transfer electrodes that are formed in the same layer and deposited alternately above the transfer channel; insulating regions each formed above the transfer channel and between one of the first transfer electrodes and one of the second transfer electrodes which are adjacent to each other; an antireflection film formed above the light-receiving units, and formed on the insulating regions to cover the insulating regions; a first wire formed in each row in a layer upper than the antireflection film, and electrically connected to second transfer electrodes; and a light-shielding film which is formed in a layer upper than the first wire, covers the transfer channel, and has an opening above each of the light-receiving units. | 2010-08-05 |
| 20100193845 | BACKSIDE ILLUMINATION SEMICONDUCTOR IMAGE SENSOR - A backside illumination semiconductor image sensor, wherein each photodetection cell includes a semiconductor body of a first conductivity type of a first doping level delimited by an insulation wall, electron-hole pairs being capable in said body after a backside illumination; on the front surface side of said body, a ring-shaped well of the second conductivity type, this well delimiting a substantially central region having its upper portion of the first conductivity type of a second doping level greater than the first doping level; and means for controlling the transfer of charge carriers from said body to said upper portion. | 2010-08-05 |
| 20100193846 | SEMICONDUCTOR DEVICE WITH STRAIN - A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region. | 2010-08-05 |
| 20100193847 | METAL GATE TRANSISTOR WITH BARRIER LAYER - A semiconductor fabrication process for forming a gate electrode for a metal-oxide-semiconductor (MOS) transistor includes forming a gate electrode layer of an electrically conductive ceramic, e.g., titanium nitride, overlying a gate dielectric layer, e.g., a high K dielectric. A gate barrier layer is then formed overlying the gate electrode layer. The gate barrier layer may be a metal or transition metal material including, as an example, titanium. Portions of the gate electrode layer and the gate barrier layer are then etched or otherwise removed to form the gate electrode. | 2010-08-05 |
| 20100193848 | IMAGE SENSOR OF STACKED LAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided is a stacked image sensor. Particularly, provided are a stacked image sensor including a photosensitive element portion having a photo-conductive thin film on an upper portion of a wafer where a peripheral circuit is formed and a method of manufacturing the stacked image sensor. In the stacked image sensor according to the present invention, since a wafer where a circuit is formed and a photosensitive element portion are formed in a stacked structure, a whole size of the image sensor can be reduced, and there is no optical crosstalk due to absorption of incident light to adjacent pixels. In addition, since a photo-conductive element having a high light absorbance is used, a high photo-electric conversion efficiency can be obtained. In addition, in the method of manufacturing a stacked image sensor according to the present invention, since the upper photosensitive element can be formed by using a simple low-temperature process, a production cost can be reduced. | 2010-08-05 |
| 20100193849 | SEMICONDUCTOR MEMORY DEVICE INCLUDING FERROELECTRIC FILM AND A METHOD FOR FABRICATING THE SAME - According to one embodiment, a semiconductor memory device having a ferroelectric film, includes a semiconductor substrate, a field effect transistor formed on the semiconductor substrate, an inter-layer insulating film formed on the field effect transistor and the semiconductor substrate, a plug constituted with a single-crystalline structure, the plug being formed in the inter-layer insulating film and being connected with a source or a drain of the field effect transistor, a lower electrode constituted with a single-crystalline structure formed on the plug, a ferroelectric film formed on the lower electrode an upper electrode formed on the ferroelectric film. | 2010-08-05 |
| 20100193850 | SEMICONDUCTOR MEMORY DEVICE - First and second transistors are formed on a substrate. An interlayer insulating film is formed on the first transistor. A first contact is formed in the interlayer film on a source or a drain of the first transistor. A second contact is formed in the interlayer film on the other of the source or the drain. A first interconnect is formed on the first contact. A magnetoresistive element is formed on the second contact. The magnetoresistive element is arranged in a layer having a height equal to that of the first interconnect from a substrate surface. A third contact is formed in the interlayer film on a source or a drain of the second transistor. A second interconnect is formed on the third contact. The second interconnect is arranged in a layer having a height equal to those of the first interconnect and the magnetoresistive element from the substrate surface. | 2010-08-05 |
| 20100193851 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring. | 2010-08-05 |
| 20100193852 | EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION - The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation. | 2010-08-05 |
| 20100193853 | SEMICONDUCTOR DEVICES AND STRUCTURES INCLUDING AT LEAST PARTIALLY FORMED CONTAINER CAPACITORS AND METHODS OF FORMING THE SAME - Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods. | 2010-08-05 |
| 20100193854 | NON-VOLATILE MEMORY DEVICE USING HOT-CARRIER INJECTION - Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation). | 2010-08-05 |
| 20100193855 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A non-volatile semiconductor memory device of small size and high reliability includes a semiconductor substrate; a charge storage film disposed on the semiconductor substrate; a first gate electrode disposed on the charge storage film; a gate insulating film disposed on the semiconductor substrate; a second gate electrode disposed on the gate insulating film; and an inter-gate insulating film disposed between the first gate electrode and the second gate electrode. The length of the first gate electrode is smaller than the length of the second gate electrode. The top surface of the first gate electrode is neither curved nor inclined with respect to the semiconductor substrate. | 2010-08-05 |
| 20100193856 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved. | 2010-08-05 |
| 20100193857 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either the select or the memory gate electrodes are formed prior to the other gate electrodes, each remaining gate electrode is formed adjacent to a side wall of each of the gate electrodes. The semiconductor memory device includes source/drain regions each formed between each pair of the select gate electrodes and between each pair of the memory gate electrodes in protruding portions between each pair of the trenches. A difference between heights of the select gate electrodes and the memory gate electrodes is equal to or greater than a difference between heights of insulation layers formed on the bottom of each of the trenches and the source/drain regions. | 2010-08-05 |
| 20100193858 | NAND MEMORY DEVICE WITH INVERSION BIT LINES AND METHODS FOR MAKING THE SAME - A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed. | 2010-08-05 |
| 20100193859 | BLOCKING DIELECTRIC ENGINEERED CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE - A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. | 2010-08-05 |
| 20100193860 | SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION - In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions. | 2010-08-05 |
| 20100193861 | Three-Dimensional Memory Device - A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer. | 2010-08-05 |
| 20100193862 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing according to the present invention includes forming a trench to a semiconductor substrate, depositing an insulating film to the trench, etching the insulating film of a bottom part of the trench by plasma etching and thereby forming to an opening part of the trench, an inclined surface at an angle of inclination a to a principal surface of the semiconductor substrate, forming a gate insulating film from a top surface of the semiconductor substrate to the insulating film of the bottom part of the trench, and forming a gate electrode on the gate insulating film. | 2010-08-05 |
| 20100193863 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset. | 2010-08-05 |
| 20100193864 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first gate electrodes that are arranged above a semiconductor substrate in a first direction, and a plurality of second gate electrodes that are arranged above the semiconductor substrate in a second direction. The semiconductor device further includes a first gate lead-out electrode to which the first gate electrodes are connected, a second gate lead-out electrode to which the second gate electrodes are connected, and a third gate lead-out electrode to which the first gate lead-out electrode and the second gate lead-out electrode are connected. In the semiconductor device according to the present invention, a punched pattern is formed in the third gate lead-out electrode. | 2010-08-05 |
| 20100193865 | DMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer | 2010-08-05 |
| 20100193866 | GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES - In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration. | 2010-08-05 |
| 20100193867 | Silicided Semiconductor Structure and Method of Forming the Same - A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer. | 2010-08-05 |
| 20100193868 | HIGH-VOLTAGE VARIABLE BREAKDOWN VOLTAGE (BV) DIODE FOR ELECTROSTATIC DISCHARGE (ESD) APPLICATIONS - Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV | 2010-08-05 |
| 20100193869 | Semiconductor device having electro-static discharge protection element - A semiconductor device includes a semiconductor substrate of a first conductivity-type, a buried diffusion layer of a second conductivity-type formed in the semiconductor substrate, a first well of the second conductivity-type having a bottom portion in contact with a top portion of the buried diffusion layer, the first well having an annular shape in a planar view, and a second well of the first conductivity-type formed to be surrounded by the first well. The semiconductor device further includes a diffusion region formed between a first portion of the second well and a second portion of the second well, the diffusion region having an impurity concentration lower than that of the second well, so that a depletion layer formed in the diffusion region can be provided, a transistor formed on the second well to function as an ESD (electro-static discharge) protection element, and an external terminal connected to a drain of the transistor. | 2010-08-05 |
| 20100193870 | TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY - An integrated circuit ( | 2010-08-05 |
