31st week of 2022 patent applcation highlights part 64 |
Patent application number | Title | Published |
20220246739 | REPLACEMENT GATE CROSS-COUPLE FOR STATIC RANDOM-ACCESS MEMORY SCALING - A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact. | 2022-08-04 |
20220246740 | DUMBBELL SHAPED SELF-ALIGNED CAPPING LAYER OVER SOURCE/DRAIN CONTACTS AND METHOD THEREOF - A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact. | 2022-08-04 |
20220246741 | SEMICONDUCTOR WITH FASTER CONDUCTION FOR RAPID WRITING TO MEMORY - A semiconductor with 3D flash memory storing cells includes a stack structure in each storing cell, a blocking layer, at least one floating gate layer, a tunnel dielectric layer, and a channel layer. The stack structure includes at least one control gate layer, at least one dielectric layer, and at least one erasing layer. | 2022-08-04 |
20220246742 | GATE ALL AROUND DEVICE WITH FULLY-DEPLETED SILICON-ON-INSULATOR - Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiO | 2022-08-04 |
20220246743 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN ON INSULATOR SUBSTRATE - Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin. | 2022-08-04 |
20220246744 | TRANSISTOR DEVICE AND METHOD OF MANUFACTURING - A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon. | 2022-08-04 |
20220246745 | Silicon Carbide Devices, Semiconductor Devices and Methods for Forming Silicon Carbide Devices and Semiconductor Devices - A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell. | 2022-08-04 |
20220246746 | IMPLANT TO FORM VERTICAL FETS WITH SELF-ALIGNED DRAIN SPACER AND JUNCTION - Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars. | 2022-08-04 |
20220246747 | Contact Etch Stop Layer with Improved Etch Stop Capability - Improved process flows and methods are provided herein for fabricating a transistor on a substrate. In the disclosed process flows and methods, a contact etch stop layer (CESL) is conformally deposited directly onto a plurality of transistor structures, and a sacrificial layer is conformally deposited directly onto the CESL to protect the CESL from oxidation and thinning during subsequent processing step(s). The sacrificial layer improves the etch stop capability of the CESL during a subsequently performed oxide etch process. By providing a CESL with improved etch stop capability, the disclosed process flows and methods provide a controlled CESL etch process, which reduces or avoids damage to underlying transistor structures. | 2022-08-04 |
20220246748 | Cell Structure and Semiconductor Device Using Same - A cell structure and a semiconductor device using the same. The cell structure comprises a semiconductor substrate; a plurality of slot units are provided at the top end of the semiconductor substrate; a corresponding carrier barrier region is provided at the bottom of each slot unit; a conductive material is provided in each slot; source body regions are provided between the adjacent slot units; one or more source regions are closely attached on the surface of each source body region, and the source regions and the source body regions are in contact with a first metal layer at the top of the semiconductor substrate; a first semiconductor region and a second metal layer in contact with the first semiconductor region are provided at the bottom of the semiconductor substrate. | 2022-08-04 |
20220246749 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES AND METHODS FOR FABRICATING ELECTROSTATIC DISCHARGE PROTECTION DEVICES - An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type. | 2022-08-04 |
20220246750 | Semiconductor Device and Fabricating Method Thereof - The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode. | 2022-08-04 |
20220246751 | COMPOUND SEMICONDUCTOR DEVICE - Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate. | 2022-08-04 |
20220246752 | Semiconductor Structure And Manufacturing Method For The Same - The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure. | 2022-08-04 |
20220246753 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer. | 2022-08-04 |
20220246754 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device. The semiconductor device includes a drift region of a first conductivity type, a channel region of a second conductivity type on the drift region, a source region of the first conductivity type on the channel region, a trench, which forms an insulated gate and extends through the source region and the channel region so that its bottom is situated in the drift region, and at least one buried region of the second conductivity type, which extends within the drift region from an edge region of the drift region to the trench and is in direct contact with a first subarea of a surface of the trench, a second subarea of a surface of the trench being in direct contact with the drift region, and the buried region being connected to the source region in an electrically conducting manner. | 2022-08-04 |
20220246755 | METHOD OF MANUFACTURING MOSFET - A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region. | 2022-08-04 |
20220246756 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body. | 2022-08-04 |
20220246757 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion. | 2022-08-04 |
20220246758 | HIGH VOLTAGE SWITCH DEVICE - A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure. | 2022-08-04 |
20220246759 | ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES - Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance. | 2022-08-04 |
20220246760 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed. | 2022-08-04 |
20220246761 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure. | 2022-08-04 |
20220246762 | METAL GATE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a metal gate which is formed by replacing a polysilicon pseudo-gate. First a gate trench is created after the polysilicon pseudo-gate is removed. The gate trench is divided into atop trench and a bottom trench. A first sidewall of the polysilicon pseudo-gate is partially remove to the level of the top trench depth and it is then replaced with a second sidewall with a smaller width, such that the width of the top trench is expanded from the width of the first sidewall to the width of the second sidewall, so that the top trench is wider than the bottom trench. The metal gate is then disposed in the gate trench. A method for manufacturing the metal gate is also disclosed. The present application can improve the metal gate filling process window and eliminate the void left by the current metal gate filling process. | 2022-08-04 |
20220246763 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with less variations in transistor characteristics is provided. The semiconductor device includes: a first insulator; a first oxide over the first insulator; a first conductor and a second conductor over the first oxide; a first layer and a second layer which are in contact with a side surface of the first oxide; a second insulator over the first insulator, the first layer, the second layer, the first conductor, and the second conductor; a third insulator over the second insulator; a second oxide between the first conductor and the second conductor and over the first oxide; a fourth insulator over the second oxide; and a third conductor over the fourth insulator. Each of the first layer and the second layer includes a metal contained in the first conductor and the second conductor. The first insulator in a region in contact with the second insulator includes a region where a concentration of the metal is lower than that of the first layer or the second layer. | 2022-08-04 |
20220246764 | THIN FILM TRANSISTOR USING OXIDE SEMICONDUCTOR, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - The present invention addresses the problem of: realizing a TFT that uses an oxide semiconductor and that is capable of maintaining stable characteristics even in the case where the TFT is miniaturized; and realizing a display device that has high-definition pixels using such a TFT. To solve this problem, the present invention has the following configuration. A semiconductor device including an oxide semiconductor TFT formed using an oxide semiconductor film | 2022-08-04 |
20220246765 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator. | 2022-08-04 |
20220246766 | TWO-DIMENSIONAL (2D) MATERIAL FOR OXIDE SEMICONDUCTOR (OS) FERROELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICE - The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type. | 2022-08-04 |
20220246767 | THIN FILM TRANSISTOR INCLUDING A HYDROGEN-BLOCKING DIELECTRIC BARRIER AND METHODS FOR FORMING THE SAME - A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate. | 2022-08-04 |
20220246768 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. The bottom isolation layer has a seam therein, and the seam exposes a sidewall of the bottom spacer. | 2022-08-04 |
20220246769 | SEMICONDUCTOR CHIP - Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P | 2022-08-04 |
20220246770 | JBS DEVICE WITH IMPROVED ELECTRICAL PERFORMANCES, AND MANUFACTURING PROCESS OF THE JBS DEVICE - A Junction Barrier Schottky device includes a semiconductor body of SiC having a first conductivity. An implanted region having a second conductivity, extends into the semiconductor body from a top surface of the semiconductor body to form a junction barrier diode with the semiconductor body. An electrical terminal is in ohmic contact with the implanted region and in direct electrical contact with the top surface, laterally to the implanted region, to form a Schottky diode with the semiconductor body. The implanted region is formed by a first and a second portion electrically connected directly to each other and aligned along an alignment axis transverse to the top surface. Orthogonally to the alignment axis, the first portion has a first maximum width and the second portion has a second maximum width greater than the first maximum width. | 2022-08-04 |
20220246771 | VERTICAL CONDUCTION ELECTRONIC DEVICE COMPRISING A JBS DIODE AND MANUFACTURING PROCESS THEREOF - A vertical conduction electronic device is formed by a body of wide-bandgap semiconductor material having a first conductivity type and a surface, which defines a first direction and a second direction. The body has a drift region. The electronic device includes a plurality of superficial implanted regions having a second conductivity type, which extend in the drift region from the surface and delimit between them, in the drift region, at least one superficial portion facing the surface. At least one deep implanted region has the second conductivity type, and extends in the drift region, at a distance from the surface of the body. A metal region extends on the surface of the body, in Schottky contact with the superficial portion of the drift region. | 2022-08-04 |
20220246772 | OPTICALLY CLEAR THERMAL SPREADER FOR STATUS INDICATION WITHIN AN ELECTRONICS PACKAGE - A system is disclosed that includes an electronic package. The electronic package includes a package base couplable to a host substrate, and a package lid mechanically coupled to the package base that includes one or more transparent lid areas, configured to permit transmission of light. The electronic package further includes a thermal spreader bonded on a first side to a first side of the package lid. The thermal spreader includes one or more transparent spreader areas that are configured to allow transmission of light through the thermal spreader. The electronic package further includes one or more integrated circuits bonded to a second side of the thermal spreader that communicatively coupled to the host substrate. The electronic package further includes one or more optical paths that include at least one of the one or more transparent spreader areas configured adjacent to at least one of the transparent lid areas. | 2022-08-04 |
20220246773 | OPTICAL SOLAR ENHANCER - An optical solar enhancer comprises a panel that has a top surface and a bottom surface and an imaginary central plane that extends between the top surface and the bottom surface. The panel includes a plurality of generally parallel features configured to variably increase radiant energy entering the top surface at an acute angle relative to the central plane such that the effect is strongest at lower angles (early morning and late day sun) and weakest at higher angles (mid-day sun) and then redirect the increased radiant energy through the bottom surface. | 2022-08-04 |
20220246774 | METHOD FOR TREATING A STACK OBTAINED DURING THE MANUFACTURE OF A HETEROJUNCTION PHOTOVOLTAIC CELL - A method for treating a stack includes a substrate of n-doped crystalline silicon and a passivation layer of hydrogenated amorphous silicon disposed on a face of the substrate, the method including exposing the stack to electromagnetic radiation during a treatment period (t) less than or equal to 12 s, the electromagnetic radiation having an irradiance (E) greater than or equal to 200 kW/m | 2022-08-04 |
20220246775 | MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES - Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. | 2022-08-04 |
20220246776 | SOLAR CELL MODULE, PRODUCTION METHOD FOR SAME, AND BUILDING EXTERNAL WALL MATERIAL USING SAME - To provide a solar cell module excellent in processability at the time of production, a method for producing it, and a building exterior wall material using it. | 2022-08-04 |
20220246777 | METHOD FOR MANUFACTURING GRAPHIC COVER SUBSTRATE FOR SOLAR PANEL, SOLAR PANEL AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a graphic cover substrate for a solar cell panel according to an embodiment of the present disclosure includes applying a cover layer, which is forming the cover layer composed of a ceramic material layer on a transfer member; transferring, which is transferring the cover layer to a base member; and reinforcing, which is forming a cover portion by reinforcing or semi-reinforcing the base member on which the cover layer is formed. | 2022-08-04 |
20220246778 | SOLAR MODULE WITH METAL FOIL INTERCONNECTION OF BACK-CONTACTED PHOTOVOLTAIC CELLS - A photovoltaic module includes a metal foil defining a multiplicity of electrical contacts, each electrical contact electrically isolated from the other electrical contacts, and a plurality of back-contact photovoltaic cells superimposed over the metal foil and electrically connected via the multiplicity of electrical contacts. Each photovoltaic cell includes a first side configured to absorb light and a second side including a first electrically conductive protrusion and a second electrically conductive protrusion. The first electrically conductive protrusion of a first one of the photovoltaic cells is in direct electrical communication with a first one of the multiplicity of electrical contacts, and the second electrically conductive protrusion of the first one of the photovoltaic cells is in direct electrical communication with a second one of the electrical contacts. | 2022-08-04 |
20220246779 | MULTIJUNCTION SOLAR CELLS - A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of the active layer. | 2022-08-04 |
20220246780 | PHOTOVOLTAIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an interdigitated back contact photovoltaic device that includes a first patterned silicon layer situated on an intrinsic layer, and having the same type of doping as the one of the substrate. First charge collection portions are deposited on predetermined areas of the intrinsic layer, and include each an amorphous layer portion situated between the predetermined areas and the at least partially nano-crystalline layer portions. The amorphous layer portions have a larger width than the width of the nano-crystalline layer portions. On top if the first patterned silicon layer, a second nano-crystalline silicon layer is deposited that has a doping of a second type being the other of the p-type doping or the n-type doping with respect to the doping-type of the first patterned silicon layer. | 2022-08-04 |
20220246781 | HIGH MODULATION SPEED PIN-TYPE PHOTODIODE - Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact. | 2022-08-04 |
20220246782 | PHOTO SENSOR AND DISTANCE MEASURING SYSTEM USING SAID PHOTO SENSOR - A photosensor includes a plurality of avalanche photodiodes (APD) provided on a first main surface, a first isolation region that is provided on the first main surface and electrically separates the plurality of APDs from one another in a first direction, and a second isolation region that is provided on the first main surface and electrically separates the plurality of APDs from one another in a second direction different from a direction of the first isolation region. The first isolation region and the second isolation region are depleted. At least one of the first isolation region or the second isolation region is terminated at a first connection portion at which the first isolation region and the second isolation region are connected. | 2022-08-04 |
20220246783 | Photodetector Systems with Low-Power Time-to-Digital Converter Architectures to Determine an Arrival Time of Photon at a Photodetector Based on Event Detection Time Window - An illustrative system may include a component configured to be worn on a body of a user, the component comprising a time-to-digital converter (TDC) configured to: receive, during a predetermined event detection time window that commences in response to an application of a light pulse to a target within the body, a signal triggered by an event in which a photodetector detects a photon of the light pulse after the light pulse reflects from the target; and measure, based on the receiving the signal, a time interval between when the event occurred and an end of the predetermined event detection time window. The system may further include a processor configured to determine, based on the time interval and the predetermined event detection time window, an arrival time of the photon at the photodetector. | 2022-08-04 |
20220246784 | PHOTODETECTION DEVICE AND MANUFACTURING METHOD THEREOF - A photodetection device and a manufacturing method are provided. The photodetection device includes an absorption structure, a cathode, a charge multiplication region and an anode. The absorption structure is formed in a recess at a surface region of a semiconductor substrate, and configured to receive an incident light. The cathode is formed on a top surface of the absorption structure, and has a first conductive type. The charge multiplication layer is in lateral contact with the absorption structure, and is an intrinsic portion of the semiconductor substrate extending into the semiconductor substrate from a topmost surface of the semiconductor substrate. The anode is in lateral contact with the charge multiplication layer from a side of the charge multiplication region away from the absorption structure, and is a doped region in the semiconductor substrate having a second conductive type complementary to the first conductive type. | 2022-08-04 |
20220246786 | METHOD FOR PRODUCING A DOUBLE GRADED CDSETE THIN FILM STRUCTURE - The present invention proposes a method to form a double-graded CdSeTe thin film. The method comprises providing a base substrate, forming a first CdSe | 2022-08-04 |
20220246787 | TUNING OF EMISSION PROPERTIES OF QUANTUM EMISSION DEVICES USING STRAIN-TUNED PIEZOELECTRIC TEMPLATE LAYERS - A quantum device includes a substrate including a first material and including an upper surface thereof, a first layer comprising a compound of the first material disposed on the upper surface of the substrate, a second layer, comprising a metal oxide, disposed on the first layer, a third layer, comprising a noble metal, disposed on the second layer, a fourth layer, comprising a metal oxide, disposed on the third layer, a fifth layer, comprising a piezoelectric material, disposed on the fourth layer, a sixth layer, comprising a noble metal, disposed on the fifth layer, a seventh layer, comprising a material capable of quantum emission, disposed on the sixth layer, and an eighth layer, comprising a noble metal, disposed on the seventh layer, and at least one of the eighth layer and the seventh layer are sized to enable quantum emission from the seventh layer. | 2022-08-04 |
20220246788 | FILM COATING METHOD AND LIGHT-EMITTING DEVICE - A film coating method includes the following steps of: providing an object to be coated; providing a mask; disposing the mask above the object; disposing a coating material film above the object and the mask; and making the coating material film and the object approach each other so as to make the coating material film form a coating layer on a surface area to be coated of the object through a pattern of the mask. A light-emitting device includes a substrate and a plurality of light-emitting parts separately arranged on an upper surface of the substrate. An optical wavelength conversion layer covers a light-emitting surface of the light-emitting part. The optical wavelength conversion layer is a compact powder layer and touches the upper surface. The upper surface has a clearance area without the compact powder layers thereon between adjacent two of the light-emitting parts. | 2022-08-04 |
20220246789 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A buried layer forming step includes three steps of a facet structure forming step, a c-plane forming step, and a flattening step. In the facet structure forming step, a buried layer grows to form a periodic facet structure that matches an arrangement pattern of columnar semiconductors. In the c-plane forming step, the buried layer grows such that a {0001} plane (upper surface) is formed in a region of the buried layer corresponding to an upper portion of the columnar semiconductor. In the flattening step, lateral growth of the buried layer is promoted and the c-plane formed in the c-plane forming step is widened to flatten a surface of the buried layer. | 2022-08-04 |
20220246790 | METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array. | 2022-08-04 |
20220246791 | METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array. | 2022-08-04 |
20220246792 | SELECTABLE-REPAIRING MICRO LIGHT EMITTING DIODE DISPLAY AND REPAIRING METHOD THEREOF - A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively. | 2022-08-04 |
20220246793 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - To suppress current leakage between the semiconductor layer below the mask and the buried layer above the mask. To reduce the drive voltage and improve the emission efficiency by improving the efficiency of carrier injection into the active layer. The semiconductor light-emitting device includes a substrate, a mask, a columnar semiconductor, a buried layer, a cathode electrode, and an anode electrode. The substrate has a conductive substrate, an n-type semiconductor layer disposed on the conductive substrate, and a p-type semiconductor layer disposed on the n-type semiconductor layer. The p-type semiconductor layer has a high resistance, thereby enhancing insulation between the n-type semiconductor layer and the buried layer. | 2022-08-04 |
20220246794 | MICRO LIGHT-EMITTING DIODE DISPLAY PANEL - A micro light-emitting diode (LED) display panel including a substrate, a first micro LED, a first light-shielding wall, a second micro LED, and a second light-shielding wall is provided. The substrate includes a plurality of pixel regions arranged in an array. The first micro LED is disposed on one of the pixel regions of the substrate. The first light-shielding wall is disposed on the substrate and located beside the first micro LED. The second micro LED is disposed on the one of the pixel regions of the substrate and located beside the first micro LED. The second light-shielding wall is disposed on the substrate and located beside the second micro LED. A light wavelength of the first micro LED is different from a light wavelength of the second micro LED. A height of the first light-shielding wall is smaller than a height of the second light-shielding wall. | 2022-08-04 |
20220246795 | LIGHT-EMITTING DEVICE - A light-emitting device is provided. The light-emitting device includes a light-emitting diode, a reflective structure, and a package structure. The reflective structure includes a bottom surface and a lateral part. The light-emitting diode is disposed on the bottom surface. The lateral part is disposed surrounding the bottom surface and disposed on the bottom surface. The package structure is configured to package the light-emitting diode and the reflective structure. The package structure includes a first package part and a second package part. The first package part has a phosphorescent powder. An interface is between the first package part and the second package part. The interface is disposed below a top surface of the lateral part. | 2022-08-04 |
20220246796 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a light emitting device including a buffer layer, a body provided on the buffer layer, the body including a first semiconductor layer, an active layer, and a second semiconductor layer, a reflective layer configured to reflect light incident from the active layer, and a scattering pattern provided between the first semiconductor layer and the buffer layer, the scattering pattern being configured to scatter the light incident from the active layer and light incident from the reflective layer. | 2022-08-04 |
20220246797 | SEMICONDUCTOR TEMPLATE AND FABRICATION METHOD - A method for fabrication of an InGaN semiconductor template, comprising growing an InGaN pyramid having inclined facets on a semiconductor substrate; processing the pyramid by removing semiconductor material to form a truncated pyramid having a first upper surface; growing InGaN, over the first upper surface, to form an InGaN template layer having a c-plane crystal facet forming a top surface. The InGaN semiconductor template is suitable for further fabrication of semiconductor devices, such as microLEDs configured to emit red, green or blue light. | 2022-08-04 |
20220246798 | MICRO LIGHT EMITTING DIODE AND DISPLAY PANEL - A micro light emitting diode including an epitaxy layer, a first pad, a second pad, a first ohmic contact metal, a second ohmic contact metal and at least one etch protection conductive layer is provided. The first pad and the second pad are electrically connected to a first type semiconductor layer and a second type semiconductor layer of the epitaxy layer, respectively. The first ohmic contact metal is disposed between the first type semiconductor layer and the first pad. The second ohmic contact metal is disposed between the second type semiconductor layer and the second pad. The at least one etch protection conductive layer is disposed between the first ohmic contact metal and the first pad and/or between the second ohmic contact metal and the second pad. A display panel is also provided. | 2022-08-04 |
20220246799 | MICRO LIGHT-EMITTING DIODE AND DISPLAY PANEL - A micro light-emitting diode including an epitaxy structure, a first pad, a first ohmic contact layer and a current conducting layer is provided. The epitaxy structure includes a first type semiconductor layer, a second type semiconductor layer and an active layer. The first pad is electrically connected to the first type semiconductor layer. The first ohmic contact layer is electrically connected between the first type semiconductor layer and the first pad. The current conducting layer is electrically connected between the first ohmic contact layer and the first pad. At least a portion of the orthogonal projection of the first ohmic contact layer on the plane upon which the first type semiconductor layer is located is away from the orthogonal projection of the first pad on the plane. A display panel is also provided. | 2022-08-04 |
20220246800 | MICRO-LIGHT-EMITTING DIODE CHIP AND MICRO-LIGHT-EMITTING DIODE DISPLAY - A micro-light-emitting diode chip includes an epitaxial structure, an electrode, a transparent structure, and a reflection layer. The epitaxial structure has a light exit surface, a back surface opposite to the light exit surface, and a sidewall surface. The sidewall surface is connected to the light exit surface and the back surface. The electrode is electrically coupled to the epitaxial structure. The transparent structure has an inner surface and an outer surface opposite to the inner surface. The inner surface is connected to the sidewall surface. A distance between the outer surface and the inner surface on a plane where the back surface is located is less than a distance between the outer surface and the inner surface on a plane where the light exit surface is located. The reflection layer is in direct contact with the outer surface. A micro-light-emitting diode display is also provided. | 2022-08-04 |
20220246801 | LIGHT-EMITTING DEVICE AND DISPLAY APPARATUS INCLUDING THE SAME - Provided is a light-emitting device including a body including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode and a second electrode provided on a first surface of the body, the first electrode and the second electrode being in contact with the first semiconductor layer and the second semiconductor layer, respectively, and a third electrode and a fourth electrode provided on a second surface of the body, the third electrode and the fourth electrode being in contact with the first semiconductor layer and the second semiconductor layer, respectively. | 2022-08-04 |
20220246802 | DISPLAY DEVICE - A display device includes a first electrode and a second electrode spaced apart from each other; first light emitting elements disposed between the first electrode and the second electrode and emitting first light; second light emitting elements disposed between the first electrode and the second electrode and emitting second light; and a wavelength conversion pattern disposed on the first light emitting elements and the second light emitting elements, wherein a peak wavelength of the first light is different from a peak wavelength of the second light, and the first light emitting elements and the second light emitting elements are disposed on a same layer. | 2022-08-04 |
20220246803 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of manufacturing a semiconductor light emitting device, the method including forming a first conductivity-type semiconductor layer on a substrate; forming an active layer on the first conductivity-type semiconductor layer; forming a mask layer having an opening on the active layer; growing a second conductivity-type semiconductor layer through the opening; removing the mask layer; removing a portion of the active layer and a portion of the first conductivity-type semiconductor layer that do not overlap the second conductivity-type semiconductor layer; and removing a portion of the first conductivity-type semiconductor layer to expose the substrate. | 2022-08-04 |
20220246804 | QUANTUM DOT, AND A COMPOSITE AND AN ELECTRONIC DEVICE INCLUDING THE SAME - A quantum dot composite includes a matrix and a plurality of quantum dots dispersed in the matrix, and a color conversion panel and a display panel including the same. The plurality of quantum dots include a metal including indium (In) and zinc and a non-metal including phosphorous (P), selenium, and sulfur, wherein the plurality of quantum dots includes a mole ratio of sulfur to indium of greater than or equal to about 3:1 and less than or equal to about 6:1, and a mole ratio of sulfur to selenium of greater than or equal about 0.69:1 and less than or equal to about 0.89, and a mole ratio of zinc to indium of greater than or equal to about 10:1 and less than or equal to about 12.4:1, and wherein the plurality of the quantum dots are configured to emit red light. | 2022-08-04 |
20220246805 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device is provided. The device includes: an LED chip having a lower surface, an upper surface, and a side surface between the upper surface and the lower surface; first and second conductive bumps disposed on first and second conductive bumps provided on the lower surface; a first wavelength conversion layer having a first region provided on the upper surface of the LED chip and a second region which extends past the side surface of the LED chip; a second wavelength conversion layer having a first surface contacting the side surface of the LED chip, a second surface, a third surface connecting the first surface and the second surface, and contacting the second region, and a fourth surface located opposite to the third surface and inclined; and a reflective resin portion provided on the lower surface of the LED chip and the fourth surface. | 2022-08-04 |
20220246806 | DETECTING DEVICE AND MEASURING DEVICE - A detecting device includes: a first light-emitting section configured to emit first light having a green wavelength band; a second light-emitting section configured to emit second light having a wavelength band longer than the green wavelength band; a first light-receiving section configured to receive the first light emitted from the first light-emitting section and passed through a living body; and a second light-receiving section configured to receive the second light emitted from the second light-emitting section and passed through the living body. In the direction intersecting the direction in which the first light-emitting section and the second light-emitting section are aligned, in the second direction, at least a portion of the first light-receiving section is disposed closer to the first light-emitting section than the second light-receiving section. An area of the first light-receiving section is smaller than an area of the second light-receiving section. | 2022-08-04 |
20220246807 | LIGHTING DEVICE - An embodiment may include a lighting device comprising: a substrate; a light emitting device disposed on the substrate; a resin layer disposed on the light emitting device and covering the light emitting device; a diffusion layer disposed on the resin layer; an optical pattern disposed between the lower surface of the diffusion layer and the resin layer; and a cover layer surrounding the optical pattern, wherein the cover layer comprises a release agent. | 2022-08-04 |
20220246808 | LIGHT EMITTING DIODE PACKAGE - A light emitting module unit includes a circuit board and a light emitting device. The light emitting device includes a plurality of light emitting elements electrically coupled through the circuit board, one or more electrodes arranged on a first surface of the plurality of light emitting elements, a surface barrier formed on a second surface of one or more of the plurality of light emitting elements, and an encapsulation portion disposed above a third surface of the plurality of light emitting elements. The surface barrier is disposed between the encapsulation portion and the second surface of one or more of the plurality of light emitting elements. | 2022-08-04 |
20220246809 | METHOD OF INTEGRATING FUNCTIONAL TUNING MATERIALS WITH MICRO DEVICES AND STRUCTURES THEREOF - The disclosure is related to creating different functional micro devices by integrating functional tuning materials and creating an encapsulation capsule to protect these materials. Various embodiments of the present disclosure also related to improve light extraction efficiencies of micro devices by mounting micro devices at a proximity of a corner of a pixel active area and arranging QD films with optical layers in a micro device structure. | 2022-08-04 |
20220246810 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer. | 2022-08-04 |
20220246811 | DISPLAY MODULE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display module, a manufacturing method thereof, and a display device. The display module includes: a display panel including a substrate; a chip on film connected to the display panel; a circuit board connected to the chip on film; and a first film layer attached to surfaces of the display panel and the circuit board facing away from the substrate and covering at least the chip on film and the circuit board. | 2022-08-04 |
20220246812 | LIGHT-EMITTING SUBSTRATE, METHOD FOR FORMING THE LIGHT-EMITTING SUBSTRATE AND DISPLAY DEVICE - The present disclosure discloses a light-emitting substrate, a method for forming the light-emitting substrate and a display device. The light-emitting substrate includes: a base substrate; a first signal line located at one side of the base substrate; an insulation layer located at one side of the first signal line away from the base substrate; an electrode layer located at one side of the insulation layer away from the base substrate and including a first electrode terminal, a second electrode terminal and a second signal line, where the first electrode terminal is electrically connected to the first signal line via a first through hole penetrating the insulation layer; and at least one light-emitting element bound and connected to the first electrode terminal and the second electrode terminal. | 2022-08-04 |
20220246813 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device includes a substrate, a circuit layer, a plurality of conductive connection portions, and a plurality of semiconductor light-emitting sources. The circuit layer on the substrate having a plurality of conductive structures, in which each conductive structure includes at least one bonding pad. An interval is between two adjacent ones of the conductive structures. Each conductive connection portion is correspondingly located on each bonding pad. Each semiconductor light-emitting source crosses each interval and contacts two adjacent ones of the conductive connection portions, such that the semiconductor light-emitting sources are respectively electrically connected to two adjacent ones of the conductive structures. | 2022-08-04 |
20220246814 | MICRO LIGHT-EMITTING DEVICE, METHOD FOR MAKING THE SAME AND DISPLAY SCREEN - A micro light-emitting device includes an epitaxial unit and a current-spreading layer. The epitaxial unit has a top portion that includes an ohmic contact region and a non-ohmic contact region. The top portion has a periphery area which forms at least a part of the non-ohmic contact region. The periphery area has a reduced conductivity compared with the remainder of the top portion. The current-spreading layer is disposed on the ohmic contact region. A method for making the micro light-emitting device, and a display screen including the same are also disclosed. | 2022-08-04 |
20220246815 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A light emitting element includes a semiconductor layered body, an insulating film, first and second electrodes, and first and second external connection portions. The semiconductor layered body defines exposed portions in which the first semiconductor layer is exposed from the second semiconductor layer and the light emitting layer. In the plan view, the first external connection portion includes a plurality of first portions located between the exposed portions in a first direction, and arrayed in the first direction, with a number of the first portions disposed between adjacent ones of the exposed portions being two or more, and a plurality of second portions not located between the exposed portions in the first direction, and arrayed in the first direction. Each of the second portions is different in shape or size from each of the first portions. | 2022-08-04 |
20220246816 | INTERCONNECTS FOR LIGHT EMITTING DIODE CHIPS - Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies. | 2022-08-04 |
20220246817 | EMITTER AND METHOD FOR EMITTING LIGHT - An emitter and a method for emitting light are described. The emitter has a substrate with a substrate surface and at least one LED element arranged on the substrate surface for generating the light to be emitted. An active cooling unit for cooling the at least one LED element has at least one cooling channel. The at least one cooling channel is arranged on the substrate surface in a beam path of at least one portion of the light to be emitted, which can be generated by means of the at least one LED element, for redirecting the light to be emitted. | 2022-08-04 |
20220246818 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - A semiconductor structure includes an optical component and a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component. The thermal control mechanism includes a conductive structure, a first thermoelectric member and a second thermoelectric member opposite to the first thermoelectric member. The first thermoelectric member and the second thermoelectric member are electrically connected to the conductive structure. The first thermoelectric member and the second thermoelectric member have opposite conductive types. The semiconductor structure further includes a first dielectric layer surrounding the optical component and a portion of the thermal control mechanism, wherein the conductive structure is over the first dielectric layer, and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer. The semiconductor structure further includes a first via extending through the first dielectric layer and electrically connected to the conductive structure. | 2022-08-04 |
20220246819 | Woven Thermoelectric Ribbon - A woven structure includes thermoelectric ribbons interwoven with thread. Each thermoelectric ribbon includes a folded matrix of thermoelectric elements, the matrix having an insulating substrate that supports plural rows of thermoelectric elements, a plurality of conductive elements, and two terminals. The conductive elements form a series connection of the thermoelectric elements between the two terminals. A set of first conductive elements have a first temperature and a set of second conductive contacts have a second temperature lower than the first temperature when a first current flows in a first direction between the first matrix terminal and the second matrix terminal. The folded matrix is configured to form spaced-apart alternating stacks of the first conductive contacts and second conductive contacts. Each length of the yard or thread is interwoven such that it passes alternately under stacks of first conductive contacts and over stacks of second conductive contacts. | 2022-08-04 |
20220246820 | THERMOELECTRIC CONVERSION ELEMENT AND THERMOELECTRIC CONVERSION DEVICE - A thermoelectric conversion element is made of: a first material with a stoichiometric composition of Fe | 2022-08-04 |
20220246821 | ULTRA-THIN FILM SUPERCONDUCTING TAPES - An ultra-thin film superconducting tape and method for fabricating same is disclosed. Embodiments are directed to a superconducting tape being fabricated by processes which include removing a portion of the superconducting tape's substrate subsequent the substrate's initial formation, whereby a thickness of the superconducting tape is reduced to 15-80 μm. | 2022-08-04 |
20220246822 | Josephson Junction using Molecular Beam Epitaxy - According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers. | 2022-08-04 |
20220246823 | PHOTO-INDUCED TUNABLE METAMATERIAL - A tunable metamaterial structure can have a flexible substrate that is elastically deformable. The tunable metamaterial structure can have a photo-responsive stiffness-modulating patch. The photo-responsive stiffness-modulating patch can be fixed to a surface of the flexible substrate. The photo-responsive stiffness-modulating patch can include a piezoelectric element and a photo-responsive element. The piezoelectric element and the photo-responsive element are electrically connected to one another. | 2022-08-04 |
20220246824 | PISTON MODE GENERATION IN THIN PLATE LAMB WAVE DEVICE - An acoustic wave resonator comprises a plurality of interdigital transducer (IDT) electrodes disposed on upper and lower sides of a piezoelectric film, the IDT electrodes on the upper side of the piezoelectric film being offset from the IDT electrodes on the lower side of the piezoelectric film by λ/4, λ being a wavelength of a main acoustic wave generated by the acoustic wave resonator to enable the acoustic wave resonator to generate piston mode acoustic waves responsive to electrical excitation of the plurality of IDT electrodes with an alternating current. | 2022-08-04 |
20220246825 | VIBRATION DEVICE - A vibration device that includes: a vibration part having a flat plate shape and connected to an operation target on which a user performs a pushing operation; a fixing member; a support part connecting the vibration part and the fixing member; and a vibration film connected to the vibration part and the fixing member, extending across the vibration part and the fixing member in a tensioned state, and constructed to vibrate in a planar direction. | 2022-08-04 |
20220246826 | Piezoelectric Element - A piezoelectric element includes a piezoelectric layer containing a helical chiral polymer exhibiting piezoelectric properties, a first electrode layer, a second electrode layer, a first coupling portion provided on the first electrode layer, and a second coupling portion provided on the second electrode layer, in which an overlapped portion where the piezoelectric layer, the first electrode layer, and the second electrode layer overlap is circular shaped when viewed along a thickness direction of the piezoelectric layer, and the first coupling portion and the second coupling portion overlap with a center of the overlapped portion when viewed along the thickness direction of the piezoelectric layer. | 2022-08-04 |
20220246827 | Injection-Molded Article Of Polymer Piezoelectric Material, Piezoelectric Element, Apparatus For Manufacturing Injection-Molded Article Of Polymer Piezoelectric Material, And Method For Manufacturing Injection-Molded Article Of Polymer Piezoelectric Material - An injection-molded article of polymer piezoelectric material includes: a helical chiral polymer constituted by a polymer chain and having a unit cell with an a-axis, a b-axis, and a c-axis as crystal axes, wherein b-axis2022-08-04 | |
20220246828 | SENSOR DEVICE - A sensor device includes a substrate; a piezoelectric film on the substrate; a lower electrode and an upper electrode that face each other with at least part of the piezoelectric film sandwiched therebetween; and a sensitive film in a region on the upper electrode that approximately corresponds to a resonance region, the resonance region being defined as a region in a plan view in which the lower electrode and the upper electrode face each other with the piezoelectric film sandwiched therebetween and in which a resonance in a thickness longitudinal vibration mode occurs, the sensitive film being absent in regions on the upper electrode and on the lower electrode that are outside of the resonance region in the plan view. | 2022-08-04 |
20220246829 | COMPOSITIONS FOR ACTIVE COMPRESSION DEVICES AND RELATED METHODS - Some embodiments relate to compositions for active compression devices and related methods. In some embodiments, a composition for an active compression device comprises an electro-active polymer film. In some embodiments, the electro-active polymer film comprises at least one polymer and at least one additive. | 2022-08-04 |
20220246830 | PIEZOELECTRIC DEVICE - In a piezoelectric device, a cantilever portion includes a fixed edge portion and a free edge portion. A plate-shaped portion includes a facing edge portion, a support edge portion, a first lateral support edge portion, and a second lateral support edge portion. The facing edge portion faces the free edge portion. The support edge portion is on an opposite side from the facing edge portion in an extension direction of the cantilever portion. The plate-shaped portion is connected to an inner surface at at least a portion of the support edge portion, at least a portion of the first lateral support edge portion, and at least a portion of the second lateral support edge portion. | 2022-08-04 |
20220246831 | PIEZOELECTRIC DEVICE - A piezoelectric device includes a beam portion with a fixed end portion and a free end portion opposite to the fixed end portion. The beam portion extends from the fixed end portion towards the free end portion. The beam portion includes a multilayer body including a piezoelectric layer and first and second electrode layers. A base is connected with the fixed end portion of the beam portion. As viewed from a layering direction of the multilayer body, the base surrounds the beam portion at an interval from the beam portion except for the fixed end portion. As viewed from the layering direction, an average of a dimension of a width of the beam portion in an orthogonal or substantially orthogonal direction to an extension direction of the beam portion is greater than a maximal dimension of a length thereof in the extension direction. | 2022-08-04 |
20220246832 | MEMS PIEZOELECTRIC DEVICE AND CORRESPONDING MANUFACTURING PROCESS - A MEMS piezoelectric device includes a monolithic semiconductor body having first and second main surfaces extending parallel to a horizontal plane formed by first and second horizontal axes. A housing cavity is arranged within the monolithic semiconductor body. A membrane is suspended above the housing cavity at the first main surface. A piezoelectric material layer is arranged above a first surface of the membrane with a proof mass coupled to a second surface, opposite to the first surface, along the vertical axis. An electrode arrangement is provided in contact with the piezoelectric material layer. The proof mass causes deformation of the piezoelectric material layer in response to environmental mechanical vibrations. The proof mass is coupled to the membrane by a connection element arranged, in a central position, between the membrane and the proof mass in the direction of the vertical axis. | 2022-08-04 |
20220246833 | PIEZOELECTRIC FILM LAYERED STRUCTURE AND METHOD FOR PRODUCING THEREOF - A piezoelectric film layered structure includes a base, and a ScAlN film formed on the base. The ScAlN film has an unpaired electron density within a range between 1.7×10 | 2022-08-04 |
20220246834 | METHOD OF MANUFACTURING A CURVED CERAMIC STRUCTURE - A method of manufacturing a ceramic structure, a method of manufacturing a ceramic structure with multiple layers of ceramic material, and a method of manufacturing a piezoelectric ceramic structure. The method of manufacturing a ceramic structure includes the steps of: placing a sheet of ceramic material on a supporting platform, wherein the supporting platform is arranged to elevate the sheet of ceramic material from a base of the supporting platform by supporting only a first portion of the sheet of ceramic material; sintering the sheet of ceramic material; and during the step of sintering of the sheet of ceramic material, facilitating forming a curvature on the sheet of ceramic material at a second portion of the sheet of ceramic material which is not supported by the supporting platform. | 2022-08-04 |
20220246835 | Method For Manufacturing Vibration Element - A method for manufacturing a vibration element that includes a base portion, a first vibration arm and a second vibration arm that extend from the base portion along a first direction and are arranged along a second direction intersecting the first direction, and bottomed grooves on both main surfaces of the first vibration arm and both main surfaces of the second vibration arm includes: a preparing step of preparing a crystal substrate; a protective film forming step of forming a protective film on the crystal substrate except for groove regions that are regions in which the grooves are formed; and a dry etching step of dry etching the crystal substrate through the protective film to form the grooves. The grooves provided in at least one of the first vibration arm and the second vibration arm include a first groove and a second groove arranged along the second direction. | 2022-08-04 |
20220246836 | COMPOSITE RECORDING STRUCTURE FOR AN IMPROVED WRITE PROFERMANCE - A composite recording structure comprising a first magnetic free layer comprising an amorphous magnetic material sub-layer, a Boron-absorbing material sub-layer atop the amorphous magnetic material sub-layer and a Co/Ni superlattice sub-layer atop the Boron-absorbing material sub-layer; one or many repeats of a substructure including a nonmagnetic spacing layer and a Co/Ni superlattice free layer, atop the first magnetic free layer, wherein said first magnetic free layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, said each Co/Ni superlattice free layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface. | 2022-08-04 |
20220246837 | NONVOLATILE MEMORY DEVICES HAVING MAGNETIC TUNNEL JUNCTION MEMORY CELLS THEREIN - A magnetic memory device includes a substrate having a first mold insulating film on a first region thereof, and a first structure on the substrate. The first structure includes a lower electrode, a magnetic tunnel junction (MTJ) structure on the lower electrode, and an upper electrode on the MTJ structure. A capping film is provided, which extends on the first mold insulating film and sidewalls of the first structure. A first etching stop layer is provided on the first structure and the capping film. A second mold insulating film is provided, which at least partially fills a space between the capping film and the first etching stop layer. A first metal structure is provided, which extends through a portion of the first etching stop layer and a portion of the second mold insulating film, and is electrically coupled to the MTJ structure. | 2022-08-04 |
20220246838 | MEMORY DEVICE - The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element. | 2022-08-04 |
20220246839 | MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME - An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces. | 2022-08-04 |