31st week of 2022 patent applcation highlights part 62 |
Patent application number | Title | Published |
20220246539 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a substrate; a semiconductor chip provided on the substrate; a resin covering the semiconductor chip; and a metal film provided on the resin. The metal film includes a first metal layer provided on the resin, a second metal layer provided on the first metal layer, and a third metal layer provided on the second metal layer. The first metal layer and the second metal layer contain a same material, and a particle diameter of the second metal layer is smaller than a particle diameter of the first metal layer. | 2022-08-04 |
20220246540 | PACKAGING STRUCTURE AND FORMATION METHOD THEREOF - Packaging structure and formation method are provided. The packaging structure includes a pre-encapsulation panel, which includes an encapsulation layer containing a plurality of semiconductor chips. Each semiconductor chip includes a functional surface and a non-functional surface opposite to the functional surface. A plurality of pads are formed on the functional surface, and the encapsulation layer exposes the plurality of pads. The packaging structure also includes a first shielding layer and a second shielding layer disposed between a semiconductor chip and the encapsulation layer. The first shielding layer covers the non-functional surface and a sidewall surface of the semiconductor chip. The second shielding layer is disposed between the first shielding layer and the encapsulation layer and fully covers a surface of the first shielding layer. Further, the packaging structure includes an external contact structure disposed on a back side of the pre-encapsulation panel and connected to a pad. | 2022-08-04 |
20220246541 | EMI Shielding for Flip Chip Package with Exposed Die Backside - A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die. | 2022-08-04 |
20220246542 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one example, an electronic device structure includes a substrate having a conductive structure adjacent to a surface. The conductive structure can include a plurality of conductive traces. First and second electronic devices are disposed adjacent to the top surface. The first electronic device is interposed between a first conductive trace and a second conductive trace, and the second electronic device is interposed between the second conductive trace and a third conductive trace. A continuous wire structure including a first bond structure is connected to the first conductive trace, a second bond structure is connected to the second conductive trace, a third bond structure is connected to the third conductive trace, a first wire portion is interconnected between the first bond structure and the second bond structure and disposed to overlie the first electronic device, and a second wire portion is interconnected between the second bond structure and the third bond structure and disposed to overlie the second electronic device. Other examples and related methods are also disclosed herein. | 2022-08-04 |
20220246543 | COMPOSITE STRUCTURE FOR IMAGE PLANE NORMALIZATION OF A MICROELECTRONIC HYBRID DEVICE - A composite structure includes a first surface and a second surface sandwiched together with a field array of individual and discrete pillars extending therebetween. The plurality of discrete pillars each have a tailored coefficient of thermal expansion and are designed to expand and contract over varying temperatures. The discrete pillars are specifically arranged within the composite structure to compensate for the shrinkage and expansion of different components of a microelectronic hybrid device, to reduce thermal expansion induced deformations imparted on facets of the microelectronic hybrid device under varying temperatures. | 2022-08-04 |
20220246544 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF - Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure. | 2022-08-04 |
20220246545 | SEMICONDUCTOR PACKAGE SUBSTRATE WITH A SMOOTH GROOVE ABOUT A PERIMETER OF A SEMICONDUCTOR DIE - A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad. | 2022-08-04 |
20220246546 | ELECTRIC COMPONENT WITH PAD FOR A BUMP AND MANUFACTURING METHOD THEREOF - A bump pad enclosure providing an improved reliability of a bump connection is provided. The bump pad enclosure comprises an electrode pad, a UBM and a first shield. The first shield covers at least a first perimeter area of the electrode pad. The first shield is provided and configured to shield the first perimeter area from a detrimental influence of the environment. | 2022-08-04 |
20220246547 | ELECTRONIC DEVICE INCLUDING ONE OR MORE MONOLAYER AMORPHOUS FILMS AND METHOD OF FORMING THE SAME - Various embodiments relate to an electronic device including a substrate comprising a semiconductor or polymeric inhibit and a barrier comprising one or more monolayer amorphous films over the substrate, wherein the barrier is configured to or reduce permeation of moisture or gas from environment to the substrate. Various embodiments relate to an electronic device comprising a first device structure including an electrically conductive material, a second device structure including a further electrically conductive material or a semiconductor material, and a barrier including one or more monolayer amorphous films between the first device structure and the second device structure, wherein the barrier is configured to inhibit or reduce interdiffusion between the first device structure and the second device structure. In specific embodiments, the electronic device is an organic light emitting diode (OLED) or a thin film transistor (TFT), and the monolayer amorphous films are monolayer amorphous carbon (MAC) films. | 2022-08-04 |
20220246548 | Integrated Circuit Layout, Integrated Circuit, and Method for Fabricating the Same - An integrated circuit layout is provided. The integrated circuit layout includes: a first active region having a first plurality of field effect transistors (FETs); and an interconnect contacting sources and drains of the first plurality of FETs in the first active region through a first set of contact structures. At least one of the first set of contact structures is electrically non-conductive. | 2022-08-04 |
20220246549 | DEVICE CRACK-STOP STRUCTURE TO PREVENT DAMAGE DUE TO DICING CRACK - Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device, the method including forming a plurality of photodetectors in a substrate. A device isolation structure is formed within the substrate. The device isolation structure laterally wraps around the plurality of photodetectors. An outer isolation structure is formed within the substrate. The device isolation structure is spaced between sidewalls of the outer isolation structure. The device isolation structure and the outer isolation structure comprise a dielectric material. | 2022-08-04 |
20220246550 | Transient Stabilized SOI FETs - Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V | 2022-08-04 |
20220246551 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin. | 2022-08-04 |
20220246552 | CHIP MODULES EMPLOYING CONDUCTIVE PILLARS TO COUPLE A PASSIVE COMPONENT DEVICE TO CONDUCTIVE TRACES IN A METALLIZATION STRUCTURE TO FORM A PASSIVE COMPONENT - Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies can be blocked or filtered out by, for example, a lumped-element circuit or a lumped-element filter consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device, or integrated passive device, is one example of a lumped-element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted on (i.e., coupled to) a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of hand-held mobile devices drives a need for reducing the sizes of chip modules that are inside a mobile device. | 2022-08-04 |
20220246553 | Amplifier Having Improved Stability - Example embodiments relate to amplifiers haying improved stability. One example amplifier includes a conductive substrate, an input terminal arranged spaced apart from the conduct substrate, a first bondwire attachment structure electrically connected to or integrally formed with the input terminal, a first input matching capacitor having a non-grounded terminal and a grounded terminal, a second bondwire attachment structure electrically connected to the non-grounded terminal of the first input matching capacitor, a first semiconductor die on which a radiofrequency power transistor is arranged that has an output electrically connected to a fourth bondwire attachment structure, an output matching capacitor having a non-grounded terminal and a grounded terminal (the non-grounded terminal being electrically connected to a fifth bondwire attachment structure), an output terminal arranged spaced apart from the conductive substrate, a sixth bondwire attachment structure electrically connected to or integrally formed with the output terminal, and multiple bondwire assemblies. | 2022-08-04 |
20220246554 | MICROELECTRONIC DEVICES DESIGNED WITH COMPOUND SEMICONDUCTOR DEVICES AND INTEGRATED ON AN INTER DIE FABRIC - Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. | 2022-08-04 |
20220246555 | SEMICONDUCTOR DEVICE PACKAGE - The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE. | 2022-08-04 |
20220246556 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity. | 2022-08-04 |
20220246557 | PACKAGE CHIP AND METHOD OF MANUFACTURING THE SAME, REWIRING PACKAGE CHIP AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a package chip, a package chip, a method of manufacturing a rewiring package chip, and a rewiring package chip are provided. Since a dielectric layer covering a surface of a chip and conductive surfaces of pads does not need to be partially removed by etching, air tightness of the package chip may be improved to prevent the pads from being oxidized by the air, and at the same time, an etching operation may not be performed to etch the pads. In this way, the pads may be prevented from being etched, and a short circuit, which is caused by the surface of the chip being corroded by the etching solution, may be prevented. | 2022-08-04 |
20220246558 | Methods Of Forming Microvias With Reduced Diameter - A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer. | 2022-08-04 |
20220246559 | Methods of Forming Semiconductor Packages Having a Die with an Encapsulant - An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor. | 2022-08-04 |
20220246560 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor chip, a plurality of bonding pads on a surface of the semiconductor chip, a plurality of probe pads on a surface of the semiconductor chip, a plurality of connection pads on a surface of the substrate, and a plurality of bonding wires that electrically connect the bonding pads and the connection pads. The plurality of bonding pads include a first bonding pad and a second bonding pad, the plurality of probe pads include a first probe pad and a second probe pad, and a part of the first probe pad is disposed between the second bonding pad and the second probe pad. | 2022-08-04 |
20220246561 | METHOD FOR MANUFACTURING SIDE WETTABLE PACKAGE - A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality. | 2022-08-04 |
20220246562 | BONDED SEMICONDUCTOR DIE ASSEMBLY WITH METAL ALLOY BONDING PADS AND METHODS OF FORMING THE SAME - A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal. | 2022-08-04 |
20220246563 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space. | 2022-08-04 |
20220246564 | BOND ENHANCEMENT STRUCTURE IN MICROELECTRONICS FOR TRAPPING CONTAMINANTS DURING DIRECT-BONDING PROCESSES - Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process. | 2022-08-04 |
20220246565 | Bump Integration with Redistribution Layer - A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via. | 2022-08-04 |
20220246566 | MULTI-FUNCTION BOND PAD - An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation. | 2022-08-04 |
20220246567 | UPPER CONDUCTIVE STRUCTURE HAVING MULTILAYER STACK TO DECREASE FABRICATION COSTS AND INCREASE PERFORMANCE - Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire. | 2022-08-04 |
20220246568 | SEMICONDUCTOR PACKAGE INCLUDING POST - A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating laver, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The lost has a ring shape having an inner surface and an outer surface when viewed a top view. A maximum width of the inner surface is less than a Maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section. | 2022-08-04 |
20220246569 | COMBINATION-BONDED DIE PAIR PACKAGING AND ASSOCIATED SYSTEMS AND METHODS - Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs. | 2022-08-04 |
20220246570 | PACKAGE STRUCTURE HAVING HOLLOW CYLINDERS AND METHOD OF FABRICATING THE SAME - A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders. | 2022-08-04 |
20220246571 | MULTI-FEED PACKAGED ANTENNA BASED ON FAN-OUT PACKAGE - A multi-feed packaged antenna based on fan-out package, which relates to packaged antennas. A first passivation layer is arranged under a packaging layer, and first and second redistribution layers are arranged on the first passivation layer to build the multi-feed packaged antenna. Connecting ends of multiple channels of a chip are connected to a feed structure of a packaged antenna. A metal layer of the feed structure is achieved by the first redistribution layer, and the second redistribution layer is mainly configured to package an antenna. The coaxial feed is adopted herein, in which two redistribution layers are provided, by which a multi-port power combining can be achieved on the antenna, providing a wide-beam performance. | 2022-08-04 |
20220246572 | COMPRESSIBLE FOAMED THERMAL INTERFACE MATERIALS AND METHODS OF MAKING THE SAME - Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials. | 2022-08-04 |
20220246573 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure. | 2022-08-04 |
20220246574 | Bonded Semiconductor Devices and Methods of Forming The Same - A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component. | 2022-08-04 |
20220246575 | BONDING METHOD AND STRUCTURE - A bonding method is capable of realizing high bonding strength and connection reliability even at a connection part in a high temperature area by means of simple operation low temperature bonding. The method includes a first step wherein, on at least one of the bonded surfaces of two materials to be bonded having a smooth surface, a thin film of noble metal with a volume diffusion coefficient greater than that of the base metal of the material to be bonded is formed using an atomic layer deposition method at a vacuum of 1.0 Pa or higher, a second step wherein a laminate is formed by overlapping the two materials to be bonded so that the bonded surfaces of the two materials are connected through the thin film, and a third step wherein the two materials to be bonded are bonded by holding the laminate at a predetermined temperature. | 2022-08-04 |
20220246576 | Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly - A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-stage assembly, including: align and fix at least one first-stage device to a target position on a carrier plate by utilizing the self-alignment capability of first-stage alignment solder joints; and while using a clamping board to support an exposed side of the at least one first-stage device, performing injection molding through an opening in the carrier board or the clamping board. The packaging method further comprises align and fix a second-stage device to a target position on the first-stage assembly by utilizing the self-alignment capability of second-level alignment solder joints between the first-stage assembly and the second-stage device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-stage device and the second-stage device, resulting in improved process efficiency and reduced process cost. | 2022-08-04 |
20220246577 | Power Semiconductor Module and Method of Forming the Same - A terminal can be connected to a substrate for forming a power semiconductor module by using ultrasound welding. The terminal includes a first connection area located at a terminal foot. The first connection area is adapted for connecting the terminal to the substrate. The terminal also includes a second connection area that is located opposite to the first connection area at the terminal foot. The substrate includes a third connection area adapted to be connected to the first connection area. The method includes bringing the first connection area in contact to the third connection area, connecting the terminal to the substrate by acting on the second connection area with an ultrasound welding tool, and smoothening the second connection area after connecting the terminal to the substrate | 2022-08-04 |
20220246578 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die. | 2022-08-04 |
20220246579 | MULTI-CHIP PACKAGES - Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip. | 2022-08-04 |
20220246580 | PACKAGE COMPRISING AN INTEGRATED DEVICE CONFIGURED FOR SHAREABLE POWER RESOURCE - A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device. | 2022-08-04 |
20220246581 | Stacked Integrated Circuit Structure and Method of Forming - A semiconductor device and a method of forming the device are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material. | 2022-08-04 |
20220246582 | SEMICONDUCTOR PACKAGE - Disclosed is a semiconductor package comprising a lower semiconductor chip and upper semiconductor chips vertically stacked on a top surface of the lower semiconductor chip. The upper semiconductor chips include first upper semiconductor chips and a second upper semiconductor chip. The first upper semiconductor chips are between the lower semiconductor chip and the second upper semiconductor chip. A thickness of each of the first upper semiconductor chips is 0.4 to 0.95 times that of the lower semiconductor chip. A thickness of the second upper semiconductor chip is the same as or greater than that of the first upper semiconductor chip. A total number of the first and second upper semiconductor chips is 4n, wherein n is a natural number equal to or greater than three. | 2022-08-04 |
20220246583 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENTS, AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a display device according to an embodiment of the present invention has a step for assembling semiconductor light-emitting devices on a substrate; a step for applying a photosensitive organic insulator onto the semiconductor light-emitting devices and the substrate; a step for removing the photosensitive organic insulator from the regions other than a space between the substrate and bottoms of the semiconductor light-emitting devices; and a step for curing the photosensitive organic insulator filled in the space. | 2022-08-04 |
20220246584 | DISPLAY TRANSFERRING STRUCTURE AND DISPLAY DEVICE INCLUDING THE SAME - A display transferring structure includes a transferring substrate including a mold including a plurality of recesses, and a plurality of protrusions provided on an outer surface of the mold connected to the plurality of recesses; and micro semiconductor chips arranged in the recesses. When the micro semiconductor chips are wet aligned, by such protrusions, sliding of the micro semiconductor chips toward the inside of the recesses may be improved. | 2022-08-04 |
20220246585 | APPARATUS FOR ILLUMINATION USING LED DIE ARRAY AND METHOD THEREOF - An apparatus for illumination using a light emitting element die array, includes a base sheet; a plurality of light emitting element die array attached to the base sheet and arranged in a matrix shape, the light emitting element including a light emitting surface and an electrode formation surface facing the light emitting surface, flip chip bonding electrodes being formed on the electrode formation surface; and a transparent support layer covering the light emitting surface of the plurality of light emitting element dies, and fixing the plurality of light element dies by a constant light source interval, the transparent support layer including a fluorescent material absorbing light emitting through the light emitting surface to change a wavelength of the light. | 2022-08-04 |
20220246586 | Tunable LED-Filaments and Tunable LED-Filament Lamps - A color temperature tunable LED-filament includes an elongated light-transmissive substrate; a first array of LED chips on a front face of the substrate; a second array of LED chips on the front face of the substrate; a first photoluminescence layer covering the first array of LED chips; a second photoluminescence layer covering the second array of LED chips; and a circuit arrangement enabling independent power control to the first and second LED arrays or relative power control to the first and second array of LED chips to control the color temperature of light generated by the LED-filament. | 2022-08-04 |
20220246587 | -LED, ;-LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-08-04 |
20220246588 | LIGHT EMITTING ELEMENT WITH PARTICULAR PHOSPHORS - A light emitting device includes a first light emitting element, a second light emitting element, a first phosphor sheet containing a first phosphor and a third phosphor, and covering a top face of the first light emitting element, and a second phosphor sheet containing a second phosphor and a fourth phosphor, and covering a top face of the second light emitting element, wherein a peak wavelength of light which is wavelength-converted by the first phosphor or the third phosphor is equal to or less than a peak wavelength of light which is wavelength-converted by the second phosphor or the fourth phosphor. | 2022-08-04 |
20220246589 | Edge-Connected Semiconductor Systems - Edge-connected semiconductor systems are described along with methods of making and using the same. First and second integrated circuit packages are obtained, each including a substrate assembly having top and bottom sides and an edge that extends between the top and the bottom sides. Edge contacts are disposed on the edges of the substrate assemblies. A ganged assembly is formed by establishing conductive paths between the edge contacts of the substrate assemblies. The ganged assembly is coupled to a printed circuit board (“PCB”) by coupling host contacts on one or more of the substrate assemblies to corresponding contacts on the PCB. | 2022-08-04 |
20220246590 | Integrated Fan-Out Packages and Methods of Forming the Same - A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias. | 2022-08-04 |
20220246591 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval. | 2022-08-04 |
20220246592 | OPTICAL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a first die, a bumping structure, and a second die. The first die is on a carrier. The bumping structure is over the first die. The bumping structure includes a light-transmitting portion and a light-blocking portion embedded in the light-transmitting portion. The second die is electrically connected to the carrier. The light-blocking portion of the bumping structure is free from covering the second die. | 2022-08-04 |
20220246593 | DISPLAY DEVICE USING MICRO-LED, AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a display device can include forming an assembly electrode on a substrate; applying an insulating layer on the assembly electrode; disposing a partition wall on the insulating layer; defining an assembly groove in the partition wall; providing an light emitting diode (LED) having an assembly face corresponding to a shape of the assembly groove in the partition wall; and assembling the assembly face of the LED into the assembly groove in the partition wall, in which the LED includes a first electrode, a first semiconductor layer, an active layer, a second semiconductor layer, and a second electrode stacked in a first direction to form a stacked structure. | 2022-08-04 |
20220246594 | LIGHT EMITTER BOARD AND DISPLAY DEVICE - A light emitter board includes a substrate such as a glass substrate, a resin insulating layer as a first insulating layer on the substrate, a light shield layer as a second insulating layer on the resin insulating layer, an opening portion in the light shield layer, a mount located on a part of the resin insulating layer exposed in the opening portion and receiving a light emitter, and the light emitter on the mount. The mount includes a protrusion on the part of the resin insulating layer. The light emitter on the mount has an upper surface located above an upper surface of the light shield layer. | 2022-08-04 |
20220246595 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device. | 2022-08-04 |
20220246596 | Display Device - A display device having a narrow bezel region is provided. The display device includes a first layer and a second layer. The first layer includes a source driver and one part of a sensor, and the second layer includes a gate driver, a plurality of pixels, and the other part of the sensor. The plurality of pixels include a pixel in which a light-emitting element emits light and a pixel having a function of the gate driver. An opening portion where the one part of the sensor is formed and a first terminal connected to the source driver are provided on the top surface of the first layer, and a second terminal is provided on the opposite side of the surface where the pixels included in the second layer are arranged. The first terminal is bonded to the second terminal, so that they are electrically connected to each other and the sensor is formed. Since an output signal of the source driver is directly supplied through the first terminal to a wiring to which the plurality of pixels are connected, the source driver and the gate driver do not need to be provided in a peripheral region of a display region where the plurality of pixels are provided. | 2022-08-04 |
20220246597 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICE AND ELECTRONIC COMPONENT DEVICE - Disclosed is a method for manufacturing an electronic component device, including: preparing a sealing structure having a sealing layer having two opposing main surfaces, an electronic component, and a connection portion, the connection portion being exposed on a circuit surface that is one main surface of the sealing layer; preparing a rewiring structure having a rewiring portion having two opposing main surfaces, and a plurality of bumps; and bonding the sealing structure and the rewiring structure in a direction that the circuit surface and the plurality of bumps face each other, with an insulating layer intervening. | 2022-08-04 |
20220246598 | Semiconductor Devices and Methods of Manufacture - Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device. | 2022-08-04 |
20220246599 | INTEGRATED CIRCUIT DEVICE AND METHOD - An integrated circuit (IC) device includes a functional circuit electrically coupled to a first power supply node and operable by a first power supply voltage on the first power supply node, and a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to the first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal configured to receive the control signal, and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes to provide or cutoff power supply to the functional circuit. | 2022-08-04 |
20220246600 | INTEGRATED CIRCUIT FILLER AND METHOD THEREOF - Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process. | 2022-08-04 |
20220246601 | INTEGRATED CIRCUIT INCLUDING INTEGRATED STANDARD CELL STRUCTURE - An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region. | 2022-08-04 |
20220246602 | STACK-GATE CIRCUIT - A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion. | 2022-08-04 |
20220246603 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main IGBT, a sense, a resistor, a MOSFET and a diode, as main components. The sense IGBT and the main IGBT are connected in parallel with each other. The drain of MOSFET is connected to the gate of the sense IGBT, the source thereof is connected to the gate of the main IGBT, and the gate thereof is connected to the emitter of the sense IGBT and the cathode of diode. One end of the resistor is connected to the gate of the main IGBT and the source of the MOSFET, and the other end of the resistor is connected to the emitter of the main IGBT and the anode of the diode. | 2022-08-04 |
20220246604 | CAPACITOR INTEGRATED IN FINFET DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a capacitor integrated in a FinFET. The capacitor and a resistor are both integrated in a middle-end-of-line process layer. A resistor main body layer and a resistor cover layer of the resistor and the forming regions of the intermediate dielectric layer and the lower electrode plate of the capacitor are patterned in a lithography process applying a first photomask; a forming region of an upper electrode plate is patterned in another lithography process applying a second photomask; the lower electrode plate, the upper electrode plate and the resistor main body layer are respectively connected with a metal zeroth layer. The present application further discloses a method for fabricating a capacitor integrated in a FinFET device. The disclosed method can reduce the process cost and improve the process efficiency, as well as flexibly select the capacitance of the capacitor by the process. | 2022-08-04 |
20220246605 | Variable Capacitance Circuit, Circuit Device, And Oscillator - A variable capacitance circuit includes a capacitor array having a first capacitor in which a plurality of MIM capacitors are coupled in parallel and a second capacitor in which a plurality of MIM capacitors are coupled in series, and a switch array having a first switch and a second switch. A shape pattern of at least one of a first electrode of the first capacitor, a first ground shield, a second electrode of the second capacitor, and a second ground shield is set so that a first capacitance difference per 1 LSB between first capacitance values of the first capacitor when the first switch is turned on and off and a second capacitance difference per 1 LSB between second capacitance values of the second capacitor when the second switch is turned on and off are close to each other. | 2022-08-04 |
20220246606 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor part, first and second electrodes, a control electrode and a control interconnect. The semiconductor part includes first to sixth layers and is provided between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are arranged between the first layer and the first electrode. The second electrode and the control interconnect are arranged on the semiconductor part. The control electrode is provided between the second electrode and the semiconductor part. The sixth layer is provided between the first layer and the control interconnect. The fifth semiconductor layer is provided between the first electrode and the sixth layer. The first semiconductor layer includes a carrier trap provided between the fifth and sixth layers. | 2022-08-04 |
20220246607 | THREE-WAY SWITCH ARRAY STRUCTURE AND SWITCH ARRAY SUBSTRATE BASED ON NVM - A three-way switch array structure including N first connectors, M second connectors, N×M third connectors and N×M three-way switches is provided, each three-way switch has a first terminal, a second terminal, a third terminal, a first switch and a second switch. Each of first terminals is disposed on one of the first connectors, each of second terminals is disposed on one of the second connectors, and each of third terminals is disposed on one of the third connectors, the first switch is disposed between the first terminal and the third terminal, and the second switch is disposed between the second terminal and the third terminal, wherein N and M are positive integers greater than or equal to 1. | 2022-08-04 |
20220246608 | LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE - Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer. | 2022-08-04 |
20220246609 | INTEGRATED CIRCUIT WITH ANTI-PUNCH THROUGH CONTROL - An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses. | 2022-08-04 |
20220246610 | CROSS-COUPLED GATE DESIGN FOR STACKED DEVICE WITH SEPARATED TOP-DOWN GATE - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively. | 2022-08-04 |
20220246611 | SEMICONDUCTOR DEVICE AND METHODS OF FORMING - An embodiment includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, an outer surface of the epitaxial first source/drain region having more than eight facets in a first plane, the first plane being orthogonal to a top surface of the substrate. | 2022-08-04 |
20220246612 | MULTIPLE NANO LAYER TRANSISTOR LAYERS WITH DIFFERENT TRANSISTOR ARCHITECTURES FOR IMPROVED CIRCUIT LAYOUT AND PERFORMANCE - A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other. | 2022-08-04 |
20220246613 | Isolation Structure For Preventing Unintentional Merging Of Epitaxially Grown Source/Drain - A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component. | 2022-08-04 |
20220246614 | Uniform Gate Width For Nanostructure Devices - According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack. | 2022-08-04 |
20220246615 | SEMICONDUCTOR DEVICE OR OSCILLATOR - A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor. | 2022-08-04 |
20220246616 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - An embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate has a peripheral region and an array region; stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate; etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; reserving the mask layer; in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region; forming a first material layer; forming a second material layer; etching a part of the mask layer with the second material layer as the mask; and removing the remaining second material layer, the remaining mask layer and the first material layer on the remaining mask layer. | 2022-08-04 |
20220246617 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer. | 2022-08-04 |
20220246618 | SUPPORT PILLARS FOR VERTICAL THREE-DIMENSIONAL (3D) MEMORY - Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers. A third vertical opening is formed through the vertical stack extending to expose second sidewalls adjacent areas where horizontal access devices will be formed. The sacrificial material is selectively etched to form first horizontal openings, removing the sacrificial material a first horizontal distance (D1) back from the third vertical opening. A fourth vertical opening is formed through the vertical stack to expose third sidewalls adjacent areas where storage nodes will be formed. The support-pillar material of the formed structural support pillars may serve as an etch stop in selectively etching to form the second horizontal openings. | 2022-08-04 |
20220246619 | MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line. | 2022-08-04 |
20220246620 | DRAM DEVICE INCLUDING AN AIR GAP AND A SEALING LAYER - A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer. | 2022-08-04 |
20220246621 | SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE ELECTRODE INCLUDING STEP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode. | 2022-08-04 |
20220246622 | Integrated Circuitry, Memory Circuitry, Method Used In Forming Integrated Circuitry, And Method Used In Forming Memory Circuitry - A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed. | 2022-08-04 |
20220246623 | STATIC RANDOM ACCESS MEMORY OF 3D STACKED DEVICES - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM) including a plurality of transistors disposed in a first layer and a second layer. The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, among the plurality of transistors. The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, among the plurality of transistors. The third shared gate is disposed above the first shared gate, and the fourth shared gate is disposed above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-couple contact connecting the fourth shared gate and the first shared contact, and a second cross-couple contact connecting the third shared gate and the second shared contact. | 2022-08-04 |
20220246624 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A STRING SELECTION LINE GATE ELECTRODE HAVING A SILICIDE LAYER - A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide. | 2022-08-04 |
20220246625 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device includes a substrate and an eFuse structure. The substrate includes an array region and an eFuse region and the eFuse region of the substrate has an eFuse trench. The eFuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line, and an eFuse gate electrode. The first gate oxide layer is conformally formed on a surface of the eFuse trench. The doped regions are respectively formed in the substrate on opposite sides outside the eFuse trench, and in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The eFuse gate electrode is formed on the dummy buried word line and in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the eFuse gate electrode. | 2022-08-04 |
20220246626 | RAISED PAD FORMATIONS FOR CONTACTS IN THREE-DIMENSIONAL STRUCTURES ON MICROELECTRONIC WORKPIECES - Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces. | 2022-08-04 |
20220246627 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer. | 2022-08-04 |
20220246628 | Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Simultaneously, (a), (b), and (c) are formed, where (a): horizontally-elongated trenches into the stack laterally-between immediately-laterally-adjacent of the memory-block regions; (b): channel openings into the stack laterally-between the horizontally-elongated trenches; and (c): through-array-via (TAV) openings into the stack in a stair-step region. Intervening material is formed in the horizontally-elongated trenches, a channel-material string in individual of the channel openings, and conductive material in the TAV openings. Other aspects, including structure independent of method, are disclosed. | 2022-08-04 |
20220246629 | SEMICONDUCTOR WITH EXTENDED LIFE TIME FLASH MEMORY AND FABRICATION METHOD THEREOF - A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed. | 2022-08-04 |
20220246630 | MEMORY SYSTEM - According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation. | 2022-08-04 |
20220246631 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer. | 2022-08-04 |
20220246632 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A semiconductor device includes a semiconductor substrate that includes a first surface and a second surface, a semiconductor region between the first and second surfaces, a first well region in the first surface and having one of a donor concentration and a acceptor concentration higher than the semiconductor region, a second well region between the first well region and the second surface and having a higher acceptor concentration than the semiconductor region, a third well region between the second well region and the second surface and having a higher donor concentration than the semiconductor region, a conductor surrounding at least a portion of the first well region along the first surface and extending from the first surface to the third well region in a first direction intersecting the first surface, and an insulator between the conductor and the first well region and between the conductor and the second well region. | 2022-08-04 |
20220246633 | MEMORY DEVICE AND METHOD OF CONTROLLING MEMORY DEVICE - According to one embodiment, a memory device includes: first and second stacks each including a first semiconductor layers arranged in a first direction perpendicular to a surface of a substrate, the first and second stacks arranged in a second direction parallel to the surface of the substrate; a second semiconductor layer above the first stack in the first direction; a third semiconductor layer above the second stack in the first direction; memory cells between the first semiconductor layers and the word lines; a first transistor on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacks are arranged at a first pitch, the first and second semiconductor layers are arranged at a second pitch equal to the first pitch. | 2022-08-04 |
20220246634 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies. | 2022-08-04 |
20220246635 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies. | 2022-08-04 |
20220246636 | METHOD OF FORMING A STEPPED SURFACE IN A THREE-DIMENSIONAL MEMORY DEVICE AND STRUCTURES INCORPORATING THE SAME - A method includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming a joint dielectric layer over the first-tier alternating stack, such that the joint dielectric layer is thicker than each of the first insulating layers and the first sacrificial material layers, forming a second-tier alternating stack of second insulating layers and second sacrificial material layers over the joint dielectric layer and the first-tier alternating stack, performing a level-shift anisotropic etch process to form a recess trench or via cavities vertically extending through the second-tier alternating stack and down to the joint dielectric layer, and performing an extension etching process to extend the recess trench or the via cavities through at least the joint dielectric level. At least one of etching time or etching power used during the extension etching process is different from that used during the level-shift anisotropic etch process. | 2022-08-04 |
20220246637 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device includes a substrate, a laminated structure and a memory string. The laminated structure is disposed on the substrate. The laminated structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The memory string is accommodated in the laminated structure along the first direction. The memory string includes a memory layer and a channel layer, and the memory layer is disposed between the laminated structure and the channel layer. At least a portion of the memory layer and the insulating layers are overlapped along the first direction. | 2022-08-04 |
20220246638 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes preparing a lower structure including an interconnection, forming a first contact plug coupled to the interconnection, and forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure. The method further includes forming an opening that penetrates the alternating stack and exposes the first contact plug, forming a sacrificial plug including a void in the opening, forming a contact hole that exposes the first contact plug by etching a portion of the sacrificial plug, and forming a second contact plug in the contact hole. | 2022-08-04 |