31st week of 2022 patent applcation highlights part 61 |
Patent application number | Title | Published |
20220246439 | PLASMA ETCHING METHOD - A plasma etching method includes a first step of supplying a mixed gas containing vaporized heptafluoroisopropyl methyl ether gas having a molecular structure of a following Chemical Formula 1 or vaporized heptafluoropropyl methyl ether gas having a molecular structure of a following Chemical Formula 2 and argon gas into a plasma chamber in which an etching target is disposed; and a second step of etching the etching target using plasma generated from the mixed gas: | 2022-08-04 |
20220246440 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes: (a) providing a substrate including an etching target film, a first mask formed on the etching target film, and a second mask formed on the first mask, the second mask being different in film type from the first mask and having an opening; (b) selectively etching the first mask with respect to the second mask, thereby forming an opening in the first mask such that an opening dimension of at least a portion of the first mask is larger than an opening dimension of a bottom of the second mask; and (c) etching the etching target film. | 2022-08-04 |
20220246441 | Gate Structure of Semiconductor Device and Method for Forming the Same - A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width. | 2022-08-04 |
20220246442 | Semiconductor Device and Method of Manufacture - In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group. | 2022-08-04 |
20220246443 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A technique improves selectivity in etching of a silicon-containing film over etching of a mask in plasma etching. A substrate processing method includes placing a substrate in a chamber in a plasma processing apparatus. The substrate includes a silicon-containing film and a mask on the silicon-containing film. The substrate processing method further includes generating plasma from a first process gas containing a hydrogen fluoride gas in the chamber. The generating plasma includes etching the silicon-containing film with a chemical species contained in the plasma. A flow rate of the hydrogen fluoride gas is at least 80 vol % of a total flow rate of now-inert components of the first process gas. | 2022-08-04 |
20220246444 | INCORPORATING SEMICONDUCTORS ON A POLYCRYSTALLINE DIAMOND SUBSTRATE - A method for incorporating semiconductors on a diamond substrate. A buffer layer (e.g., GaN) is grown on a transition layer (e.g., AlN/AlGaN) residing on a substrate. A silicon nitride layer is then grown on the buffer layer. After selectively seeding diamond on the silicon nitride layer, the selective seeding of the diamond is dry etched to form regions with seeded diamond and regions without seeded diamond. The silicon nitride is selectively etched in the regions without seeded diamond and diamond is grown in the regions with seeded diamond forming regions of diamond. Additional Group III-nitride semiconductor material (e.g., GaN) is grown in the etched regions without seeded diamond to fill such regions to reach a level of the regions with diamond. An epitaxial overgrowth of the Group III semiconductor material at and above the level of the regions with diamond is then performed. | 2022-08-04 |
20220246445 | PRINTED CIRCUIT BOARD - A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer. | 2022-08-04 |
20220246446 | PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF - A packaging structure and fabrication method thereof are provided. The method includes: providing semiconductor chips including functional surfaces, non-functional surfaces, and first soldering pads; providing electronic devices that do not need shielding including second soldering pads; providing a carrier plate; adhering functional surfaces of the semiconductor chips to the carrier plate; forming a first shielding layer covering non-functional surfaces and sidewalls of the semiconductor chips; adhering each electronic device to the carrier plate at a side of a corresponding semiconductor chip; forming a second shielding layer on the first shielding layer; forming a plastic encapsulation layer covering the second shielding layer, the electronic devices that do not need shielding, and the carrier plate; peeling off the carrier plate to form a pre-packaging plate; and forming first external contact structures connected to the first soldering pads and second external contact structures connected to the second soldering pads. | 2022-08-04 |
20220246447 | METHOD OF MANUFACTURING PASSIVATION FILM - A method of manufacturing a passivation film, which includes a passivation process in which a substrate on the surface of which at least one of germanium and molybdenum is contained is treated with a passivation gas containing an oxygen-containing compound, which is a compound containing an oxygen atom in the molecule, and hydrogen sulfide to form a passivation film containing a sulfur atom on the surface of the substrate. The concentration of the oxygen-containing compound in the passivation gas is from 0.001 mole ppm to less than 75 mole ppm. | 2022-08-04 |
20220246448 | DISPENSER FOR MICRO LED SUSPENSION AND METHOD OF TRANSFERRING MICRO LED - Provided is a dispenser for a solution including a reservoir configured to hold a suspension of micro light-emitting diodes (LEDs) suspended in a solvent; a stirrer configured to stir the suspension in the reservoir; a discharge path including a first valve configured to control outflow of the suspension from the reservoir; a filling path including a second valve configured to control inflow of the suspension into the reservoir; a hydraulic path including a third valve configured to control a pressure inside the reservoir; and a washing path connected to the first valve and configured to input a washing fluid for washing the discharge path into the discharge path, wherein the first valve includes a multi-way valve configured to selectively connect the discharge path to one of the reservoir and the washing path. | 2022-08-04 |
20220246449 | WAFER TREATMENT DEVICE - Provided is an exhaust system of a wafer treatment device, and the main purpose thereof is to prevent secondary contamination of a wafer by not allowing foreign substances such as process gases and fumes and the like floating in the wafer treatment device to make contact with the wafer in a side storage. The wafer treatment device comprises: a cleaning device for removing foreign substances remaining on a wafer; and an exhaust device comprising first and second main bodies at the lower side of a main body of the wafer treatment device. By not allowing foreign substances such as process gases and fumes and the like floating in the wafer treatment device to make contact with a wafer in a side storage, secondary contamination of the wafer is prevented. | 2022-08-04 |
20220246450 | SEMICONDUCTOR WAFER CASSETTE WAREHOUSE TRANSPORTATION STRUCTURE SYSTEM - A semiconductor wafer cassette warehouse transportation structure system includes a wafer cassette lift transportation structure body, a wafer cassette frame structure body, an arm structure body, an arm gripping wafer cassette structure body, and a wafer cassette warehouse structure body. The suspension support rods are suspended on a ceiling. The wafer cassette lift transportation structure body lifts the wafer cassettes to the inlet and outlet. The arm structure body grips the wafer cassettes and puts same on the tracks so that the wafer cassettes can be transported to the wafer cassette warehouse structure body to be precisely accessed. The system saves space and facilitates the access of the wafer cassettes because the wafer cassettes are stored on the wafer cassette warehouse structure body suspended on the ceiling. | 2022-08-04 |
20220246451 | MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A member for semiconductor manufacturing apparatus includes an upper plate that has a wafer placement surface, that contains an electrostatic electrode and an upper auxiliary electrode parallel to each other, and that comprises ceramics; an intermediate plate that is joined to a surface of the upper plate opposite the wafer placement surface with a first metal joining layer interposed therebetween; and a lower plate that is joined to a surface of the intermediate plate opposite a surface joined to the upper plate with a second metal joining layer interposed therebetween and that contains a heater electrode and a lower auxiliary electrode parallel to each other. | 2022-08-04 |
20220246452 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - Provided are an apparatus and a method for treating a substrate at a high-pressure atmosphere. The apparatus for treating the substrate includes a first body and a second body combined with each other to define a treatment space in which the substrate is treated, a sealing member interposed between the first body and the second body to seal the treatment space from an outside at a position in which the first body is in close contact with the second body, and a driving member to drive the first body or the second body such that the treatment space is open or closed. The sealing member is positioned in a sealing groove formed in the first body. The sealing member is deformed to be in close contact with the second body by pressure of the treatment space when a process is performed. | 2022-08-04 |
20220246453 | METHODS AND APPARATUS FOR MEASURING EDGE RING TEMPERATURE - An apparatus for measuring a temperature of an assembly that is internal to a process chamber. The apparatus may include a light pipe positioned between a lamp radiation filtering window and the assembly, the light pipe has a first end with a bevel configured to redirect infrared radiation emitted from the assembly through the light pipe and has a second end distal to the first end, an optical assembly configured to collimate, filter, and focus infrared radiation from the second end of the light pipe, an optical detector configured to receive an output from the optical assembly and generate at least one signal representative of the infrared radiation, a temperature circuit that transforms the at least one signal into a temperature value, and a controller that is configured to receive the temperature value and to make adjustments to other process parameters of process chamber based on the temperature value. | 2022-08-04 |
20220246454 | PROCESS ABNORMALITY IDENTIFICATION USING MEASUREMENT VIOLATION ANALYSIS - The subject matter of this specification can be implemented in, among other things, a method, system, and/or device to receive current metrology data for an operation on a current sample in a fabrication process. The metrology data includes a current value for a parameter at each of one or more locations on the current sample. The method includes obtaining a reference rate of change of the parameter value of the parameter for each of the one or more locations. The method further includes determining a current rate of change of the parameter value for each of the one or more locations. The current rate of change is associated with the current sample. The method further includes comparing the current rate of change of the parameter value to the reference rate of change of the parameter value and identifying an instance of abnormality of the fabrication process based on the comparison. | 2022-08-04 |
20220246455 | SUBSTRATE PROCESSING SYSTEM, LOAD PORT AND METHOD - A system includes at least one sensor and at least one controller. The at least one sensor is configured to generate a first weight signal corresponding to a first weight of a first lot of substrates, and a second weight signal corresponding to a second weight of a second lot of substrates. The at least one controller is coupled to the at least one sensor to receive the first weight signal and the second weight signal. The at least one controller is configured to convert a weight difference between the first weight and the second weight into a number of substrates each having a predetermined weight. The at least one controller is further configured to, based on the converted number of substrates, control a processing apparatus to rotate the first lot of substrates and the second lot of substrates simultaneously. | 2022-08-04 |
20220246456 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, ARTICLE MANUFACTURING SYSTEM, AND ARTICLE MANUFACTURING METHOD - An information processing apparatus includes an acquisition unit configured to acquire information including a processing result of processing a substrate by a substrate processing apparatus configured to perform substrate processing at a first timing, event information about an event having occurred in the substrate processing apparatus at a second timing after the first timing, and a processing result of processing the substrate by the substrate processing apparatus at a third timing after the second timing, and a display control unit configured to perform control so that a display device displays a chronological graph of a processing result including the processing result at the first timing and the processing result at the third timing based on the information acquired by the acquisition unit, wherein the display control unit performs control to display information in a superimposed manner on the graph, the information indicating the second timing. | 2022-08-04 |
20220246457 | DETECTING OUTLIERS AT A MANUFACTURING SYSTEM USING MACHINE LEARNING - Methods and systems for detecting outliers at a manufacturing system using machine learning are provided. Data collected by a sensors at a manufacturing system during a current process performed for a first set of substrates is provided as input to a trained machine learning model. One or more outputs are obtained from the trained machine learning model. A first amount of drift of a first set of parameter values for the first set of substrates from a target set of parameter values for the first set of substrates is extracted from the one or more outputs. A second amount of drift of each of the first set of parameter values for the first set of substrates from a corresponding parameter value of a second set of parameter values for a second set of substrates processed according to the current process at the manufacturing system prior to the performance of the current process for the first set of substrates is also extracted from the one or more outputs. A substrate health rating is assigned for each of the first set of substrates based on the first amount of drift. A sensor health rating is assigned for each of the sensors at the manufacturing system based on the second amount of drift. An indication of the substrate health rating for each of the first set of substrates and the sensor health rating for each of the sensors are transmitted to a client device connected to the manufacturing system. | 2022-08-04 |
20220246458 | MAGNETIC TRANSFER APPARATUS AND FABRICATION METHOD OF THE SAME - A magnetic transfer apparatus includes: a magnetomotive force source providing magnetic flux, a first magnetic flux distribution circuit connected to one end of the magnetomotive force source, having a single input terminal and a plurality of output terminals, and distributing the magnetic flux, and a second magnetic flux distribution circuit connected to the other end of the magnetomotive force source, having a single output terminal and a plurality of input terminals, and collecting the distributed magnetic flux. The output terminals of the first magnetic flux distribution circuit are disposed to be adjacent to each other to form a pair with the input terminals of the second magnetic flux distribution circuit. | 2022-08-04 |
20220246459 | SUBSTRATE SUPPORT DEVICE - A substrate support device includes a placement part formed in a plate shape which extends in a horizontal direction and having a placement surface on which a substrate is placed, and a movable part which makes the placement surface conform to the substrate by moving according to a warpage of the substrate placed on the placement surface. The movable part includes an arm part including an expansion and contraction part which expands and contracts in the horizontal direction according to the warpage of the substrate placed on the placement surface, an arm body having a longitudinal direction in a vertical direction in a state in which the substrate is not placed on the placement surface, and an arm connection part which connects a lower end of the arm body to an outer end of the expansion and contraction part in the horizontal direction. | 2022-08-04 |
20220246460 | APPARATUS FOR TRANSFERRING LIGHT-EMITTING DIODE CHIP - The disclosure provides an apparatus for transferring LED chips, including: first light source configured to generate and emit first light rays; first support structure configured to carry load substrate, load substrate including light-transmissive substrate and the LED chips fixed on side of the light-transmissive substrate away from first light source by dissociation adhesive; second support structure configured to carry to-be-transferred substrate on side of the LED chips away from light-transmissive substrate; and optical control mechanism on side of light-transmissive substrate away from the LED chips and configured to control propagation direction of first light rays that irradiate onto first radiation region of the optical control mechanism to form target light rays that irradiate onto target radiation region of load substrate, so that dissociation adhesive in target radiation region is dissociated to transfer LED chips in target radiation region to to-be-transferred substrate. | 2022-08-04 |
20220246461 | MANUFACTURING METHOD OF CHIPS AND TAPE STICKING APPARATUS - A manufacturing method of chips includes forming modified layers that become points of origin of dividing along planned dividing lines, grinding the back surface of the wafer by grinding abrasive stones to thin the wafer into a finished thickness, and dividing the wafer into the chips along the planned dividing lines using the modified layers as the points of origin. The manufacturing method also includes sticking an expanding tape having elasticity to the back surface of the wafer for which grinding processing has been executed, expanding the expanding tape and widening the interval between the respective chips along the planned dividing lines. | 2022-08-04 |
20220246462 | SIC EDGE RING - Described herein are edge ring among components for manufacturing semiconductors used in a semiconductor manufacturing process. The SiC edge ring includes: a first deposition part having a plasma-damaged portion and a non-damaged portion and including SiC; and a second deposition part formed on the first deposition part and including SiC, wherein a boundary between the damaged portion of the first deposition part and the second deposition part includes an uneven surface. | 2022-08-04 |
20220246463 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE HOLDING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a technique that includes a process chamber configured to process at least one substrate; a microwave generator configured to generate a microwave; a substrate holder configured to load and hold the at least one substrate; and a rotator which includes an output shaft configured to support the substrate holder and an input shaft installed at an off-centered position with respect to the output shaft. | 2022-08-04 |
20220246464 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap. | 2022-08-04 |
20220246465 | FINFET CIRCUIT DEVICES WITH WELL ISOLATION - A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess. | 2022-08-04 |
20220246466 | METHOD FOR FORMING INTERMETALLIC AIR GAP - The present invention discloses a method for forming an intermetallic air gap, which comprises following steps: S01: forming a trench in a solid dielectric; S02: preparing an insulating sheet-like two-dimensional material, wherein the insulating sheet-like two-dimensional material comprises an insulating nano sheet-like layer, the size of the insulating nano sheet-like layer in the sheet-like two-dimensional direction is greater than the size of the trench; S03: the insulating sheet-like two-dimensional material is deposited on the solid dielectric and the trench; S04: annealing the solid dielectric and the insulating sheet-like two-dimensional material to form a stable thin film composed of insulating sheet-like two-dimensional material on the trench. The method for forming an intermetallic air gap provided by the present disclosure can effectively increase the intermetallic air gap formation ratio, and greatly reduce the effective dielectric constant and interconnection delay, further reduce costs, and improve product performance. | 2022-08-04 |
20220246467 | STRUCTURE MANUFACTURING METHOD AND MANUFACTURING DEVICE, AND LIGHT IRRADIATION DEVICE - There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition. | 2022-08-04 |
20220246468 | Metal Oxide Composite As Etch Stop Layer - A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen. | 2022-08-04 |
20220246469 | HIGH CAPACITANCE MIM DEVICE WITH SELF ALIGNED SPACER - The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode. | 2022-08-04 |
20220246470 | NEW METHOD TO FORM CONTACTS WITH MULTIPLE DEPTH BY ENHANCED CESL - The present invention relates to a method of forming contact holes of a CMOS device and a method of making a CMOS device. Because a carbon cap layer or a carbon rich layer is formed on a etching stop layer, when etching reaches the etching stop layer with less depth, great polymer protecting the etching stop layer from etching will be formed in the etching stop layer. As such, when etching reaches the contact holes with more depth, the contact holes with less depth may be protected from over-etching until etching the contact holes with more depth is finished. Over-etching may be avoided, and meanwhile the contact holes with more depth may be fully etched to avoid from under-etching. | 2022-08-04 |
20220246471 | THERMAL PROCESS CHAMBER LID WITH BACKSIDE PUMPING - Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate. | 2022-08-04 |
20220246472 | DUAL REDISTRIBUTION LAYER STRUCTURE - A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer. | 2022-08-04 |
20220246473 | HYBRID FILM SCHEME FOR SELF-ALIGNED CONTACT - A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a metal gate over the fin, the metal gate being surround by a dielectric layer; etching the metal gate to reduce a height of the metal gate, where after the etching, a recess is formed over the metal gate between gate spacers of the metal gate; lining sidewalls and a bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming a mask layer over the metal gate, where a first opening of the mask layer is directly over a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, the second opening exposing an underlying source/drain region; and filling the second opening with a conductive material. | 2022-08-04 |
20220246474 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: preparing a substrate made of a compound semiconductor containing a first element and a second element that is bonded to the first element and has an electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate; and dividing the substrate at a position including a current region where the electric current is caused to flow and along a cleavage plane of the substrate. A method for manufacturing a semiconductor device includes: stacking a first substrate and a second substrate each made of the compound semiconductor; and bonding the first substrate and the second substrate by causing an electric current to flow between the first substrate and the second substrate. | 2022-08-04 |
20220246475 | Component and Method of Manufacturing a Component Using an Ultrathin Carrier - A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier. | 2022-08-04 |
20220246476 | HYBRID WAFER DICING APPROACH USING AN ACTIVELY-FOCUSED LASER BEAM LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits. | 2022-08-04 |
20220246477 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region. | 2022-08-04 |
20220246478 | Forming Nitrogen-Containing Low-K Gate Spacer - A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia. | 2022-08-04 |
20220246479 | SOURCE/DRAIN REGIONS AND METHODS OF FORMING SAME - A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask. | 2022-08-04 |
20220246480 | FinFET Device and Method of Forming Same - A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess. | 2022-08-04 |
20220246481 | SYSTEMS AND METHODS FOR PREDICTING FILM THICKNESS OF INDIVIDUAL LAYERS USING VIRTUAL METROLOGY - A method includes obtaining sensor data associated with a deposition process performed in a process chamber to deposit a film stack on a surface of a substrate, wherein the film stack comprises a plurality of layers of a first material and a plurality of layers of a second material. The method further includes obtaining metrology data associated with the film stack. The method further includes training a first machine-learning model based on the sensor data and the metrology data, wherein the first machine-learning model is trained to generate predictive metrology data associated with layers of the first material. The method further includes training a second machine-learning model based on the sensor data and the metrology data, wherein the second machine-learning model is trained to generate predictive metrology data associated with layers of the second material. | 2022-08-04 |
20220246482 | METHOD FOR SUPPRESSING MATERIAL WARPAGE BY INCREASING GAS DENSITY - Disclosed is a method for suppressing material warpage by increasing a gas density. The method comprises the following steps: a. placing a plurality of semiconductor elements in a processing chamber; b. increasing a temperature in the processing chamber to a first predetermined temperature and importing a gas, to increase pressure to predetermined pressure and apply the processing chamber in a high-temperature and high-pressure working environment; and performing an isothermal-isobaric process at the first predetermined temperature and the predetermined pressure, to improve temperature uniformity by the high pressure gas; and c. decreasing the temperature in the processing chamber from the first predetermined temperature to a second predetermined temperature and continuing to import the gas into the processing chamber, to maintain the processing chamber at the predetermined pressure; and performing a cooling and isobaric process on each semiconductor element, to suppress warpage of each semiconductor element. | 2022-08-04 |
20220246483 | SYSTEMS AND METHODS FOR SUCTION PAD ASSEMBLIES - In an embodiment, a system includes: a pad comprising a first side and a second side opposite the first side, wherein the first side is configured to receive a wafer during chemical mechanical planarization (CMP), and a platen adjacent the pad along the second side, wherein the platen comprises a suction opening that interfaces with the second side; a pump configured to produce suction at the suction opening to adhere the second side to the platen; and a sensor configured to collect sensor data characterizing a uniformity of adherence between the pad and the platen, wherein the pump is configured to produce the suction at the suction opening based on the sensor data. | 2022-08-04 |
20220246484 | STACKED SEMICONDUCTOR DEVICE WITH REMOVABLE PROBE PADS - Disclosed herein is a method that includes forming a contact plug to be embedded in a first insulating film formed on a semiconductor substrate; forming a probe pad on the first insulating film to contact with the contact plug; performing a test operation by probing the probe pad; removing the probe pad; forming a second insulating film to cover the contact plug after removing the probe pad; and forming a pad electrode to be embedded in the second insulating film. | 2022-08-04 |
20220246485 | SEMICONDUCTOR STRUCTURE - The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type. | 2022-08-04 |
20220246486 | SEMICONDUCTOR PACKAGE SYSTEM AND RELATED METHODS - Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate. | 2022-08-04 |
20220246487 | Through-Hole Mounted Semiconductor Assemblies - Through-hole mounted semiconductor assemblies are described. A printed circuit board (“PCB”) has first and second PCB sides and has a through hole therein. The through hole defines a hole area. A semiconductor package may be disposed in the hole area such that the semiconductor package is at least partially exposed on one or more of the first and the second PCB sides. Package contacts on the semiconductor package may be electrically coupled to PCB contacts disposed on one or more of the PCB sides. In some embodiments, one or more support structures may be coupled to the PCB and may touch the semiconductor package. In some embodiments, cooling devices may be placed in thermal communication with the semiconductor package on both sides of the PCB. | 2022-08-04 |
20220246488 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICE, AND ELECTRONIC COMPONENT DEVICE - Disclosed is a method for manufacturing an electronic component device, including: preparing a sealing structure including a sealing layer having two opposing main surfaces, an electronic component, and a connection portion, the connection portion being exposed on a circuit surface that is one main surface of the sealing layer; preparing a rewiring structure including a rewiring portion having two opposing main surfaces, and a plurality of bumps; and bonding the sealing structure and the rewiring structure in a direction that the circuit surface and the plurality of bumps face each other, with an insulating adhesive layer intervening, and thereby connecting the sealing structure and the rewiring structure. | 2022-08-04 |
20220246489 | SEMICONDUCTOR DEVICE PACKAGE WITH REDUCED STRESS - A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die. | 2022-08-04 |
20220246490 | Semiconductor Device and Method of Manufacture - Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant. | 2022-08-04 |
20220246491 | THERMAL CONDUCTIVE FILM - An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer. | 2022-08-04 |
20220246492 | POWER ELECTRONICS ASSEMBLIES HAVING VAPOR CHAMBERS WITH INTEGRATED PEDESTALS - A power electronics assembly includes a vapor chamber and a heat-generating device. The vapor chamber includes a housing defining an evaporator side and a condenser side and a pedestal integrally formed with an extending from the evaporator side, the pedestal comprising a non-rectangular shape corresponding to a thermal management objective. The heat-generating device is coupled to the pedestal. | 2022-08-04 |
20220246493 | WATER-COOLING DEVICE WITH COMPOSITE HEAT-DISSIPATING STRUCTURE - A water-cooling device with a composite heat-dissipating structure is provided, which includes a casing, a main heat-dissipating structure and a layered heat-dissipating structure. The casing is used for accommodating a working fluid, and the casing includes a heat-dissipating substrate. The main heat-dissipating structure includes a plurality of heat-dissipating fins arranged vertically and in parallel to each other that are connected to the heat-dissipating substrate. The layered heat-dissipating structure includes a plurality of horizontal heat-dissipating bodies arranged horizontally and in parallel to each other that are connected to the plurality of heat-dissipating fins arranged vertically and in parallel to each other, and a distance between the plurality of horizontal heat-dissipating bodies arranged horizontally and in parallel to each other is greater than or equal to a distance between the plurality of heat-dissipating fins arranged vertically and in parallel to each other. | 2022-08-04 |
20220246494 | SYSTEM FOR COOLING SEMICONDUCTOR COMPONENT, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SYSTEM - Provided is a system for cooling semiconductor components including: a cover body including at least one upper cover and lower cover, which are separated from each other, face each other, and are combined to form a coolant flow path in an inner space thereof; an inlet combined to one side of the cover body and used for a coolant to flow in; an outlet combined to the other side of the cover body and used for the coolant to be discharged; at least one connecting part pin inserted and arranged toward a flowing direction of the coolant in the inner space of the cover body; and insertion grooves formed for the connecting part pins to be inserted in the inner space of the cover body, wherein the upper cover or the lower cover of the cover body is combined to at least one of the upper surfaces or the lower surfaces of semiconductor components by using connecting members so that heat transmitted from the semiconductor components to the connecting part pins is efficiently radiated by enlarging an area contacting the coolant. | 2022-08-04 |
20220246495 | HEAT SINK AND SEMICONDUCTOR MODULE - A heat sink having a coolant flow path formed inside through which a coolant flows includes: a heat transfer plate having a first surface on which a semiconductor device is disposed and a second surface; a junction flow path-forming plate having a third surface and a fourth surface; a first partition wall provided in contact with the second surface and the third surface; and first fins provided in contact with the second surface. The coolant flow path includes a first flow path. A plurality of first divided regions separated by the at least one first partition wall are formed in the first flow path. The plurality of first fins are arranged by being spaced side by side in the first divided regions. | 2022-08-04 |
20220246496 | PACKAGE HAVING A SUBSTRATE COMPRISING SURFACE INTERCONNECTS ALIGNED WITH A SURFACE OF THE SUBSTRATE - A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. | 2022-08-04 |
20220246497 | STRUCTURES WITH THROUGH-SUBSTRATE VIAS AND METHODS FOR FORMING THE SAME - A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure. | 2022-08-04 |
20220246498 | SEMICONDUCTOR DEVICE - A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction. | 2022-08-04 |
20220246499 | LEAD FRAMES FOR SEMICONDUCTOR PACKAGES WITH INCREASED RELIABILITY AND RELATED SEMICONDUCTOR DEVICE PACKAGES AND METHODS - Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the die-attach pad, or of the lead fingers proximate to a geometric center of the lead frame may be rounded to exhibit a radius of curvature of at least two times a greatest thickness of the die-attach pad, the thickness measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and a largest of the lead fingers may be at least two times the greatest thickness of the die-attach pad. | 2022-08-04 |
20220246500 | FLEXIBLE ELECTRONIC STRUCTURE - There is provided a flexible electronic structure for bonding with an external circuit, comprising a flexible substrate, having a first surface, configured for bonding with the external circuit, and an opposing second surface, configured for engagement with a bonding tool, comprising at least one electronic component; at least one contact member, operatively coupled with said at least one electronic component and provided at said first surface of said flexible substrate, and adapted to operably interface with the external circuit after bonding, and at least one shield member, provided at said first surface so as to shieldingly overlap at least a portion of said at least one electronic component, adapted to withstand a predetermined pressure applied to said first surface and/or said opposing second surface during bonding with the external circuit. | 2022-08-04 |
20220246501 | PACKAGE STRUCTURE - A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four peripheral regions of the die pad, and each of the leads includes a main body, at least one extending portion and a plurality of plating surfaces. The extending portion is connected to the main body, and the main body and the extending portion are integrally formed. The plating surfaces are disposed on the main body and the extending portion. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. The main body and the extending portion of each of the leads protrude a peripheral region of the plastic package material. | 2022-08-04 |
20220246502 | PACKAGE STRUCTURE WITH PHOTONIC DIE AND METHOD - Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided. | 2022-08-04 |
20220246503 | EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES - Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability. | 2022-08-04 |
20220246504 | SEMICONDUCTOR DEVICE - The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip. | 2022-08-04 |
20220246505 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided, including four flat surfaces on four sides, and two sides include a full lead end height with electroless plating, and the other two sides comprise un-plated exposed Cu tie bar. The full lead end height with electroless plating is an ENIG plating or an ENEPIG plating. | 2022-08-04 |
20220246506 | PACKAGE MODULE - A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames. | 2022-08-04 |
20220246507 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction. The first/second terminals are connected to the first/second terminal portions, respectively. | 2022-08-04 |
20220246508 | BALL PAD DESIGN FOR SEMICONDUCTOR PACKAGES - A semiconductor structure includes a semiconductor die having an active surface, a passivation layer covering the active surface of the semiconductor die, and a post-passivation interconnect (PPI) layer disposed over the passivation layer. The PPI layer includes a ball pad having a first diameter. A polymer layer covers a perimeter of the ball pad. An under-bump-metallurgy (UBM) layer is disposed on the ball pad. The UBM layer has a second diameter that is greater than the first diameter of the ball pad. A solder ball is mounted on the UBM layer. | 2022-08-04 |
20220246509 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer. | 2022-08-04 |
20220246510 | OPEN WEB ELECTRICAL SUPPORT FOR CONTACT PAD AND METHOD OF MANUFACTURE - In some aspects, it is disclosed an electrical support for at least one electrical contact pad, including an insulating viscoelastic matrix, and at least one elastically deformable structure made of a conductive material to form an open web, the at least one structure including at least a core part which is embedded within the insulating matrix, and at least one connection part which extends out of the insulating matrix and is configured to be connected to the at least one electrical contact pad, wherein the structure includes a stiffer section corresponding substantially to the core part of the structure and at least one more flexible section corresponding substantially to the at least one connection part of the structure. | 2022-08-04 |
20220246511 | SEMICONDUCTOR PACKAGE AND MANUFACTURING PROCESS THEREOF - A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages. | 2022-08-04 |
20220246512 | THROUGH-HOLE ELECTRODE SUBSTRATE - A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface. | 2022-08-04 |
20220246513 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via. | 2022-08-04 |
20220246514 | CHIP SCALE PACKAGE - The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps. | 2022-08-04 |
20220246515 | INTERCONNECT SUBSTRATE AND METHOD OF MAKING THE SAME - An interconnect substrate includes an insulating layer, and an interconnect layer formed on a surface of the insulating layer, wherein the interconnect layer includes a plating layer, and an electrically conductive layer made of a sintered body comprised of an electrically conductive material. | 2022-08-04 |
20220246516 | SEMICONDUCTOR DEVICE AND SUBSTRATE - A semiconductor device according to an embodiment includes a substrate and a semiconductor chip. The semiconductor chip is provided over the substrate. The substrate includes a wire layer and an insulating layer. The wire layer includes a wire electrically connected to the semiconductor chip. The insulating layer is provided in contact with the wire layer and includes a glass woven fabric containing a resin. The glass woven fabric includes a plurality of glass fibers that are provided along two or more directions parallel with the glass woven fabric and are woven. The glass fibers differ in at least one of the material, number, and thickness depending on the directions parallel with the glass woven fabric. | 2022-08-04 |
20220246517 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE CONTAINING COMPOSITE CONTACT VIA STRUCTURES AND METHODS OF MAKING THE SAME - A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms. | 2022-08-04 |
20220246518 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a plurality of first conductive layers stacked apart from each other and including a plate-like shape extending in a first direction intersecting a stacking direction of the plurality of first conductive layers, one of both side surfaces extending in the first direction having larger surface roughness than the other; a plurality of channel bodies configured to penetrate the plurality of first conductive layers in the stacking direction, the plurality of channel bodies including semiconductors; and a memory film extending in the stacking direction between each of the plurality of channel bodies and the plurality of first conductive layers and including a charge accumulation film. | 2022-08-04 |
20220246519 | INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR STRUCTURE - The present disclosure provides an interconnection structure and a manufacturing method thereof and a semiconductor structure, and relates to the technical field of semiconductors. The interconnection structure includes a substrate, a dielectric layer arranged on the substrate and an insulation layer, wherein a plurality of wires are arranged in the dielectric layer at intervals; a recess is arranged in a portion, between adjacent wires, of the dielectric layer, and a bottom of the recess exposes a surface of the substrate; and the insulation layer includes an extension portion extending into the recess, and a gap is arranged between the extension portion and the substrate. | 2022-08-04 |
20220246520 | INTERCONNECTION STRUCTURE, CIRCUIT AND ELECTRONIC APPARATUS INCLUDING THE INTERCONNECTION STRUCTURE OR CIRCUIT - An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate. | 2022-08-04 |
20220246521 | PACKAGE COMPONENT, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes a functional circuit structure and a seal ring structure embedded in an insulating layer. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure, the seal ring structure includes a stack of alternating interconnect layers and via patterns, the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the insulating layer, and the first features are offset lengthwise relative to each other to overlap therewith, and the first features are spaced apart widthwise relative to each other. | 2022-08-04 |
20220246522 | Conductive Rail Structure for Semiconductor Devices - The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures. | 2022-08-04 |
20220246523 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a channel region of a transistor in a semiconductor fin, source and drain regions of the transistor on the semiconductor fin and at opposite sides of the channel region, a gate of the transistor over the channel region, and a first metal structure. The first metal structure is disposed over a first one of the source and drain regions. The first metal structure includes a first portion lower than a top surface of the gate, a second portion higher than the top surface of the gate, and a third portion over the second portion, wherein the second portion is narrower than the first portion, and the third portion is wider than the second portion. | 2022-08-04 |
20220246524 | PACKAGE HAVING DIFFERENT METAL DENSITIES IN DIFFERENT REGIONS AND MANUFACTURING METHOD THEREOF - A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region. | 2022-08-04 |
20220246525 | CONTACTS FOR TWISTED CONDUCTIVE LINES WITHIN MEMORY ARRAYS - Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines. | 2022-08-04 |
20220246526 | L-SHAPED STEPPED WORD LINE STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND THREE-DIMENSIONAL MEMORY - There is provided an L-shaped stepped word line structure, a method of manufacturing the same, and a three-dimensional memory. the word line structure includes: a plurality of L-shaped word line units, wherein each L-shaped word line unit includes a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction and including a word line terminal; wherein the word line terminal is formed in a stepped stacked layer structure including a plurality of stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region, the replacement metal region includes a short side region surface metal layer located on a surface and a short side region internal metal layer located in an interior, a length of the short side region surface metal layer in the first direction is greater than that of the short side region internal metal layer in the first direction, and the word line terminal corresponds to the short side region surface metal layer. It may be ensured that even if the etching is excessive in a case that the etching selection ratio is not high enough, a word line short circuit may not occur. | 2022-08-04 |
20220246527 | 3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases. | 2022-08-04 |
20220246528 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness. | 2022-08-04 |
20220246529 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate. | 2022-08-04 |
20220246530 | CHIP-ON-FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME - A chip on film (COF) package includes a base film having an upper surface and a lower surface opposite to each other, a bridge film having an edge that overlaps the base film, and an upper surface and a lower surface opposite to each other, a display driver integrated circuit (IC) mounted on the upper surface of the base film, and a heat dissipation member arranged in correspondence with the display driver IC on the lower surface of the base film. The upper surface of the base film and the lower surface of the bridge film adhere to each other in their respective long axis directions, and a long axis length of the bridge film is greater than a long axis length of the base film. | 2022-08-04 |
20220246531 | PACKAGE WITH A SUBSTRATE COMPRISING PERIPHERY INTERCONNECTS - A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects. | 2022-08-04 |
20220246532 | MULTI-STEP HIGH ASPECT RATIO VERTICAL INTERCONNECT AND METHOD OF MAKING THE SAME - A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 μm-20 μm. | 2022-08-04 |
20220246533 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure. | 2022-08-04 |
20220246534 | LOW-RESISTANCE COPPER INTERCONNECTS - Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiO | 2022-08-04 |
20220246535 | RUTHENIUM OXIDE FILM AND RUTHENIUM LINER FOR LOW-RESISTANCE COPPER INTERCONNECTS IN A DEVICE - Selective ruthenium and selective ruthenium oxide may be used in single damascene processes and/or dual damascene processes to form BEOL metallization layers and vias of an electronic device. A selective ruthenium liner may be formed to achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias. | 2022-08-04 |
20220246536 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the first memory region, the intermediate region and the second memory region. The panel is between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the first memory region, the second memory region and the intermediate region, and is directly adjacent the panel. The doped-semiconductor-material is at least part of conductive source structures within the first and second memory regions. Insulative rings surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies. | 2022-08-04 |
20220246537 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step. | 2022-08-04 |
20220246538 | CIRCUIT BOARD, SEMICONDUCTOR APPARATUS, AND ELECTRONIC EQUIPMENT - The present technology relates to a semiconductor apparatus and electronic equipment that are configured to make it possible to take measures more effectively against malfunctions arising from electromagnetic waves. A semiconductor apparatus includes a first base that transmits at least part of an electromagnetic wave, a first transistor group related to to-be-protected information, and an electromagnetic-wave attenuating unit that is provided in at least part of a region between the first base and the first transistor group and attenuates the electromagnetic wave. The present technology can be applied to a solid-state image pickup apparatus and the like, for example. | 2022-08-04 |