31st week of 2022 patent applcation highlights part 58 |
Patent application number | Title | Published |
20220246138 | LEARNING APPARATUS, SPEECH RECOGNITION APPARATUS, METHODS AND PROGRAMS FOR THE SAME - A learning device includes: a speech recognition portion configured to perform speech recognition processing on an acoustic feature value sequence O of an utterance unit using a recognition parameter λ | 2022-08-04 |
20220246139 | DISPLAY-BASED CONTEXTUAL NATURAL LANGUAGE PROCESSING - Multi-modal natural language processing systems are provided. Some systems are context-aware systems that use multi-modal data to improve the accuracy of natural language understanding as it is applied to spoken language input. Machine learning architectures are provided that jointly model spoken language input (“utterances”) and information displayed on a visual display (“on-screen information”). Such machine learning architectures can improve upon, and solve problems inherent in, existing spoken language understanding systems that operate in multi-modal contexts. | 2022-08-04 |
20220246140 | DYNAMIC AND/OR CONTEXT-SPECIFIC HOT WORDS TO INVOKE AUTOMATED ASSISTANT - Techniques are described herein for enabling the use of “dynamic” or “context-specific” hot words to invoke an automated assistant. In various implementations, an automated assistant may be executed in a default listening state at least in part on a user's computing device(s). While in the default listening state, audio data captured by microphone(s) may be monitored for default hot words. Detection of the default hot word(s) transitions of the automated assistant into a speech recognition state. Sensor signal(s) generated by hardware sensor(s) integral with the computing device(s) may be detected and analyzed to determine an attribute of the user. Based on the analysis, the automated assistant may transition into an enhanced listening state in which the audio data may be monitored for enhanced hot word(s). Detection of enhanced hot word(s) triggers the automated assistant to perform a responsive action without requiring detection of default hot word(s). | 2022-08-04 |
20220246141 | ENHANCED SPOKEN LANGUAGE UNDERSTANDING USING JOINT MODEL TRAINING - Systems and methods for improved Spoken Language Understanding (“SLU”) are provided. The methods may comprise receiving an utterance from a user, contextualizing a plurality of words in the utterance, providing the contextualized words to the slot detector to determine the probability of a word forming the beginning or end of a slot to determine slots and nested slots, an intent classifier to determine the probability of a word conveying a user intent, and a slot classifier that applies specific labels to each slot and nest slot. The SLU method may employ a model and jointly trains the model for each task (determining beginning and end of slots, intents, and slot classifications) using a combined loss function. | 2022-08-04 |
20220246142 | CONVERSATION ANALYSIS SYSTEM - [Problem] To provide a system capable of correcting an error in speech recognition by easier work than in the prior art. [Solution] A conversation analysis system comprising: a speech analysis unit | 2022-08-04 |
20220246143 | SYSTEM AND METHOD FOR MULTI-SPOKEN LANGUAGE DETECTION - A method includes performing, using at least one processor, feature extraction of input audio data to identify extracted features associated with the input audio data. The method also includes detecting, using the at least one processor, a language associated with the input audio data by processing the extracted features using a plurality of language models, where each language model is associated with a different language. The method further includes directing, using the at least one processor, the input audio data to one of a plurality of automatic speech recognition (ASR) models based on the language associated with the input audio data. | 2022-08-04 |
20220246144 | INTENT DISAMBIGUATION WITHIN A VIRTUAL AGENT PLATFORM - The present disclosure is directed techniques for executing a task or service using a virtual agent. A method includes: executing, using a virtual agent, one or more tiers of a plurality of tiers of machine learning analysis to identify a desired action to be performed based on a user command, the user command being received from an external computing device; responsive to the one or more tiers of the plurality of tiers of machine learning analysis identifying a plurality of actions associated with the user command, determining a series of inquiries to present via the external computing device, wherein each inquiry of the series of inquiries is selected based on a number of actions associated with each inquiry, and wherein each subsequent inquiry in the series of inquires is based on a user response to a preceding inquiry; identifying, based on responses to the series of inquiries, the desired action to be performed; and executing the desired action to be performed | 2022-08-04 |
20220246145 | SYSTEMS AND METHODS FOR SUGGESTING USER ACTIONS DURING A VIDEO CONFERENCE - One example method includes receiving, by a computing device, audio during a video conference having a plurality of participants, the audio comprising spoken words by a user of the computing device; recognizing one or more words from the spoken words; identifying one or more keywords within the one or more recognized words; accessing a set of rules comprising one or more rules, each rule of the one or more rules associated with an application of a set of applications, and at least one rule of the one or more rules associated with a functionality of a respective application; determining a context associated with the one or more keywords; determining an application to execute based on the one or more keywords, the context, and the one or more rules, wherein determining the application comprises determining a functionality of the application to invoke; and in response to receiving user confirmation of the functionality of the application to invoke, executing the application and invoking the functionality. | 2022-08-04 |
20220246146 | DETERMINATION OF TASK URGENCY BASED ON ACOUSTIC FEATURES OF AUDIO DATA - Systems and methods are provided for determining importance and urgency of a task based on acoustic features of audio input associated with the task. The determining includes classifying the task into one or more classes associated with importance, urgency, and priority of the task. The classification may use a trained machine learning model of acoustic features and embedding for a neural network. The task classifier uses feature acoustics of either or both the foreground and background audio. The feature acoustics include a pitch, a tone, and a volume over a time duration of the audio input. A combination of the acoustic features determines a class associated with the task. The machine learning model includes a regression model of acoustic features over time and a model with embedding for a neural network. | 2022-08-04 |
20220246147 | SYSTEMS AND METHODS FOR AUTOMATING VOICE COMMANDS - A method of detecting establishment of a voice communication between a first voice communication equipment and a second voice communication equipment and automating requests for content. The method includes analyzing the voice communication to identify a request for content, analyzing the voice communication to identify an affirmative response to the request for content, and correlating the request for content with a first user account and correlating the affirmative response with a second user account. In response to identifying the affirmative response and based upon at least one of the first user account or the second user account, identifying from a data storage, the requested content and causing the transmission of the requested content. | 2022-08-04 |
20220246148 | VOICE ACTIVATED LABORATORY ENVIRONMENTS - A method, system and apparatus for implementation and use of voice activated laboratory environments (VALET) are disclosed. According to one aspect, a VALET controls a first instrument in a first location, and has, in acoustic proximity to the first location, an audio interface configured to receive voice commands, to enunciate responses to the voice commands, and to transmit a first signal responsive to a first voice command to an intermediary location. The VALET also includes a computer configured to receive a computer instruction from the intermediary location, the computer instruction configuring the computer to select and issue an instrument command to cause the first instrument to effectuate the voice command. | 2022-08-04 |
20220246149 | PROACTIVE COMMAND FRAMEWORK - Techniques for determining a command or intent likely to be subsequently invoked by a user of a system are described. A user inputs a command (either via a spoken utterance or textual input) to a system. The system determines content responsive to the command. The system also determines a second command or corresponding intent likely to be invoked by the user subsequent to the previous command. Such determination may involve analyzing pairs of intents, with each pair being associated with a probability that one intent of the pair will be invoked by a user subsequent to a second intent of the pair. The system then outputs first content responsive to the first command and second content soliciting the user as to whether the system to execute the second command. | 2022-08-04 |
20220246150 | SYSTEM AND/OR METHOD FOR SEMANTIC PARSING OF AIR TRAFFIC CONTROL AUDIO - The method S | 2022-08-04 |
20220246151 | METHODS, SYSTEMS, AND MEDIA FOR CONNECTING AN IoT DEVICE TO A CALL - Methods, systems, and media for connecting an IoT device to a call are provided. In some embodiments, a method is provided, the method comprising: establishing, at a first end-point device, a telecommunication channel with a second end-point device; subsequent to establishing the telecommunication channel, and prior to a termination of the telecommunication channel, detecting, using the first end-point device, a voice command that includes a keyword; and in response to detecting the voice command, causing information associated with an IoT device that corresponds to the keyword to be transmitted to the second end-point device. | 2022-08-04 |
20220246152 | DIRECTING A VEHICLE CLIENT DEVICE TO USE ON-DEVICE FUNCTIONALITY - Implementations set forth herein relate to phasing-out of vehicle computing device versions while ensuring useful responsiveness of any vehicle computing device versions that are still in operation. Certain features of updated computing devices may not be available to prior versions of computing devices because of hardware limitations. The implementations set forth herein eliminate crashes and wasteful data transmissions caused by prior versions of computing devices that have not been, or cannot be, upgraded. A server device can be responsive to a particular intent request provided to a vehicle computing device, despite the intent request being associated with an action that a particular version of the vehicle computing device cannot execute. In response, the server device can elect to provide speech to text data, and/or natural language understanding data, in furtherance of allowing the vehicle computing device to continue leveraging resources at the server device. | 2022-08-04 |
20220246153 | SYSTEM AND METHOD FOR DETECTING FRAUDSTERS - A system and method may classify a plurality of interactions, by: obtaining a plurality of voiceprints of the plurality of interactions, wherein each voiceprint of the plurality of voiceprints represents a speaker participating in an interaction of the plurality of interactions; calculating, for each interaction, a plurality of scores, wherein each score of the plurality of scores is indicative of a similarity between the voiceprint of the interaction and one voiceprint of a set of benchmark voiceprints; calculating, for each interaction, statistics of the scores; and determining that a plurality of interactions pertain to a single cluster of interactions based on statistics of the scores of the interactions in the cluster. | 2022-08-04 |
20220246154 | PROVIDING ACCESS WITH A PORTABLE DEVICE AND VOICE COMMANDS - A system comprising a transponder having a user interface to receive commands from a user and to operate a virtual assistant. A micro-computer in an automobile, which is responsive to the transponder, and wherein the transponder and the micro-computer configured to have conversations. These include conversations regarding the automobile, and between a user of the transponder and the virtual assistant utilized by the transponder. The conversations are recorded and recallable at a later time, wherein the virtual assistant responds to future commands or questions from the user based on prior commands or questions from the user. | 2022-08-04 |
20220246155 | SELECTABLE LINEAR PREDICTIVE OR TRANSFORM CODING MODES WITH ADVANCED STEREO CODING - Methods and systems for advanced stereo processing of an audio signal are disclosed. The methods and systems include selecting a coding mode of either transform coding or linear predictive coding and performing advanced stereo processing when in the selected coding mode. Both encoding and decoding operations are provided. | 2022-08-04 |
20220246156 | TIME REVERSED AUDIO SUBFRAME ERROR CONCEALMENT - A method and a decoder device of generating a concealment audio subframe of an audio signal are provided. The method comprises generating frequency spectra on a subframe basis where consecutive subframes of the audio signal have a property that an applied window shape of first subframe of the consecutive subframes is a mirrored version or a time reversed version of a second subframe of the consecutive subframes. Peaks of a signal spectrum of a previously received audio signal are detected for a concealment subframe, and a phase of each of the peaks is estimated. A time reversed phase adjustment is derived based on the estimated phase and applied to the peaks of the signal spectrum to form time reversed phase adjusted peaks. | 2022-08-04 |
20220246157 | SOUND SIGNAL RECEIVING AND DECODING METHOD, SOUND SIGNAL DECODING METHOD, SOUND SIGNAL RECEIVING SIDE APPARATUS, DECODING APPARATUS, PROGRAM AND STORAGE MEDIUM - Provided is a technique according to which it is possible to obtain a decoded sound signal of high sound quality without significantly increasing the delay time compared to a configuration in which only a decoded sound signal of the minimum necessary sound quality is obtained. In a terminal apparatus connected to a first communication line and a second communication line with a lower priority level there than, sound signals of multiple channels are obtained and output based on a monaural code included in a first code string input from the first communication line and an extended code included in a second code string with the closest frame number to that of the monaural code among extended codes included in the second code string input from the second communication line. | 2022-08-04 |
20220246158 | APPARATUS AND METHOD FOR PROCESSING AUDIO - An audio processing apparatus may obtain second audio signals corresponding to channels included in a second channel group from first audio signals corresponding to channels included in a first channel group, downsample at least one third audio signal corresponding to at least one channel identified based on a correlation with the second channel group from among the channels included in the first channel group, by using an artificial intelligence (AI) model, and generate a bitstream including the second audio signals corresponding to the channels included in the second channel group and the downsampled at least one third audio signal. The first channel group includes a channel group of an original audio signal, and the second channel group is constructed by combining at least two channels from among the channels included in the first channel group. | 2022-08-04 |
20220246159 | BANDWIDTH EXTENSION METHOD, BANDWIDTH EXTENSION APPARATUS, PROGRAM, INTEGRATED CIRCUIT, AND AUDIO DECODING APPARATUS - To provide a bandwidth extension method which allows reduction of computation amount in bandwidth extension and suppression of deterioration of quality in the bandwidth to be extended. In the bandwidth extension method: a low frequency bandwidth signal is transformed into a QMF domain to generate a first low frequency QMF spectrum; pitch-shifted signals are generated by applying different shifting factors on the low frequency bandwidth signal; a high frequency QMF spectrum is generated by time-stretching the pitch-shifted signals in the QMF domain; the high frequency QMF spectrum is modified; and the modified high frequency QMF spectrum is combined with the first low frequency QMF spectrum. | 2022-08-04 |
20220246160 | PSYCHOACOUSTIC ENHANCEMENT BASED ON AUDIO SOURCE DIRECTIVITY - A device includes a memory configured to store directivity data of one or more audio sources corresponding to one or more input audio signals. The device also includes one or more processors configured to determine one or more equalizer settings based at least in part on the directivity data. The one or more processors are also configured to generate, based on the equalizer settings, one or more output audio signals that correspond to a psychoacoustic enhanced version of the one or more input audio signals. | 2022-08-04 |
20220246161 | SOUND MODIFICATION BASED ON FREQUENCY COMPOSITION - In various embodiments, a sound modification application selectively modifies one or more sounds included in one or more audio signals. In operation, the sound modification application determines classifications associated with multiple sounds included in one or more audio signals. The sound modification application selects a first frequency sub-band of a first sound included in the multiple sounds based on a first classification associated with the first sound. The sound modification application then modifies the first frequency sub-band of the first sound, without modifying at least a second frequency sub-band of the first sound, to generate a modified audio signal. | 2022-08-04 |
20220246162 | CALL AUDIO MIXING PROCESSING - A call audio mixing processing method is provided. In the method, call audio streams from terminals of call members participating in a call are obtained. Voice analysis is performed on the call audio streams to determine voice activity corresponding to each of the terminals. The voice activity of the terminals indicate activity levels of the call members participating in the call. According to the voice activity of the terminals, respective voice adjustment parameters corresponding to the terminals are determined. According to the respective voice adjustment parameters corresponding to the terminals, the call audio streams of the terminals are adjusted. Further, mixing processing is performed on the adjusted call audio streams to obtain a mixed audio stream. | 2022-08-04 |
20220246163 | TECHNOLOGIES FOR SYNCRONIZING RENDERING OF MULTI-CHANNEL AUDIO - Technologies are disclosed for synchronously rendering audio content by a plurality of network connected speakers. In various embodiments, a media control device may receive media content comprising an audio component, the device may derive and transmit instructions for buffering and rendering the audio component to a plurality of speakers, wherein the instructions include instructions for synchronizing a rendering clock comprised within each of the more than one speakers. The device may transmit the audio component to the more than one speaker of the plurality of speakers; while monitoring status information transmitted by the plurality of speakers; and maintain or restore synchronous rendering of the audio component by the plurality of speakers in response to the status information received from the speakers. | 2022-08-04 |
20220246164 | SYSTEMS AND METHODS FOR IMPROVING FUNCTIONAL HEARING - Embodiments of the present disclosure are directed to systems and methods for improving functional hearing. In one aspect, the system may include a housing configured to fit within an ear of a user. The housing may include a speaker, an amplifier, a transmitter, and a power supply. Additionally, the housing may include a memory storing instructions and at least one processor configured to execute instructions. The instructions may include receiving an audio input and amplifying the audio input. The instructions may include outputting the amplified audio input from a speaker. The instructions may include converting the audio input into a visual representation of the audio input and transmitting the visual representation to at least one display. | 2022-08-04 |
20220246165 | ABNORMALITY ESTIMATION DEVICE, ABNORMALITY ESTIMATION METHOD, AND PROGRAM - Provided is an abnormality estimation device capable of appropriately determining normal data appearing less frequently as normal. The abnormality estimation device includes an estimation unit that estimates an anomaly degree of an acoustic signal, by using an abnormality estimation model that is optimized while using a set of normal sounds and is optimized so as to minimize a difference between an anomaly degree of a normal sound appearing more frequently and an anomaly degree of a normal sound appearing less frequently. | 2022-08-04 |
20220246166 | Audio Playout Report for Ride-Sharing Session - In one aspect, an example method to be performed by a computing device includes (a) determining that a ride-sharing session is active; (b) in response to determining the ride-sharing session is active, using a microphone of the computing device to capture audio content; (c) identifying reference audio content that has at least a threshold extent of similarity with the captured audio content; (d) determining that the ride-sharing session is inactive; and (e) outputting an indication of the identified reference audio content. | 2022-08-04 |
20220246167 | SPEAKER ADAPTIVE END OF SPEECH DETECTION FOR CONVERSATIONAL AI APPLICATIONS - In various examples, end of speech (EOS) for an audio signal is determined based at least in part on a rate of speech for a speaker. For a segment of the audio signal, EOS is indicated based at least in part on an EOS threshold determined based at least in part on the rate of speech for the speaker. | 2022-08-04 |
20220246168 | TECHNIQUES FOR DETECTING AND PROCESSING DOMAIN-SPECIFIC TERMINOLOGY - Various embodiments set forth systems and techniques for explaining domain-specific terms detected in a media content stream. The techniques include detecting a speech portion included in an audio signal; determining that the speech portion comprises a domain-specific term; determining an explanatory phrase associated with the domain-specific term; and integrating the explanatory phrase associated with the domain-specific term into playback of the audio signal. | 2022-08-04 |
20220246169 | Method For Robust Directed Source Separation - An apparatus includes an interface for microphones, a separated source processor configured to analyze channels from the microphones, and a voice activity detector (VAD) circuit. The VAD circuit is configured to generate a voice estimate (VE) value. The VE value is to indicate a likelihood of human speech received by the microphones. Generating the VE value includes adjusting the VE value based upon a delay between two of the microphones. The VAD circuit is configured to provide the VE value to the separated source processor. | 2022-08-04 |
20220246170 | METHOD AND APPARATUS FOR DETECTING VALID VOICE SIGNAL AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM - A method and apparatus for detecting a valid voice signal and a non-transitory computer readable storage medium are provided. A first audio signal including at least one audio frame signal is obtained. Multiple wavelet decomposition signals respectively corresponding to the at least one audio frame signal are obtained. A wavelet signal sequence is obtained by combining the multiple wavelet decomposition signals. A maximum value and a minimum value among audio intensity values of all sample points are obtained, and a first audio intensity threshold is determined according to the maximum value and the minimum value. Sample points each having an audio intensity value greater than the first audio intensity threshold in the wavelet signal sequence are obtained, and a signal of sample points in the first audio signal corresponding to the sample points each having an audio intensity value greater than the first audio intensity threshold is determined as the valid voice signal. | 2022-08-04 |
20220246171 | MAGNETORESISTIVE ASYMMETRY COMPENSATION - Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains. | 2022-08-04 |
20220246172 | SPLIT-ACTUATOR DRIVE THAT COORDINATES TIMING OF AGGRESSOR AND VICTIM FOR EFFECTIVE VICTIM DISTURBANCE-FEEDFORWARD - A victim feedforward signal is added to a microactuator control signal of the victim actuator in response to a voice-coil motor (VCM) control signal that is applied to the aggressor actuator, where the victim feedforward signal is configured to compensate for disturbances to a victim head caused by assertion of the aggressor VCM control signal. Each aggressor VCM control signal is asserted at a specific time by the aggressor actuator, for example in response to the aggressor head passing over a first servo wedge. A feedforward signal that compensates for the effect of the aggressor VCM control signal is then determined based on the aggressor VCM control signal, stored, and asserted via the victim microactuator at a predetermined time relative to when the aggressor VCM control signal is asserted. | 2022-08-04 |
20220246173 | DATA STORAGE DEVICE WITH HISTORY DEPENDENT WRITE BOOST - A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of tracks. A first pattern of magnetic transitions is written to a first segment of a first track. Preparation is made to write a second pattern of magnetic transitions to a second segment of a second track adjacent the first segment of the first track. When the second pattern matches the first pattern, a write boost is configured to a first setting, and when the second pattern does not match the first pattern, the write boost is configured to a second setting. The second pattern of magnetic transitions is then written to the second segment of the second track using the configured write boost. | 2022-08-04 |
20220246174 | MAGNETIC DISK DEVICE - A magnetic disk device includes a plurality of magnetic disks, a plurality of sliders each including one or more resistive elements, each of which is arranged to face a recording surface of one of the plurality of magnetic disks, and is provided corresponding to the plurality of magnetic disks, and a processor configured to detect a change in a resistance value of one or more of the plurality resistive elements. | 2022-08-04 |
20220246175 | MAGNETIC DISK DEVICE AND CONTACT DETECTING METHOD OF THE MAGNETIC DISK DEVICE - According to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head including a read head, a write head, a heater and the magnetic head, and a sensor and the control section. The control section when applying electric power to the heater, the control section predicts, on the basis of a relationship between a value of the electric power to be applied to the heater and an output value of a spectrum at a pulse frequency of a DC output of the sensor in a state where pulsed electric power is applied to the heater, the output value of the spectrum, and detects contact between the magnetic head and the magnetic disk before the predicted output value of the spectrum becomes less than or equal to a threshold. | 2022-08-04 |
20220246176 | MAGNETIC RECORDING MEDIUM, MAGNETIC RECORDING AND REPRODUCING APPARATUS, AND METHOD OF MANUFACTURING MAGNETIC RECORDING MEDIUM - A magnetic recording medium including: a non-magnetic substrate; an underlayer; a perpendicular magnetic layer; a diffusion preventing layer; and a protective layer, wherein the underlayer, the perpendicular magnetic layer, the diffusion preventing layer, and the protective layer are layered on the non-magnetic substrate in this order, the perpendicular magnetic layer has a multi-layer structure, the perpendicular magnetic layer includes an uppermost layer and at least one layer other than the uppermost layer, the uppermost layer including Co or Fe in magnetic particles, and the at least one layer other than the uppermost layer including an oxide, the diffusion preventing layer is provided between the perpendicular magnetic layer and the protective layer, and the diffusion preventing layer includes at least one component selected from a group consisting of Si, Ti, Cr, B, and Ru, or either a carbide, an oxide, or both, of the at least one component. | 2022-08-04 |
20220246177 | MULTI-SPEED HARD DISK DRIVE - A hard disk drive includes a base deck, a motor coupled to the base deck, a magnetic recording medium coupled to the motor and having a first zone and a second zone, and a controller. The controller is programmed to cause the motor to rotate at either a first speed or a second speed when data is to be read from the first zone and to cause the motor to rotate at the first speed when data is to be written to the first zone and the second zone. | 2022-08-04 |
20220246178 | System and Method for Performing a Rewind Operation with a Mobile Image Capture Device - A mobile image capture device is provided that can include an image capture system operable to capture image frames and be configured to: provide a live video stream for display in a viewfinder portion of a user interface that depicts at least a portion of a current field of view of the image capture system; store a video segment from the live video stream in a temporary image buffer that includes a plurality of image frames captured by the image capture system; receive a user input that is directed to the viewfinder portion of the user interface that requests a rewind operation; and, in response to such user input, perform the rewind operation in the viewfinder portion of the user interface with respect to the video segment in which at least two of the image frames of the video segment can be provided for display in the user interface in a reverse chronological order. | 2022-08-04 |
20220246179 | TIMECODE GENERATION AND ASSIGNMENT - A timecoding technique for determining and assigning timecodes for variable frame rate video. Content identified for timecode assignment is decoded, and for sequential frames of the content, portions of timestamps are compared to determine if the frames are from a same time period (e.g., from the same second in time). For a subsequent frame from the same time period, an index is atomically incremented, a timecode generated from a combination of the time period and the index, and the timecode assigned to the frame. For a subsequent frame from a different time period, the index is initialized, a timecode generated from a combination of the different time period and the initialized index, and the timecode assigned to the frame. Accumulated durations of frames may be used in place of timestamps, in some instances. | 2022-08-04 |
20220246180 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other. | 2022-08-04 |
20220246181 | METHOD AND APPARATUS FOR ACCESSING TO DATA IN RESPONSE TO POWER-SUPPLY EVENT - The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0 | 2022-08-04 |
20220246182 | CONTROL CIRCUIT OF MEMORY DEVICE - A circuit includes a first inverter, a second inverter, a first header circuit and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal transmitted to a complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal transmitted to a bit line. The first header circuit connects or disconnects a power terminal of the first inverter with a positive reference voltage supply in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power terminal of the second inverter with the positive reference voltage supply in response to a write enable signal and the first global write signal. | 2022-08-04 |
20220246183 | TECHNIQUES FOR PERFORMING COMMAND ADDRESS INTERFACE TRAINING ON A DYNAMIC RANDOM-ACCESS MEMORY - Various embodiments include a memory device that is capable of performing command address interface training operations, to determine that certain timing conditions are met, with fewer I/O pins relative to prior approaches. Prior approaches for command address interface training involve loading data via a set of input pins, a clock signal, and a clock enable signal that identifies when the input pins should be sampled. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern continuously being transmitted to the memory device by an external memory controller. The memory device compares the generated data pattern with the received data pattern and transmits the result of the comparison on one or more data output pins. The memory controller receives and analyzes the result of the comparison to determine whether the command address interface training passed or failed. | 2022-08-04 |
20220246184 | TECHNIQUES FOR PERFORMING WRITE TRAINING ON A DYNAMIC RANDOM-ACCESS MEMORY - Various embodiments include a memory device that is capable of performing write training operations, to determine that certain timing conditions are met, without storing data patterns in memory. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern being transmitted to the memory device by an external memory controller. If the data pattern generated by the memory device matches the data pattern received from the memory controller, then the memory device stores a pass status in a register. The data patterns do not match, then the memory device stores a pass status in a register. The memory controller reads the register to determine whether the write training passed or failed. | 2022-08-04 |
20220246185 | SEMICONDUCTOR DEVICE - Provision of a novel semiconductor device. The semiconductor device includes a first control circuit including a first transistor using a silicon substrate for a channel; a second control circuit provided over the first control circuit, which includes a second transistor using a metal oxide for a channel; a memory circuit provided over the second control circuit, which includes a third transistor using a metal oxide for a channel; and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal. In a first period for reading data from the memory circuit to the first control circuit, the second control circuit controls whether the global bit line and the inverted global bit line from which electric charge is discharged are charged or not in accordance with the data read from the memory circuit. | 2022-08-04 |
20220246186 | INDICATION IN MEMORY SYSTEM OR SUB-SYSTEM OF LATENCY ASSOCIATED WITH PERFORMING AN ACCESS COMMAND - Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay. | 2022-08-04 |
20220246187 | MEMORY CONTROLLER AND METHOD OF CONTROLLING THE MEMORY CONTROLLER - A memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access. | 2022-08-04 |
20220246188 | MEMORY CLOCK MANAGEMENT AND ESTIMATION PROCEDURES - Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles. | 2022-08-04 |
20220246189 | MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE AND OPERATION METHOD OF MEMORY CIRCUIT - A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state. | 2022-08-04 |
20220246190 | GIANT SPIN HALL-BASED COMPACT NEUROMORPHIC CELL OPTIMIZED FOR DIFFERENTIAL READ INFERENCE - A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals. | 2022-08-04 |
20220246191 | REFRESH CIRCUIT AND MEMORY - Embodiments of the present application provide a refresh circuit and a memory. The refresh circuit includes: a refresh control module configured to receive and execute a refresh command to output a row address refresh signal; and further configured to receive a process corner signal to adjust an execution proportion of the refresh command, the faster a process corner represented by the process corner signal, the higher the adjusted execution proportion; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. The embodiments of the present application help reduce the consumption of refresh currents. | 2022-08-04 |
20220246192 | DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUIT - The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period. | 2022-08-04 |
20220246193 | Reference-Voltage-Generators Within Integrated Assemblies - Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another. | 2022-08-04 |
20220246194 | FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS - A flash memory storage apparatus includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line and including memory cells; each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array and configured to output a bias voltage to the word line. A first voltage is applied to a selected word line. A second voltage and a third voltage are applied to unselected second and third word lines, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the first word line. A biasing method of a flash memory storage apparatus is also provided. | 2022-08-04 |
20220246195 | MEMORY DEVICE AND OPERATION METHOD FOR THE SAME - A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not. | 2022-08-04 |
20220246196 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line. | 2022-08-04 |
20220246197 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node. | 2022-08-04 |
20220246198 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more. | 2022-08-04 |
20220246199 | DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE - The present invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word line coupled to a gate terminal of the access transistor. During the period between the word line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM. | 2022-08-04 |
20220246200 | MEMORY DEVICE SKIPPING REFRESH OPERATION AND OPERATION METHOD THEREOF - Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row | 2022-08-04 |
20220246201 | MEMORY DEVICE, MEMORY SYSTEM AND OPERATING METHOD - A method of operating a memory device includes; receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller for an adjacent row, relative to the target row, during a refresh operation period defining a refresh operation performed by the memory device. | 2022-08-04 |
20220246202 | PERFORMING REFRESH OPERATIONS ON MEMORY CELLS - The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells. | 2022-08-04 |
20220246203 | REFRESH CIRCUIT AND MEMORY - A refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. | 2022-08-04 |
20220246204 | ELECTRONIC DEVICE FOR CONFIGURING NEURAL NETWORK - Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line. | 2022-08-04 |
20220246205 | Memory Device Comprising An Electrically Floating Body Transistor - A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region. | 2022-08-04 |
20220246206 | Circuitry Apportioning of an Integrated Circuit - According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier. | 2022-08-04 |
20220246207 | ERROR AVOIDANCE BASED ON VOLTAGE DISTRIBUTION PARAMETERS - A method can include receiving a request to read data from a memory cell of a memory device coupled with the processing device, determining a voltage distribution parameter value associated with the memory cell, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, and reading, using the determined set of read levels, data from the memory cell. The voltage distribution parameter value can be determined by identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels, and determining the voltage distribution parameter value based on the particular voltage distribution. The voltage distribution parameter value can be a voltage value that is included in the particular voltage distribution. | 2022-08-04 |
20220246208 | DYNAMIC SENSE NODE VOLTAGE TO COMPENSATE FOR VARIANCES WHEN SENSING THRESHOLD VOLTAGES OF MEMORY CELLS - Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors. | 2022-08-04 |
20220246209 | SYSTEMS AND METHODS FOR MEMORY CELL ACCESSES - A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements. | 2022-08-04 |
20220246210 | THREE-STATE PROGRAMMING OF MEMORY CELLS - The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back. | 2022-08-04 |
20220246211 | DEVICE COMPRISING A NON-VOLATILE MEMORY CIRCUIT - The present description concerns a memory device ( | 2022-08-04 |
20220246212 | MEMORY DEVICE AND OPERATION METHOD THEREOF - A memory device and an operation method thereof are provided. The operation method comprises: in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of first signal lines; outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells; summing the cell currents on each of the second signal lines into a plurality of signal line currents: summing the signal line currents into a global signal line current: and converting the global signal line current into an output, wherein the output represents a MAC operation result of the inputs and the weights. | 2022-08-04 |
20220246213 | Memory Device - According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode. | 2022-08-04 |
20220246214 | One-Ladder Read of Memory Cells Coarsely Programmed via Interleaved Two-Pass Data Programming Techniques - A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell. | 2022-08-04 |
20220246215 | MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS - Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing. | 2022-08-04 |
20220246216 | NONVOLATILE MEMORY DEVICE FOR INCREASING RELIABILITY OF DATA DETECTED THROUGH PAGE BUFFER - A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer. | 2022-08-04 |
20220246217 | SEMICONDUCTOR APPARATUS AND CONTINUOUS READOUT METHOD - A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal. | 2022-08-04 |
20220246218 | FLASH MEMORY AND FLASH MEMORY CELL THEREOF - A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line. | 2022-08-04 |
20220246219 | SEQUENTIAL VOLTAGE CONTROL FOR A MEMORY DEVICE - Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages. | 2022-08-04 |
20220246220 | OPERATIONAL MODES FOR REDUCED POWER CONSUMPTION IN A MEMORY SYSTEM - Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor. | 2022-08-04 |
20220246221 | EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES - Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage. | 2022-08-04 |
20220246222 | DESTRUCTION OF DATA AND VERIFICATION OF DATA DESTRUCTION ON A MEMORY DEVICE - A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed. | 2022-08-04 |
20220246223 | NON-VOLATILE STORAGE DEVICE - A non-volatile storage device includes a memory that stores data in a non-volatile manner, a power supply that generates an internal voltage to feed it to the memory, a controller that controls the memory and the power supply, an A/D converter that performs A/D conversion on the internal voltage, and a fault detector that detects a fault related to data written in the memory based on the output of the A/D converter. | 2022-08-04 |
20220246224 | ARCHITECTURE AND METHOD FOR NAND MEMORY PROGRAMMING - A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data. | 2022-08-04 |
20220246225 | ONE-TIME PROGRAMMABLE MEMORY BIT CELL - A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line. | 2022-08-04 |
20220246226 | POWER CIRCUIT, ELECTRONIC FUSE CIRCUIT, AND METHOD FOR PROVIDING POWER TO ELECTRONIC FUSE CIRCUIT - A power circuit is adapted for providing a programming voltage to an electronic fuse circuit, and includes a pass transistor of a P-type metal-oxide-semiconductor transistor, a buffer circuit, and a bulk voltage control circuit. The pass transistor includes a bulk electrode, a gate electrode, a first source/drain electrode receiving a system high voltage, and a second source/drain electrode connected to a bit line. The buffer circuit provides a control voltage to the gate electrode of the pass transistor. The pass transistor is turned on during a programming operation and turned off during a reading operation. The bulk voltage control circuit independently provides a bulk voltage to the bulk electrode. A last-stage buffer of the buffer circuit is also activated by the bulk voltage to control the pass transistor during the reading operation of the electronic fuse circuit. A method for providing power to an electronic fuse circuit is also provided. | 2022-08-04 |
20220246227 | TEST CIRCUIT USING CLOCK SIGNALS HAVING MUTUALLY DIFFERENT FREQUENCY - Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit. | 2022-08-04 |
20220246228 | SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD OF THE SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN SUPPORT SYSTEM OF THE SEMICONDUCTOR INTEGRATED CIRCUIT, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - According to a certain embodiment, the semiconductor integrated circuit includes a plurality of memories and a first control circuit configured to control the plurality of memories. The first control circuit includes a first state transition circuit configured to execute at least one of write control and read control during an operation of the plurality of memories; and a second state transition circuit connected to the first state transition circuit, the second state transition circuit capable of causing the first state transition circuit to sequentially execute tests of the plurality of memories. | 2022-08-04 |
20220246229 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device which can perform various memory tests without increasing a size of the memory device. The memory device includes: a first pad for receiving external ROM data from a memory controller; a second pad for receiving an external clock signal corresponding to the external ROM data from the memory controller; and a control logic connected to the first pad and the second pad and configured to perform an operation corresponding to the external ROM data in response to the external clock signal in a test mode. | 2022-08-04 |
20220246230 | MEMORY SYSTEM - A memory system includes a memory device and a controller. The controller is coupled to the memory device through input/output (I/O) lines. The controller includes an interface component and a dummy power consumption component. The interface component performs a signal training operation for adjusting a timing of a clock signal, to which test data is synchronized. The dummy power consumption component performs a dummy power consumption operation while the signal training operation is performed. | 2022-08-04 |
20220246231 | METHOD FOR CONSTRUCTING MODEL FOR PREDICTING DIFFERENTIATION EFFICIENCY OF IPS CELL AND METHOD FOR PREDICTING DIFFERENTIATION EFFICIENCY OF IPS CELL - A plurality of metabolites contained in culture supernatants of a plurality of iPS cell clones whose differentiation efficiency into chondrocytes or neural crest cells is known is quantified, and a relationship between the measured values of the plurality of metabolites obtained by the quantification and the differentiation efficiencies is subjected to a multivariate analysis, and a model for predicting a differentiation efficiency of iPS cells is constructed. Furthermore, the plurality of metabolites contained in a culture supernatant of a test cell group including a single type of iPS cell clones is quantified, and the values, obtained by the quantification, are applied to the model, thereby predicting a differentiation efficiency of the test cell group into chondrocytes or neural crest cells. This makes it possible to predict the differentiation efficiency of iPS cells into chondrocytes or neural crest cells in a short time. | 2022-08-04 |
20220246232 | METHOD FOR DIAGNOSING DISEASE RISK BASED ON COMPLEX BIOMARKER NETWORK - Provided is a method for diagnosing a disease risk based on a complex biomarker network. More particularly, provided is a method for predicting or diagnosing a disease risk by constructing a complex disease relation network from biomarkers extracted from a liquid biological specimen and automatically extracting a disease marker from the complex disease relation network. It was confirmed that the method for predicting or diagnosing a disease risk using the biomarkers extracted from the liquid biological specimen developed according to the present invention applies an improved network analysis and learning method as compared to conventional methods, and thus enables disease-related diagnosis which shows high sensitivity and specificity even when only a few biomarkers are applied, which indicates that the method of the present invention shows superior extraction performance, compared to the methods using conventional variational dropout-based biomarker extraction. | 2022-08-04 |
20220246233 | STRUCTURE-BASED, LIGAND ACTIVITY PREDICTION USING BINDING MODE PREDICTION INFORMATION - A system and method for structure-based, small molecule activity prediction using binding mode prediction information. Binding scores between ligands and target molecules, (e.g. proteins, RNA, DNA, lipids, sugars) are first generated using molecular docking. A first machine learned deep neural network (DNN) model is developed using data representing the molecular ligand-target pair 3D structures and docking features to predict binding modes. Using transfer learning, weights of layers learned in the first machine learned model are used as weights in layers of a second machine learned DNN model used to more accurately improve the performance of activity prediction of the second machine learned model. For a target newly paired ligand-target complex, the method further implements a binding mode selector for selecting one or more particular binding poses for input to the activity prediction model for use in activity mode prediction of an activity of the target paired ligand-protein complex. | 2022-08-04 |
20220246234 | USING CELL-FREE DNA FRAGMENT SIZE TO DETECT TUMOR-ASSOCIATED VARIANT - Methods and systems are provided for determining a variant of interest by analyzing sizes and sequences of cfDNA fragments obtained from a test sample. The methods and systems provided herein implement processes that synergistically combine size and sequence information, thereby improving specificity and sensitivity of assays over conventional methods. | 2022-08-04 |
20220246235 | SYSTEM AND METHOD FOR GENE EDITING CASSETTE DESIGN - The present disclosure is drawn to creating cassette designs for nucleic acid-guided nuclease editing. In designing editing cassettes, a set of edit specifications must first be obtained. These edit specifications are taken together with a set of configuration parameters to start a computational pipeline that generates a collection of cassette designs. The process of designing editing cassettes involves the following exemplary steps: 1) creation of a set of candidate cassette designs for each unique edit specification, 2) enumeration of features describing biophysical characteristics of each candidate design, 3) providing each candidate design with a score, and 4) returning a number of scored and rank-ordered candidate cassette designs for each edit specification. | 2022-08-04 |
20220246236 | SYSTEMS FOR POLYNUCLEOTIDE CONSTRUCT DESIGN, VISUALIZATION AND TRANSACTIONS TO MANUFACTURE THE SAME - The present invention disclose a computerized system for designing nucleic acid sequences for gene expression comprising; (a) a server [ | 2022-08-04 |
20220246237 | OPTIMAL SELECTION METHOD OF GENE CHIP PROBES FOR CANCER SCREENING - The invention relates to an optimal selection method of gene chip probes for cancer screening. The method is characterized in that the gene chip probes capable of being used for cancer screening are obtained through three stages of constructing a point mutation site (SNV) group, constructing a candidate probe group and verifying and confirming probes on the basis of nucleic acid data of a confirmed case of a selected cancer. | 2022-08-04 |