31st week of 2011 patent applcation highlights part 61 |
Patent application number | Title | Published |
20110191474 | SYSTEM AND METHOD OF A RELAY SERVER FOR MANAGING COMMUNICATIONS AND NOTIFICATION BETWEEN A MOBILE DEVICE AND APPLICATION SERVER - Providing a mobile device with web-based access to data objects is disclosed. Authentication information is sent from a mobile device to a relay server. The relay server executes a connection application to establish a connection to a web access server. The authentication information is provided to the web access server associated with a data store hosting a data object. Upon authentication, the data object is provided to the relay server from the data store. The data object is then provided to the mobile device. | 2011-08-04 |
20110191475 | SYSTEM AND METHOD FOR MANAGING DELIVERY OF PUBLIC SERVICES - Systems and methods of managing public services provided by a utility are described. The method includes determining a presence of one or more users at a particular location based on a current status of one or more communication devices. The method further includes predicting consumption of the public service responsive to the determining step. | 2011-08-04 |
20110191476 | System and Method for Migration of Digital Assets - A system, method, and computer-readable medium are disclosed for automatically migrating entitled digital assets from a source system to the target system. A first personalization agent is installed on a target system. A first set of digital assets entitlement data is provided along with an associated first set of digital assets data, which is then installed on the target system by the first personalization agent. A second set of digital assets entitlement data associated with a second set of digital assets data installed on a source system is determined by a second personalization agent. The second set of digital assets entitlement data is disassociated from the second set of system identifier data and then associated with the first set of system identifier data. The second set of digital assets is then installed the target system by the first personalization agent. | 2011-08-04 |
20110191477 | System and Method for Automatically Optimizing Capacity Between Server Clusters - A resource management system for a virtual machine computing environment includes a software component that optimizes capacity between server clusters or groups by monitoring the capacity of server clusters or groups and automatically adding and removing host systems to and from server clusters or groups. The software component may be implemented at a server cluster management level to monitor and execute host system moves between server clusters and/or at a higher level in the resource management hierarchy. At the higher level, the software component is configured to monitor and execute host system moves between sets of server clusters being managed by different server cluster management agents. | 2011-08-04 |
20110191478 | QUICK ACCESS DISPLAY - A quick access display with a small screen is physically attached to the outside of a laptop computer. Selected and key information in formatted display frames is electronically pushed to the quick access display by an application program loaded to run on the laptop computer's operating system. The formatted display frames are communicated over a universal serial bus (USB), or wirelessly by radio frequency identification (RFID) chips, BLUETOOTH, or IEEE-802.11 Wi-Fi. Operating power for the quick access display is provided by long-life watch batteries and the electronics are implemented in low power MOS technologies. | 2011-08-04 |
20110191479 | SYSTEM FOR RAPIDLY ESTABLISHING HUMAN/MACHINE COMMUNICATION LINKS BY MAINTAINING SIMULTANEOUS AWARENESS OF MULTIPLE CALL-HOST ENDPOINT-STATES - A method and system are provided that enhance human/machine communication so as to more closely approximate natural human/human communication by more effectively establishing communications links for human-interactive media. Specifically, the speed and quality of the connection are improved by the method and system, resulting in a more natural user experience. The method includes a communication system receiving a call request from a requestor. The communication system has a Connection Proxy (CP) and a plurality of Endpoints (EPs). The CP has an endpoint state table (EST) configured to store state information associated with each of the plurality of endpoints (EPs). Based on the call request, the CP selects an EP using the EST. If the selected EP accepts the requested communications link, the CP establishes a communications link that excludes the CP itself. The CP also updates the EST based on a response to the call request from the selected EP. | 2011-08-04 |
20110191480 | PACKET-BASED DIGITAL DISPLAY INTERFACE SIGNAL MAPPING TO MICRO SERIAL INTERFACE - A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal. | 2011-08-04 |
20110191481 | SYSTEMS AND METHODS FOR TRANSFERRING DATA - Data transfer systems and methods are disclosed. A method of transferring data includes initiating a session for transferring data, establishing a session connection between a first gateway and a second gateway, buffering a predetermined amount of data received by the first gateway, generating a data block using a session-layer protocol when the predetermined amount of data is buffered, and transmitting the data block from the first gateway to the second gateway over the session connection. A system for transferring data includes a first gateway, a second gateway, and a network. The first gateway includes memory for buffering received data and a processor operable to execute a session-layer protocol for generating a data block when a predetermined amount of data is buffered. The first gateway is configured to transmit the data block to the second gateway via the network during a session. | 2011-08-04 |
20110191482 | Notification of resource restrictions in a multimedia communications network - The invention relates to a method of notifying an Application Function, AF, in a communications network of resource restrictions relating to a communications session. The network includes a Policy and Charging Rules Function, PCRF, for authorising and controlling flows of data in the session. In the method the AF sends an authorisation request to the PCRF for establishing the communication session. The authorisation request includes an indication that the AF is to be notified of resource restrictions for the data flows in the session. The PCRF notifies the AF of the resource restrictions. | 2011-08-04 |
20110191483 | METHOD AND APPLICATION SERVER FOR USING A SIP SERVICE FROM A NON-SIP DEVICE - A method and an Application Server for enabling a non-SIP device to use a SIP service are described. The method is executed in an Application Server and comprises the steps of receiving a request for a SIP service from a non-SIP device. The method comprises retrieving a contact card corresponding to the non-SIP device from a Contact Server, the contact card containing at least one identity. The method also comprises inserting the at least one identity retrieved from the contact card in the request for the SIP service and forwarding the request for the SIP Service to the Service Server. | 2011-08-04 |
20110191484 | HIERARCHICAL ROUTING AND INTERFACE SELECTION FOR MULTI-PROCESSOR MULTIMODE NETWORK DEVICES - The embodiments simplify the development of applications for current and future wireless communication devices, resolving the deficiencies of current methods by providing a hierarchical routing layer which abstracts the actual proximity of the network connection. An application can request and receive a type of network connection without having to address details of the actual connection established. A hierarchical routing layer is provided within the software architecture of each processor within the computing device. The hierarchical routing layer abstracts the actual proximity of the network connectivity on the modem from the applications using proxy network interfaces. The hierarchical routing layers on each processor cooperate to identify a best network interface for an application network request. The routing layer enables response to an application request for a network interface in a simple manner regardless of whether the network interface is provided on the application host processor or another processor. | 2011-08-04 |
20110191485 | ROLE BASED ACCESS CONTROL UTILIZING SCOPED PERMISSIONS - Systems and methods authorizing access to storage system resources are presented herein. A scoped permission assignment can be associated with an operation related to a type of at least one resource. The scoped permission assignment can be assigned to a role; and the role can be associated with user(s). A resource, or one or more resources of a resource group, can be associated with user(s) or user group(s). Further, a user can be authorized to perform the operation on the resource and/or one or more resources based on, at least in part, permission assignments directly granted to the user or granted in a role of the user. In addition, one or more resource flags can be assigned to the one or more resources. Accordingly, the user can be authorized to perform the operation based on, at least in part, the one or more resource flags and the scoped permission assignment. | 2011-08-04 |
20110191486 | METHOD AND APPARATUS FOR S.I.P./H.323 INTERWORKING - An interworking function (IWF) for a first and second protocol based network, for example, an H.323 protocol based network and an SIP protocol based network comprises an interworking gateway server including a state machine for defining each call processing state and a translation table for use in translating addresses formatted in each protocol. A method of interworking for use in interworking between said first protocol based network and said second protocol based network comprises the steps of receiving at said interworking gateway server serving said first and second protocol based networks a request from an endpoint in the first or second protocol based networks, establishing a state machine in memory whereby, for each state of said state machine, a message associated with that state is categorized as one of a triggering message, a non-triggering message and an error message, establishing a translation table in said memory whereby an address formatted in said first protocol has a one-for-one correspondence with an address formatted in said second protocol, processing said request in accordance with said translation table and said state machine and permitting communication between said first and second endpoints utilizing a realtime transport protocol. In the event media is terminated at said interworking gateway server, the interworking gateway server, in one embodiment, comprises a media switching fabric for switching media terminated at the gateway to an addressed endpoint capable of receiving it. | 2011-08-04 |
20110191487 | Method and Network Equipment for Maintaining a Media Stream Through Another Network Equipment While Suspending an Associated Media Stream Connection in a Communication Network - A method for maintaining a media stream through a first network equipment while suspending the associated media stream connection in a communication network, comprising receiving within a second network equipment a trigger for suspending a media stream, sending a signalling command for maintaining the media stream and blocking the maintained media stream is provided. | 2011-08-04 |
20110191488 | NETWORK MEDIA PROCESSING DEVICE AND NETWORK MEDIA DISPLAY SYSTEM - A network media processing device includes a network connection module and a graphics processor. The network connection module is electrically connected to the graphics processor directly. The network connection module is used for connecting to a local area network (LAN). Through the LAN, a host may transmit or broadcast digital image data to the network connection module. The network media processing device can receive media data transmitted by the network with a very simple hardware construction. Therefore, the use convenience can be greatly improved when media data is transmitted using a LAN. | 2011-08-04 |
20110191489 | COMMUNICATION SYSTEM WITH SERVER FOR IDENTIFICATION INFORMATION RETRIEVAL AND RELATED METHODS - A communication system may include a mobile wireless communications device, and a server having an email source interface module configured to communicate with an email source, and a proxy module cooperating with the email source interface module. The proxy module may be configured to communicate with the mobile wireless communications device using a first communications protocol and a second different communications protocol, authenticate the mobile wireless communications device by at least retrieving identification information therefrom using an initial display screen based upon the first communications protocol, and transmit a selectable settings interface to the mobile wireless communications device for accessing the email source and being based upon the second different communications protocol. | 2011-08-04 |
20110191490 | METHOD AND APPARATUS FOR RATE MATCHING - A method and apparatus for rate matching are disclosed by the invention, wherein the method includes: determining an initial value according to the total amount of data in the data stream and a predetermined initial offset value; performing an accumulation processing and an even distribution processing on said initial value and the amount of the data needing rate matching; determining the data needing rate matching from the data stream according to the processing result. With the solution proposed by the invention, a rate matching method using even distribution principle and accumulation principle can be determined. The method is simple, clear and accurate, and can be understood easily. | 2011-08-04 |
20110191491 | METHOD AND APPARATUS FOR REPRODUCING MULTIMEDIA DATA BY CONTROLLING REPRODUCING SPEED - Provided are a multimedia data reproducing method and an apparatus for controlling a multimedia data reproducing speed based on a multimedia data packet receiving speed. The method including controlling a reproducing speed of the multimedia data based on a first time difference between times at which a plurality of packets including the multimedia data are respectively received and a second time difference between times to respectively reproduce the multimedia data corresponding to the plurality of packets; and reproducing the multimedia data at the controlled reproducing speed. | 2011-08-04 |
20110191492 | ROUTER, ROUTING METHOD, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONSTRUCTING VIRTUAL MACHINE - A method of constructing a virtual machine includes receiving information specifying processing power of an information processing apparatus to be provided from a router connected through a virtual private network to an external apparatus connected through the router; constructing a virtual machine satisfying the processing power specified by the information; and transmitting information regarding the virtual machine to the router. | 2011-08-04 |
20110191493 | INTERWORKING SYSTEM BETWEEN IP NETWORKS USING DIFFERENT IP ADDRESS FORMAT, APPLICATION LAYER GATEWAY (ALG) SERVER, STUN SERVER, NETWORK ADDRESS TRANSLATOR, INTERWORKING METHOD THEREOF, AND SIP MESSAGE ROUTING METHOD THEREOF - Disclosed are an interworking system between IP networks using different IP address format, an application layer gateway (ALG) server, a network address translator, an interworking method, and a SIP message routing method. The interworking system between a local network using a private IP and a public network using a public IP includes a STUN server and an application layer gateway (ALG) server. The STUN server provides binding information of header information of a public IP binding request. The application layer gateway (ALG) server performs a public IP binding request with header information changed by IP masquerading, and performs routing by applying the received binding information to media receiving address information of a SIP message. | 2011-08-04 |
20110191494 | SYSTEM AND METHOD FOR BACKWARDS COMPATIBLE MULTI-ACCESS WITH PROXY MOBILE INTERNET PROTOCOL - A system and method of changing traffic from a first access associated with a first access router to a second access associated with a second access router utilized by a terminal in a telecommunication network using PMIP. The method begins by the terminal sending a first message to a Local Mobility Anchor (LMA), through the second access router, requesting a change of access from the first access to the second access. The LMA receives the first message and installs a new routing state associated with the second access router and the second access. A second message is then sent from the LMA to the terminal acknowledging the change in access of the terminal to the second access. The routing state associated with the second access router and the second access is then installed in the terminal. | 2011-08-04 |
20110191495 | SYSTEMS AND METHODS FOR DISCERNING AND CONTROLLING COMMUNICATION TRAFFIC - Communication traffic redirection systems and methods are disclosed that allow for redirection of communication traffic over the Internet based, at least in part, on the type of higher-level communication protocol intended to be used. The systems and methods permit redirection of only certain types of communication traffic of interest, for example HTTP traffic, while permitting other types of communication, for example SMTP traffic, to pass without redirection. The systems and method can employ a training and dynamic feedback procedure to ensure only traffic of interest is redirected. The systems and methods provide efficient redirection of specific types of traffic to redirect landing pages, and allow for efficient methods of generating revenue through advertising. | 2011-08-04 |
20110191496 | COMPRESSIVE DATA GATHERING FOR LARGE-SCALE WIRELESS SENSOR NETWORKS - Techniques for data gathering in large-scale wireless sensor networks are described. A data collection device receives aggregate data from at least one sensor node of a group of N sensor nodes. The aggregate data includes M weighted sums. Each of the M weighted sums includes a respective sum of N products each of which being a product of a respective coefficient and a sensor reading from a respective one of the N sensor nodes. M and N are positive integers and M is less than N. Computation is performed on the aggregate data to recover sensor readings from the N sensor nodes. | 2011-08-04 |
20110191497 | METHOD FOR SYNCHRONIZING EXECUTION OF MULTIPLE PROCESSING DEVICES AND RELATED SYSTEM - A system includes multiple processing devices. Each processing device is configured to receive first and second status flags from first and second neighboring processing devices, respectively. Each status flag identifies whether one or more of the processing devices are ready for operation. Each processing device is also configured to determine that all processing devices are ready for operation using the status flags. Each processing device is further configured to wait for a specified amount of time before entering operation. The specified amount of time is selected so that the processing devices are substantially synchronized. The processing devices could be coupled together in a ring configuration, the first neighboring processing device could include a right neighboring processing device in the ring configuration, and the second neighboring processing device could include a left neighboring processing device in the ring configuration. | 2011-08-04 |
20110191498 | Verifiable Date Stamp Across Multiple Time Zones - A verifiable date stamp for use in portable electronic devices automatically and transparently determines within the portable device or devices the correct date and time that a document or image is created. By keeping periodic records of tests for accuracy of the date and time of the device(s), it will be possible to provide admissible evidence of the date stamps generated by the portable devices. The date stamp provided by the invention includes not only date and time but, in addition, GPS location (latitude, longitude and altitude) and time zone. In some embodiments which involve the use of video, the date stamp includes beginning and ending time and, optionally, average velocity, if any, for the time duration of the video clip. | 2011-08-04 |
20110191499 | USB to SD Bridge - A USB-to-SDIO bridge (UTSB) to efficiently transmit SD/SDIO commands in USB packets. The UTSB may allow the majority of the device drivers for a given SD/SDIO device to remain intact, requiring changes only in the lowest hardware adaptation layer to put a USB wrapper around native SD commands. These commands may be sent over USB-to-SD card reader devices that may include various embodiments of a UTSB, where they may be unwrapped and transmitted to the SD port as if the port were native to the host controller. Additionally, the SD/SDIO commands may be packaged into groups of commands, or transactions, to optimize performance. The host driver may instruct the UTSB bridge device to repeatedly read data from the SDIO device until a communications FIFO on the device is empty (corresponding to a termination condition), and return the collected data to the host. | 2011-08-04 |
20110191500 | DEPLOYING A CONFIGURATION FOR MULTIPLE FIELD DEVICES - A method and system are disclosed for deploying a configuration in a process control system wherein at least a portion of the configuration is deployed to a set of field devices. Initially the set of deployment packages are stored within a configuration storage. Thereafter, deployment is initiated on the set of deployment packages from the configuration storage. In response to the initiating deployment step, an automated cascaded deployment is commenced to the set of connected field devices. The automated cascaded deployment includes first deploying the sets of deployment packages to a set of control module assemblies. The method furthermore includes second deploying the received portions of the set of deployment packages to a set of I/O module assemblies. The set of I/O module assemblies maintain and pass the received sub-portions of the set of deployment packages to sets of field devices. | 2011-08-04 |
20110191501 | SYSTEMS AND METHODS OF TRANSFERRING DATA BETWEEN A DISK DEVICE AND AN EXTERNAL STORAGE DEVICE - Provided are systems and methods to communicate data transfer of data between a disk device and an external storage device. A host can generate a control command to communicate with an external storage device, and a disk device to receive the control command from a host to identify and communicate with an external storage device when connected to the external storage device and to configure the external storage device by assigning an ID code to each storage area of the external storage device. | 2011-08-04 |
20110191502 | MOTOR CONTROLLER FOR ELECTRONIC DRIVING MOTOR AND METHOD FOR CONTROLLING THEREOF - A motor controller for an electronic driving motor, including at least a controlling and processing unit, an interface circuit unit, and an identifying circuit. The controlling and processing unit is disposed on a mother circuit board. The interface circuit unit and the identifying circuit are disposed on a daughter circuit board. The mother circuit board and the daughter circuit board are connected to each other whereby forming electric connection. The identifying circuit inputs an identifying signal to the controlling and processing unit. The controlling and processing unit automatically configured types of input/output ports of the interface circuit unit according to the identifying signal. The motor controller of the invention enables motor manufactures to reduce the number of motor types for management, reduces development cost, development cycle, and product cost, simplifies a production technique, and improves efficiency. | 2011-08-04 |
20110191503 | Motherboard Compatible with Multiple Versions of Universal Serial Bus (USB) and Related Method - A mother board compatible with multiple versions of universal serial bus (USB) is disclosed. The motherboard comprises a connector, a host controller interface (HCI) means, a serial bus slot, and a detection unit. The connector is used for exchanging signals of a first USB version and signals of a second USB version with an external USB device. The host HCI means is coupled to the connector through a first data line, for proving the signals of the first USB version. The serial bus slot is coupled to the connector through a second data line, for conveying the signals of the second USB version. The detection unit is coupled to the serial bus slot for detecting an insertion state of the serial bus slot and the functionality of the second USB version, and generating a detection result. | 2011-08-04 |
20110191504 | Satellite Irrigation Controller - In one embodiment, the present invention provides a satellite irrigation controller that allows a user to insert a input/output card into any position in any sequence and be recognized as an input card or an output card. When the correct card type is determined, the card is service according to its specified functionality. In another embodiment, the satellite irrigation controller includes firmware which allows a user to program a range of stations at one time. In yet another embodiment, the satellite irrigation controller provides three user input programs that reduce the amount of input data needed to program the irrigation cycle of an irrigation station. | 2011-08-04 |
20110191505 | KEY ACTIVITY DETECTION SYSTEM AND METHOD THEREOF - A key activity detection method, applied in an electronic device having at least a first key and a digital I/O pin, includes: switching the digital I/O pin to a first operation mode, so that a voltage of the digital I/O pin is decreased to a ground voltage; switching the digital I/O pin to a second operation mode, so that the voltage of the digital I/O pin is increased; measuring a first charge period of the voltage of the digital I/O pin; counting a first appearance times of the first charge period; judging whether the first key is stably activated according to the first appearance times of the first charge period. | 2011-08-04 |
20110191506 | VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is stored in at least one buffer, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions, by speculatively moving the packets forward even while DMA engines perform their processing to facilitate their transfer. | 2011-08-04 |
20110191507 | DMA ENGINE - A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors. | 2011-08-04 |
20110191508 | Low-Contention Update Buffer Queuing For Large Systems - A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue. | 2011-08-04 |
20110191509 | Automatically Launching a Measurement Application in Response to Measurement Device Connection - Automatically launching a measurement program in response to measurement device connection. The measurement device may be connected to a host device. The measurement device may store a measurement program. The host device may automatically detect the measurement device. However, a measurement device specific driver may not be required for communication between the host device and the measurement device. The host device may automatically execute the measurement program stored on the measurement device in response to the connecting. During execution, the measurement device may acquire data and provide the acquired data to the host device. | 2011-08-04 |
20110191510 | WIRELESS HUMAN INTERFACE DEVICE (HID) COORDINATION - A method relating to wireless human interface device (HID) coordination is disclosed. A first human interface device (HID) is wirelessly coupled to two or more computing devices, wherein the first HID is configured to toggle between interactions with each of the two or more computing devices. An inquiry or paging message is broadcast to one or more HIDs, including a second HID wirelessly coupled to the two or more computing devices, wherein the second HID is configured to receive and provide a response to the inquiry or paging message. The second HID is located based on the response to the inquiry or paging message. A wireless link is established between the first HID and the second HID based on the identifying, wherein the first HID is configured to coordinate, via the wireless link, interactions with the two or more computing devices by both the first HID and the second HID based on the toggle. | 2011-08-04 |
20110191511 | SERIAL TRANSMISSION DEVICE, METHOD, AND COMPUTER READABLE MEDIUM STORING PROGRAM - A serial transmission device includes a transmitting unit that transmits data, a receiving unit that receives the data, and a plurality of serial transmission paths that connect the transmitting unit with the receiving unit and are used to transmit data. The receiving unit includes an inter-lane skew information generation unit that generates inter-lane skew information about skew of each of the serial transmission paths and transmits the generated inter-lane skew information to the transmitting unit. The transmitting unit includes a data conversion rule generation unit that generates a conversion rule used to determine distribution of the data to each of the serial transmission paths based on the inter-lane skew information. | 2011-08-04 |
20110191512 | Single Pin Read-Write Method And Interface - A method of communicating on a single serial line between two devices is disclosed. The method includes combining a data stream and a clock to form a three-voltage level stream such that the third voltage level records the transitions of the clock while the serial data is either high or low. Either the first or the second device can send a combined stream on the line. The method further includes, in some embodiments, the second device driving the same voltage levels as those transmitted by the first device and the first device sensing current on the single serial line to determine that the second device has received data from the first device. | 2011-08-04 |
20110191513 | INTERRUPT CONTROL METHOD AND SYSTEM - An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit. | 2011-08-04 |
20110191514 | SERVER SYSTEM - A server system includes a management board having a baseboard management controller provided thereon; a plurality of middle boards separately connected to the management board; a plurality of mainboards separately connected to the middle boards; and a hard disk (HD) module connected to the middle boards. Each of the middle boards has a plurality of mainboard connection ports and at least one HD signal connection port. The mainboards are separately connected to the mainboard connection ports, and the baseboard management controller manages the mainboards via the middle boards. The HD module has an HD backplane being connected to the HD signal connection ports, and the mainboards are connected to the HD module via respective correspondingly connected middle board. | 2011-08-04 |
20110191515 | Internet Synchronization Timepiece System - An internet synchronization timepiece system includes a timepiece having a timepiece signal transceiver and a time-keeping synchronization hub. The time-keeping synchronization hub includes a hub casing connected to a computer, a time-keeping device received in the hub casing for periodically receiving the real-time time and the weather forecast information acquired through internet, and a synchronization transceiver received in the hub casing for transmitting synchronized time information and the weather forecast information in a wireless manner as time signal and weather forecast signal to the timepiece. | 2011-08-04 |
20110191516 | Universal touch-screen remote controller - A remote controller has a control processor and a plurality of client device remote interfaces. A touchscreen display displays a rendering depicting a remote controller user interface having user operable control elements. The processor has associated storage that stores remote controller programs that configure the touchscreen according to a remote control configuration defined by a selected remote controller programs. The processor carries out functions defined in the selected one of the remote controller programs to transmit control commands from one of said client device remote interfaces to a client device upon receipt of input via the touchscreen user interface to implement the command to the client device. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 2011-08-04 |
20110191517 | SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit. | 2011-08-04 |
20110191518 | VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions. | 2011-08-04 |
20110191519 | SWITCHING DEVICE, SWITCH CONTROL METHOD, AND STORAGE SYSTEM - A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk. | 2011-08-04 |
20110191520 | STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD - The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor | 2011-08-04 |
20110191521 | FLASH MEMORY DEVICE - A controller in a flash memory device manages erase count of each physical block and manages the erase frequency of each logical block. The controller allocates a logical block whose erase frequency is high to one or more physical blocks whose erase count is low. | 2011-08-04 |
20110191522 | Managing Metadata and Page Replacement in a Persistent Cache in Flash Memory - A persistent cache is implemented in a flash memory that includes a journal section that stores metadata and a low frequency section and a high frequency section that store data entries. Writing new metadata to the persistent cache includes sequentially advancing to a next sector containing an invalid metadata entry, saving a working copy of the sector in RAM, writing metadata corresponding to one or more new data entries in the working copy, and overwriting the sector in the flash memory containing the invalid entry with the working copy. Writes to the low frequency and high frequency sections occur sequentially in the current locations of a low frequency section pointer and a high frequency section pointer, respectively. In a persistent cache, the reconstruction of a non-persistent cache utilizes the metadata entry that has the most recent timestamp. | 2011-08-04 |
20110191523 | Priority Ordered Multi-Medium Solid-State Storage System and Methods for Use - A hierarchical data-storage system has a volatile storage medium, a first non-volatile storage medium, and a controller including a ranking engine tracking data writes to each of the memory mediums. Each medium is associated with a pre-set capacity threshold, and the controller, upon the volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the volatile medium, copies the data in those blocks to the non-volatile medium, and marks those blocks as available for new data writes, and the controller, upon the non-volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the non-volatile medium, and marks those blocks as available for new data writes from the volatile medium. | 2011-08-04 |
20110191524 | FLASH MEMORY STORAGE DEVICE, CONTROLLER THEREOF, AND PROGRAM MANAGEMENT METHOD THEREOF - A flash memory storage device, a controller thereof, and a programming management method thereof are provide for the flash memory storage device including a flash memory chip, wherein at least a first thread and a second thread are to be implemented within the flash memory storage device. The method includes defining a predetermined programming unit and receiving a first write command sent by a host. The method also includes distributing a control right of the flash memory chip to the first thread if the first write command is determined to be executed by the first thread, and controlling the first thread to release the control right of the flash memory chip after the first thread finishes a programming operation of the predetermined programming unit. | 2011-08-04 |
20110191525 | FLASH MEMORY STORAGE DEVICE, CONTROLLER THEREOF, AND DATA PROGRAMMING METHOD THEREOF - A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks. | 2011-08-04 |
20110191526 | Flash Memory Timing Pre-Characterization - This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly. A mechanism is also provided for recalibrating memory previously marked. By minimizing variability, flash memory can be applied to a broader range of designs and potentially to a broader set of main memory applications. | 2011-08-04 |
20110191527 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises processors, a nonvolatile memory with channels, a list storage, and a command generator. The list storage is configured to store an erase address list includes erase addresses of each of the channels of the nonvolatile memory. The command generator is configured to continuously generate a series of erase commands concerning the erase addresses in the erase address list in response to a single erase request generated from any one of the processors. | 2011-08-04 |
20110191528 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises a main memory, a request issue module, a delay module, and an access module. The main memory is configured to store candidate information for determining a compaction candidate for a nonvolatile memory. The request issue module is configured to issue an access request for the candidate information in the main memory. The delay module is configured to delay the access request issued from the request issue module. The access module is configured to access the candidate information in the main memory based on an access request delayed by the delay module. | 2011-08-04 |
20110191529 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory. | 2011-08-04 |
20110191530 | Adaptive Deterministic Grouping of Blocks into Multi-Block Units - The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing. | 2011-08-04 |
20110191531 | MEMORY DEVICE AND CONTROL METHOD THEREOF - A control method of a memory device including a storage area formed of a nonvolatile semiconductor memory, includes updating a file stored in the storage area by using a file system which supports an incremental write method, recording, in the storage area, an allocation table representing a correlation between a logical address indicating a recording position of the file and a virtual address representing a virtual recording position of the file and management information of the allocation table, and recording position information representing a recording position of the management information in a position information area of the storage area. | 2011-08-04 |
20110191532 | PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT - A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory. | 2011-08-04 |
20110191533 | DIGITAL FORENSIC ACQUISITION KIT AND METHODS OF USE THEREOF - Disclosed are compositions, methods, and kits, for issuing and conducting automated imaging and preservation for obtaining digital forensic data from active (i.e., powered-on) and non-active (i.e., powered-off) computer systems. In certain embodiments, the invention further encompasses providing a customer base a preliminary report of data. In other embodiments, the invention encompasses the option to receive a virtual machine file set of the acquired information for additional viewing and examination by the customer. The invention further encompasses methods and systems for implementing the embodiments of the invention. The invention also encompasses methods, apparatuses, and systems for secure forensic investigation of a target machine. | 2011-08-04 |
20110191534 | DYNAMIC MANAGEMENT OF DESTAGE TASKS IN A STORAGE CONTROLLER - Method, system, and computer program product embodiments for facilitating data transfer from a write cache and NVS via a device adapter to a pool of storage devices by a processor or processors are provided. The processor(s) adaptively varies the destage rate based on the current occupancy of the NVS for a particular storage device and stage activity related to that storage device. The stage activity includes one or more of the storage device stage activity, device adapter stage activity, device adapter utilized bandwidth and the read/write speed of the storage device. These factors are generally associated with read response time in the event of a cache miss and not ordinarily associated with dynamic management of the destage rate. This combination maintains the desired overall occupancy of the NVS while improving response time performance. | 2011-08-04 |
20110191535 | METHOD FOR CONTROLLING DISK ARRAY APPARATUS AND DISK ARRAY APPARATUS - According to an aspect of the embodiment, a cache controller sets, when power supply capacity information is acquired at an update period, a size of a permitted area in which the writing of dirty data is permitted and a size of an inhibited area in which the writing of the dirty data is inhibited in a cache memory, according to the power supply capacity information. The cache controller stores the dirty data or read data read out from a disk array in the permitted area, or stores only the read data in the inhibited area. | 2011-08-04 |
20110191536 | STORAGE SYSTEM, STORAGE APPARATUS, AND OPTIMIZATION METHOD OF STORAGE AREAS OF STORAGE SYSTEM - This invention is intended for the purpose of providing the storage system, the storage apparatus, and the storage system by which, even if the storage areas allocated to the virtual volume are managed in management units set by the RAID group, overhead for parity calculation does not become excessive. This invention, by releasing a specific management unit not fully utilized for page allocation from allocation to the virtual volume and migrating the allocated pages belonging to this specific management unit to the other management unit, makes the storage areas of the specific management unit available for the write accesses for the other virtual volumes from the host computer. | 2011-08-04 |
20110191537 | STORAGE CONTROLLER AND VIRTUAL VOLUME CONTROL METHOD - A storage controller allocates a real storage area to a virtual volume in chunk units each comprising a plurality of pages. In a case where load bias occurs between RAID groups, data reallocation is carried out. A real storage area inside a pool is allocated to a virtual volume | 2011-08-04 |
20110191538 | STORAGE DEVICE, METHOD FOR RESTORING DATA IN STORAGE DEVICE AND STORAGE CONTROLLER - A virtual volume control unit allocates, upon detection of a write request for new data in a virtual volume to be accessed, an actual storage space of a physical medium existing in the same storage group to the virtual volume in accordance with volume capacity of the new data. A storage control unit stores the new data as actual data in the actual storage space of the physical medium allocated to the virtual volume. And a restoration control unit causes, upon detection of a fallback in data redundancy in the storage group, the actual data in a stored space among the actual storage spaces in the physical medium that caused the fallback to be preferentially restored in an actual storage space in a destination physical medium with reference to the physical media other than the physical medium that caused the fallback in the storage group. | 2011-08-04 |
20110191539 | Coprocessor session switching - A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data. | 2011-08-04 |
20110191540 | PROCESSING READ AND WRITE REQUESTS IN A STORAGE CONTROLLER - Provided are a method, system, and computer program product for processing read and write requests in a storage controller. A host adaptor in the storage controller receives a write request from a host system for a storage address in a storage device. The host adaptor sends write information indicating the storage address updated by the write request to a device adaptor in the storage controller. The host adaptor writes the write data to a cache in the storage controller. The device adaptor indicates the storage address indicated in the write information to a modified storage address list stored in the device adaptor, wherein the modified storage address list indicates modified data in the cache for storage addresses in the storage device. | 2011-08-04 |
20110191541 | TECHNIQUES FOR DISTRIBUTED CACHE MANAGEMENT - Techniques for distributed cache management are provided. A server having backend resource includes a global cache and a global cache agent. Individual clients each have client cache agents and client caches. When data items associated with the backend resources are added, modified, or deleted in the client caches, the client cache agents report the changes to the global cache agent. The global cache agent records the changes and notifies the other client cache agents to update a status of the changes within their client caches. When the changes are committed to the backend resource each of the statuses in each of the caches are updated accordingly. | 2011-08-04 |
20110191542 | SYSTEM-WIDE QUIESCENCE AND PER-THREAD TRANSACTION FENCE IN A DISTRIBUTED CACHING AGENT - Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed. | 2011-08-04 |
20110191543 | Area and power efficient data coherency maintenance - An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device. | 2011-08-04 |
20110191544 | Data Storage and Access - A data cache wherein contents of the cache are arranged and organised according to a hierarchy. When a member of a first hierarchy is accessed, all contents of that member are copied to the cache. The cache may be arranged according to folders which contain data or blocks of data. A process for caching data using such an arrangement is also provided for. | 2011-08-04 |
20110191545 | SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN A COMPUTING SYSTEM - A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded. | 2011-08-04 |
20110191546 | MEMORY ACCESS PREDICTION - An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, and a physical memory shared with the processors, saturation counters and memory caches. Upon a cache miss for a data item, a cache snoop and access to physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined bit (one (1) or zero (0)) whereas a cache snoop is initiated if the most significant bit is a second predetermined bit (zero (0) or one (1)). | 2011-08-04 |
20110191547 | COMPUTER SYSTEM AND LOAD EQUALIZATION CONTROL METHOD FOR THE SAME - A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided. | 2011-08-04 |
20110191548 | High Utilization Multi-Partitioned Serial Memory - A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency. | 2011-08-04 |
20110191549 | Data Array Manipulation - Data array manipulation is described. In an embodiment, concurrent access to a multi-dimensional data array stored on a storage device is enabled by providing separate computational elements with access to a model of the data array for processing the data and consequently request changes to the model. The data array is updated in accordance with the changes, and notification of the changes is provided to the other computational elements concurrently accessing the model. In another embodiment, a data interface apparatus is provided that comprises a storage interface that generates a model of the data array, and an application interface that provides access to the model to the computational element for processing. The application interface receives changes to the model resulting from the processing, and a command to commit the changes to the data array. The storage interface then writes the changes to the data array as an atomic operation. | 2011-08-04 |
20110191550 | APPARATUS AND METHOD FOR PROCESSING DATA - An apparatus and method for processing data capable of providing an application with data converted based on various data types is provided. The data processing apparatus converts data, which is input from an input system, into various types of data. Various applications receive and use the data that is converted in the data processing apparatus. | 2011-08-04 |
20110191551 | STORAGE APPARATUS AND STORAGE MANAGEMENT METHOD - A storage apparatus capable of copying data to a destination apparatus includes storages including a plurality of volumes for storing data, memories for temporarily storing data to be copied to the destination apparatus, and processors for controlling to copy the data, each processor being configured to manage the memories and parts of the volumes, respectively, and wherein one processor executes storing received write data to one memory and the part, detecting each data amounts stored in the memories when an data amount of one memory is greater than a predetermined amount, allocating management of a part of the part managed by the one processor to other processor when the amount of the data stored in the one memory is greater than an amount calculated by using the data stored in the memories, and transmitting the data stored in the memories to the destination apparatus. | 2011-08-04 |
20110191552 | MEMORY CONTROLLER, MEMORY SYSTEM, RECORDING AND REPRODUCING METHOD FOR MEMORY SYSTEM, AND RECORDING APPARATUS - A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation. | 2011-08-04 |
20110191553 | Data Storage Control Apparatus and Data Storage Control Method - According to one embodiment, a data storage control method, which is applied to a virtual memory that controls access to the data stored in each of the physical memory regions by the corresponding one of the virtual addresses on the basis of an address management table that manages the correspondence relationship between a plurality of virtual addresses corresponding to a plurality of virtual memory regions and a plurality of physical addresses corresponding to a plurality of physical memory regions of a first memory, includes writing the data stored in a specific number of nonconsecutive physical memory regions made to correspond to a specific number of virtual memory regions on the basis of the address management table to a specific number of consecutive physical memory regions. | 2011-08-04 |
20110191554 | STORAGE SYSTEM AND ITS CONTROL METHOD - Proposed are a highly reliable storage system and its control method capable of accelerating the processing speed of the copy processing seen from the host device. | 2011-08-04 |
20110191555 | MANAGING COPY-ON-WRITES TO SNAPSHOTS - An attempt to write to a block of data in a main volume of data is detected. An indicator associated with the block of data is accessed before a copy-on-write operation to a snapshot volume is performed for the block of data. The indicator is used to determine whether the copy-on-write operation is to be performed for the block of data. | 2011-08-04 |
20110191556 | OPTIMIZATION OF DATA MIGRATION BETWEEN STORAGE MEDIUMS - Exemplary method, system, and computer program embodiments for data migration between first and second storage mediums of an available plurality of storage mediums in a computing storage environment are provided. In one embodiment, pursuant to migrating the data from the first to the second storage medium, the data is allocated to the second storage medium while retaining an allocation of the data in the first storage medium. If the data is migrated from the second storage medium back to the first storage medium, the data is pointed to the allocation of the data in the first storage medium to alleviate data movement from the second storage medium to the first storage medium. If the allocation of the data in the first storage medium is determined to be needed for other data, the allocation of the data in the first storage medium is freed. | 2011-08-04 |
20110191557 | SYNCHRONIZING DATA STORAGE SYSTEMS IN A DATA STORAGE ENVIRONMENT - A method for synchronizing data storage systems is provided. The method comprises designating a relationship between a first data storage system and a second data storage system, such that data stored in the first data storage system is copied to the second data storage system, in response to determining that the data stored in the first data storage system has been modified; receiving a first request to modify data stored in a first data block of a first storage volume in the first data storage system, wherein the data block is modified according to the first request; determining that the first data block has not been successfully synchronized when the modified data stored in the first data block is not copied to the second data storage system; and executing a process to retry synchronization of the first data block until synchronization of the first data block is successful, without suspending the relationship while the process is executed. | 2011-08-04 |
20110191558 | DATA MIGRATION METHODOLOGY FOR USE WITH ARRAYS OF POWERED-DOWN STORAGE DEVICES - A method for managing extents in a data storage system includes monitoring usage statistics for an extent residing on one or more powered-up storage devices. In the event the extent has not been accessed for specified period of time (as determined from the usage statistics), the method automatically compresses the extent and migrates the extent to an intermediate repository. Once the amount of data in the intermediate repository reaches a specified level, the method migrates the extent from the intermediate repository to one or more normally powered-down storage devices. If I/O is received for the extent while it resides in the normally powered-down storage devices or the intermediate repository, the method automatically migrates the extent from the normally powered-down storage devices or the intermediate repository to the normally powered-up storage devices. A corresponding apparatus and computer program product are also disclosed. | 2011-08-04 |
20110191559 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DATA PROCESSING AND SYSTEM DEPLOYMENT IN A VIRTUAL ENVIRONMENT - Systems, methods, and computer program products for processing data are disclosed. A method according to one embodiment includes reading a data processing instruction locally called by a virtual work unit; optimizing the read data processing instruction; and performing data processing for the virtual work unit using the optimized data processing instruction. The step of optimizing the read data processing instruction may include one or more of: merging data processing instructions from different virtual work units for same data, and analyzing data processing instructions from different virtual work units to select suitable data processing timing. The data processing method is executed in a virtual environment. | 2011-08-04 |
20110191560 | EFFICIENT DATA STORAGE USING TWO LEVEL DELTA RESEMBLANCE - Storage using resemblance of data segments is disclosed. It is determined that a new segment resembles a second prior stored segment wherein the second prior stored segment is represented as a first stored delta and a first prior stored segment. A second delta between the new segment and the prior stored segment is determined. A representation of the new segment based at least in part on the second delta is stored. | 2011-08-04 |
20110191561 | AUGMENTED ADVISORY LOCK MECHANISM FOR TIGHTLY-COUPLED CLUSTERS - An inter-machine locking mechanism coordinates the access of shared resources in a tightly-coupled cluster that includes a number of processing systems. When a requesting processing system acquires a lock to access a resource, a comparison is made between values of a global counter and a local counter. The global counter indicates the number of times the lock is acquired exclusively by any of the processing systems. Based on the comparison result, the requesting processing system determines whether the resource has been modified since the last time it held the lock. | 2011-08-04 |
20110191562 | Apparatus and method for partitioning, sandboxing and protecting external memories - A technique to provide an integrated circuit that performs memory partitioning to partition a memory into a plurality of regions, in which the memory is accessed by a plurality of heterogeneous processing devices that operate to access the memory. The integrated circuit also assigns a security level for each region of the memory and permits a memory access by a transaction to a particular region of the memory, only when a level of security assigned to the transaction meets or exceeds the assigned security level for the particular region. The integrated circuit also performs sandboxing by assigning which of the plurality of processing devices are permitted access to each of the plurality of regions. The integrated circuit may implement only the security level function or only the sandboxing function, or the integrated circuit may implement them both. In some instances, a scrambling/descrambling function is included to scramble/descramble data. In one application, the integrated circuit is included within a mobile phone. | 2011-08-04 |
20110191563 | ON DEMAND CONVERSION OF STANDARD LOGICAL VOLUMES TO THIN-PROVISIONED LOGICAL VOLUMES - A method for concurrently converting a standard volume to a thin-provisioned volume includes initially establishing metadata for a thin-provisioned volume. The method then updates the metadata for the thin-provisioned volume to point to extents residing in a standard volume. The method then suspends I/O to metadata for the standard volume. Upon suspending the I/O, the method migrates control of the extents in the standard volume from a standard-volume control algorithm to a thin-provisioned-volume control algorithm. The method then resumes the I/O to the metadata for the thin-provisioned volume. Using this technique, standard volumes may be rapidly converted to thin-provisioned volumes while minimally disrupting I/O to the volumes. A corresponding apparatus and computer program product are also disclosed and claimed herein. | 2011-08-04 |
20110191564 | Hierarchical Organization Of Large Memory Blocks - A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency. | 2011-08-04 |
20110191565 | EXTENT SIZE OPTIMIZATION - A method for automatically optimizing an allocation amount for a data set includes receiving an extend request, specifying an allocation amount, for a data set in a storage pool. The method increments a counter in response to receiving the extend request. In the event the counter has reached a threshold value, the method automatically increases the allocation amount of the extend request, such as by multiplying the allocation amount by a multiplier. In the event the allocation amount is larger than a largest free extent in the storage pool, the method automatically decreases the allocation amount of the extend request to correspond to the largest available free extent. Such a method reduces or eliminates the chance that an extend request will fail, and reduces overhead associated with extending and consolidating extents. A corresponding apparatus and computer program product are also disclosed herein. | 2011-08-04 |
20110191566 | MEMORY CONTROLLER AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is configured to set the block as an object of compaction when the number of valid pages counted by the counter is smaller than a predetermined number. | 2011-08-04 |
20110191567 | Relating to Single Instruction Multiple Data (SIMD) Architectures - Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks. | 2011-08-04 |
20110191568 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - An information processing apparatus is provided. The apparatus includes a communication unit configured to communicate with another apparatus, a main processing unit capable of controlling communication processing by the communication unit and other processing, a communication processing unit capable of controlling the communication processing by the communication unit and a deciding unit configured to decide, during communication by the communication unit and based on one of a transfer condition of communication by the communication unit and priority of data to be communicated, which one of the main processing unit and the communication processing unit should control the communication processing by the communication unit. | 2011-08-04 |
20110191569 | DATA PROCESSING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data. | 2011-08-04 |
20110191570 | Method And Apparatus For Performing Logical Compare Operations - A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting one or more flags, which in turn may be utilized by a branching unit. Alternatively, the branch support actions may include branching to an indicated target code location. | 2011-08-04 |
20110191571 | Embedded Managed System Services Repository - An embedded management system that allows an administrator to manage the systems hardware without having to install and setup any management software. In certain embodiments, the embedded management ecosystem includes a unified extensible firmware interface (UEFI), internal persistent storage and a service processor to provide a single interface that allows the administrator to consistently manage system hardware independent of any operating system without installing an operating system or specific agents. | 2011-08-04 |
20110191572 | Configurable Access Kernel - A highly configurable kernel supports a wide variety of content protection systems. The kernel may reside in a host that interacts with a secure processor maintaining content protection clients. After establishing communication with the secure processor, the host receives messages from content protection clients requesting rules for message handling operations to support client operations. This flexible configuration allows for dynamic reconfiguration of host and secure processor operation. | 2011-08-04 |
20110191573 | MULTI-MOTHERBOARD SERVER SYSTEM - A multi-motherboard server system, having a management board and a plurality of motherboards, is disclosed. The multi-motherboard server system is applicable to a sever system. The management board has a BMC, and the motherboards are respectively connected to the management board. The BMC can transmit data to a far-end control system through sideband communication. | 2011-08-04 |