| 31st week of 2012 patent applcation highlights part 20 |
| Patent application number | Title | Published |
|---|
| 20120194231 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal. | 2012-08-02 |
| 20120194232 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a pre-charge signal generator configured to pre-charge a plurality of oscillation signals to a certain voltage level in a pre-charge mode, wherein the pre-charge signal generator includes: a first storage unit for storing a first pre-charge oscillation signal in response to a reference oscillation signal, a feedback unit for feeding back a second pre-charge oscillation signal, a second storage unit for storing the second pre-charge oscillation signal corresponding to an output signal of the first storage unit in response to the reference oscillation signal, and a pre-charge signal output unit for outputting a pre-charge signal in response to the first pre-charge oscillation signal and the second pre-charge oscillation signal. | 2012-08-02 |
| 20120194233 | DEVICE CHARACTERISTIC COMPENSATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage. | 2012-08-02 |
| 20120194234 | APPARATUS FOR COMMUNICATING ANOTHER DEVICE - A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal. | 2012-08-02 |
| 20120194235 | HIGH-SPEED FREQUENCY DRIVER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER - A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. | 2012-08-02 |
| 20120194236 | IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO. | 2012-08-02 |
| 20120194237 | DELAY LOCK LOOP AND METHOD FOR GENERATING CLOCK SIGNAL - A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided. | 2012-08-02 |
| 20120194238 | Delay-Locked Loop with Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. A charge pump system is coupled with the phase detector, including (1) a charge pump responsive to assertion of actuating signals from the UP output and the DOWN output to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust a bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output. | 2012-08-02 |
| 20120194239 | DELAY LOCKED LOOP - A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks. | 2012-08-02 |
| 20120194240 | LATENCY CONTROL CIRCUIT AND METHOD OF CONTROLLING LATENCY - A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal. | 2012-08-02 |
| 20120194241 | SYNCHRONIZATION CIRCUIT - A synchronization circuit includes a first delay unit configured to delay an input signal by a delay time corresponding to first initial delay information and generate a pre-delayed signal; a second delay unit configured to delay the pre-delayed signal by a delay time corresponding to second initial delay information and generate a delayed signal; and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to internal delayed signals of the first delay unit and the input signal. | 2012-08-02 |
| 20120194242 | SIGNAL DELAY APPARATUS FOR PROVIDING EXACT DELAY AMOUNT, MEMORY APPARATUS UTILIZING THE SIGNAL DELAY APPARATUS, AND SIGNAL DELAY METHOD - A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal. | 2012-08-02 |
| 20120194243 | SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF - A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals. | 2012-08-02 |
| 20120194244 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CORRECTING DUTY THEREOF - A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal. | 2012-08-02 |
| 20120194245 | PULSE WIDTH MODULATOR - Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided. | 2012-08-02 |
| 20120194246 | DELAY LATCH CIRCUIT AND DELAY FLIP-FLOP - Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween. | 2012-08-02 |
| 20120194247 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first master-slave flip-flop having a first master latch which receives and latches first data signal in synchronism with first clock and a first slave latch which receives and latches the first data signal from the first master latch in synchronism with second clock; and a second master-slave flip-flop disposed side by side with the first master-slave flip-flop and having a second master latch which receives and latches second data signal in synchronism with third clock and a second slave latch which receives and latches the second data signal from the second master latch in synchronism with fourth clock, and wherein the second slave latch of the second master-slave flip-flop is disposed adjacent to the first master latch of the first master-slave flip-flop and the second master latch of the second master-slave flip-flop is disposed adjacent to the first slave latch of the first master-slave flip-flop. | 2012-08-02 |
| 20120194248 | NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA STROBE - A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects. | 2012-08-02 |
| 20120194249 | Semiconductor Integrated Circuit - According to an embodiment, a semiconductor integrated circuit includes a first clock domain driven at a first frequency, a second clock domain adjacent to the first clock domain and driven at a second frequency which is different from the first frequency, a signal line provided between the first clock domain and the second clock domain, first and second DF/Fs connected to the first signal line and provided for the first clock domain and the second clock domain respectively and first and second multiplexers provided in correspondence with the first and the second DF/Fs respectively, to select one of the first frequency and the second frequency and output the selected frequency to the first and the second DF/Fs. | 2012-08-02 |
| 20120194250 | MULTIPLEXER CIRCUIT WITH LOAD BALANCED FANOUT CHARACTERISTICS - A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit. | 2012-08-02 |
| 20120194251 | RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD AND TEST METHOD - Provided is a receiving apparatus that receives a data signal and a clock signal indicating a reference timing to acquire the data signal. The receiving apparatus includes a multi-strobe generating section that generates, based on a pulse of the recovered clock, a plurality of strobes of which phases are different from each other, a first detecting section that detects a position of an edge of the clock signal relative to the strobes based on values of the clock signal that are acquired at respective timings of the strobe, a first adjusting section that adjusts a phase of the recovered clock according to the edge position of the clock signal, and a second adjusting section that adjusts the timing to acquire the data signal according to a phase adjustment amount of the recovered clock made by the first adjusting section. | 2012-08-02 |
| 20120194252 | METHOD OF SHIFTING AUTO-ZERO VOLTAGE IN ANALOG COMPARATORS - Aspects of the invention provide, inter alia, techniques for shifting auto-zero voltage in analog comparators. An embodiment of the invention may include at least one diode configured transistor to increase a drain voltage of at least one NMOS load transistor. A first switch and a second switch may be implemented to increase a voltage at a gate of a first PMOS input transistor and a voltage at a gate of a second PMOS input transistor when the first switch and the second switch are closed. | 2012-08-02 |
| 20120194253 | High Voltage Tolerant Differential Receiver - A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry. | 2012-08-02 |
| 20120194254 | High Voltage Tolerant Receiver - A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit. | 2012-08-02 |
| 20120194255 | MULTIVOLTAGE CLOCK SYNCHRONIZATION - A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal. | 2012-08-02 |
| 20120194256 | LEVEL SHIFTER - A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal. | 2012-08-02 |
| 20120194257 | CONTINUOUS-TIME CIRCUIT AND METHOD FOR CAPACITANCE EQUALIZATION BASED ON ELECTRICALLY TUNABLE VOLTAGE PRE-DISTORTION OF A C-V CHARACTERISTIC - A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 2012-08-02 |
| 20120194258 | ADAPTIVE THERMAL COMPENSATION CIRCUIT AND METHOD - For thermal compensation for an intrinsic element in a system, a circuit and method are proposed to predict the temperature variation caused by power loss of the intrinsic element, in addition to sense the external environment temperature variation of the intrinsic element, and thus sense the operational temperature of the intrinsic element more precisely. | 2012-08-02 |
| 20120194259 | TOUCH PANEL WITH INTERFERENCE SHIELDING ABILITY - A touch panel with interference shielding ability mainly has a substrate with four edges and a transparent electrode formed on a top surface of the substrate. The substrate is rectangular and transparent. The transparent electrode has an active area with four edges. A routing region is defined between the edges of the active area and the edges of the substrate. A structure of compensating impedance is formed on the routing region. An anti-interference layer is formed on the top surface or a bottom surface corresponding to the routing region. The compensating impedance on the routing region forms a shield. The interference induced by directly touching the routing region is avoided for determination of coordinates of a touch point. | 2012-08-02 |
| 20120194260 | SEMICONDUCTOR DEVICE HAVING PLURAL OPTICAL FUSES AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range. | 2012-08-02 |
| 20120194261 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 2012-08-02 |
| 20120194262 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - Data is written in the following manner: potentials of first and second control gates of a transistor are set at a potential for making a storage gate of the transistor a conductor, a potential of data to be stored is supplied to the storage gate, and at least one of the potentials of the first and second control gates is set at a potential for making the storage gate an insulator. Data is read in the following manner: the potential of the second control gate is set at a potential for making the storage gate an insulator; a potential is supplied to a wiring connected to one of a source and a drain of the transistor; then, a potential for reading is supplied to the first control gate to detect a change in the potential of a bit line connected to the other of the source and the drain. | 2012-08-02 |
| 20120194263 | CHARGE PUMP AND METHOD OF BIASING DEEP N-WELL IN CHARGE PUMP - A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), and is coupled to at least one capacitor, an input node, and an output node. The input node is arranged to receive an input signal. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the output node, and the DNW is arranged to float for a positive pump operation. | 2012-08-02 |
| 20120194264 | CURRENT MIRROR AND CURRENT CANCELLATION CIRCUIT - Techniques are described to mirror currents and subtract currents accurately. In an implementation, a circuit includes a first current source coupled to a first node to provide a current IPD | 2012-08-02 |
| 20120194265 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD OF THE SAME - The present invention is directed to accurately set a frequency characteristic of a filter integrated in a semiconductor integrated circuit. A semiconductor integrated circuit includes a filter circuit, a cutoff frequency calibration circuit, and a Q-factor calibration circuit. The cutoff frequency calibration circuit adjusts cutoff frequency of the filter circuit to a desired value by adjusting capacitance components of the filter circuit. After adjustment of the cutoff frequency of the filter circuit by the cutoff frequency calibration circuit, the Q-factor calibration circuit adjusts the Q factor of the filter circuit to a desired value by adjusting a resistance component of the filter circuit. | 2012-08-02 |
| 20120194266 | Reduction of the Sensitivity to the Jitter Demodulation of the Sampling Clock Signal - The invention relates to a method for the demodulation of a radiofrequency signal (Y), that comprises the steps of: providing a synchronous sampling clock signal (HE) of said radiofrequency signal to be demodulated; sampling said radiofrequency signal using said sampling clock signal; and processing the samples thus obtained in order to determine the phase and/or amplitude of said radiofrequency signal; characterized in that it further comprises the step of adjusting the phase, as measured relative to the sampling clock signal, of said signal to be demodulated and/or of a synchronous reference signal (R) relative to which the signal is demodulated in order to minimize the phase and/or amplitude error generated by a jitter of said sampling clock signal. The invention also relates to a demodulator circuit for implementing said method. | 2012-08-02 |
| 20120194267 | DISTRIBUTED AMPLIFIER FOR BAND PASS RADIO FRONT-END - A distributed amplifier is provided that is broadband and band pass with controllable bandwidth. In the distributed amplifier circuit, termination impedance of the input transmission line is not matched with the characteristics impedance of the input transmission line and/or the termination impedance of the output transmission line is not matched with the characteristics impedance of the output transmission line, thus providing the broadband and band pass with controllable bandwidth attributes. | 2012-08-02 |
| 20120194268 | DIFFERENTIAL VOLTAGE SENSING METHOD - A differential voltage sensing method for achieving input impedance matching comprises the steps of: providing a first bio-potential signal to a first variable resistor for generating a first signal; providing a second bio-potential signal to a second variable resistor for generating a second signal; differentially amplifying first and second signals for generating a third signal; selecting an operation band of the third signal for generating first and second logic signals; and dynamically adjusting one of the impedances of the first and second variable resistors according to the first and second logic signals, wherein each of the first and second bio-potential signals has a common signal voltage level and a differential signal voltage level. | 2012-08-02 |
| 20120194269 | PASSIVE AMPLIFIER - A passive amplifier for use with enhanced power supplies, signal preamplifiers and power amplifiers in communications systems particularly in mobile phones, laptop computers and other battery-powered and battery-limited devices. The passive amplifier can be used as an attachment to electric appliances or other power consuming equipment to significantly reduce the electric power requirements of such equipment. These passive amplifiers do not require an outside source of power and can be used to elevate battery power outputs and serve as either low noise signal preamplifiers or transmit power amplifiers for higher performance and extended battery life. Passive amplifier technology is either electromagnetic or dielectric in nature with component parts limited to inductive, capacitive and resistive components. Dielectric amplifier prototypes have gain values in the range of the 10 dB level so as to be useful in communications applications and power amplification. | 2012-08-02 |
| 20120194270 | Broadband Linearization Module And Method - A system including a power amplifier and a pre-distortion module coupled to the power amplifier. The pre-distortion module includes one or more smaller versions of the power amplifier to generate a pre-distortion signal that compensates for any memory-effect or inertia present in the power amplifier with application on frequency hopping and larger (up to 1 octave) instantaneous bandwidth communication systems. | 2012-08-02 |
| 20120194271 | AMPLIFYING DEVICE AND WIRELESS TRANSMISSION DEVICE USING THE SAME - An amplifying device | 2012-08-02 |
| 20120194272 | RF POWER AMPLIFIER INCLUDING BROADBAND INPUT MATCHING NETWORK - An RF power amplifier is disclosed that has improved input matching or reduced return losses over a wider frequency range. The amplifier includes an input impedance matching network, a resistive element, a transistor, and an output impedance matching network. The resistive element is coupled between the input impedance matching network and the input of the transistor. The resistive element is configured to lower the quality factor (Q) of the input impedance matching network. This has the effect of reducing the input impedance variation over a given frequency range. As a result, the overall impedance matching over the given frequency range is improved, thereby reducing the input return losses. This allows the RF power amplifier to be used in wider bandwidth applications. | 2012-08-02 |
| 20120194273 | DIFFERENTIAL RECEIVER - A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained. | 2012-08-02 |
| 20120194274 | INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD FOR PROVIDING A POWER SUPPLY - An integrated circuit is described for providing a power supply to a radio frequency (RF) power amplifier (PA). The integrated circuit includes a low-frequency power supply path including a switching regulator and a high-frequency power supply path arranged to regulate an output voltage of a combined power supply at an output port of the integrated circuit for coupling to a load. The combined power supply is provided by the low-frequency power supply path and high-frequency power supply path. The high-frequency power supply path includes: an amplifier including a voltage feedback and arranged to drive a power supply signal on the high-frequency power supply path; and a capacitor operably coupled to the output of the amplifier and arranged to perform dc level shifting of the power supply signal. | 2012-08-02 |
| 20120194275 | Distributed Doherty Amplifiers - Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module. | 2012-08-02 |
| 20120194276 | Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors - A low noise amplifier includes a first Group III-nitride based transistor and a second Group III-nitride based transistor coupled to the first Group III-nitride based transistor. The first Group III-nitride based transistor is configured to provide a first stage of amplification to an input signal, and the second Group III-nitride based transistor is configured to provide a second stage of amplification to the input signal. | 2012-08-02 |
| 20120194277 | OSCILLATION DEVICE - To perform, in an oscillation device compensating an output frequency based on a detection result of ambient temperature, temperature compensation of the output frequency with high accuracy. First and second quartz-crystal oscillators are structured by using a common quartz-crystal piece, and when oscillation outputs of first and second oscillation circuits respectively connected to these quartz-crystal oscillators are set to f | 2012-08-02 |
| 20120194278 | TEMPERATURE CORRECTING CURRENT-CONTROLLED RING OSCILLATORS - A thermally-compensated oscillator has a current reference with an output current which relates to an ambient temperature with a first relationship, a ring oscillator having an operating frequency which relates to the ambient temperature with a second relationship, and which receives the output current of the current reference and outputs an oscillator signal, and a level shifter which receives the oscillator signal from the ring oscillator and outputs a corresponding voltage-regulated clock signal. | 2012-08-02 |
| 20120194279 | RELAXATION OSCILLATOR HAVING A SUPPLY VOLTAGE INDEPENDENT OUTPUT FREQUENCY - Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator. | 2012-08-02 |
| 20120194280 | OSCILLATION DEVICE - An oscillation device capable of highly accurate temperature compensation of an output frequency is provided. The oscillation device includes: first and second oscillator circuits oscillating first and second quartz-crystal resonators with overtones respectively; a frequency difference detecting part finding a value corresponding to a difference value between values corresponding to differences between f | 2012-08-02 |
| 20120194281 | Oscillation-Stop Detection Circuit, Semiconductor Device, Timepiece, And Electronic Device - An oscillation-stop detection circuit can be manufactured at low cost without requiring controlling difficult manufacturing process conditions. Inverter | 2012-08-02 |
| 20120194282 | INTERNALLY TRANSDUCED PN-DIODE-BASED ULTRA HIGH FREQUENCY MICROMECHANICAL RESONATOR - A radio frequency microelectromechanical (RF MEMS) device can comprise an actuation p-n junction and a sensing p-n junction formed within a semiconductor substrate. The RF MEMS device can be configured to operate in a mode in which an excitation voltage is applied across the actuation p-n junction varying a non-mobile charge within the actuation p-n junction to modulate an electric field acting upon dopant ions and creating electrostatic forces. The electrostatic forces can create a mechanical motion within the actuation p-n junction. The mechanical motion can modulate a depletion capacitance of the sensing p-n junction, thereby creating a motional current. At least one of the p-n junctions can be located at an optimal location to maximize the efficiency of the RF MEMS device at high resonant frequencies. | 2012-08-02 |
| 20120194283 | VIBRATOR ELEMENT, VIBRATOR, OSCILLATOR, AND ELECTRONIC APPARATUS - A vibrator element includes a base section, vibration arms, and excitation electrodes provided to the respective vibration arms, the excitation electrodes each include a first electrode disposed on a principal surface side of the vibration arm, a second electrode disposed so as to be opposed to the first electrode, and a piezoelectric body extending between the first electrode and the second electrode, and ITO is used as at least one of the first electrode and the second electrode. | 2012-08-02 |
| 20120194284 | OSCILLATION CIRCUIT HAVING SHIELD WIRE, AND ELECTRONIC APPARATUS - There is provided an oscillation circuit including a crystal vibrator that is connected between input and output terminals of a CMOS inverter making up the oscillation circuit; an input wiring line that includes a crystal vibrator-side input terminal connected to an input terminal pad of the CMOS inverter; an output wiring line that includes a crystal vibrator-side output terminal connected to an output terminal pad of the CMOS inverter; a ground power source wiring line that includes a crystal vibrator-side ground power source terminal; and a capacitative element that is connected between the input wiring line and the ground power source wiring line, and between the output wiring line and the ground power source wiring line, wherein the ground power source wiring line is disposed at least a part of between the input wiring line and the output wiring line. | 2012-08-02 |
| 20120194285 | VIBRATOR ELEMENT, VIBRATOR, OSCILLATOR, AND ELECTRONIC DEVICE - A vibrator element includes: a base portion; and three vibrating arms that extend from the base portion in the Y axis direction. The vibrating arms are arranged in the X axis direction, include excitation electrodes on a principal face, and vibrate in the Z axis direction . When an arm width of the vibrating arm, which is located at the center of the arrangement, in the X axis direction is W1, each arm width of the other vibrating arms in the X axis direction is W, an electrode width of the excitation electrode of the vibrating arm, which is located at the center of the arrangement, in the X axis direction is Al, and each electrode width of the excitation electrodes of the other vibrating arms in the X axis direction is A, 1.35| 2012-08-02 | |
| 20120194286 | METHODS AND SYSTEMS FOR MEMS CMOS DEVICES HAVING ARRAYS OF ELEMENTS - Systems and methods for manufacturing a chip comprising a plurality of MEMS devices arranged in an integrated circuit are provided. In one aspect, the systems and methods provide for a chip including electronic elements formed on a semiconductor material substrate. The chip further includes a stack of interconnection layers including layers of conductor material separated by layers of dielectric material. MEMS devices are formed within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material positioned highest in the stack of interconnection layers. The stack of interconnection layers includes at least one unetched layer of dielectric material, and at least one layer of conductor material for routing connections to and from the electronic elements. | 2012-08-02 |
| 20120194287 | RADIO FREQUENCY DRIVE LEVEL CONTROL SYSTEM AND METHOD FOR AN ELECTRO-OPTIC PHASE MODULATOR - The present disclosure provides Radio Frequency (RF) drive level control systems and methods for an Electro-Optic (EO) M-ary Phase-Shift Keying (M-PSK) phase modulator. Specifically, an M-PSK drive waveform is tightly controlled for maximum symmetry in the associated constellation. In an exemplary embodiment, the present disclosure includes an M-PSK transmitter, an M-PSK electro-optic phase modulator, and phase modulation method that each control RF drive level based upon a carrier suppression ratio defined as a measure of ratio of a modulated time-averaged E-field to the magnitude of the E-field. In an exemplary embodiment, the carrier suppression ratio is measured based on a modulation depth measurement. | 2012-08-02 |
| 20120194288 | Two-Terminal Modulator - The invention is an electronic Two-Terminal Modulator. It is used electrically in series between a Power Source and a Target Device, and can modulate the power that is sent to the Target Device, at speeds and with modulating complexity that exceed present capability. The invention includes implementation of the modulator as a unit that is inserted into or appended to another device and is used to modulate the power in the other device. | 2012-08-02 |
| 20120194289 | FREQUENCY MODULATION FEEDBACK SYSTEM - A frequency modulation feedback system applied to an actuation device composed of a carrier and a drive unit for driving the carrier. The frequency modulation feedback system includes: a feedback device for reading a feedback signal of the carrier and transmitting the feedback signal; a control section for receiving and reading the feedback signal to drive the drive unit; a passage, the feedback signal being transmitted from the feedback device via the passage to the control section; and a modulation device for modulating the waveform of the transmitted feedback signal. After the feedback device reads the feedback signal, the feedback device first transmits the feedback signal to the modulation device for the modulation device to change the waveform of the feedback signal. Then the feedback signal is transmitted via the passage to the control section for reading. | 2012-08-02 |
| 20120194290 | ELECTROMAGNETIC NOISE SUPPRESSION CIRCUIT - An electromagnetic noise suppression circuit is provided. The suppression circuit comprises a first substrate, a first grounding plane and at least one transmission line. The transmission line is configured on a top surface of the first substrate and the first grounding plane is configured on the bottom surface of the first substrate. The first grounding plane comprises a first distributed coupling structure. The first distributed coupling structure and the transmission line can be equivalent to an inductor-capacitor resonant circuit. The electromagnetic noise within a designated frequency band can be suppressed by the distributed coupling structure of the electromagnetic noise suppression circuit to avoid interfering the signal transmitted by the transmission line and the electromagnetic radiation induced by the electromagnetic noise. | 2012-08-02 |
| 20120194291 | COMMON-MODE SUPPRESSION FILTER FOR MICROSTRIP 10-Gb/s DIFFERENTIAL LINES - Several implementations disclosed herein are directed to compact-size common-mode filters that are suitable for implementation in densely populated multilayered printed circuit boards (PCBs) with numerous I/O ports—as well as integrated circuit (IC) chips and I/O connectors—to suppress EMI emissions. Certain implementation are specifically directed to filters for four differential signal lines that carry 10-Gb/s digital signals. These implementations provide common-mode suppression within gigahertz frequencies where common-mode noise comprising 10-Gb/s signal is problematic, but without any significant degradation of differential-mode signals. Moreover, certain of these implementations are directed to compact-size filters that suppress common-mode signal noise at 10.3 GHz associated with the fundamental harmonic 10 Gb/s-signals of XFI and SFI. In other implementations, a combination of filters is presented to provide common-mode noise suppression at both the first harmonic frequency of 10.3 GHz as well as the second harmonic frequency of 20.6 GHz. | 2012-08-02 |
| 20120194292 | HIGH AND LOW SPEED SERIAL INTERFACE MULTIPLEXING CIRCUIT - A high and low speed serial interface multiplexing circuit includes a low speed transceiver, a high speed transceiver, an inductor coupled to a communication interface port of the low speed transceiver, a capacitor coupled to a communication interface port of the high speed transceiver, and a transformer coupled to the communication interface port of the high speed transceiver. | 2012-08-02 |
| 20120194293 | IMPROVEMENT OF THE SELECTIVITY OF A DUAL COUPLER - A directional dual distributed coupler including: a first conductive line between first and second ports, intended to convey a signal to be transmitted in a first frequency band; a second conductive line coupled to the first one; a third conductive line between third and fourth ports, intended to convey a signal to be transmitted in a greater frequency band than the first one; a fourth conductive line coupled to the third one; and at least one diplexer connecting, on the side of the second and fourth ports, the respective ends of the second and fourth lines to a fifth port. | 2012-08-02 |
| 20120194294 | DUPLEXER - A duplexer includes a package substrate having layers stacked, a transmission filter and a reception filter that are provided on an upper surface of a first layer that is one of the layers of the package substrate, the transmission and reception filters being acoustic wave filters, a metal pattern provided on the upper surface of the first layer and formed to surround the transmission and reception filters, a transmission line provided on an upper surface of a second layer that is one of the layers of the package substrate and is positionally lower than the first layer, the transmission line electrically connecting the transmission filter and a transmission terminal together, and a reception line that is provided on the upper surface of the second layer and electrically connects the reception filter and a reception terminal. The thickness of the first layer is greater than that of the second layer. | 2012-08-02 |
| 20120194295 | PHASE SHIFTER WITH REVERSELY CONFIGURED ELECTRIC REGULATION UNITS - The present invention provides a phase shifter with reversely configured electric regulation units. The phase shifter has a chamber with a holding space, a first feeder unit and a second feeder unit at the sides of the holding space, and at least one reversely configured electric regulation unit. The regulation unit contains a first coupling set with a movable and a fixed coupling, and a second coupling set with a movable and a fixed coupling. A sync linkage mechanism is used to link the respective movable couplings. A push-pull unit is linked to a driven connection of the sync linkage mechanism. A cover plate seals the holding space. The phase shifter configuration makes it possible to reduce markedly the volume and space of the phase shifter, cut down the manufacturing cost and improve the mating accuracy with higher applicability. | 2012-08-02 |
| 20120194296 | SIMULTANEOUS PHASE AND AMPLITUDE CONTROL USING TRIPLE STUB TOPOLOGY AND ITS IMPLEMENTATION USING RF MEMS TECHNOLOGY - This invention relates to techniques for controlling the amplitude and the insertion phase of an input signal in RF applications. More particularly, this invention relates to phase shifters, vector modulators, and attenuators employing both semi-conductor and RF microelectromechanical systems (MEMS) technologies. | 2012-08-02 |
| 20120194297 | ACOUSTIC RESONATOR STRUCTURE COMPRISING A BRIDGE - An acoustic resonator comprises a first electrode a second electrode and a piezoelectric layer disposed between the first and second electrodes. The acoustic resonator further comprises a reflective element disposed beneath the first electrode, the second electrode and the piezoelectric layer. An overlap of the reflective element, the first electrode, the second electrode and the piezoelectric layer comprises an active area of the acoustic resonator. The acoustic resonator also comprises a bridge adjacent to a termination of the active area of the acoustic resonator. | 2012-08-02 |
| 20120194298 | Filter Circuit Having Improved Filter Characteristic - A ladder-type-like filter circuit is specified with improved filter behavior. Inductive elements that interconnect parallel resonators with ground are electromagnetically coupled to one another. | 2012-08-02 |
| 20120194299 | LOW PASS FILTER - A low pass filter includes a signal transmission line, a first open stub, a second open stub, a first coupling line, and a second coupling line. The signal transmission line is connected between a first port and a second port, and operable to transmit RF signals from the first port to the second port. The signal transmission line defines a first side and a second side opposite to the first side. The first open stub and the second stub are disposed on the first side and perpendicularly connected to the signal transmission line. The second open stub and the first open stub co-define a T-shaped gap. The first coupling line is parallel to the signal transmission line and disposed in the T-shaped gap. The second coupling line is parallel to the signal transmission line and disposed on the second side of the signal transmission line. | 2012-08-02 |
| 20120194300 | COMMUNICATION SHEET STRUCTURE AND INFORMATION MANAGEMENT SYSTEM - To provide a communication sheet structure that is used in combination with an IC tag, has stable read rate and can be easily introduced and installed on an existing shelf, and also an information management system using the same. | 2012-08-02 |
| 20120194301 | CAPACITIVE COUPLER PACKAGING STRUCTURE - Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor. | 2012-08-02 |
| 20120194302 | STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE - A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance. | 2012-08-02 |
| 20120194303 | PRECISION WAVEGUIDE INTERFACE - A waveguide interface and a method of manufacturing is disclosed. The interface includes a support block that has a printed circuit board. A communication device is coupled to the circuit board. A launch transducer is positioned adjacent to and coupled to the communication device. The launch transducer includes one or more transmission lines in a first portion and at least one antenna element in a second portion. The antenna element radiates millimeter wave frequency signals. An interface plate coupled to the support block has a rectangular slot having predetermined dimensions. A waveguide component is coupled to the interface plate and has a waveguide opening. The first portion of the launch transducer is positioned within the slot such that the slot prevents energy from the transmission line from emitting toward the circuit board or the waveguide opening but allows energy to pass from the antenna element into the waveguide opening. | 2012-08-02 |
| 20120194304 | Equalizer Circuit and Printed Circuit Board - An equalizer circuit includes a passive equalizer having an inductor connected in parallel to a signal interconnection line, the inductor being made up of a conductor portion formed on a side face of a through-hole of a circuit board. | 2012-08-02 |
| 20120194305 | TUNER MODULE - A tuner module is characterized by: a chassis formed with lateral surfaces wrapping four corners to open both sides; an upper cover covering one opened side of the chassis to be provided with an elastic fixation end that is fixed at the lateral surface; and a lower cover applying pressure to an external surface of the elastic fixation end to cover the other opened side of the chassis whereby another elastic hitching end that is fixed at the lateral surface is provided. | 2012-08-02 |
| 20120194306 | PREVENTING CONTACT STICTION IN MICRO RELAYS - A micro relay of a micro-electro-mechanical system (MEMS), includes a cap substrate, a first electrical contact, an actuator, and a second electrical contact. The first electrical contact is formed on the cap substrate, includes a platinum group metal, and includes a first surface layer of an oxide of the platinum group metal. The second electrical contact is formed on the actuator, includes the platinum group metal, and includes a second surface layer of the oxide of the platinum group metal. At least a first portion of the first surface layer contacts at least a second portion of the second surface layer during cycling of the micro relay. | 2012-08-02 |
| 20120194307 | HIGH SECURITY SWITCH ASSEMBLY - Tamper-resistant switch assemblies ( | 2012-08-02 |
| 20120194308 | FOLDABLE ACCESSORY DEVICE - A magnetic attachment mechanism and method is described. The magnetic attachment mechanism can be used to releasably attach at least two objects together in a preferred configuration without fasteners and without external intervention. The magnetic attachment mechanism can be used to releasably attach an accessory device to an electronic device. The accessory device can be used to augment the functionality of usefulness of the electronic device. | 2012-08-02 |
| 20120194309 | MAGNETIC POWDER MATERIAL, LOW-LOSS COMPOSITE MAGNETIC MATERIAL CONTAINING SAME, AND MAGNETIC ELEMENT USING SAME - The present invention provides a material which can be used for low pressure molding, and which has a low core loss while maintaining the characteristic of an amorphous powder that is the high coercive force. It provides a magnetic powder material containing, relative to the weight thereof, amorphous powders of 45 to 80 wt %, crystalline powders of 55 to 20 wt %, and a bonding agent. The magnetic powder material contains, relative to the mass thereof, Si of 4.605 to 6.60 mass %, Cr of 2.64 to 3.80 mass %, C of 0.225 to 0.806 mass %, Mn of 0.018 to 0.432 mass %, B of 0.99 to 2.24 mass %, P of equal to or less than 0.0248 mass %, S of equal to or less than 0.0165 mass %, Co of equal to or less than 0.0165 mass %, and a balance of Fe and inevitable impurities. | 2012-08-02 |
| 20120194310 | PERMANENT MAGNET AND MANUFACTURING METHOD THEREOF - There are provided a permanent magnet and a manufacturing method thereof capable of densely sintering the entirety of the magnet without making a gap between a main phase and a grain boundary phase in the sintered magnet. To fine powder of milled neodymium magnet is added an organometallic compound solution containing an organometallic compound expressed with a structural formula of M- (OR) | 2012-08-02 |
| 20120194311 | CORE FIXING MEMBER AND COIL DEVICE - A core fixing member including: a core fixing part that has a plate-like shape and is to be fixed to a core; a case fixing part that has a plate-like shape and is to be fixed to a case; and at least one an arm part connecting the case fixing part with the core fixing part, and wherein the core fixing part and the case fixing part are arranged in a same plane, and the at least one arm part is formed in a shape of a letter ‘U’, and one end of the at least one arm part is connected to the core fixing part and the other end of the at least one arm part is connected to the case fixing part. | 2012-08-02 |
| 20120194312 | APPARATUS AND METHOD FOR GENERATING ELECTRIC ENERGY IN AN ELECTRIC POWER TRANSMISSION SYSTEM - Apparatus and method for generating electric energy in an electric power transmission system includes an AC cable including a core, wherein a portion of the core is partially surrounded by an apparatus including a ferromagnetic body and an electrically conducting winding. The ferromagnetic body extends along a longitudinal axis and has, in a cross section taken along said longitudinal axis, a shape defined by an arc. The electrically conducting winding is wound around the ferromagnetic body to form turns in planes substantially perpendicular to the arc. | 2012-08-02 |
| 20120194313 | AC POWER CONDITIONING CIRCUIT - A multi-coil choke for an AC power conditioner includes a magnetic core having first, second and third parallel legs. A first coil wrapped around the first leg terminates in first and second leads at respective ends. A second coil wrapped around the second leg terminates in first and second leads at respective ends. A third coil wrapped around the third leg terminates in first and second leads at respective ends. A fourth coil is formed from a proximal portion of the second lead of said first coil. The fourth coil is wrapped around a distal portion of the second lead of the third coil. A fifth coil is formed from a proximal portion of the second lead of the third coil. The fifth coil is wrapped around a distal portion of the second lead of the first coil. AC power conditioners using one or more such chokes are also disclosed. | 2012-08-02 |
| 20120194314 | LOW-PROFILE INDUCATOR AND ITS FABRICATION METHOD - A low-profile inductor includes
| 2012-08-02 |
| 20120194315 | Three-Function Reflowable Circuit Protection Device - A circuit protection device is configured to protect circuit elements under any one of the following three activation conditions: an over current condition, an over temperature condition, and an activation control current received by a heater element. The circuit element includes first and second electrodes, and the heater element. A sliding contact is connected by a sensing element to the first electrode, second electrode, and heater element, thereby bridging and providing a conductive path between each. A spring element is held in tension by, and exerts a force against, the sliding contact. Upon detection of any one of three activation conditions, the sensing element releases the sliding contact and the force exerted by the spring element moves the sliding contact to another location on the substrate at which the sliding contact no longer provides a conductive path between the first electrode, second electrode, and heater element. | 2012-08-02 |
| 20120194316 | FUSE BOX STRUCTURE IN SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - A fuse box structure includes a first fuse, an insulating film formed on the first fuse, and a second fuse disposed on the insulating film to partially overlap the first fuse. Each of the first and second fuse includes a main portion and one or more cutting portions connected to the main portion. The configuration of the first and second fuse requires a reduced area of occupancy of the fuse box structure. | 2012-08-02 |
| 20120194317 | Three-Function Reflowable Circuit Protection Device - A circuit protection device includes a substrate with first and second electrodes connected to the circuit to be protected. The circuit protection device also includes a heater element between the first and second electrodes. A sliding contact is connected by a sensing element to the first electrode, second electrode, and heater element, thereby bridging and providing a conductive path between each. A spring element is held in tension by, and exerts a force parallel to a length of the substrate against, the sliding contact. Upon detection of an activation condition, the sensing element releases the sliding contact and the force exerted by the spring element moves the sliding contact to another location on the substrate at which the sliding contact no longer provides a conductive path between the first electrode, second electrode, and heater element. | 2012-08-02 |
| 20120194318 | Variable resistor device for display device and method of controlling variable resistance using the same - A display device includes a display panel on which a pixel electrode and a common electrode are patterned, and a variable resistor configured to vary a common voltage applied to the common electrode. The variable resistor includes a variable resistance control unit configured to control resistances between resistance terminals that are electrically connected to one another. The variable resistance control unit includes a crown unit, a crown axis combined with the crown unit and configured to guide up/down movement of the crown unit, a first motion variable unit combined with the crown axis, a second motion variable unit selectively combined with the first motion variable unit and configured to vary a variable resistance due to rotary power transmitted from the crown unit, and a housing unit configured to accommodate the crown unit, the crown axis, the first motion variable unit, and the second motion variable unit | 2012-08-02 |
| 20120194319 | Automatic Teller Machine Capable of Performing Remote Controlling Function and Opening and Closing Operation Method of Automatic Teller Machine Using Same - The present invention relates to an automatic teller machine (ATM) capable of control with a remote controller and an opening and closing operation method of the automatic teller machine using the same. In addition, the invention provides an automatic teller machine capable of performing a remote control function and an opening and closing operation method of the automatic teller machine using the same, which can enable the user to easily control power on/off, module reset, and rebooting operations of the automatic teller machine with a remote controller, thereby quickly and simply carrying out the opening and closing operations of the automatic teller machine, which were complicated and took a lot of time in the past, and easily performing some processes for maintaining the automatic teller machine. Further, the invention provides an automatic teller machine capable of performing a remote control function, comprising: a plurality of buttons and an automatic teller machine body equipped with a short-range wireless receiving device; and a remote controller which can execute the short-range wireless communication with the automatic teller machine body, wherein a system controlling program stored in the automatic teller machine body is activated through the remote controller in such a manner that the opening and closing operations of the automatic teller machine are conducted automatically through the button operation of the remote controller. | 2012-08-02 |
| 20120194320 | DATA COLLECTION SYSTEM HAVING RECONFIGURABLE DATA COLLECTION TERMINAL - There is provided in one embodiment a data collection system including a data collection terminal having an encoded information reader device and a computer spaced apart from the data collection terminal. The data collection terminal in one embodiment can be configured to be responsive to configuration data expressed in an extensible markup language. | 2012-08-02 |
| 20120194321 | IC TAG, METHOD OF CONTROLLING THE IC TAG, AND IC TAG SYSTEM - To provide an IC tag, a method of controlling the IC tag, and an IC tag system which can reduce a communication sequence between the reader/writer and the IC tag and can shorten a communication period or a period necessary for executing the command. According to an embodiment of the invention, an IC tag that executes a command processing based on a command received from a redder/writer, includes: a command analyzing unit determining an execution condition of the command received from the redder/writer; and a command execution unit executing a first command processing if the execution condition is met, and executing a second command processing different from the first command processing if the execution condition is not met. | 2012-08-02 |
| 20120194322 | LONG RANGE RFID DEVICE AS MODEM AND SYSTEMS IMPLEMENTING SAME - A Radio Frequency Identification (RFID) system according to one embodiment of the present invention includes an RFID device having a memory; and an electronic device in electrical communication with the RFID device via a direct physical connection; wherein data received by the RFID device from a remote device is stored in the memory of the RFID device, the data being communicated to the electronic device via the direct physical connection. An RFID system according to another embodiment of the present invention includes an RFID device having a memory; and an electronic device in electrical communication with the RFID device via a direct physical connection; wherein data initiating with the electronic device is stored in the memory of the RFID device for subsequent transmission to a remote device. Methods are also provided. | 2012-08-02 |
| 20120194323 | Method for Wireless Data Transmission Between a Base Station and a Passive Transponder, as Well as a Passive Transponder - A method for wireless data transmission, in, for example, RFID systems, between a base station and a passive transponder, as well as a passive transponder is provided by inductive coupling, as well as a passive transponder. It is possible to transmit data from the base station to the transponder by a first data transmission protocol type and by at least one second data transmission protocol type, whereby the first or the at least second data transmission protocol type is selected by writing a configuration register in the transponder. | 2012-08-02 |
| 20120194324 | DIRECTION AND HOLDING-STYLE INVARIANT, SYMMETRIC DESIGN, AND TOUCH- AND BUTTON-BASED REMOTE USER INTERACTION DEVICE - A remote control unit selectively transmits a control signal for remotely controlling an electronic device. The unit defines an imaginary cut plane that substantially bisects the unit. The unit includes a plurality of input features collectively disposed symmetrically with respect to the imaginary cut plane. The input features include a first and second input feature. The first and second input features are disposed on opposite sides of the cut plane. Furthermore, the unit includes a sensor that detects a first and second holding position of the unit. The first holding position and the second holding position are substantially opposite to each other. Moreover, the unit includes a controller that associates the control signal with the first input feature when the sensor detects the first holding position, and the controller associates the control signal with the second input feature when the sensor detects the second holding position. | 2012-08-02 |
| 20120194325 | SYSTEM AND METHOD FOR SIMPLIFIED SETUP OF A UNIVERSAL REMOTE CONTROL - A system and method for enabling set up of a controlling device capable of controlling a plurality of appliances, via an interactive instruction set and associated programming. The programming is accessible by a STB or other controllable appliance and is configured to appropriately display interactive instructions and prompts to a user during a user initiated set up procedure for configuration of another controllable device (e.g., DVD, VCR, DVR, etc) available to the user. Appropriate set up data, generally in the form of command library codes, is displayed to the user by the interactive instruction set and associated programming for entry and trial by the user in set up of the desired appliance(s). | 2012-08-02 |
| 20120194326 | Remote Controller and Method of Controlling Light Emission From Light-Emitting Unit Thereof - When a key input acknowledging unit acknowledges user input from a valid key enabled to control a first electronic device, a light-emission control unit causes a first light-emitting unit for a first selection key to emit light. On the other hand, when the key input acknowledging unit acknowledges user input from a control key other than the valid key, the light-emission control unit causes a second light-emitting unit for a second selection key or a third light-emitting unit for a third selection key to emit light. | 2012-08-02 |
| 20120194327 | USER STATION FOR HEALTHCARE COMMUNICATION SYSTEM - A user station configurable for use in a healthcare communication system, such as a nurse call system, is provided. | 2012-08-02 |
| 20120194328 | VEHICLE APPROACH WARNING APPARATUS - A vehicle warning apparatus has a vehicular horn disposed in an overlapping arrangement with a supersonic speaker, such that the vehicular horn is positioned between the supersonic speaker and a heat exchanger. The vehicular horn blocks the supersonic speaker from heat produced by the heat exchanger, which prevents the temperature of the supersonic speaker from increasing. Accordingly, troubles such as frequency change of supersonic wave output from the speaker and/or decrease of speaker's product life, without deteriorating heat dissipation capacity of the heat exchanger, are prevented. Furthermore, collective arrangement of the supersonic speakers on a single board attached on the vehicular horn improves the install-ability of the vehicle warning apparatus in the vehicle, and improves the directional reach of the supersonic wave. | 2012-08-02 |
| 20120194329 | SOUND WAVE GENERATOR - A sound wave generator includes a speaker control circuit and a speaker. The speaker control circuit includes a signal generating unit that is configured to generate an electric signal having a humming frequency property. The humming frequency property includes a plurality of frequencies that have an overtone relationship with respect to A Hz and are pitched at the A Hz, the A Hz being a target generation frequency and corresponding to a low pitch frequency in an audible range. The speaker generates a sound wave from the electric signal by applying the electric signal to a vibration plate that produces the sound wave. | 2012-08-02 |
| 20120194330 | Vehicle anti-jacking apparatus, systems, and methods for hi-speed pursuit avoidance and occupant safety - An anti-carjacking system includes a transmitter programmed to receive a selected vehicle identification number or other code for use with a car assigned with that particular number or code. The system further includes a receiver associated with the computer system of the car so identified by the selected vehicle identification number and means for disabling normal driving operation of the car. There is further provided means for sending a disable command from the transmitter to the receiver so that the particular car with the selected vehicle identification number is rendered non-operational. The system may be implemented in various embodiments including a modified car radio system and a RFID embedded license plate configuration. Methods related to vehicle operation and occupant safety are also provided. | 2012-08-02 |
