| 31st week of 2012 patent applcation highlights part 15 |
| Patent application number | Title | Published |
|---|
| 20120193731 | EDGE-MOUNTED SENSOR - Sensor packages and methods for making a sensor device package for side mounting on a circuit board. A sensor device(s) in a mechanical layer of silicon is sandwiched between first and second layers of glass to create a wafer. A first via(s) is created in the first or second layers to expose a predefined area of the mechanical layer of silicon. A second via(s) is created in the first or second layers. The least one second via has a depth dimension that is less than a depth dimension of the first via. A metallic trace is applied between the exposed area on the mechanical layer and a portion of the second via. The wafer is sliced such that the second via is separated into two sections, thereby creating a sensor die. The sensor die is then electrically and mechanically bonded to a circuit board at the sliced second via. | 2012-08-02 |
| 20120193732 | MEMS DEVICE AND METHOD FOR FORMING THE SAME - An MEMS device and a method for forming the same are provided. The MEMS device comprises a first interlayer dielectric layer on a semiconductor substrate; a cavity in the first interlayer dielectric layer; first openings in the first interlayer dielectric layer over the cavity and connected with the cavity, each first opening comprising a lower portion and an upper portion having non-aligned sidewalls, convex sections are formed in the first interlayer dielectric layer between the lower and upper portions; an electrode being suspended in the cavity and movable relative to the substrate; a second interlayer dielectric layer on the first interlayer dielectric layer; second openings in the second interlayer dielectric layer and connected with the first openings, each second opening is disposed at a location that does not extend past the convex section; a third interlayer dielectric layer fully filling at least the second openings to seal the cavity. | 2012-08-02 |
| 20120193733 | CAPACITANCE TYPE MEMS SENSOR - A capacitance type MEMS sensor has a first electrode portion and a second electrode portion facing each other. The sensor includes a semiconductor substrate having a recess dug in a thickness direction of the semiconductor substrate, the recess having sidewalls, one of which serves as the first electrode portion. The sensor further includes a diaphragm serving as the second electrode portion, the diaphragm arranged within the recess to face the first electrode portion in a posture extending along a depth direction of the recess, the diaphragm having a lower edge spaced apart from the bottom surface of the recess, and is made of the same material as the semiconductor substrate. The sensor further includes an insulating film arranged to join the diaphragm to the semiconductor substrate. | 2012-08-02 |
| 20120193734 | STRESS SENSOR FOR IN-SITU MEASUREMENT OF PACKAGE-INDUCED STRESS IN SEMICONDUCTOR DEVICES - A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed. | 2012-08-02 |
| 20120193735 | MICROELECTROMECHANICAL SYSTEM MICROPHONE PACKAGE STRUCTURE - A microelectromechanical system microphone package structure includes a base plate and a plurality of chips is provided. The plurality of chips are disposed on the base plate, wherein an active area of each of the chips is disposed with a microelectromechanical system microphone structure, each of the active areas comprises a normal line, and the normal lines of the chips are not parallel to each other. | 2012-08-02 |
| 20120193736 | FABRICATION PROCESS AND LAYOUT FOR MAGNETIC SENSOR ARRAYS - A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout. The X and Y pitch of the sense elements are arranged such that the line segment that stabilizes, for example, the right side of one sense element; also stabilizes the left side of the adjacent sense element. | 2012-08-02 |
| 20120193737 | MRAM DEVICE AND METHOD OF ASSEMBLING SAME - A method of packaging a magnetoresistive random access memory (MRAM) die includes providing a lead frame having a die pad and lead fingers. The MRAM die is attached to the die pad with a first die attach adhesive and bond pads of the MRAM die are electrically connected to the lead fingers of the lead frame with wires using a wire bonding process. A pre-formed composite magnetic shield is attached to a top surface of the MRAM die with a second die attach adhesive. The magnetic shield includes a magnetic permeable filler material dispersed within an organic matrix. An encapsulating material is dispensed onto a top surface of the lead frame, MRAM die and magnetic shield such that the encapsulating material covers the MRAM die and the magnetic shield. The encapsulating material is then cured. | 2012-08-02 |
| 20120193738 | TMR Device with Low Magnetorestriction Free Layer - A high performance TMR sensor is fabricated by employing a free layer with a trilayer configurations represented by FeCo/CoFeB/CoB, FeCo/CoB/CoFeB, FeCo/CoFe/CoB, or FeCo/FeB/CoB may also be employed. Alternatively, CoNiFeB or CoNiFeBM formed by co-sputtering CoB with CoNiFe or CoNiFeM, respectively, where M is V, Ti, Zr, Nb, Hf, Ta, or Mo may be included in a composite free layer or as a single free layer in the case of CoNiFeBM. A 15 to 30% in improvement in TMR ratio over a conventional CoFe/NiFe free layer is achieved while maintaining low Hc and RA <3 ohm-um | 2012-08-02 |
| 20120193739 | Direct Radiation Converter, Radiation Detector, Medical Apparatus And Method For Producing A Direct Radiation Converter - A direct radiation converter is disclosed which includes a radiation detection material having an anode side and a cathode side in which the radiation detection material has a doping profile running in the anode-side to cathode-side direction. A radiation detector is further disclosed having such a direct radiation converter and having an anode array and a cathode array, and optionally having evaluation electronics for reading out a detector signal, as well as a medical apparatus having such a radiation detector. Also described is a method for producing a direct radiation converter which includes incorporating into a radiation detection material a doping profile running in the anode-side to cathode-side direction. | 2012-08-02 |
| 20120193740 | OPTICAL SEMICONDUCTOR DEVICE - The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment. | 2012-08-02 |
| 20120193741 | METHODS FOR FORMING BACKSIDE ILLUMINATED IMAGE SENSORS WITH FRONT SIDE METAL REDISTRIBUTION LAYERS - Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer. | 2012-08-02 |
| 20120193742 | PHOTOELECTRIC CONVERSION MODULE AND METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION MODULE - A photoelectric conversion module includes: a substrate having a light transmitting property and having a mounting surface; a photoelectric conversion element mounted on the mounting surface of the substrate; a cover member fixed to the substrate via a solder layer constituted by solder and forming, cooperatively with the substrate, an airtight chamber housing the photoelectric conversion element; and a solder adsorbing film provided near an area fixed to the substrate by the solder layer, in a surface, of the cover member, facing the mounting surface, the solder having an adhesive property to the solder adsorbing film. | 2012-08-02 |
| 20120193743 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges. | 2012-08-02 |
| 20120193744 | IMAGERS WITH BURIED METAL TRENCHES AND THOUGH-SILICON VIAS - An imaging system may include an imager with frontside components such as imaging pixels and backside components. The backside components may include at least a first redistribution layer having metal trenches and through-silicon vias (TSVs) that couple at least some of the backside components to the frontside components. The metal trenches and through-silicon vias may be formed simultaneously. The through-silicon vias may have a width greater than the width of the metal trenches. The greater width of the through-silicon vias may facilitate forming the through-silicon vias simultaneously with the metal trenches. | 2012-08-02 |
| 20120193745 | SOLID-STATE IMAGE PICKUP DEVICE - A photoelectric conversion portion, a charge holding portion, a transfer portion, and a sense node are formed in a P-type well. The charge holding portion is configured to include an N-type semiconductor region, which is a first semiconductor region holding charges in a portion different from the photoelectric conversion portion. A P-type semiconductor region having a higher concentration than the P-type well is disposed under the N-type semiconductor region. | 2012-08-02 |
| 20120193746 | SEMICONDUCTOR CHIP AND MULTI-CHIP PACKAGE HAVING THE SAME - A semiconductor chip includes: a semiconductor substrate; an interface member formed through the semiconductor substrate and electrically coupled to an external signal transfer terminal; and a backward diode formed between the semiconductor substrate and the interface member. | 2012-08-02 |
| 20120193747 | SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE - Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode. | 2012-08-02 |
| 20120193748 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 2012-08-02 |
| 20120193749 | SEMICONDUCTOR DEVICE - In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region. | 2012-08-02 |
| 20120193750 | POWER MANAGEMENT INTEGRATED CIRCUIT - A Power Management Integrated Circuit (PMIC) that includes a substrate, a high-side (HS) region on the substrate, a low-side (LS) region spaced from the first region, a device isolation layer interposed between the HS region and the LS region, a metal interconnection connected to the HS region across the device isolation layer and configured to permit a high-voltage current to flow in the HS region, and at least one electric field shield between the metal interconnection and the device isolation layer. Since the electric field shield is disposed under the metal interconnection, a sufficient breakdown voltage can be ensured for the HS region and the LS region. | 2012-08-02 |
| 20120193751 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess. | 2012-08-02 |
| 20120193752 | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby - A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. | 2012-08-02 |
| 20120193753 | METHODS FOR REDUCING THE METAL CONTENT IN THE DEVICE LAYER OF SOI STRUCTURES AND SOI STRUCTURES PRODUCED BY SUCH METHODS - Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed. | 2012-08-02 |
| 20120193754 | MEMS DEVICE WITH INTEGRAL PACKAGING - A MEMS device and method of making same is disclosed. In one embodiment, a micro-switch includes a base assembly comprising a movable structure bearing a contact pad. The base assembly is wafer-scale bonded to a lid assembly comprising an activator and a signal path. The movable structure moves within a sealed cavity formed during the bonding process. The signal path includes an input line and an output line separated by a gap, which prevents signals from propagating through the micro-switch when the switch is deactivated. In operation, a signal is launched into the signal path. When the micro-switch is activated, a force is established by the actuator, which pulls a portion of the movable structure upwards towards the gap in the signal path, until the contact pad bridges the gap between the input line and output line, allowing the signal to propagate through the micro-switch. | 2012-08-02 |
| 20120193755 | COPPER-BASED METALLIZATION SYSTEM INCLUDING AN ALUMINUM-BASED TERMINAL LAYER - In a copper-based metallization system of a semiconductor device the contact pad, such as a bond pad, is formed on the basis of two lithography steps by depositing the cap metal layer stack directly on any exposed copper surface areas of the last metallization layer. After patterning of the cap layer stack therefore reliable confinement of any exposed metal region is accomplished on the basis of a conductive barrier material, while the actual passivation materials are formed and patterned subsequently, thereby avoiding any negative influence on these materials, as may be the case in some conventional approaches. Moreover, superior mechanical integrity of the contact pad in combination with superior electrical performance of any metal region in the last metallization layer is achieved. | 2012-08-02 |
| 20120193756 | DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME - In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided. | 2012-08-02 |
| 20120193757 | CAPACITOR STRUCTURE AND FABRICATION METHOD THEREOF - A DRAM capacitor structure is disposed on the interior surface of a vertical hollow cylinder of a support structure overlying a semiconductor substrate. The support structure further includes a horizontal supporting layer that is integrally connected with the vertical hollow cylinder. A fabrication method for forming the DRAM capacitor structure is also provided. | 2012-08-02 |
| 20120193758 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus includes a first capacitor formed in a normal cell area and including a lower electrode coupled to one end of a cell transistor, and a second capacitor formed in a dummy cell area and including a lower electrode coupled to a power terminal. | 2012-08-02 |
| 20120193759 | CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor that has an electrode of an n-type semiconductor that is provided in contact with one surface of a dielectric, has a work function of 5.0 eV or higher, preferably 5.5 eV or higher, and includes nitrogen and at least one of indium, tin, and zinc. Since the electrode has a high work function, the dielectric can have a high potential barrier, and thus even when the dielectric is as thin as 10 nm or less, a sufficient insulating property can be maintained. In particular, a striking effect can be obtained when the dielectric is formed of a high-k material. | 2012-08-02 |
| 20120193760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane. | 2012-08-02 |
| 20120193761 | Highly Integrated Semiconductor Devices Including Capacitors - A capacitor of semiconductor device is provided including a lower electrode on a semiconductor substrate; a dielectric film covering a surface of the lower electrode; and an upper electrode covering the dielectric film. The lower electrode includes a first conductive pattern having a groove region defined by a bottom portion and a sidewall portion; and a first core support pattern disposed in the groove region of the first conductive pattern and exposing a portion of inner sidewall of the first conductive pattern. Related methods are also provided herein. | 2012-08-02 |
| 20120193762 | REVERSAL LITHOGRAPHY APPROACH BY SELECTIVE DEPOSITION OF NANOPARTICLES - A novel reversal lithography process without etch back is described. The reversal material comprises nanoparticles that are selectively deposited into the gaps between features without overcoating the tops of the features. As a result, a patterned imaging layer can be removed using solvent, blanket exposure followed by developer washing, or dry etching directly, without an etch-back process, and the original bright field lithography pattern can be reversed into dark field features, and transferred into subsequent layers using the nanoparticle reversal material as an etch mask. | 2012-08-02 |
| 20120193763 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND RESIST COATER - To provide a method of manufacturing a semiconductor device with reduced generation of humps, a semiconductor device with reduced generation of humps, and a resist coater. An inactive liquid such as pure water is discharged at a predetermined pressure from a nozzle for discharging fluid for processing hump while spinning the semiconductor substrate to spray a region where a hump is generated. The hump is crushed by spraying the inactive liquid at a high pressure onto the hump, and the film thickness of the bottom-layer resist becomes almost uniform across the entire semiconductor substrate. | 2012-08-02 |
| 20120193764 | NANOSTRUCTURING PROCESS FOR INGOT SURFACE, WAFER MANUFACTURING METHOD, AND WAFER USING THE SAME - The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing. | 2012-08-02 |
| 20120193765 | EMISSIVITY PROFILE CONTROL FOR THERMAL UNIFORMITY - A substrate for processing in a heating system is disclosed. The substrate includes a bottom portion for absorbing heat from a radiating heat source, the bottom portion having a first region having a first emissivity and a second region having a second emissivity less than the first emissivity. The first region and the second region promote thermal uniformity of the substrate by compensating for thermal non-uniformity of the radiating heat source. | 2012-08-02 |
| 20120193766 | SEMICONDUCTOR DEVICE WITH FRONT AND BACK SIDE RESIN LAYERS HAVING DIFFERENT THERMAL EXPANSION COEFFICIENT AND ELASTICITY MODULUS - Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer. | 2012-08-02 |
| 20120193767 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. | 2012-08-02 |
| 20120193768 | MULTIPLE-LAYER, MULTIPLE FILM HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME - The present invention provides a multiple layer that comprises two or more first inorganic material layers; and one or more second inorganic material layers that are positioned between the two first inorganic material layers and have the thickness of less than 5 nm, in which the first inorganic material layer is formed of one or more materials that are selected from silicon oxides, silicon carbide, silicon nitride, aluminum nitride and ITO, and the second inorganic material layer is formed of one or more materials that are selected from magnesium, calcium, aluminum, gallium, indium, zinc, tin, barium, and oxides and fluorides thereof, a multiple film that comprises the multiple layer, and an electronic device that comprises the multiple film. | 2012-08-02 |
| 20120193769 | SILICON SUBSTRATES WITH DOPED SURFACE CONTACTS FORMED FROM DOPED SILICON INKS AND CORRESPONDING PROCESSES - The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells. | 2012-08-02 |
| 20120193770 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected. | 2012-08-02 |
| 20120193771 | TRANSMISSION LINE, IMPEDANCE TRANSFORMER, INTEGRATED CIRCUIT MOUNTED DEVICE, AND COMMUNICATION DEVICE MODULE - A transmission line includes two tapered lines having a tapered planar shape and arranged in parallel, opposite lines provided in opposition to the narrower width sides of the two tapered lines, and a bonding wire for connecting the narrower width sides of the two tapered lines and the opposite lines, wherein the width between two outer edges on the narrower width sides of the two tapered lines arranged in parallel is greater than the width between outer edges on the opposite side of the opposite lines in opposition to the narrower width sides of the two tapered lines. | 2012-08-02 |
| 20120193772 | STACKED DIE PACKAGES WITH FLIP-CHIP AND WIRE BONDING DIES - The present technology discloses a stacked die package. In one embodiment, a package comprises a first die, a second die, and a leadframe. The first die is electrically coupled to the bottom surface of the leadframe through contact bump/bumps. The second die is electrically coupled to the top surface of the leadframe through wirebond/wires. The second die is mounted on the top surface of the first die. | 2012-08-02 |
| 20120193773 | Adhesion Promoting Composition for Metal Leadframes - A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content. | 2012-08-02 |
| 20120193774 | CONTACTLESS COMMUNICATION MEDIUM - Provided is a contactless communication medium which can prevent invasion of static electricity and has an outer surface which can satisfy requirements on the flatness thereof. A contactless communication medium is provided, in which a sealing member including an insulating layer and a conductive layer provided in a stacked manner and having a shape covering an IC module is located such that the insulating layer is on the IC module side. Owing to this, static electricity coming from outside is diffused by the conductive layer and blocked by the insulating layer. Thus, adverse influence of the static electricity on the IC module is prevented with certainty. The contactless communication medium can also satisfy the requirements on the flatness of an outer surface thereof. | 2012-08-02 |
| 20120193775 | SEMICONDUCTOR STRUCTURE WITH LOW RESISTANCE OF SUBSTRATE AND LOW POWER CONSUMPTION - A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit. | 2012-08-02 |
| 20120193776 | COMPLIANT SPRING INTERPOSER FOR WAFER LEVEL THREE DIMENSIONAL (3D) INTEGRATION AND METHOD OF MANUFACTURING - The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring. | 2012-08-02 |
| 20120193777 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 2012-08-02 |
| 20120193778 | INTEGRATED CIRCUIT HAVING PROTRUDING BONDING FEATURES WITH REINFORCING DIELECTRIC SUPPORTS - An integrated circuit (IC) die includes a substrate including a topside surface having active circuitry and a bottomside surface. A plurality of protruding bonding features are on the topside surface or bottomside surface and include at least one metal. The protruding bonding features including sidewalls having a neck region that includes an interface at or proximate to the topside surface or the bottomside surface. The protruding bonding features extend outward to a distal top edge. A dielectric support is positioned on the topside surface or bottomside surface between protruding bonding features. The dielectric support contacts and surrounds the sidewalls of the neck regions, does not extend beyond a height of the distal top edge, and is at least twenty percent taller where contacting the sidewalls as compared to a minimum non-zero height in a location between adjacent bonding features. | 2012-08-02 |
| 20120193779 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip. | 2012-08-02 |
| 20120193780 | SEMICONDUCTOR MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTING DEVICE - A semiconductor mounting device including a first substrate having first insulation layers, first conductor layers formed on the first insulation layers and via conductors connecting the first conductor layers, a second substrate having a core substrate, second conductor layers, through-hole conductors and buildup layers having second insulation layers and third conductor layers, first bumps connecting the first and second substrates and formed on the outermost first conductor layer on the outermost first insulation layer, and second bumps positioned to connect a semiconductor element and formed on the outermost third conductor layer on the outermost second insulation layer. The second substrate has greater thickness than the first substrate, the second conductor layers are formed on surfaces of the core substrate, respectively, the through-hole conductors are formed through the core substrate and connecting the second conductor layers, and the buildup layers are formed on the core substrate and second conductor layers, respectively. | 2012-08-02 |
| 20120193781 | CUSTOMIZED RF MEMS CAPACITOR ARRAY USING REDISTRIBUTION LAYER - Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces. | 2012-08-02 |
| 20120193782 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device includes a semiconductor element and an electronic element. The semiconductor element has a first protruding electrode, and the electronic element has a second protruding electrode. A substrate is disposed between the semiconductor element and the electronic element. The substrate has a through-hole in which the first and second protruding electrodes are fitted. The first and second protruding electrodes are connected together inside the through-hole of the substrate. | 2012-08-02 |
| 20120193783 | PACKAGE ON PACKAGE - A package on package is provided herein, the package on package including a first semiconductor package including a first substrate, a first semiconductor chip stacked on the first substrate, a plurality of first connection members on an upper surface of the first substrate and in a first molding material, and a plurality of via holes which respectively expose the plurality of first connection members through the first molding material; a second semiconductor package including a second substrate, a second semiconductor chip stacked on the second substrate, and a plurality of second connection members on a lower surface of the second substrate; and a plurality of connection portions including a plurality of cores and a plurality of conductive fusion layers surrounding the plurality of cores, wherein the plurality of conductive fusion layers contact the upper surface of the first substrate and the lower surface of the second substrate. | 2012-08-02 |
| 20120193784 | METHOD FOR JOINING BONDING WIRE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for joining a bonding wire, the method including wedge-joining a bonding wire which has a core whose main component is a non-noble metal and a noble metal layer covering the core to a bump formed on an electrode of a semiconductor element via the noble metal layer. | 2012-08-02 |
| 20120193785 | Multichip Packages - Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips. | 2012-08-02 |
| 20120193786 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate. | 2012-08-02 |
| 20120193787 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness. | 2012-08-02 |
| 20120193788 | STACKED SEMICONDUCTOR CHIPS PACKAGING - Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate. | 2012-08-02 |
| 20120193789 | PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF - A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate. | 2012-08-02 |
| 20120193790 | ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE - A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip. | 2012-08-02 |
| 20120193791 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire. | 2012-08-02 |
| 20120193792 | SEMICONDUCTOR DEVICE CONDUCTIVE PATTERN STRUCTURES INCLUDING DUMMY CONDUCTIVE PATTERNS, AND METHODS OF MANUFACTURING THE SAME - Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described. | 2012-08-02 |
| 20120193793 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to an embodiment, a semiconductor device includes a first wiring member, an opening portion and an electrode terminal portion. The first wiring member is provided on a first interlayer insulating film on a semiconductor substrate and used as a wiring layer. The opening portion is provided in a second interlayer insulating film on the first wiring member. The electrode terminal portion is provided on the opening portion and the second interlayer insulating film around the opening portion. In the electrode terminal portion, a barrier metal film in contact with the first wiring member, a seed metal film and a second wiring member are stacked and thus formed in such a manner as to cover the opening portion, and a coating metal film is formed on an upper portion and a side surface of the second wiring member. | 2012-08-02 |
| 20120193794 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first, second, third and fourth conductive plates are electrically connected and constitute at least two capacitors. | 2012-08-02 |
| 20120193795 | SEMICONDUCTOR DEVICE HAVING AN AIRBRIDGE AND METHOD OF FABRICATING THE SAME - A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer. | 2012-08-02 |
| 20120193796 | POLYSILICON LAYER AND METHOD OF FORMING THE SAME - The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 2012-08-02 |
| 20120193797 | 3D INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices. | 2012-08-02 |
| 20120193798 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards. | 2012-08-02 |
| 20120193799 | Circuit substrate and method of manufacturing same - A circuit substrate is presented. The circuit substrate comprises internal terminal electrode | 2012-08-02 |
| 20120193800 | SOLDER, SOLDERING METHOD, AND SEMICONDUCTOR DEVICE - A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight. | 2012-08-02 |
| 20120193801 | RFID TRANSPONDER AND METHOD FOR CONNECTING A SEMICONDUCTOR DIE TO AN ANTENNA - An RFID transponder having a semiconductor die with a solderable contact area and an antenna made from a winding wire, wherein the winding wire is soldered to the contact area, and the solderable contact area is made from a nickel based alloy. | 2012-08-02 |
| 20120193802 | GLOB TOP SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed including a substrate, a solder mask layer, one or more semiconductor die mounted to the solder mask layer and electrically coupled to the substrate, and a glob top cover over the semiconductor die. The solder mask further includes a dam protruding above surrounding areas of the solder mask layer and a cavity recessed into the solder mask layer for limiting flow of the glob top cover when the glob top material is applied. | 2012-08-02 |
| 20120193803 | SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND DISPLAY - It is desired to enhance reliability of thermal coupling between a semiconductor chip and a radiating member. A driver assembly has a sheetlike wiring sheet on which lead wires are provided, a driver chip that is mounted over the wiring sheet and is electrically coupled to the lead wire, and a radiator plate in which a housing part for partially housing the driver chip is provided and that is thermally coupled to the driver chip, wherein the wiring sheet and the radiator plate are adhered to each other so as to sandwich the driver chip housed in the housing part between them, and a depth profile of the housing part is set so that the wiring sheet may approach toward the radiator plate side as the wiring sheet extends in such a direction that so as to separate from the driver chip. | 2012-08-02 |
| 20120193804 | OHMIC CONNECTION USING WIDENED CONNECTION ZONES IN A PORTABLE ELECTRONIC OBJECT - The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects. | 2012-08-02 |
| 20120193805 | DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM - A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system. | 2012-08-02 |
| 20120193806 | 3D SEMICONDUCTOR DEVICE - A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias. | 2012-08-02 |
| 20120193807 | DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE - A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask. | 2012-08-02 |
| 20120193808 | BONDED STACKED WAFERS AND METHODS OF ELECTROPLATING BONDED STACKED WAFERS - A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs. | 2012-08-02 |
| 20120193809 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer having a first dielectric block and a first conductive block on the first dielectric block; at least one stacking wafer having a second dielectric block and at least one second conductive block on the second dielectric block, wherein the stacking wafers are bonded to the bottom wafer by an adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer; and a conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the conductive via is positioned within the first conductive block and the second conductive block. | 2012-08-02 |
| 20120193810 | WIRELESS APPARATUS AND WIRELESS SYSTEM - According to one embodiment, a wireless apparatus includes an integrated circuit package, a board having a first layer. The integrated circuit package includes an integrated circuit and at least one antenna. The board has a first surface and a second surface opposite to the first surface, the integrated circuit package is mounted on the board and is electrically connected to the board. The first layer is formed on the second surface, a part of the first layer in a first region is formed of a conductor, the first region is a region on which the antenna is projected in a thickness direction of the board, the part of the first layer in the first region is electrically connected to a particular region included in a third region, the third region is formed of a second region included in the board and the first surface. | 2012-08-02 |
| 20120193811 | INTERPOSER AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole. | 2012-08-02 |
| 20120193812 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. | 2012-08-02 |
| 20120193813 | WIRING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE WIRING STRUCTURE - A wiring structure of a semiconductor device, includes: an insulating layer formed on a base member; a first metal layer covered with the insulating layer; a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer, the insulating layer having a plurality of via holes which connect the first metal layer and the plurality of electrode parts; and a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer. | 2012-08-02 |
| 20120193814 | IC Device Having Low Resistance TSV Comprising Ground Connection - A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs. | 2012-08-02 |
| 20120193815 | STACKED STRUCTURE OF CHIPS - A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function. | 2012-08-02 |
| 20120193816 | Electronic Component and Method for Producing an Electronic Component - An electronic component having an encapsulation which has at least two double layers is described. In addition, a method for producing an electronic component in which a layer sequence is encapsulated is described. | 2012-08-02 |
| 20120193817 | EPOXY RESIN COMPOSITION, DIE ATTACH METHOD USING SAME, AND SEMICONDUCTOR DEVICE CONTAINING CURED PRODUCT THEREOF - An epoxy resin composition including (A) an epoxy resin that is solid at room temperature and has a softening point of 40° C. to 110° C., (B) a curing agent that is solid at room temperature and has a softening point of not less than 40° C. to 110° C., (C) a curing accelerator, (D) an inorganic filler having a mass-average particle size of 0.05 to 5 μm, (E) a diluent, and (F) a specific dimethyl silicone, in which at least one of the component (A) and the component (B) is silicone-modified is provided. The composition can be used in a silicon chip die attach method or to produce a semiconductor device containing a silicon chip, a substrate and a cured product of the composition, in which the silicon chip is bonded to the substrate via the cured product. | 2012-08-02 |
| 20120193818 | DIFFUSER TUBE - A diffuser tube is capable of preventing sludge from entering the tube when a diffusion operation is not performed, thereby preventing clogging of diffusion holes and inside of the tube and reducing a pressure loss during the diffusion operation. The diffuser tube is formed of an elastic tubular body, and slit cutting surfaces of a diffusion slit are slanted with respect to a radial direction of a membrane member in a slanted surface portion. | 2012-08-02 |
| 20120193819 | COUPLING ELEMENT FOR CONNECTING AN AERATION BODY WITH THE FEED LINE OF A WATER AERATING DEVICE - The invention relates to a coupling element for connecting at least one aeration body to the feed line of a water aerating device. According to the invention, said coupling element has at least one integrated flow channel for a gaseous medium along a curved section, the inlet opening and outlet opening of said channel being arranged at different angular positions. The invention further relates to an aerating device for introducing a gaseous medium into a body of water, comprising at least one such coupling element | 2012-08-02 |
| 20120193820 | CROSS-PLEATED MEMBRANE CARTRIDGES, AND METHOD AND APPARATUS FOR MAKING CROSS-PLEATED MEMBRANE CARTRIDGES - A membrane cartridge is manufactured by repeatedly folding and joining two strips of membrane to form a cross-pleated cartridge with a stack of openings or fluid passageways configured in an alternating cross-flow arrangement. The cartridge can be modified for other flow configurations including co-flow and counter-flow arrangements. Methods for manufacturing such cross-pleated membrane cartridges, as well as apparatus used in the manufacturing process are described. Cross-pleated membrane cartridges comprising water-permeable membranes can be used in a variety of applications, including in heat and water vapor exchangers. In particular they can be incorporated into energy recovery ventilators (ERVs) for exchanging heat and water vapor between air streams being directed into and out of buildings. | 2012-08-02 |
| 20120193821 | METHOD OF MANUFACTURING LENS - A manufacturing method uses a molding unit to manufacture lenses out of a structure with a plurality of lens intermediates coupled to each other through a runner. The molding unit includes a holding member provided with first opening parts and second opening parts coaxial with each other, and molding chambers. First molding dies and second molding dies are inserted into the first opening parts and the second opening parts respectively. The holding member is further provided with a path that allows introduction of the lens intermediates into the molding chambers. In a manufacturing process, the lens intermediates are guided to predetermined positions in the corresponding molding chambers by operating the structure to cause the lens intermediates and the runner to move along the path. Next, a pressing pressure is applied to the lens intermediates to form molded lenses. | 2012-08-02 |
| 20120193822 | BIOMEDICAL DEVICES CONTAINING INTERNAL WETTING AGENTS - This invention includes a wettable biomedical device containing a high molecular weight hydrophilic polymer and a hydroxyl-functionalized silicone-containing monomer. | 2012-08-02 |
| 20120193823 | SYSTEMS AND METHODS FOR MAKING LAYERED DENTAL APPLIANCES - A system and method for making a layered dental appliance. The system can include a mold comprising a negative of an outer shape of a layered dental appliance, and a dental core dimensioned to be at least partially received in the mold. The method can include positioning a first slurry in the mold, and pressing the dental core into the first slurry in the mold to form a first article comprising the dental core and a first layer formed from the first slurry. The method can further include removing the first article from the mold, and firing the first article. The method can further include positioning a second slurry in the mold, and pressing the first article into the second slurry in the mold to form a second article comprising the dental core, the first layer, and a second layer formed from the second slurry. | 2012-08-02 |
| 20120193824 | METHOD FOR CONTROLLING TEMPERATURES IN HOT RUNNERS OF MULTI-CAVITY INJECTION MOLD, METHOD FOR WARNING, AND CONTROL SYSTEM BASED ON THOSE METHODS - A method for controlling temperatures in hot runners of a multi-cavity injection mold, a warning method, and a control system based on those methods are provided, in which a temperature sensor is positioned at the same location as each of the cavities of the mold, one of the cavities is chosen as a standard cavity, and a standard filling time is defined. Besides, in every injection cycle, a calculating and controlling module is to calculate the differences between the standard filling time and the filling times of the cavities, and according to the differences, the temperatures in the hot runners may be adjusted by a temperature-adjusting device and a warning device may be started. So, the volumetric filling of the cavities can be balanced very quickly, the process can avoid fluctuations of external environment so as to reduce the time for product development, and the quality of production can be maintained. | 2012-08-02 |
| 20120193825 | CONTROL METHOD FOR SCREW OF INJECTION MOLDING MACHINE - A screw control method of an injection molding machine including a barrel into which a resin is inserted, a screw installed to be rotatable inside the barrel, a check ring on a rear side of a screw head, and a controller controlling operations of the screw includes: measuring an amount of resin to be injected and inserting the resin into the barrel until the amount of resin reaches the measured amount of resin; completing the measurement while melting the inserted resin through rotation of the screw; stopping the rotation of the screw after completing the measurement of the resin; after retracting the screw of which the rotation is stopped a pre-set distance, advancing the screw a pre-set distance; and performing injection molding of the melted resin by advancing the screw, where the rotation, advance, and retraction operations of the screw are made according to control signals of the controller. | 2012-08-02 |
| 20120193826 | Color Variation Control Process for Molding Plastic and Composite Multi-Color Articles - A process to effect random color variation in multi-color molded articles includes feeding individual colors to molding equipment in a pre-established sequence and manner that prevents substantial mixing of the colors, and at pre-established ratios in relation to a non-integer multiple of volume associated with the molded article. | 2012-08-02 |
| 20120193827 | Microporous Film - A microporous film is described made from a polyacetal polymer. in one embodiment, the microporous film is formed from a composition comprising a polyacetal copolymer combined with an inorganic filler and a plasticizer. The polymer composition is extruded or molded into a sheet. The sheet is then passed through an extraction medium in order to remove a portion of the plasticizer. The extraction medium is then removed from the sheet. | 2012-08-02 |
| 20120193828 | WET PROCESS OF FABRICATING FIBER WALL PANELS - This invention discloses a wet process of fabrication of fiber wall panel, which includes the following steps: 1) slurry making: mix nontimber type natural plant fiber slurry with grass family slurry according to 1:0˜1.5 dry weight ratio, and add water to dilute this slurry; 2) slurry storage: pour the mixed slurry into slurry storage tank and add water for dilution; 3) suction straining and forming: pour slurry into mold cavity for cold pressing, dewatering, and forming, to yield wet blanks; 4) hot pressing, forming, and drying: move the wet blanks to the hot pressing mold for hot pressing and remove moisture generated during hot pressing, to yield fiber wall panel. Fiber wall panel made by this process features environment friendliness and high strength. | 2012-08-02 |
| 20120193829 | METHOD OF MANUFACTURING POLYIMIDE FILM AND TENTER APPARATUS - In manufacture of a polyimide film, self-supporting film is heated with both ends in a width direction held and carried by the tenter apparatus. The tenter apparatus has a guide member placed on each side of a carry path for the self-supporting film and a pair of tenter chains each moved along the guide member and each including a film holding mechanism for holding an edge portion of the self-supporting film. The tenter chain has a rotating body supported rotatably around a shaft member extending in a direction in parallel with a carry face of the self-supporting film and perpendicular to a longitudinal direction of the guide member for movably supporting the tenter chain. The shaft member is directly or indirectly fixed to a member identical to a member to which the film holding mechanism is fixed. | 2012-08-02 |
| 20120193830 | PRODUCTION METHOD FOR A FLEXIBLE CONVERTIBLE-TOP CLOTH FOR A CONVERTIBLE - A method produces a flexible convertible-top cloth for a convertible top, an outside of which convertible-top cloth is provided with a decoration. The cost-effective production method is distinguished in that use is made of a convertible-top cloth which has plastic fibers, and in that the decoration is produced on the convertible-top cloth in the form of a permanent depression deforming the plastic fibers by a stamp having a negative of the decoration. The convertible-top cloth is heated to a predetermined temperature and the stamp is pressed onto the convertible-top cloth with a predetermined force. | 2012-08-02 |
