| 31st week of 2012 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20120193631 | POLYSILICON CONTROL ETCH BACK INDICATOR - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 2012-08-02 |
| 20120193632 | SILICON STRUCTURE AND MANUFACTURING METHODS THEREOF AND OF CAPACITOR INCLUDING SILICON STRUCTURE - Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided. | 2012-08-02 |
| 20120193633 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate ( | 2012-08-02 |
| 20120193634 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other. | 2012-08-02 |
| 20120193635 | SEMICONDUCTOR DEVICE, PROCESS FOR PRODUCTION OF THE SEMICONDUCTOR DEVICE, AND DISPLAY DEVICE EQUIPPED WITH THE SEMICONDUCTOR DEVICE - A thin film diode ( | 2012-08-02 |
| 20120193636 | Very high transmittance, back-illuminated, silicon-on-sapphire semiconductor wafer substrate for high quantum efficiency and high resolution, solid-state, imaging focal plane arrays - An advanced, very high transmittance, back-illuminated, silicon-on-sapphire wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon layers, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiN | 2012-08-02 |
| 20120193637 | LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR - The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; and a gate stack disposed on the AlGaN layer. The gate stack includes a III-V compound n-type doped layer; a III-V compound p-type doped layer adjacent the III-V compound n-type doped layer; and a metal layer formed over the III-V compound p-type doped layer and the III-V compound n-type doped layer. | 2012-08-02 |
| 20120193638 | METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GaN, InN, AND AIN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION - Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible. | 2012-08-02 |
| 20120193639 | GaN-BASED SEMICONDUCTOR ELEMENT - A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer. | 2012-08-02 |
| 20120193640 | CRYSTALLINE ALUMINUM CARBIDE THIN FILM, SEMICONDUCTOR SUBSTRATE HAVING THE ALUMINUM CARBIDE THIN FILM FORMED THEREON AND METHOD OF FABRICATING THE SAME - Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate. | 2012-08-02 |
| 20120193641 | NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF - In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times. | 2012-08-02 |
| 20120193642 | DIAMOND SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In one aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers. | 2012-08-02 |
| 20120193643 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a p type body region in which an inversion layer is formed when the gate electrode is fed with a voltage. The inversion layer has an electron mobility μ dependent more strongly on an acceptor concentration N | 2012-08-02 |
| 20120193644 | BORON-DOPED DIAMOND SEMICONDUCTOR - First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead. | 2012-08-02 |
| 20120193645 | Radiation Emitting Device - A radiation-emitting device having an organic radiation-emitting functional layer and a radiation decoupling layer. The organic radiation-emitting functional layer emits a primary radiation; the radiation decoupling layer is disposed in the beam path of the primary radiation. On the side remote from the radiation-emitting functional layer the radiation decoupling layer comprises a microstructure having regularly disposed geometric structural elements; at least partial regions of the radiation decoupling layer contain regions which effect scattering of the primary radiation. | 2012-08-02 |
| 20120193646 | METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DIODE BY LIFT-OFF - A method of manufacturing an Organic Light Emitting Diode (OLED). The method comprises using a solution or a solvent for removing a photo-resist used for patterning, which photo-resist is at least partly covered with a material other than photo-resist. The method of manufacturing the OLED thus comprises a lift-off process. The new method provides the benefits of low cost manufacturing and high OLED performance. | 2012-08-02 |
| 20120193647 | SOLID STATE LIGHTING COMPONENT PACKAGE WITH REFLECTIVE LAYER - A solid state lighting package is provided. The package comprising at least one LED element positioned on a top surface of a substrate or a submount capable of absorbing light emitted by the at least one LED element; and a reflective layer, the reflective layer covering at least a portion of the top surface of the substrate or the submount, whereby at least of portion of the light emitted by the LED element is reflected by the reflective layer. A method of manufacturing a solid state lighting package comprising the reflective layer, and a method of increasing the luminous flux thereof, is also provided. | 2012-08-02 |
| 20120193648 | CONFORMALLY COATED LIGHT EMITTING DEVICES AND METHODS FOR PROVIDING THE SAME - Methods are disclosed including applying a conformal coating to multiple light emitters. The conformal coating forms in gap areas between adjacent ones of the light emitters. The plurality of light emitters are separated into individual light emitters. The individual light emitters include the conformal coating that extends to a space corresponding to respective gap areas. Light emitting structures are disclosed including a semiconductor light emitting diode (LED) having an active region and a conformal coating including a first portion and a second portion, the first portion corresponding to at least one surface of the LED and the second portion extending from the first portion. | 2012-08-02 |
| 20120193649 | LIGHT EMITTING DIODE (LED) ARRAYS INCLUDING DIRECT DIE ATTACH AND RELATED ASSEMBLIES - An electronic device may include a packaging substrate having a packaging substrate face with a plurality of electrically conductive pads on the packaging substrate face. A first light emitting diode die may bridge first and second ones of the electrically conductive pads. More particularly, the first light emitting diode die may include first anode and cathode contacts respectively coupled to the first and second electrically conductive pads using metallic bonds. Moreover, widths of the metallic bonds between the first anode contact and the first pad and between the first cathode contact and the second pad may be at least 60 percent of a width of the first light emitting diode die. A second light emitting diode die may bridge third and fourth ones of the electrically conductive pads. The second light emitting diode die may include second anode and cathode contacts respectively coupled to the third and fourth electrically conductive pads using metallic bonds. Widths of the metallic bonds between the second anode contact and the second pad and between the second cathode contact and the third pad may be at least 60 percent of a width of the first light emitting diode die. | 2012-08-02 |
| 20120193650 | Method for Packaging an LED Emitting Light Omnidirectionally and an LED Package - The present invention discloses a method for packaging an LED emitting light omnidirectionally and an LED package. The present invention utilizes a transparent glue to bond LED chips and electrodes onto one or more transparent glass or organic films, and vertically fixes the transparent bracket having the LED chips, electrodes and welding wires in a transparent vessel. When the diode power is on, the front face of the LED chips on the vertical transparent bracket can emit light properly, while the rear face of the LED chips can emit brighter light via the transparent glass or organic film. The present invention makes it possible to demonstrate the brightest face of an LED, and thus improves LED light extraction. | 2012-08-02 |
| 20120193651 | LIGHT EMITTING DEVICES, SYSTEMS, AND METHODS - Light emitting devices, systems, and methods are disclosed. In one embodiment a light emitting device can include an emission area having one or more light emitting diodes (LEDs) mounted over an irregularly shaped mounting area. The light emitting device can further include a retention material disposed about the emission area. The retention material can also be irregularly shaped, and can be dispensed. Light emitting device can include more than one emission area per device. | 2012-08-02 |
| 20120193652 | LED ARRAY FORMED BY INTERCONNECTED AND SURROUNDED LED CHIPS - A light emitting diode array includes a first light emitting diode having a first electrode and a second light emitting diode having a second electrode. The first and second light emitting diodes are separated. A first polymer layer is positioned between the light emitting diodes. An interconnect located at least partially on the first polymer layer connects the first electrode to the second electrode. A permanent substrate is coupled to the light emitting diodes. The permanent substrate is coupled to the side of the light emitting diodes with the interconnect. A second polymer layer at least partially encapsulates the side of the light emitting diodes opposite the permanent substrate (the side opposite the interconnect). | 2012-08-02 |
| 20120193653 | LED ARRAY FORMED BY INTERCONNECTED AND SURROUNDED LED CHIPS - A light emitting diode array includes a first light emitting diode having a first electrode and a second light emitting diode having a second electrode. The first and second light emitting diodes are separated. A first polymer layer is positioned between the light emitting diodes. An interconnect located at least partially on the first polymer layer connects the first electrode to the second electrode. A permanent substrate is coupled to the light emitting diodes. The permanent substrate is coupled to the side of the light emitting diodes opposite the interconnect. A second polymer layer at least partially encapsulates the side of the light emitting diodes with the interconnect. | 2012-08-02 |
| 20120193654 | LIGHT EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes a support member, a light emitting structure disposed over the support member and includes first and second light emitting structures, the first and second light emitting structures including a first semiconductor layer, a second semiconductor layer, and an active layer, a passivation layer disposed on one side surface of the first light emitting structure, a first electrode disposed between the support member and the first semiconductor layer in the first light emitting structure, a second electrode disposed on a side surface of the passivation layer and on the second semiconductor layer in the first light emitting structure, a third electrode disposed between the support member and the first semiconductor layer in the second light emitting structure, an insulation layer disposed with a through hole, and a fourth electrode disposed in the through hole. | 2012-08-02 |
| 20120193655 | ALIGNMENT TOLERANT PATTERNING ON FLEXIBLE SUBSTRATES - A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer. | 2012-08-02 |
| 20120193656 | DISPLAY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A display device structure includes an active device, a passivation layer, a pixel electrode and a first conductive material. The passivation layer covers the active device and has a first through hole exposing a portion of the active device. The pixel electrode is disposed on the passivation layer, and the pixel electrode is a non-thin-film electrode consituted by a plurality of micro-conductive structures or includes an organic conductive polymer material. The first conductive material is disposed around the first through hole and electrically connected to the exposed active device. The pixel electrode is electrically connected to the first conductive material. | 2012-08-02 |
| 20120193657 | Radiation-Emitting Semiconductor Component - A radiation-emitting semiconductor component includes a light-emitting diode chip with at least two emission regions that can be operated independently of each other and at least two differently designed conversion elements. During operation of the light-emitting diode chips each of the emission regions is provided for generating electromagnetic primary radiation. Each emission region has an emission surface by which at least part of the primary radiation is decoupled from the light-emitting diode chip. The conversion elements are provided for absorbing at least part of the primary radiation and for re-emitting secondary radiation. The differently designed conversion elements are disposed downstream of different emission surfaces. An electric resistance element is connected in series or parallel to at least one of the emission regions. | 2012-08-02 |
| 20120193658 | ORGANIC LIGHT-EMITTING PANEL, MANUFACTURING METHOD THEREOF, AND ORGANIC DISPLAY DEVICE - A pixel in the panel includes sub-pixels | 2012-08-02 |
| 20120193659 | STRUCTURES AND SUBSTRATES FOR MOUNTING OPTICAL ELEMENTS AND METHODS AND DEVICES FOR PROVIDING THE SAME BACKGROUND - Methods are disclosed including generating a substrate surface topography that includes a mounting portion that is higher than a relief portion that defines a perimeter of the mounting portion. | 2012-08-02 |
| 20120193660 | HORIZONTAL LIGHT EMITTING DIODES INCLUDING PHOSPHOR PARTICLES - Horizontal light emitting diodes include anode and cathode contacts on the same face and a transparent substrate having an oblique sidewall. A conformal phosphor layer having an average equivalent particle diameter d50 of at least about 10 μm is provided on the oblique sidewall. High aspect ratio substrates may be provided. The LED may be directly attached to a submount. | 2012-08-02 |
| 20120193661 | GAP ENGINEERING FOR FLIP-CHIP MOUNTED HORIZONTAL LEDS - A horizontal LED die is flip-chip mounted on a mounting substrate to define a gap that extends between the closely spaced apart anode and cathode contacts of the LED die, and between the closely spaced apart anode and cathode pads of the substrate. An encapsulant is provided on the light emitting diode die and the mounting substrate. The gap is configured to prevent sufficient encapsulant from entering the gap that would degrade operation of the LED. | 2012-08-02 |
| 20120193662 | REFLECTIVE MOUNTING SUBSTRATES FOR FLIP-CHIP MOUNTED HORIZONTAL LEDS - A light emitting device includes a mounting substrate having a reflective layer that defines spaced apart anode and cathode pads, and a gap between them. A light emitting diode die is flip-chip mounted on the mounting substrate, such that the anode contact of the LED die is bonded to the anode pad and the cathode contact of the LED die is bonded to the cathode pad. A lens extends from the mounting substrate to surround the LED die. The reflective layer extends on the mounting substrate to cover substantially all of the mounting substrate that lies beneath the lens, excluding the gap, and may also extend beyond the lens. | 2012-08-02 |
| 20120193663 | LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - A fabrication method of a light-emitting diode including forming an epitaxial layer on a first substrate; forming a metal pad and a stress release ring on the epitaxial layer, wherein the stress release ring surrounds the metal pad; performing a substrate replacement process to transfer the epitaxial layer, the metal pad, and the stress release ring onto a second substrate, wherein the metal pad and the stress release ring are disposed between the epitaxial layer and the second substrate; patterning the epitaxial layer to expose a portion of the stress release ring; and removing the stress release ring to suspend a portion of the epitaxial layer. Moreover, a light emitting diode is provided. | 2012-08-02 |
| 20120193664 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer and two electrodes. The substrate has a top surface and a bottom surface. The top surface is not parallel to the bottom light emitting surface of the active layer. The first semiconductor layer is disposed on the top surface. The active layer is disposed on at least one portion of the first semiconductor layer. The second semiconductor layer is disposed on the active layer. In an embodiment, the top surface can be realized by an oblique surface, a curved surface or a zigzag surface. | 2012-08-02 |
| 20120193665 | LIGHT EMITTING DEVICE - A light emitting device which includes: a base body; a conductive member disposed on the base body; a light emitting element placed on the conductive member; and a translucent member disposed above the light emitting element. A surface of the translucent member is formed in a lens shape, and when a portion formed in the lens shape of the translucent member on a surface of the conductive member is perspectively seen from above, an area other than a portion where the light emitting element is placed is coated with an insulating filler to form a light reflection layer. | 2012-08-02 |
| 20120193666 | LIGHT-REFLECTIVE ANISOTROPIC CONDUCTIVE ADHESIVE AND LIGHT-EMITTING DEVICE - A light-reflective anisotropic conductive adhesive used for anisotropic conductive connection of a light-emitting element to a wiring board includes a thermosetting resin composition, conductive particles, and light-reflective insulating particles. The light-reflective insulating particles are at least one of inorganic particles selected from the group consisting of titanium oxide, boron nitride, zinc oxide, and aluminum oxide, or resin-coated metal particles formed by coating the surface of scale-like or spherical metal particles with an insulating resin. | 2012-08-02 |
| 20120193667 | Method for Controlling Fluidity of Phosphor, Phosphor and Phosphor Paste - Disclosed herein is a method for controlling the fluidity of a phosphor, a phosphor and a phosphor paste, the method comprising the steps of: treating the surface of a phosphor with a silane compound comprising a double bond; and polymerizing the monomer on the surface of the phosphor to form a polymer membrane thereon. The phosphor having the polymer membrane formed thereon exhibits significantly stabilized fluidity within a polymer encapsulant. | 2012-08-02 |
| 20120193668 | LIGHT EMITTING DEVICE - A light emitting device including a light emitting structure having a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a first electrode on the light emitting structure; and a photon escape layer on the light emitting structure. Further, the photon escape layer has a refractive index that is between a refractive index of the light emitting structure and a refractive index of an encapsulating material with respect to the light emitting structure such that an escape probability for photons emitted by the light emitting structure is increased. | 2012-08-02 |
| 20120193669 | Contacting an Optoelectronic Semiconductor Component Through a Conversion Element and Corresponding Optoelectronic Semiconductor Component - A method for manufacturing an optoelectronic semiconductor component, comprising: providing a semiconductor chip in a composite wafer, comprising an active side for emitting a primary radiation and a contact terminal which is arranged on the active side; depositing a coupling element on the active side; attaching a luminescence conversion element, for converting part of the primary radiation into a secondary radiation, to the coupling element. | 2012-08-02 |
| 20120193670 | LIGHT EMITTING DEVICE HAVING WAVELENGTH CONVERTING LAYER AND METHOD OF FABRICATING THE SAME - A light emitting device having a wavelength converting layer. The light emitting device includes a substrate; a semiconductor stack having a first conductive-type semiconductor layer, an active layer and a second conductive-type semiconductor layer disposed on the substrate; a first wavelength converting layer covering a top of the semiconductor stack; and a second wavelength converting layer disposed on the first wavelength converting layer and having a width narrower than the first wavelength converting layer. The second wavelength converting layer is employed, thereby being capable of reducing a color variation according to a viewing angle. | 2012-08-02 |
| 20120193671 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode device and a method for manufacturing the same are described. The light-emitting diode device includes a metal heat dissipation bulk, a frame, a light-emitting diode chip and a package encapsulant. The metal heat dissipation bulk includes a curve protrusion ring. The frame is disposed on the metal heat dissipation bulk outside the curve protrusion ring. The frame includes at least two electrode pads respectively disposed at two sides of the curve protrusion ring. The light-emitting diode chip is disposed on the metal heat dissipation bulk in an inner side of the curve protrusion ring. The light-emitting diode chip has a first electrode and a second electrode of different conductivity types, and the first electrode and the second electrode are electrically connected to the electrode pads respectively. The package encapsulant encapsulates the light-emitting diode chip, the curve protrusion ring, and a portion of each electrode pad. | 2012-08-02 |
| 20120193672 | METHOD OF FABRICATING LIGHT-EMITTING APPARATUS WITH IMPROVED LIGHT EXTRACTION EFFICIENCY AND LIGHT-EMITTING APPARATUS FABRICATED USING THE METHOD - Provided are a method of fabricating a light-emitting apparatus with improved light extraction efficiency and a light-emitting apparatus fabricated using the method. The method includes: preparing a monocrystalline substrate; forming an intermediate structure on the substrate, the intermediate structure comprising a light-emitting structure which comprises a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type stacked sequentially, a first electrode which is electrically connected to the first conductive pattern, and a second electrode which is electrically connected to the second conductive pattern; forming a polycrystalline region, which extends in a horizontal direction, by irradiating a laser beam to the substrate in the horizontal direction such that the laser beam is focused on a beam-focusing point within the substrate; and cutting the substrate in the horizontal direction along the polycrystalline region. | 2012-08-02 |
| 20120193673 | LIGHT-EMITTING DEVICES - Light-emitting devices are provided, the light-emitting devices include a light-emitting structure layer having a first conductive layer, a light-emitting layer and a second conductive layer sequentially stacked on a first of a substrate, a plurality of seed layer patterns formed apart each other in the first conductive layer; and a plurality of first electrodes formed through the substrate, wherein each of the first electrodes extends from a second side of the substrate to each of the seed layer patterns. | 2012-08-02 |
| 20120193674 | Semiconductor Light-Emitting Device - The present disclosure relates to a semiconductor light-emitting device which includes: a substrate having a first surface and a second surface; at least one semiconductor stacked body disposed on the first surface of the substrate and each including an active layer and first and second semiconductor layers disposed on both sides of the active layer, the first semiconductor layer having first conductivity, the second semiconductor layer having second conductivity different than the first conductivity, the first semiconductor layer having an exposed surface; a substrate piercing portion leading from the second surface to the first surface with a spacing from the exposed surface and opened without being covered with the at least one semiconductor stacked body; and an electrical path leading to the at least one semiconductor stacked body via the substrate piercing portion. | 2012-08-02 |
| 20120193675 | ESD Protection Device - Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor. | 2012-08-02 |
| 20120193676 | Diode structures with controlled injection efficiency for fast switching - This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer. | 2012-08-02 |
| 20120193677 | III-N Device Structures and Methods - A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive. | 2012-08-02 |
| 20120193678 | FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET - Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region. | 2012-08-02 |
| 20120193679 | HETEROJUNCTION TUNNELING FIELD EFFECT TRANSISTORS, AND METHODS FOR FABRICATING THE SAME - The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide. | 2012-08-02 |
| 20120193680 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 2012-08-02 |
| 20120193681 | 3D SEMICONDUCTOR DEVICE - A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices. | 2012-08-02 |
| 20120193682 | SYSTEM OF DYNAMIC AND END-USER CONFIGURABLE ELECTRICAL INTERCONNECTS - A dynamic and end-user configurable controlled impedance interconnect line includes a plurality of conductive pixels, a plurality of thin-film transition material interconnects to electrically connect adjacent conductive pixels in the plurality of conductive pixels, and a plurality of addressable pixel interconnect actuators to selectively heat a respective plurality of the thin-film transition material interconnects. The plurality of addressable pixel interconnect actuators is operable to selectively heat a respective plurality of the thin-film transition material interconnects to form an interconnect line. | 2012-08-02 |
| 20120193683 | CHARGE-INTEGRATION MULTILINEAR IMAGE SENSOR - The invention relates to time-delay and signal-integration linear image sensors (or TDI sensors). According to the invention, a pixel comprises a succession of several insulated gates covering a semiconducting layer, the gates of one pixel being separated from one another and separated from the gates of an adjacent pixel of another line by narrow uncovered gaps of a gate and comprising a doped region of a second type of conductivity covered by a doped superficial region of the first type; the superficial regions are kept at one and the same reference potential; the width of the narrow gaps between adjacent gates is such that the internal potential of the region of the second type is modified in the whole width of the narrow gap when a gate sustains the alternations of potential necessary for the transfer of charges from one pixel to the following one. | 2012-08-02 |
| 20120193684 | Ultrananocrystalline Diamond Films with Optimized Dielectric Properties for Advanced RF MEMS Capacitive Switches - An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems. | 2012-08-02 |
| 20120193685 | RF-MEMS Capacitive Switches With High Reliability - A reliable long life RF-MEMS capacitive switch is provided with a dielectric layer comprising a “fast discharge diamond dielectric layer” and enabling rapid switch recovery, dielectric layer charging and discharging that is efficient and effective to enable RF-MEMS switch operation to greater than or equal to 100 billion cycles. | 2012-08-02 |
| 20120193686 | SEMICONDUCTOR DEVICES HAVING ENCAPSULATED STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One method for fabricating a semiconductor device structure involves the steps of forming a gate structure overlying the semiconductor substrate, forming recesses in the semiconductor substrate about the gate structure, forming a stress-inducing semiconductor material in the recesses, and forming a silicon material in the recesses overlying the stress-inducing semiconductor material. In an exemplary embodiment, the silicon material formed in the recesses is epitaxially-grown on the stress-inducing semiconductor material. | 2012-08-02 |
| 20120193687 | REDUCED S/D CONTACT RESISTANCE OF III-V MOSFET USING LOW TEMPERATURE METAL-INDUCED CRYSTALLIZATION OF n+ Ge - Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor. | 2012-08-02 |
| 20120193688 | ION IMPLANTED AND SELF ALIGNED GATE STRUCTURE FOR GaN TRANSISTORS - A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer. | 2012-08-02 |
| 20120193689 | PIXEL OF A MULTI-STACKED CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC. | 2012-08-02 |
| 20120193690 | PHOTOELECTRIC CONVERSION APPARATUS - There is provided a photoelectric conversion apparatus which is characterized by comprising a plurality of photoelectric conversion regions of a first conductivity type, and a plurality of semiconductor regions of a second conductivity type opposite to the first conductivity type; and in that the plurality of photoelectric conversion regions of the first conductivity type and the plurality of semiconductor regions are alternately arranged, and a voltage controlling unit is further provided to change a width of a depletion layer formed in a semiconductor substrate by controlling a voltage to be applied to the semiconductor region of the second conductivity type provided between the plurality of photoelectric conversion regions of the first conductivity type. | 2012-08-02 |
| 20120193691 | BACK-SIDE ILLUMINATION IMAGE SENSOR - A back side illumination (BSI) image sensor includes at least one pixel. The pixel area includes a photo diode and a transfer transistor. The transfer transistor has a control electrode made of a gate poly and a gate oxide for receiving a control instruction, a first electrode coupled to the photo diode, and a second electrode, wherein an induced conduction channel of the transfer transistor partially surrounds a recessed space which is filled with the gate poly and the gate oxide of the first transistor. | 2012-08-02 |
| 20120193692 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A semiconductor element includes a base-body region of p-type; a charge-generation buried region of a n-type, implementing a photodiode together with the base-body region, configured to create a first potential valley in the base-body region; an accumulation region of n-type, being buried in a part of the upper portion of the base-body region, configured to create a second potential valley deeper than the first potential valley; a transfer-gate insulation film provided on a surface of the base-body region; a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region; and a recessed-potential creation mechanism configured to create a stair-like-shaped potential barrier for electronic shuttering. | 2012-08-02 |
| 20120193693 | MAGNETIC RANDOM ACCESS MEMORY AND A METHOD OF FABRICATING THE SAME - An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode. | 2012-08-02 |
| 20120193694 | WIRELESS CHIP AND ELECTRONIC APPLIANCE HAVING THE SAME - The present invention provides a wireless chip having high mechanical strength. Moreover, the present invention also provides a wireless chip which can prevent an electric wave from being blocked. In a wireless chip of the present invention, a layer having a thin film transistor formed over an insulating substrate is fixed to an antenna by an anisotropic conductive adhesive, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer; the first conductive layer and the second conductive layer has the dielectric layer therebetween; the first conductive layer serves as a radiating electrode; and the second electrode serves as a ground contact body. | 2012-08-02 |
| 20120193695 | Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors - A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level. | 2012-08-02 |
| 20120193696 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer. | 2012-08-02 |
| 20120193697 | SEMICONDUCTOR MEMORY DEVICE - A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F | 2012-08-02 |
| 20120193698 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode. | 2012-08-02 |
| 20120193699 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD FOR THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate; an element isolation insulating film buried in the semiconductor substrate so as to isolate adjacent element; a memory cell having a first insulating film and a charge accumulation film; a second insulating film formed on the charge accumulation films of the memory cells and the element isolation insulating film; and a control electrode film formed on the second insulating film. An upper surface of the element isolation insulating film is lower than an upper surface of the charge accumulation film, the second insulating film is provided with a cell upper portion on the charge accumulation film and an inter-cell portion on the element isolation insulating film, and a dielectric constant of the cell upper portion is lower than a dielectric constant of the inter-cell portion. | 2012-08-02 |
| 20120193700 | Semiconductor Memory Device And Method Of Forming The Same - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 2012-08-02 |
| 20120193701 | POWER SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device. | 2012-08-02 |
| 20120193702 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation. | 2012-08-02 |
| 20120193703 | CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS - Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts. | 2012-08-02 |
| 20120193704 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction. | 2012-08-02 |
| 20120193705 | VERTICAL NONVOLATILE MEMORY DEVICES HAVING REFERENCE FEATURES - A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench. | 2012-08-02 |
| 20120193706 | VERTICAL TRANSISTOR FOR RANDOM-ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved. | 2012-08-02 |
| 20120193707 | High voltage multigate device and manufacturing method thereof - The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate. | 2012-08-02 |
| 20120193708 | Drive Current Increase in Field Effect Transistors by Asymmetric Concentration Profile of Alloy Species of a Channel Semiconductor Alloy - When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance. | 2012-08-02 |
| 20120193709 | MOS TRANSISTOR AND FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well. | 2012-08-02 |
| 20120193710 | DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions. | 2012-08-02 |
| 20120193711 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A | 2012-08-02 |
| 20120193712 | FinFET STRUCTURE HAVING FULLY SILICIDED FIN - A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins. | 2012-08-02 |
| 20120193713 | FinFET device having reduce capacitance, access resistance, and contact resistance - A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers. | 2012-08-02 |
| 20120193714 | SOI SUBSTRATE, METHOD OF MANUFACTURING THE SOI SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is an SOI substrate which includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film. | 2012-08-02 |
| 20120193715 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 2012-08-02 |
| 20120193716 | HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE - A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal. | 2012-08-02 |
| 20120193717 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first device isolation insulating film formed in a semiconductor substrate, a first well having a first conductivity type, defined by the first device isolation insulating film, and shallower than the first device isolation insulating film, a second device isolation insulating film formed in the first well, shallower than the first well, and defining a first part of the first well and a second part of the first well, a gate insulating film formed above the first part, a gate electrode formed above the gate insulating film, and an interconnection electrically connected to the second part of the first well and the gate electrode, wherein an electric resistance of the first well in a first region below the second device isolation insulating film is lower than an electric resistance of the first well in a second region other than the first region on the same depth level. | 2012-08-02 |
| 20120193718 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line. | 2012-08-02 |
| 20120193719 | SEMICONDUCTOR DEVICE AND STRUCTURE - A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors. | 2012-08-02 |
| 20120193720 | SEMICONDUCTOR DEVICE - The semiconductor device includes a substrate including an isolation region and an active region, the active region being defined by the isolation region; and a gate line including a first region on the active region, the first region including an open portion, and the open portion exposing a part of the active region, and a second region connected to the first region, the second region intersecting a boundary between the active region and the isolation region, a width of the second region being narrower than a width of the first region. | 2012-08-02 |
| 20120193721 | ELECTRONIC DEVICES - Forming, between a supporting substrate and the bottom conductive layer of a stack of layers a plurality of electronically functional elements, a non-conducting layer that functions to increase the adhesion of said bottom conductive layer to the supporting substrate. | 2012-08-02 |
| 20120193722 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes N fins made of a semiconductor material aligned in parallel with each other; a first gate electrode formed on both side surfaces of each of the N fins to cross the fins; and a second gate electrode formed in parallel with the first gate electrode on both side surfaces of the N fins to cross the fins, and having a larger gate length than a gate length of the first gate electrode, wherein number of fins formed with contacts of source/drain layers of first field-effect transistors having the first gate electrode is larger than number of fins formed with contacts of source/drain layers of second field-effect transistors having the second gate electrode. | 2012-08-02 |
| 20120193723 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias. | 2012-08-02 |
| 20120193724 | STATIC RAM CELL DESIGN AND MULTI-CONTACT REGIME FOR CONNECTING DOUBLE CHANNEL TRANSISTORS - A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased. | 2012-08-02 |
| 20120193725 | CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof - A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V | 2012-08-02 |
| 20120193726 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including an n-channel-type MISFET (Qn) having an Hf-containing insulating film ( | 2012-08-02 |
| 20120193727 | ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION - Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors. | 2012-08-02 |
| 20120193728 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a semiconductor substrate, a first gate insulating film, a silicon-containing second gate insulating film, and a first gate electrode. The first gate insulating film is formed on the semiconductor substrate and made of a material having a dielectric constant higher than a dielectric constant of silicon oxide or silicon oxynitride. The silicon-containing second gate insulating film is formed on the first gate insulating film. The first gate electrode is formed on the silicon-containing second gate insulating film and includes a metal nitride layer. The first gate insulating film, the silicon-containing second gate insulating film and the metal nitride layer form part of the pMOSFET. | 2012-08-02 |
| 20120193729 | DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES - Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor. | 2012-08-02 |
| 20120193730 | GAS SENSOR ELEMENT AND MANUFACTURING METHOD OF THE SAME - Provided herein are a gas sensor element in which deformation of a sensitive portion due to stress may be reduced and a method of manufacturing the gas sensor element. A base insulating layer | 2012-08-02 |
