31st week of 2019 patent applcation highlights part 67 |
Patent application number | Title | Published |
20190237462 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions. | 2019-08-01 |
20190237463 | FIN-FET DEVICES - A Fin-FET device is provided. The Fin-FET device includes a semiconductor substrate, a fin structure formed on the semiconductor substrate having a core region and two peripheral regions separated by the core region; a plurality of metal gate structures formed across the fin structure in the core region and covering top and sidewall surfaces of the fin structure; a barrier structure formed in each peripheral region across the fin structure and covering top and sidewall surfaces of the fin structure; a plurality of source/drain regions formed in the fin structure between each barrier structure and a neighboring metal gate structure and between neighboring metal gate structures; and a first interlayer dielectric layer formed at least on the fin structure. The first interlayer dielectric layer covers sidewall surfaces of the metal gate structures and the barrier structures. | 2019-08-01 |
20190237464 | NEGATIVE CAPACITANCE FINFET AND METHOD OF FABRICATING THEREOF - Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench. | 2019-08-01 |
20190237465 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LOGIC CIRCUIT - Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node. | 2019-08-01 |
20190237466 | RETROGRADE TRANSISTOR DOPING BY HETEROJUNCTION MATERIALS - A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material. | 2019-08-01 |
20190237467 | DRAM CELL ARRAY USING FACING BAR AND METHOD OF FABRICATING THE SAME - A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage. | 2019-08-01 |
20190237468 | METHOD OF FABRICATING BIT LINE - A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer. | 2019-08-01 |
20190237469 | RESISTOR FOR DYNAMIC RANDOM ACCESS MEMORY - A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion. The winding portion is electrically connected with an overlying metal layer through contacts, and the terminal portion includes a polysilicon layer and a metal multilayer from the bottom up. | 2019-08-01 |
20190237470 | VERTICAL 1T FERROELECTRIC MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME - A memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material. | 2019-08-01 |
20190237471 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device includes a substrate; a transistor formed on a surface of the substrate; a first insulating film formed above the transistor; a second semiconductor film formed on the first semiconductor film; a third semiconductor film formed on the second semiconductor film; a fourth semiconductor film formed on the third semiconductor film; and a ferroelectric capacitor formed on the fourth insulating film, wherein a hydrogen permeability of the third insulating film is higher than a hydrogen permeability of the first insulating film, and a hydrogen permeability and an oxygen permeability of the second insulating film and of the fourth insulating film are higher than the hydrogen permeability and an oxygen permeability of the first insulating film and of the third insulating film. | 2019-08-01 |
20190237472 | SEMICONDUCTOR MEMORY DEVICE OF THREE-DIMENSIONAL STRUCTURE - A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines. | 2019-08-01 |
20190237473 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. A gate electrode is provided above a semiconductor substrate. A sidewall insulation film is provided to the gate electrode. Source and drain regions are provided in the substrate and contain first conductive impurities. A first semiconductor region is provided in the substrate, is on a source region side, and has a concentration of the first conductive impurities lower than the source region. A second semiconductor region is provided in the substrate, is on a drain region side, and has a concentration of the first conductive impurities lower than the drain and first semiconductor regions. A channel region is provided between the first and second semiconductor regions. A third semiconductor region is provided under the channel region, and includes second conductive impurities higher in concentration than the channel region. Information is stored by accumulating charges in the sidewall insulation film. | 2019-08-01 |
20190237474 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface. | 2019-08-01 |
20190237475 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device including: a peripheral circuit structure disposed between first and second substrates and including a plurality of peripheral interconnections; a gate-stack structure disposed on the second substrate and including a plurality of gate electrodes stacked and spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, wherein the plurality of gate electrodes include a lower gate electrode, a plurality of intermediate gate electrodes disposed on the lower gate electrode, and an upper gate electrode disposed on the plurality of intermediate gate electrodes; a first through region passing through the second substrate and disposed below the gate-stack structure; a second through region passing through the second substrate and the gate-stack structure; and a first peripheral connection plug passing through the first through region and electrically connecting the lower gate electrode to a first peripheral interconnection of the peripheral. interconnections. | 2019-08-01 |
20190237476 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions. | 2019-08-01 |
20190237477 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures. | 2019-08-01 |
20190237478 | FLASH MEMORY DEVICE AND MANUFACTURE THEREOF - A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current. | 2019-08-01 |
20190237479 | MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE - A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member. | 2019-08-01 |
20190237480 | ARRAY SUBSTRATE, DRIVING METHOD AND DISPLAY DEVICE - An array substrate includes: a plurality of pixel units arranged in an array, selection lines, a reset circuit and readout circuits. Second terminals of transistors in pixel units belonging to a same column are connected to at least two of the read lines, so that a part of the pixel units are connected to a same read line, and another part of the pixel units are connected to the other one of the at least two of the read lines. For each column of the pixel units, each of the read lines is connected to one of the readout circuits corresponding to the column of the pixel units through a switching element; and for each column of the pixel units, each of the read lines is connected to the reset circuit through a switching element. | 2019-08-01 |
20190237481 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE - In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor. | 2019-08-01 |
20190237482 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device, the display panel comprising: a substrate ( | 2019-08-01 |
20190237483 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings. | 2019-08-01 |
20190237484 | DISPLAY PANEL STRUCTURE - A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line. | 2019-08-01 |
20190237485 | SELECTIVE POLYSILICON DOPING FOR GATE INDUCED DRAIN LEAKAGE IMPROVEMENT - Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively. | 2019-08-01 |
20190237486 | DISPLAY PANEL, ARRAY SUBSTRATE, AND FABRICATION METHOD THEREOF - The disclosure provides a display panel, an array substrate and a fabrication method thereof. The fabrication method of the array substrate includes forming a plurality of first thin film transistors and a plurality of second thin film transistors on the first substrate. The etch stopper layer of the second thin film transistor is different from an etch stopper layer of the first thin film transistor, and a threshold voltage of the second thin film transistor is higher than a threshold voltage of the first thin film transistor. By using the disclosed thin film transistors to form the gate driving circuit, the second thin film transistor with a high threshold voltage can be used as the driving signal outputting transistor. The abnormal multi-pulse of the gate driving circuit and the display panel caused by the low threshold voltage of the second thin film transistors may be therefore avoided. | 2019-08-01 |
20190237487 | DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure is related to a display panel and a display device. The non-display area of the display panel includes a chip bonding area, the display area includes first and second display areas. The display area includes sub-pixels and reflective layer portions, projection of reflective layer portion corresponds to opening region of sub-pixel. The display area further includes first and second signal lines. The second signal lines are connected to the first signal lines and the chip bonding area, and each includes first and second lines. The first line is connected to the first signal lines and the chip bonding area through the second line, and arranged in the second display area and extends along a column direction. A projection of first line overlaps a projection of reflective layer portion. The second lines are arranged in the non-display area. | 2019-08-01 |
20190237488 | LTPS SUBSTRATE AND FABRICATING METHOD THEREOF, THIN FILM TRANSISTOR THEREOF, ARRAY SUBSTRATE THEREOF AND DISPLAY DEVICE THEREOF - The present disclosure provides a field of display technologies, and in particular, to a LTPS substrate and a fabricating method thereof, a thin film transistor thereof, an array substrate thereof, and a display device thereof. The LTPS substrate, able to be used for the fabrication of a thin film transistor, includes a light shielding layer, the light shielding layer mainly composed of amorphous silicon doped with a lanthanide element. The present disclosure mainly employs an amorphous silicon film layer doped with the lanthanide element as the light shielding layer of the LTPS substrate, which not only ensures the light shielding efficiency but also reduces the production process, and further prevents the occurrence of the H explosion problem due to H exuding during the ELA process. | 2019-08-01 |
20190237489 | ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME - An active matrix substrate ( | 2019-08-01 |
20190237490 | FLEXIBLE DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR - A flexible display device includes a flexible substrate. A conductive layer is disposed on the flexible substrate. The conductive layer has at least a recessed region disposed thereon. | 2019-08-01 |
20190237491 | Display device - The disclosed display device includes: a substrate; a gate electrode disposed on the substrate, wherein a first projection is defined by projecting the gate electrode on the substrate; and a connecting member disposed on the gate electrode and electrically connecting to the gate electrode, wherein a second projection is defined by projecting the connecting member on the substrate, an overlapping region is defined as a region of the second projection overlapping the first projection, and an area of the first projection is greater than an area of the overlapping region. | 2019-08-01 |
20190237492 | ELECTRICAL CONNECTION STRUCTURE AND METHOD FOR MAKING SAME, TFT SUBSTRATE AND METHOD FOR MAKING SAME - A method for making an electrical connection structure includes: providing a substrate; forming a mating layer on the substrate; forming a connecting pad on the mating layer; forming a connecting line on the connecting pad and electrically coupling to the connecting pad; forming a covering layer covering the connecting line; and light irradiating the covering layer. Both the connecting pad and the connecting line are made of a metal or an alloy. The mating layer includes alternating yttrium oxide films and silicon oxide films. | 2019-08-01 |
20190237493 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer. | 2019-08-01 |
20190237494 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS INCLUDING THE SAME - A thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer, and a node connection line. The at least one thin film transistor is on the substrate. The capacitor is on the substrate and includes: a bottom electrode on the substrate; a top electrode overlapping the bottom electrode, the top electrode including an opening having a single closed curve shape; and a dielectric layer between the bottom electrode and the top electrode. The interlayer insulating layer covers the capacitor. The node connection line is on the interlayer insulating layer and electrically connects the capacitor to the at least one thin film transistor. An overlapping area of the bottom electrode and the top electrode is divided by the opening into two separate areas. | 2019-08-01 |
20190237495 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor apparatus, includes forming a first trench on a side of a first face of a semiconductor substrate having the first face and a second face, forming a gettering region by implanting ions in the semiconductor substrate through the first trench, and forming a second trench on the side of the first face of the semiconductor substrate after the forming the gettering region. A depth of a bottom surface of the second trench with reference to the first face is smaller than a depth of a bottom surface of the first trench with reference to the first face. | 2019-08-01 |
20190237496 | IMAGE SENSOR INCLUDING A PIXEL BLOCK HAVING 8-SHARED PIXEL STRUCTURE - An image sensor includes a first pixel group and a second pixel group positioned adjacent to the first pixel group. The first pixel group includes a first light receiving circuit and first and second driving circuits formed adjacent to one end of the first light receiving circuit. The first light receiving circuit includes a plurality of unit pixels sharing a first floating diffusion. The second pixel group includes a second light receiving circuit and third and fourth driving circuits formed adjacent to one end of the second light receiving circuit. The second light receiving circuit includes a plurality of unit pixels sharing a second floating diffusion. The first driving circuit is coupled in parallel to the third driving circuit, and the second driving circuit is coupled in parallel to the fourth driving circuit. | 2019-08-01 |
20190237497 | IMAGE SENSOR INCLUDING A PIXEL ARRAY HAVING PIXEL BLOCKS ARRANGED IN A ZIGZAG FORM - An image sensor may include a pixel array including a plurality of pixel blocks operable to convert light into electrical signals. Each of the plurality of pixel blocks may include a first light receiving circuit including a plurality of unit pixels that share a first floating diffusion; a second light receiving circuit arranged adjacent to the first light receiving circuit in a second direction, and including a plurality of unit pixels that share a second floating diffusion; a first driving circuit positioned between the first light receiving circuit and the second light receiving circuit; a second driving circuit positioned adjacent to the other side facing away from one side of the first light receiving circuit or the second light receiving circuit, which is adjacent to the first driving circuit; and a third driving circuit positioned adjacent to the first driving circuit or the second driving circuit. | 2019-08-01 |
20190237498 | IMAGE SENSOR INCLUDING A PIXEL ARRAY HAVING PIXEL BLOCKS ARRANGED IN A ZIGZAG FORM - An image sensor may include a pixel array including a plurality of pixel blocks structured to convert light into electrical signals. Each of the plurality of pixel blocks may include a first light receiving circuit including a plurality of unit pixels which share a first floating diffusion; a second light receiving circuit arranged adjacent to the first light receiving circuit in a second direction, and including a plurality of unit pixels which share a second floating diffusion; a first driving circuit and a second driving circuit positioned between the first light receiving circuit and the second light receiving circuit, and aligned in a first direction crossing the second direction; and an intercoupling circuit configured to electrically couple the first floating diffusion, the second floating diffusion, the first driving circuit and the second driving circuit. | 2019-08-01 |
20190237499 | Vertical Transfer Gate with Charge Transfer and Charge Storage Capabilities - In an embodiment, an image sensor includes a semiconductor region, a first doped region disposed over the semiconductor region, a ring shaped well disposed over the first doped region and surrounding parts of the first doped region, a second doped region formed within the ring shaped well and disposed over the first doped region, and a third doped region disposed over the second doped region. The ring shaped well is defined by a conductor surrounded by an insulator. The conductor is connected to a voltage terminal. The third doped region is more heavily doped than the second doped region, which is more heavily doped than the first region, and are all of the same doping type. The first doped region and the second doped region within the ring shaped well, form a potential barrier for controlling transfer of charge carriers from the first doped region to the third doped region. | 2019-08-01 |
20190237500 | 3D-INTEGRATED OPTICAL SENSOR AND METHOD OF PRODUCING A 3D-INTEGRATED OPTICAL SENSOR - A 3D-Integrated optical sensor comprises a semiconductor substrate, an integrated circuit, a wiring, a filter layer, a transparent spacer layer, and an on-chip diffuser. The semiconductor substrate has a main surface. The integrated circuit comprises at least one light sensitive area and is arranged in the substrate at or near the main surface. The wiring provides an electrical connection to the integrated circuit and is connected to the integrated circuit. The wiring is arranged on or in the semiconductor substrate. The filter layer has a direction dependent transmission characteristic and is arranged on the integrated circuit. In fact, the filter layer at least covers the light sensitive area. The transparent spacer layer is arranged on the main surface and, at least partly, encloses the filter layer. A spacer thickness is arranged to limit a spectral shift of the filter layer. The on-chip diffuser is arranged on the transparent spacer layer. | 2019-08-01 |
20190237501 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises an array of photosensitive elements and a grid. The grid is arranged on the array of photosensitive elements, defines an opening for receiving light respectively for each photosensitive element, and optically isolates each photosensitive element from its adjacent photosensitive elements. The grid may comprise an optical isolation portion and a dielectric portion above the optical isolation portion, wherein the dielectric portion defines a sidewall tilted at an angle toward an outer side of the opening. Methods of manufacturing semiconductor devices are also disclosed. | 2019-08-01 |
20190237502 | IMAGE SENSOR AND METHOD FOR MANUFACTURING IMAGE SENSOR - An image sensor may include a semiconductor substrate in which a photodiode is formed; a metal interconnection layer located above the semiconductor substrate; and an absorption layer located between the semiconductor substrate and the metal interconnection layer, wherein the absorption layer is configured to absorb light travelling through the semiconductor substrate. | 2019-08-01 |
20190237503 | Image Sensor, and Forming Method thereof, and Working Method Thereof - The present disclosure provides an image sensor, and a forming method and a working method thereof. The image sensor includes: a substrate, provided with a well region part of the well region having a photoelectric doped region, the well region including a second region, a first region and a third region located on two sides of the second region, the first region and the third region being adjacent to the two sides of the second region respectively; a first gate structure, located on a surface of the second region of the well region; a second gate structure, located on a surface of the first region of the well region; and a floating diffusion region, located in the third region of the well region, the floating diffusion region being adjacent to the first gate structure. The image sensor can reduce an image lag while increasing the full well capacity. | 2019-08-01 |
20190237504 | INFRARED IMAGING APPARATUS AND METHOD - A method of imaging infrared light is provided which comprises: exciting ultrasonic waves in a metal pillar (e.g., Cu pillar); measuring the Time-of-Flight (ToF) of the ultrasonic wave in the waveguide; whereas the ToF is a function of incident Infrared light energy on the waveguide, and reporting the infrared light energy to capture an image. An apparatus of imaging infrared light is provided which comprises: a transducer; a waveguide coupled with the transducer; and a pixel electronic circuit coupled to the transducer, wherein the transducer includes one or more of: PZT, LiNb, AlN, or GaN. | 2019-08-01 |
20190237505 | Methods and Apparatus for Via Last Through-Vias - Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer. | 2019-08-01 |
20190237506 | LED LIGHT DEVICE - Various implementations of lights and methods of lighting using LEDs as the illumination source are provided. In various implementations, for example, a light including an LED strip, a method of embedding the LED strip in one or more layers of material to incorporate the LED strip holistically into an illuminaire, and a method of illuminating works of art to provide an even, faithful presentation to a viewer are provided. | 2019-08-01 |
20190237507 | DISPLAY DEVICE - A display device is disclosed. The display device includes a light-transmitting substrate having one surface, a pad formed on the one surface, and an electrode layer formed on the one surface, electrically connected to the pad, and having a mesh shape. The electrode layer includes a first region adjacent to the pad and spaced apart from the pad, and a second region connecting the pad to the first region. A density of the mesh shape of the second region is higher than a density of the mesh shape of the first region. | 2019-08-01 |
20190237508 | DISPLAY DEVICE - A display device includes a substrate including a first recess portion, a semiconductor layer that overlaps the first recess portion, the semiconductor layer including protrusions and depressions conforming to a shape of the first recess portion, and a gate electrode that overlaps the first recess portion and the semiconductor layer, the gate electrode including protrusions and depressions conforming to the shape of the first recess portion. A thickness of the substrate in the first recess portion is less than a thickness of the substrate in a non-recess portion, excluding the first recess portion. | 2019-08-01 |
20190237509 | THERMOELECTRIC MICRO-SUPERCAPACITOR INTEGRATED DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a thermoelectric micro-supercapacitor integrated device comprising: a thermoelectric power generation module comprising a thermoelectric unit body including a thermoelectric channel interposed between two different heat sources and disposed on a substrate, the thermoelectric channel being composed of an n-type or p-type semiconductor; and a micro-supercapacitor module configured to be operated in cooperation with the thermoelectric power generation module and including a pair of collector electrodes between which an electric potential difference is generated through the thermoelectric channel. | 2019-08-01 |
20190237510 | TWO-TERMINAL SPINTRONIC DEVICES - This disclosure describes an example device that includes a first contact line, a second contact line, a spin-orbital coupling channel, and a magnet. The spin-orbital coupling channel is coupled to, and is positioned between, the first contact line and second contact line. The magnet is coupled to the spin-orbital coupling channel and positioned between the first contact line and the second contact line. A resistance of the magnet and spin-orbital coupling channel is a unidirectional magnetoresistance. | 2019-08-01 |
20190237511 | HYBRID HIGH ELECTRON MOBILITY TRANSISTOR AND ACTIVE MATRIX STRUCTURE - Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors. | 2019-08-01 |
20190237512 | MICRO-STRUCTURED ORGANIC SENSOR DEVICE AND METHOD FOR MANUFACTURING SAME - A micro-structured organic sensor device which has the following layers oriented in parallel to one another:
| 2019-08-01 |
20190237513 | SOLID STATE IMAGE SENSOR, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE - A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode. | 2019-08-01 |
20190237514 | DISPLAY DEVICE MANUFACTURING METHOD, AND DISPLAY DEVICE - In this manufacturing method, in a blue fluorescent light-emitting layer formation step, a blue fluorescent light-emitting layer is formed in both a subpixel and a subpixel; in a green fluorescent light-emitting layer formation step, a green fluorescent light-emitting layer is formed in both the subpixel and a subpixel; and in a red light-emitting layer formation step, a red light-emitting layer is formed in both the subpixel and a subpixel. In at least two of the abovementioned steps, linear vapor deposition is performed using a slitted mask having an opening that is provided so as to extend across a plurality of pixels. | 2019-08-01 |
20190237515 | OPTICAL FILTER FOR ANTI-REFLECTION AND ORGANIC LIGHT-EMITTING DEVICE - The present application relates to an optical filter and an organic light-emitting display device. The optical filter of the present application has excellent omnidirectional antireflection performance and color characteristics on the side as well as the front, and the optical filter can be applied to an organic light-emitting device to improve visibility. | 2019-08-01 |
20190237516 | DISPLAY APPARATUS WITH BENDING AREA CAPABLE OF MINIMIZING MANUFACTURING DEFECTS - A display apparatus includes a substrate, an inorganic insulating layer, a first conductive layer, and an organic material layer. The substrate includes a first area, a second area, and a bending area located between the first area and the second area the bending area configured to be bent about a first bending axis extending in a first direction. The inorganic insulating layer is arranged over the substrate. The first conductive layer extends from the first area to the second area passing over the bending area, and is arranged over the inorganic insulating layer. The organic material layer is arranged between the inorganic insulating layer and the first conductive layer and includes a central portion overlapping the bending area and a peripheral portion extending from the central portion. An average thickness of the central portion is greater than an average thickness of the peripheral portion. | 2019-08-01 |
20190237517 | ONE-WAY TRANSPARENT DISPLAY - A transparent emissive device is provided. The device may include one or more OLEDs having an anode, a cathode, and an organic emissive layer disposed between the anode and the cathode. In some configurations, the OLEDs may be non-transparent. The device may also include one or more locally transparent regions, which, in combination with the non-transparent OLEDs, provides an overall device transparency of 5% or more. | 2019-08-01 |
20190237518 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes pixels arranged in an array in a first direction and a second direction. Each pixel includes a first sub-pixel having a first light-emitting zone to emit light of a first color, a second sub-pixel having a second light-emitting zone to emit light of a second color, and a third sub-pixel having a third light-emitting zone to emit light of a third color. The first, second, and third light-emitting zones are arranged in a triangle such that the first, second, and third light-emitting zones cover respective vertices of the triangle, with one side of the triangle being substantially parallel to the first direction. Any two pixels directly adjacent in the first direction have respective patterns of first, second, and third light-emitting zones, which are substantially mirror-symmetrical to each other. Any two diagonally adjacent pixels have a substantially repeating pattern of first, second and third light-emitting zones. | 2019-08-01 |
20190237519 | DISPLAY DEVICE - A display device includes a substrate, first and second data lines, and first and second sub-pixel units. The first sub-pixel unit includes a first electrode and a first light emitting layer disposed on the first electrode. The first electrode has a first region with a first area overlapping the first data line. The second sub-pixel unit includes a second electrode and a second light emitting layer disposed on the second electrode. The second electrode has a second region with a second area overlapping the second data line, wherein the first area is greater than the second area. The luminescence color of the first light emitting layer and the luminescence color of are different, and the luminescence color of the first light emitting layer is blue. | 2019-08-01 |
20190237520 | ORGANIC LIGHT EMITTING DIODE PIXEL ARRANGEMENT STRUCTURE AND DISPLAY PANEL - An organic light emitting diode pixel arrangement structure and a display panel are provided. The organic light emitting diode pixel arrangement structure includes a central area and an edge area located around the central area. In the central area, four sub-pixels are arranged around a corresponding sub-pixel and have at least three different colors. A color of the corresponding sub-pixel is same as a color of one of the four sub-pixels arranged around the corresponding sub-pixel, so as to achieve high resolution display of the display panel. | 2019-08-01 |
20190237521 | DISPLAY DEVICE - A display device includes: a substrate on which a plurality of sub-pixels are arranged; a light-emitting device including a light-emitting layer in each of the plurality of sub-pixels; a thin film encapsulation layer covering the light-emitting layer in each of the plurality of sub-pixels; a black matrix around the plurality of sub-pixels; and an optical sensor on the substrate, the optical sensor including a sensing portion for sensing light emitted from a light source, wherein the black matrix has a plurality of openings, through which light emitted from the light source passes, in a path through which the light is received by the sensing portion via an input object which is in contact with the substrate. | 2019-08-01 |
20190237522 | DISPLAY ASSEMBLY AND MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS - A display assembly includes an array substrate, a package substrate adhered to the array substrate, and a photosensitive device; wherein the array substrate includes a pixel unit for emitting light to an object to be recognized on a displaying side of the display assembly; and the photosensitive device is provided on the package substrate for generating an optical signal based on received light reflected by the object to be recognized and converting the generated optical signal into an electric signal for recognizing the object to be recognized. | 2019-08-01 |
20190237523 | ORGANIC LIGHT-EMITTING DISPLAY PANEL AND DISPLAY APPARATUS THEREOF - An organic light-emitting display panel and a display apparatus are provided. An exemplary organic light-emitting display panel includes a base substrate; a pixel definition layer including a plurality of openings and disposed on the base substrate; and a plurality of sub-pixels. A sub-pixel includes an organic light-emitting diode; and at least a portion of the organic light-emitting diode is in an opening. The plurality of sub-pixels include at least one first sub-pixel; and at least one isolation element is disposed in the opening corresponding to the at least one first sub-pixel. | 2019-08-01 |
20190237524 | ORGANIC LIGHT-EMITTING DISPLAY PANEL AND DISPLAY APPARATUS THEREOF - An organic light-emitting display panel and a display apparatus are provided. An exemplary organic light-emitting display panel includes a substrate; an array layer disposed on the substrate and a display layer disposed on the array layer. The display layer includes an anode layer, a pixel definition layer having a plurality of the openings exposing the anode layer, an organic light-emitting material layer filled in the openings and connecting with the anode layer, and a cathode layer disposed on the organic light-emitting layer. The plurality of openings of the pixel definition layer includes a plurality of first openings and a plurality of second openings. Along a direction perpendicular to the organic light-emitting display panel, a height of a sidewall of at least a portion of a first opening is greater than a height of a sidewall of a second opening. | 2019-08-01 |
20190237525 | SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the present invention provide a substrate and a fabrication method thereof, and a display device. The substrate includes a base and a pixel defining layer in which a plurality of openings are formed, the pixel defining layer includes a first defining layer, a second defining layer and a third defining layer sequentially stacked on the base, wherein, the second defining layer is configured as a conductive layer, and an orthogonal projection of the second defining layer on the base is at least partially located outside an orthogonal projection of a side of the third defining layer close to the base on the base. | 2019-08-01 |
20190237526 | LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display (OLED) device includes a substrate having a display region including a plurality of sub-pixel regions, a respective driving transistor and a respective switching transistor on the substrate in each of the sub-pixel regions, an insulation layer structure on the substrate, the insulation layer structure having a respective trench surrounding the driving transistor in each of the sub-pixel regions, and a respective sub-pixel structure on the insulation layer structure in each of the sub-pixel regions. | 2019-08-01 |
20190237527 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus, including a substrate including a plurality of pixel areas and non-pixel areas in a display area, a plurality of pixel electrodes respectively corresponding to the plurality of pixel areas, a pixel-defining layer including a cover portion and openings, wherein the cover portion covers an edge of each of the plurality of pixel electrodes, and each of the openings exposes a central portion of a pixel electrode among the plurality of pixel electrodes, an auxiliary electrode located such that the auxiliary electrode corresponds to at least a portion of a top surface of the cover portion, and an intermediate layer and a counter electrode, each located in the openings. The pixel-defining layer may have an under-cut structure in which the at least a portion of the top surface of the cover portion is recessed from the auxiliary electrode. | 2019-08-01 |
20190237528 | DISPLAY DEVICE WITH TRENCH - Provided is a display device including a first sub-pixel, a second sub-pixel adjacent to the first sub-pixel. The first sub-pixel and the second sub-pixel each include a semiconductor film, a gate electrode, a gate insulating film, an interlayer insulating film, and a leveling film and further possesses a light-emitting element located over the leveling film. The display device has a partition wall located between the first sub-pixel and the second sub-pixel and a trench passing through the leveling film. | 2019-08-01 |
20190237529 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Disclosed is an organic light emitting display device including a dam structure disposed in a non-display area of a substrate and an alignment mark disposed outside the dam structure. The alignment mark is not covered by, and does not overlap with, the dam structure, because the alignment mark is disposed outside the dame structure. Thus, a scribing process may be performed smoothly. | 2019-08-01 |
20190237530 | DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer. | 2019-08-01 |
20190237531 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL - The present disclosure provides a display device and a manufacturing method thereof, and a display panel. The display panel may include a substrate defining a through hole; a driving wiring carried on the substrate; a solder pad being arranged on a back surface of the substrate. A first end of the driving wiring is located on a front surface of the substrate, and a second end of the driving wiring is connected to the solder pad via the through hole. | 2019-08-01 |
20190237532 | FOLDABLE DISPLAY DEVICE - A display device according to an exemplary embodiment includes a display panel including a bending portion, and a folding unit supporting the display panel, the display device being capable of being in-folded and out-folded. The folding unit includes: a first supporting plate including a first supporting portion; a second supporting plate including a second supporting portion spaced apart from the first supporting portion; a first elastic member including a first wing portion protruded from the first supporting portion; and a second elastic member including a second wing portion protruded from the second supporting portion. The bending portion includes a first portion attached to the first wing portion and a second portion attached to the second wing portion. | 2019-08-01 |
20190237533 | DISPLAY DEVICE - A display device includes a substrate that includes a display area and a peripheral area outside the display area, a display element on the display area, a peripheral circuit on the peripheral area, the peripheral circuit including a thin film transistor, a first shielding layer on the peripheral circuit. and a second shielding layer on the first shielding layer. At least one of the first shielding layer and the second shielding layer includes a hole. One shielding layer of the first shielding layer and the second shielding layer includes the hole and overlaps the other one of the first shielding layer and the second shielding layer. | 2019-08-01 |
20190237534 | SYSTEMS AND METHODS FOR SHIELDED INDUCTIVE DEVICES - In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer. | 2019-08-01 |
20190237535 | TRENCH ISOLATED CAPACITOR - An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench. | 2019-08-01 |
20190237536 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes: a silicon carbide substrate; a first silicon carbide layer disposed on the silicon carbide substrate; a second silicon carbide layer disposed on the first silicon carbide layer; a third silicon carbide layer disposed on the second silicon carbide layer; a fourth silicon carbide layer disposed on the third silicon carbide layer; and a first impurity region formed to extend through the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer. A trench is formed in the silicon carbide semiconductor device. The silicon carbide semiconductor device includes: a gate insulating film in contact with a wall of the trench; a gate electrode; a second impurity region disposed below the trench; a third impurity region formed below the first impurity region; and a fourth impurity region formed between the second impurity region and the third impurity region. | 2019-08-01 |
20190237537 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a field effect transistor (FET) and a method for manufacturing the same, the FET comprises: a substrate, a first well region located on the substrate, a second well region, a body contact region, a source region, a drain region and a gate conductor. The body contact region, the source region and the drain region are located in the first well region, the doping concentration of the second well region is higher than that of the first well region. A parasitic bipolar junction transistor (BJT) is located in the field effect transistor, current flowing through the BJT is controlled by adjusting doping concentration or area of the second well region. The second well region is formed in the first well region, so that the holding voltage of the FET is improved, and finally effect on the FET caused by the current flowing through the BJT can be weakened. | 2019-08-01 |
20190237538 | TRIGATE DEVICE WITH FULL SILICIDED EPI-LESS SOURCE/DRAIN FOR HIGH DENSITY ACCESS TRANSISTOR APPLICATIONS - After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin. | 2019-08-01 |
20190237539 | ISOLATION STRUCTURE FOR ACTIVE DEVICES - An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type. | 2019-08-01 |
20190237540 | INSULATING LAYER STRUCTURE FOR SEMICONDUCTOR PRODUCT, AND PREPARATION METHOD OF INSULATING LAYER STRUCTURE - An insulating layer structure for a semiconductor product. The insulating layer structure includes a device substrate, a supporting substrate and a thin film layer. The device substrate and the supporting substrate are silicon wafers. The thin film layer(s) is/are arranged on the device substrate or/and the supporting substrate. The device substrate and the supporting substrate are bonded together through the thin film layer arranged on at least one of the device substrate and the supporting substrate to form an integral multilayer SOI structure. The insulating layer structure formed by the present invention solves problems of serious spontaneous heating of an existing SOI device, severe warpage of an existing SOI structure caused by high-temperature annealing, a poor radio frequency characteristic and the like, and has a predictable relatively higher economic and social value. | 2019-08-01 |
20190237541 | SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS - Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack. | 2019-08-01 |
20190237542 | NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF - According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate. | 2019-08-01 |
20190237543 | Method for FinFET LDD Doping - A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench. | 2019-08-01 |
20190237544 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench. | 2019-08-01 |
20190237545 | SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: an n-type semiconductor substrate; a p-type base layer formed on a surface of the n-type semiconductor substrate; an n-type emitter layer formed on the p-type base layer, a trench gate penetrating through the p-type base layer and the n-type emitter layer; an n-type carrier stored layer formed between the n-type semiconductor substrate and the p-type base layer and having a higher concentration than that of the n-type semiconductor substrate; and a p-type collector layer formed on a back surface of the n-type semiconductor substrate, wherein with respect to the n-type carrier stored layer, a concentration gradient directing from a position of a peak concentration to the back surface of the n-type semiconductor substrate is larger than a concentration gradient directing from the position of the peak concentration to the p-type base layer, and a proton is implanted in the n-type carrier stored layer as an impurity. | 2019-08-01 |
20190237546 | METHOD OF FABRICATING ELECTRICALLY ISOLATED DIAMOND NANOWIRES AND ITS APPLICATION FOR NANOWIRE MOSFET - A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire. | 2019-08-01 |
20190237547 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - On a front surface of an n | 2019-08-01 |
20190237548 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor layer having n-type is made of silicon carbide, and has an element region and a terminal region. A plurality of field limiting ring regions having p-type are provided in the terminal region of the semiconductor layer, and are arranged spaced apart from one another. A field insulating film is provided in the terminal region of the semiconductor layer, and is in contact with the field limiting ring regions and the semiconductor layer. Each of the field limiting regions includes a halogen-containing field limiting ring part in contact with the field insulating film and containing halogen family atoms. | 2019-08-01 |
20190237549 | SEMICONDUCTOR DEVICE WITH A WELL REGION - Supposing x is defined as a position of an end of a depletion layer extending when a rated voltage V [V] is applied to a rear surface electrode, W | 2019-08-01 |
20190237550 | NITRIDE SEMICONDUCTOR DEVICE - In one embodiment, a nitride semiconductor device is provided with a first semiconductor layer that is a layer of Al | 2019-08-01 |
20190237551 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device | 2019-08-01 |
20190237552 | METHOD FOR FORMING GATE STRUCTURES FOR GROUP III-V FIELD EFFECT TRANSISTORS - A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process. | 2019-08-01 |
20190237553 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region. | 2019-08-01 |
20190237554 | ELECTRODE STRUCTURE FOR FIELD EFFECT TRANSISTOR - A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure. | 2019-08-01 |
20190237555 | NOVEL GATE FEATURE IN FINFET DEVICE - A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature. | 2019-08-01 |
20190237556 | STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR ELEMENT, AND ELECTRONIC CIRCUIT - A structure including a metal oxide semiconductor layer and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and a film thickness of the noble metal oxide layer is more than 10 nm. | 2019-08-01 |
20190237557 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer. | 2019-08-01 |
20190237558 | SIC SEMICONDUCTOR DEVICE HAVING PN JUNCTION INTERFACE AND METHOD FOR MANUFACTURING THE SIC SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer. | 2019-08-01 |
20190237559 | FORMING NANOSHEET TRANSISTOR USING SACRIFICIAL SPACER AND INNER SPACERS - Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity. | 2019-08-01 |
20190237560 | AIR GAP SPACER WITH CONTROLLED AIR GAP HEIGHT - A FinFET and method for fabricating an air gap spacer in a FinFET is disclosed. The FinFET includes a sidewall spacer between a gate material and an interlayer dielectric material. The sidewall spacer includes a lower portion that extends fully between the gate and the interlayer dielectric material and an upper portion that includes an airgap. The sidewall spacer is fabricated by depositing a sacrificial gate structure in a gate region having an upper sacrificial layer and a lower sacrificial layer, and removing the upper sacrificial layer to expose a sidewall spacer region. Airgap spacer material is deposited in the exposed sidewall spacer region to form an upper portion of the sidewall spacer having the air gap. | 2019-08-01 |
20190237561 | SEMICONDUCTOR STRUCTURES HAVING INCREASED CHANNEL STRAIN USING FIN RELEASE IN GATE REGIONS - A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region. | 2019-08-01 |