31st week of 2019 patent applcation highlights part 63 |
Patent application number | Title | Published |
20190237060 | APPARATUSES AND METHODS FOR SUPERPOSITION BASED WAVE SYNTHESIS - The invention provides apparatus and methods for interference based wave synthesis. The invention comprises (i) receiving information defining output wave characteristics, said output wave characteristics comprising at least an output wave frequency B, and an output signal amplitude M, (ii) determining a constant value A and (iii) driving a first input wave generator to generate a first input wave and (iv) driving a second input wave generator to generate a second input wave, such that the interfered wave synthesized by interference of the first input wave and the second input wave has output wave characteristics defined by the received information. | 2019-08-01 |
20190237061 | TRAINING NATURAL LANGUAGE SYSTEM WITH GENERATED DIALOGUES - A method for generating training data for training a natural language processing system comprises loading, into a computer memory, a computer-readable transcript representing an ordered sequence of one or more dialogue events. The method further comprises acquiring a computer-readable command describing an exemplary ordered subsequence of one or more dialogue events from the computer-readable transcript. The method further comprises re-parametrizing the computer-readable command with an alternative semantic parameter. The method further comprises generating an alternative ordered subsequence of one or more dialogue events based on the re-parametrized computer-readable command. The method further comprises outputting, to a data store, an alternative computer-readable transcript including the alternative ordered subsequence of one or more dialogue events, the alternative computer-readable transcript having a predetermined format usable to train the computerized assistant. | 2019-08-01 |
20190237062 | METHOD, APPARATUS, DEVICE AND STORAGE MEDIUM FOR PROCESSING FAR-FIELD ENVIRONMENTAL NOISE - Embodiments of the present disclosure include methods, apparatuses, devices, and computer readable storage mediums for processing far-field environmental noise. The method can comprise processing collected far-field environmental noise to a noise segment in a predetermined format. The method can further comprise establishing a far-field voice recognition model based on the noise segment and a near-field voice segment; and determining validity of the noise segment based on the far-field voice recognition model. The solution of the present disclosure can optimize anti-noise performance of the far-field voice recognition model by differentiated training of noise in different user scenarios of a far-field voice recognition product. | 2019-08-01 |
20190237063 | LANGUAGE MODEL BIASING MODULATION - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for modulating language model biasing. In some implementations, context data is received. A likely context associated with a user is determined based on at least a portion of the context data. One or more language model biasing parameters based at least on the likely context associated with the user is selected. A context confidence score associated with the likely context based on at least a portion of the context data is determined. One or more language model biasing parameters based at least on the context confidence score is adjusted. A baseline language model based at least on the one or more of the adjusted language model biasing parameters is biased. The baseline language model is provided for use by an automated speech recognizer (ASR). | 2019-08-01 |
20190237064 | SYSTEMS AND METHODS FOR CONVERSATIONS WITH DEVICES ABOUT MEDIA USING INTERRUPTIONS AND CHANGES OF SUBJECTS - Systems and methods are described herein for providing media guidance. Control circuitry may receive a first voice input and access a database of topics to identify a first topic associated with the first voice input. A user interface may generate a first response to the first voice input, and subsequent to generating the first response, the control circuitry may receive a second voice input. The control circuitry may determine a match between the second voice input and an interruption input such as a period of silence or a keyword or a phrase, such as “Ahh,”, “Umm,”, or “Hmm.” The user interface may generate a second response that is associated with a second topic related to the first topic. By interrupting the conversation and changing the subject from time to time, media guidance systems can appear to be more intelligent and human. | 2019-08-01 |
20190237065 | METHOD AND APPARATUS FOR AUDIO DATA PROCESSING - Embodiments of the disclosure provide methods and apparatuses processing audio data. The method can include: acquiring audio data by an audio capturing device, determining feature information of an enclosure in which the audio capturing device is located, and reverberating the feature information into the audio data. | 2019-08-01 |
20190237066 | SOURCE LOCALIZATION METHOD BY USING STEERING VECTOR ESTIMATION BASED ON ON-LINE COMPLEX GAUSSIAN MIXTURE MODEL - Provided is a source localization in an apparatus for performing a source localization, a target sound source enhancement or speech recognition. The source localization method using input signals input from a plurality of microphones, comprising steps of: (a) obtaining a log likelihood function or an auxiliary function under the assumption that a target source signal mixed with noises satisfies a CGMM model; (b) obtaining an equation for estimating parameter values of the log likelihood function or the auxiliary function so that a value of the log likelihood function or the auxiliary function is maximized recursively in each time frame; (c) estimating a covariance matrix recursively in each time frame; and (d) estimating a steering vector recursively by using the estimated covariance matrix, wherein the steering vector of the target sound source is estimated from the input signals. | 2019-08-01 |
20190237067 | MULTI-CHANNEL VOICE RECOGNITION FOR A VEHICLE ENVIRONMENT - A method and device for providing voice command operation in a passenger vehicle cabin having multiple occupants are disclosed. The method and device operate to monitor microphone data relating to voice commands within a vehicle cabin and determine whether the microphone data includes wake-up-word data. When the wake-up-word data relates to more than one of a plurality of vehicle cabin zones and more than one wake-up-words are coincident, the method and device operate to monitor respective microphone data for voice command data from each of the more than one of the respective ones of the plurality of vehicle cabin zones. Upon detection, the voice command data may be processed to produce respective vehicle device commands and the vehicle device command(s) can be transmitted to effect the voice command data. | 2019-08-01 |
20190237068 | Customizing Responses to Users in Automated Dialogue Systems - Mechanisms are provided for customizing responses to future questions based on identified anomalies in user profile information. An automated dialogue system monitors information associated with a plurality of entities, where the information includes quantities for variable values associated with the entities. The automated dialogue system, in response to determining that a quantity of a variable value associated with an entity in the plurality of entities has changed by an amount equal to or exceeding a corresponding threshold value, generates response information associated with a quantity of the variable value and an entity to respond to at least one future question. In addition, the automated dialogue system stores the responsive information in association with the entity for later retrieval in response to initiation of a dialogue session with the automated dialogue system. Time thresholds may be established for determining when to stop using the responsive information for responding to questions. | 2019-08-01 |
20190237069 | MULTILINGUAL VOICE ASSISTANCE SUPPORT - One general aspect includes a method including: obtaining, via a sensor, a wake-up-word from a user; obtaining, via a memory, wake-up-word language data pertaining to the respective language of the wake-up-word; identifying, via a processor, the language of the wake-up-word; identifying a selected voice assistant, from the plurality of different voice assistants, having language skills that are most appropriate for the wake-up-word, based on the wake-up-word language data; and facilitating communication with the selected voice assistant to provide assistance in the language in accordance with the wake-up-word. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. | 2019-08-01 |
20190237070 | VOICE INTERACTION METHOD, DEVICE, APPARATUS AND SERVER - A voice interaction method is provided. The method is applied to a wearable set and includes: collecting voice information through at least two microphones; processing the voice information and determining that the voice information comprises an effective voice instruction; wherein the effective voice instruction is issued by a user for a mobile terminal; and transmitting the effective voice instruction to the mobile terminal. In an embodiment, the processing of the voice information is assigned to an external device, which reduces the power consumption of a mobile terminal; and voice information is collected by at least two microphones to improve an efficiency and quality of a voice collection. | 2019-08-01 |
20190237071 | VOICE RECOGNITION METHOD, DEVICE AND SERVER - A voice recognition method, device, and a server are provided. The method includes: receiving a user voice; determining a wake-up voice of a wake-up word in the user voice, according to an acoustic feature of the user voice; and labeling the wake-up voice with a silence identifier; and ignoring the wake-up voice based on the silence identifier during voice recognition. As such, when a complex decoding algorithm is used to recognize the user voice, recognition of the wake-up word that is irrelevant to an instruction of the user is omitted, thus reducing the data amount to be processed by the decoding algorithm and improving the efficiency of voice recognition. | 2019-08-01 |
20190237072 | SMART DEVICE FUNCTION GUIDING METHOD AND SYSTEM - The present disclosure provides a smart device function guiding method and system, wherein the method comprises: obtaining a user's speech data and obtaining an operation instruction corresponding to the speech data; judging whether the operation instruction complies with a preset guidance condition, and sending a guidance speech to the smart device if the operation instruction complies with the preset guidance condition. The solution of the present disclosure can be employed to improve the efficiency of performing function guidance through speech interaction as compared with the manner of performing the function guidance through the APP or providing simple speech function guidance in the prior art. | 2019-08-01 |
20190237073 | Multi-Mode Guard for Voice Commands - Embodiments may be implemented by a computing device, such as a head-mountable display, in order to use a single guard phrase to enable different voice commands in different interface modes. An example device includes an audio sensor and a computing system configured to analyze audio data captured by the audio sensor to detect speech that includes a predefined guard phrase, and to operate in a plurality of different interface modes comprising at least a first and a second interface mode. During operation in the first interface mode, the computing system may initially disable one or more first-mode speech commands, and respond to detection of the guard phrase by enabling the one or more first-mode speech commands. During operation in the second interface mode, the computing system may initially disable a second-mode speech command, and to respond to the guard phrase by enabling the second-mode speech command. | 2019-08-01 |
20190237074 | SPEECH PROCESSING METHOD, DEVICE AND COMPUTER READABLE STORAGE MEDIUM - Embodiments of the present disclosure are directed to a speech processing method, device, and a computer readable storage medium. The electronic device includes a microphone configured to receive voice information. A first communication module is operable to be connected to a server and configured to send the voice information to the server and to receive a control instruction generated based on the voice information from the server. A second communication module is operable to be connected to the terminal device and configured to send the control instruction to the terminal device and to receive an audio response to the control instruction from the terminal device. A speaker is configured to play the audio response. | 2019-08-01 |
20190237075 | INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - An information processing device includes: a first reception unit configured to receive an input of one or more characters; a second reception unit configured to receive an input of voice; and a voice recognition unit configured to recognize the voice, and output a voice recognition result beginning with the one or more characters entered into the first reception unit when the second reception unit receives the input of voice with the input of the one or more characters received by the first reception unit. | 2019-08-01 |
20190237076 | AUGMENTATION OF KEY PHRASE USER RECOGNITION - Examples for augmenting user recognition via speech are provided. One example method comprises, on a computing device, monitoring a use environment via one or more sensors including an acoustic sensor, detecting utterance of a key phrase via data from the acoustic sensor, and based upon the selected data from the acoustic sensor and also on other environmental sensor data collected at different times than the selected data from the acoustic sensor, determining a probability that the key phrase was spoken by an identified user. The method further includes, if the probability meets or exceeds a threshold probability, then performing an action on the computing device. | 2019-08-01 |
20190237077 | AUTO-COMPLETE METHODS FOR SPOKEN COMPLETE VALUE ENTRIES - An auto-complete method for a spoken complete value entry is provided. A processor receives a possible complete value entry having a unique subset, prompts a user to speak the spoken complete value entry, receives a spoken subset of the spoken complete value entry, compares the spoken subset with the unique subset of the possible complete value entry, and automatically completes the spoken complete value entry to match the possible complete value entry if the unique subset matches the spoken subset. The spoken subset has a predetermined minimum number of characters. | 2019-08-01 |
20190237078 | VOICE RECOGNITION IMAGE FEEDBACK PROVIDING SYSTEM AND METHOD - Voice recognition image feedback providing system and method capable of providing conveniently various services to a user is disclosed. A voice recognition image feedback device in the system comprises a voice recognition unit configured to recognize user's voice, an image feedback unit configured to output an image corresponding to the voice in a direction where the voice is inputted and a control unit configured to control the voice recognition unit and the image feedback unit. Here, wherein the image is outputted to a user peripheral location area so that the image is shown to the user, the user peripheral location area means an area having a radius of 3 meter based on a point at which the user locates, and at least part of the image is shown in the area having the radius of 3 meter. | 2019-08-01 |
20190237079 | Multimodal Dialog in a Motor Vehicle - A method for carrying out a multimodal dialog in a vehicle, in particular a motor vehicle, via which method the interaction between the vehicle and a vehicle user is improved with regard to the provision of a dialog that is as natural as possible. For this purpose, the following acts are performed: sensing an input of a vehicle user for activating a voice dialog and activating gesture recognition. | 2019-08-01 |
20190237080 | CONVERSATION PRINT SYSTEM AND METHOD - Conversation Print: A method, computer program product, and computing system for receiving voice-based content from a third-party. The voice-based content is processed to define a text-based transcript for the voice-based content. The voice-based content is processed to define speech-pattern indicia for the voice-based content. A conversation print for the voice-based content is generated based, at least in part, upon the text-based transcript and the speech-pattern indicia. | 2019-08-01 |
20190237081 | CONVERSATION PRINT SYSTEM AND METHOD - A method, computer program product, and computing system for defining a conversation print for each of a plurality of known fraudsters, thus defining a plurality of fraudster conversation prints. The plurality of fraudster conversation prints is processed to identify one or more fraudster commonalities. A fraudster conversation template is generated based, at least in part, upon the one or more fraudster commonalities. | 2019-08-01 |
20190237082 | CONTEXT-BASED SMARTPHONE SENSOR LOGIC - Methods employ sensors in portable devices (e.g., smartphones) both to sense content information (e.g., audio and imagery) and context information. Device processing is desirably dependent on both. For example, some embodiments activate certain processor intensive operations (e.g., content recognition) based on classification of sensed content and context. The context can control the location where information produced from such operations is stored, or control an alert signal indicating, e.g., that sensed speech is being transcribed. Some arrangements post sensor data collected by one device to a cloud repository, for access and processing by other devices. Multiple devices can collaborate in collecting and processing data, to exploit advantages each may have (e.g., in location, processing ability, social network resources, etc.). A great many other features and arrangements are also detailed. | 2019-08-01 |
20190237083 | SYSTEM FOR CUSTOMIZED INTERACTIONS-RELATED ASSISTANCE - Examples provide a system for customizing remote interactions-related real-time assistance for trainees during training exercises. The system analyzes a first set of actions taken by a trainee during a first interaction using a set of recommended action criteria to generate an interaction score indicating a degree of conformity with recommended action criteria. The system analyzes a second set of actions taken by the trainee during a different second interaction. If the second set of actions are conforming or the interaction score is within an acceptable threshold range, the system continues to monitor the second interaction without providing assistance. If the second set of actions are non-conforming and the interaction score is within an unacceptable threshold range, the system provides real-time interaction assistance to the trainee, such as by outputting interaction recommendation instructions and/or assigning a more experience user to assist the trainee. | 2019-08-01 |
20190237084 | CONVERSATION PRINT SYSTEM AND METHOD - A method, computer program product, and computing system for defining a conversation print for each of a plurality of known entities, thus defining a plurality of conversation prints. Voice-based content is received from a third-party. The voice-based content is compared to at least one of the plurality of conversation prints to identify the third party. | 2019-08-01 |
20190237085 | DISPLAY APPARATUS AND METHOD FOR DISPLAYING SCREEN OF DISPLAY APPARATUS - A display apparatus and a method for displaying a screen of the display apparatus are provided. The display apparatus includes a display; a communication interface configured to be connected to each of a remote controller and a voice recognition server; and a processor configured to control the display and the communication interface. The processor is further configured to control the communication interface to, based on receiving a signal that corresponds to a user voice from the remote controller, transmit the signal to the voice recognition server, and based on receiving a voice recognition result that relates to the user voice from the voice recognition server, perform an operation that corresponds to the voice recognition result and control the display to display a recommendation guide that provides guidance for performing a voice control method related to the operation. | 2019-08-01 |
20190237086 | SELECTIVE FORWARD ERROR CORRECTION FOR SPATIAL AUDIO CODECS - Systems and methods for providing forward error correction for a multi-channel audio signal are described. Blocks of an audio stream are buffered into a frame. A transformation can be applied that compacts the energy of each block into a plurality of transformed channels. The energy compaction transform may compact the most energy of a block into the first transformed channel and to compact decreasing amounts of energy into each subsequent transformed channel. The transformed frame may be encoded using any suitable codec and transmitted in a packet over a network. Improved forward error correction may be provided by attaching a low bit rate encoding of the first transformed channel to a subsequent packet. To reconstruct a lost packet, the low bit rate encoding of the first channel for the lost packet may be combined with a packet loss concealment version of the other channels, constructed from a previously-received packet. | 2019-08-01 |
20190237087 | METHOD AND SYSTEM FOR ENCODING A STEREO SOUND SIGNAL USING CODING PARAMETERS OF A PRIMARY CHANNEL TO ENCODE A SECONDARY CHANNEL - A stereo sound encoding method and system for encoding left and right channels of a stereo sound signal, down mix the left and right channels of the stereo sound signal to produce primary and secondary channels, encode the primary channel, and encode the secondary channel. Encoding the secondary channel comprises analyzing coherence between coding parameters calculated during the secondary channel encoding and coding parameters calculated during the primary channel encoding to decide if the coding parameters calculated during the primary channel encoding are sufficiently close to the coding parameters calculated during the secondary channel encoding to be re-used during the secondary channel encoding | 2019-08-01 |
20190237088 | Audio Classification Based on Perceptual Quality for Low or Medium Bit Rates - The quality of encoded signals can be improved by reclassifying AUDIO signals carrying non-speech data as VOICE signals when periodicity parameters of the signal satisfy one or more criteria. In some embodiments, only low or medium bit rate signals are considered for re-classification. The periodicity parameters can include any characteristic or set of characteristics indicative of periodicity. For example, the periodicity parameter may include pitch differences between subframes in the audio signal, a normalized pitch correlation for one or more subframes, an average normalized pitch correlation for the audio signal, or combinations thereof. Audio signals which are re-classified as VOICED signals may be encoded in the time-domain, while audio signals that remain classified as AUDIO signals may be encoded in the frequency-domain. | 2019-08-01 |
20190237089 | IMAGE PROCESSING DEVICE, OPERATION METHOD OF IMAGE PROCESSING DEVICE, AND COMPUTER-READABLE RECORDING MEDIUM - The present disclosure relates to an image processing device, an operation method of the image processing device, and a computer-readable recording medium. The image processing device according to an embodiment in the present disclosure may comprise: a voice-obtaining unit for obtaining the voice of a user and generating a first voice signal; a communication interface unit for receiving a second voice signal of the user from an external device; and a processor which, after the first voice signal is received from the voice-obtaining unit, performs a first pre-processing operation employing voice amplification of the received first voice signal, and, after the second voice signal is received via the communication interface unit, performs a second pre-processing operation employing noise amplification of the second voice signal. | 2019-08-01 |
20190237090 | DENOISING A SIGNAL - A computer-implemented method according to one embodiment includes creating a clean dictionary, utilizing a clean signal, creating a noisy dictionary, utilizing a first noisy signal, determining a time varying projection, utilizing the clean dictionary and the noisy dictionary, denoising a second noisy signal, utilizing the time varying projection, and expanding the clean dictionary and the noisy dictionary by updating the clean dictionary and the noisy dictionary to include new clean spectro-temporal building blocks and new noisy spectro-temporal building blocks created utilizing additional clean and noisy signals. | 2019-08-01 |
20190237091 | A METHOD AND SYSTEM FOR ACOUSTIC COMMUNICATION OF DATA - The present invention relates to a method for receiving data transmitted acoustically. The method includes receiving an acoustically transmitted signal encoding data; processing the received signal to minimise environmental interference within the received signal; and decoding the processed signal to extract the data. The data encoded within the signal using a sequence of tones. A method for encoding data for acoustic transmission is also disclosed. This method includes encoding data into an audio signal using a sequence of tones. The audio signal in this method is configured to minimise environmental interference. A system and software are also disclosed. | 2019-08-01 |
20190237092 | IN-VEHICLE MEDIA VOCAL SUPPRESSION - An audio processor generates a vocal-free audio signal from an audio signal received from an audio source, directs a cross-fader to fade from the audio signal to the vocal-free audio signal responsive to occurrence of a trigger condition indicated by a status signal, and directs the cross-fader to fade from the vocal-free audio signal to the audio signal responsive to the trigger condition no longer being present. | 2019-08-01 |
20190237093 | Method And System For A Headset With Profanity Filter - A gaming headset receives a plurality of audio channels comprising game audio channels and a chat audio channel during play of a particular game. The gaming headset monitors the received audio channels for predefined words that are associated with particular sounds in a data structure, and in response to detecting predefined words, filters out at least a portion of the detected predefined words from the received plurality of audio channels. The monitoring compares sounds on the received audio channels with the particular sounds in the data structure and also performs signal analysis on the audio channels during game play to detect the occurrence of the predefined words. The filtering mutes one or more of the plurality of audio channels so that the detected occurrence of the one of the predefined words is not output via speakers of the gaming headset. | 2019-08-01 |
20190237094 | SYSTEMS FOR AND METHODS OF INTELLIGENT ACOUSTIC MONITORING - A system for intelligent acoustic monitoring. The system includes a microphone to capture environmental acoustic data and a processor coupled to the microphone. The processor is configured to receive and perform acoustic analysis on the captured acoustic data to generate an acoustic signature, based on a result of the acoustic analysis, identify an event indicated by the acoustic signature, and perform a remedial action based on the identified event. | 2019-08-01 |
20190237095 | SYSTEMS AND METHODS FOR A NEIGHBORHOOD VOICE ASSISTANT - A provider computing system includes a service recommendation database configured to retrievably store recommendation information, a network interface configured to communicate data over a network, and a processing circuit that includes a processor and memory. The memory is structured to store instructions that are executable by the processor and cause the processing circuit to receive a first set of recommendation information derived from a first set of voice data received by a local voice assistant and store the first set of recommendation information in the services recommendation database. The processing circuit is further caused to receive a request to generate a recommendation from a user voice assistant, derived from a second set of voice data received by the user voice assistant. The processing circuit is also caused to access the first set of recommendation information in response to the request and transmit the recommendation to the user voice assistant. | 2019-08-01 |
20190237096 | ULTRASONIC ATTACK DETECTION EMPLOYING DEEP LEARNING - A mechanism, method, and computer readable medium to enhance speech enabled devices. The method comprising receiving, by an ultrasonic attack detector of a speech enabled device, an audio stream from one or more microphones and a segmentation signal from a keyword detector indicating a location of a detected keyword within the audio stream, preprocessing, by the ultrasonic attack detector, a segmented portion of the audio stream including the detected keyword to obtain a spectrogram, and executing, by the ultrasonic attack detector, a neural network classifier using the spectrogram as input, the neural network classifier to discern real human speech from intermodulation distortion products resulting from ultrasonic attacks on the speech enabled device. | 2019-08-01 |
20190237097 | VOICE SIGNAL DETECTION METHOD AND APPARATUS - An audio signal is obtained by a user terminal. The audio signal is divided into a plurality of short-time energy frames based on a frequency of a predetermined voice signal. Energy of each short-time energy frame is determined. Based on the energy of each short-time energy frame, whether the audio signal includes a voice signal is determined. | 2019-08-01 |
20190237098 | DISK DEVICE AND METHOD OF MANUFACTURING DISK DEVICE - According to one embodiment, in a disk device, the head includes a first read element and a second read element. The disk medium is partitioned into a plurality of zones. The plurality of zones include a first zone and a second zone. The first zone includes a plurality of tracks on each of which a servo area and a data area are placed, a servo burst region in the servo area from which to detect the amount of off-track of the head from the center of a track, having a first bit length. The second zone includes a plurality of tracks on each of which a servo area and a data area are placed, a servo burst region in the servo area from which to detect the amount of off-track of the head from the center of a track, having a second bit length shorter than the first bit length. | 2019-08-01 |
20190237099 | MAGNETO-RESISTANCE ELEMENT IN WHICH I-III-VI2 COMPOUND SEMICONDUCTOR IS USED, METHOD FOR MANUFACTURING SAID MAGNETO-RESISTANCE ELEMENT, AND MAGNETIC STORAGE DEVICE AND SPIN TRANSISTOR IN WHICH SAID MAGNETO-RESISTANCE ELEMENT IS USED - An object of the present invention is to provide a Magneto-Resistance (MR) element showing a high Magneto-Resistance (MR) ratio and having a suitable Resistance-Area (RA) for device applications. The MR element of the present invention has a laminated structure including a first ferromagnetic layer | 2019-08-01 |
20190237100 | DETECTING DAMAGE TO TUNNELING MAGNETORESISTANCE SENSORS - Embodiments of the present invention provide methods, systems, and computer program products for detecting damage to tunneling magnetoresistance (TMR) sensors. In one embodiment, resistances of a TMR sensor are measured upon application of one or both of negative polarity bias current and positive polarity bias current at a plurality of current magnitudes. Resistances of the TMR sensor can then be analyzed with respect to current, voltage, voltage squared, and/or power, including analyses of changes to slopes calculated with these values and hysteresis-induced fluctuations, all of which can be used to detect damage to the TMR sensor. The present invention also describes methods to utilize the measured values of neighbor TMR sensors to distinguish normal versus damaged parts for head elements containing multiple TMR read elements. | 2019-08-01 |
20190237101 | FLUOROPOLYETHER COMPOUND AND LUBRICANT - Fluoropolyether compounds that can be used as a lubricant, such as for magnetic recording media. The compounds have a terminal group that includes a phenol or benzene. The fluoropolyether compounds reduce the head to media distance while keeping comparable reliability in a hard disk drive compared to current industrial widely used fluoropolyether based lubricants. | 2019-08-01 |
20190237102 | OPTICAL DISC RECORDING DEVICE AND OPTICAL DISC RECORDING METHOD - An optical disc recording device includes a data acquisition unit configured to acquire bitmap data corresponding to image information, an address information acquisition unit configured to acquire address information set in wobbles of an optical disc by wobble synchronization from the optical disc, a recording position determining unit configured to determine a recording position on the optical disc for recording the bitmap data using the address information, and a mark recording unit configured to form a recording mark corresponding to the bitmap data on the information recording track of the optical disc by applying a light beam having recording power to the recording position on the optical disc. | 2019-08-01 |
20190237103 | SYSTEM AND METHOD FOR WRITE PROTECTING PORTIONS OF MAGNETIC TAPE STORAGE MEDIA - A non-transitory computer readable storage medium includes a tape having a plurality of partitions configured for storing data, and a plurality of read-only partition identifiers, each read-only partition identifier associated with one of the plurality of partitions and readable by a tape drive having a processor and memory for writing and reading tape data. Each read-only partition identifier selectively designates a corresponding one of the partitions as read-only to prevent data from being written to the designated read-only partition by the tape drive. | 2019-08-01 |
20190237104 | DEVICE, METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR PROCESSING MOTION IMAGE - Provided is a non-transitory computer readable medium including computer readable instruction, which when executed by a computer processor cause the computer to read image data extracted from a moving image file stored in the storage medium, a frame rate of the image data, and speed control data of the image data, determine a reproduction speed of a first section of the moving image file by analyzing the speed control data, calculate a change rate of the first section based on the reproduction speed of the first section; and reproduce the moving image file by increasing a reproduction time or removing some of a plurality of frames included in the first section based on the calculated change rate. | 2019-08-01 |
20190237105 | SYSTEMS AND METHODS FOR GENERATING TIME LAPSE VIDEOS - Video information may define spherical video content having a duration. Spherical video content may define visual content viewable from a point of view as a function of progress through the spherical video content. Path information may define a path selection for the spherical video content. Path selection may include movement of a viewing window within the spherical video content. The viewing window may define extents of the visual content viewable from the point of view as the function of progress through the spherical video content. Time lapse parameter information may define at least two of a time portion of the duration, an image sampling rate, and a time lapse speed effect. A time lapse video may be generated based on the video information, the path information, and the time lapse parameter information. | 2019-08-01 |
20190237106 | GALLERY OF VIDEOS SET TO AN AUDIO TIME LINE - Machines, systems, and methods are provided for receiving, from a plurality of users, a plurality of messages, each message comprising audio content and video content taken by each of the plurality of users. For each message of the plurality of messages, the machines, systems, and method determine whether audio fingerprints of the audio content of the message correspond to a designated gallery comprising video content constructed to comprise a sequence of videos from a plurality of users set to an audio time line, and based on determining that the audio fingerprints of the audio content message correspond to the designated gallery, determine an audio segment of the audio time line of the designated gallery to which the audio content of the message corresponds. The machines, systems, and methods add the video content from the message to the audio time line of the designated gallery at the audio segment to which the audio content of the message corresponds. | 2019-08-01 |
20190237107 | SCENE AND ACTIVITY IDENTIFICATION IN VIDEO SUMMARY GENERATION - Video and corresponding metadata is accessed. Events of interest within the video are identified based on the corresponding metadata, and best scenes are identified based on the identified events of interest. A video summary can be generated including one or more of the identified best scenes. The video summary can be generated using a video summary template with slots corresponding to video clips selected from among sets of candidate video clips. Best scenes can also be identified by receiving an indication of an event of interest within video from a user during the capture of the video. Metadata patterns representing activities identified within video clips can be identified within other videos, which can subsequently be associated with the identified activities. | 2019-08-01 |
20190237108 | SMARTPHONE-BASED METHODS AND SYSTEMS - Arrangements involving portable devices (e.g., smartphones and tablet computers) are disclosed. One arrangement enables a content creator to select software with which that creator's content should be rendered—assuring continuity between artistic intention and delivery. Another utilizes a device camera to identify nearby subjects, and take actions based thereon. Others rely on near field chip (RFID) identification of objects, or on identification of audio streams (e.g., music, voice). Some technologies concern improvements to the user interfaces associated with such devices. Others involve use of these devices in connection with shopping, text entry, sign language interpretation, and vision-based discovery. Still other improvements are architectural in nature, e.g., relating to evidence-based state machines, and blackboard systems. Yet other technologies concern use of linked data in portable devices—some of which exploit GPU capabilities. Still other technologies concern computational photography. A great variety of other features and arrangements are also detailed. | 2019-08-01 |
20190237109 | TOOL-LESS MOUNTING APPARATUS FOR HARD DISK DRIVE AND STORAGE DEVICE USING THE SAME - An apparatus for mounting hard disk drive and storage device without the use of tools includes a supporting base, a fixing arm, and a rotating arm parallel with the fixing arm. The fixing arm includes a fixing plate with an end fixed to the supporting base and first mounting pins perpendicularly connected to the fixing plate. The rotating arm includes a rotating plate with an end rotatably connected to the supporting base and second mounting pins are perpendicularly connected to the rotating plate. The rotating plate is rotatable between a closed and pin-aligned position, where the rotating plate is substantially parallel with the fixing plate, and an open position in which the mounting pins have been rotated out of alignment. | 2019-08-01 |
20190237110 | ADJUSTABLE STORAGE DEVICE CARRIER - The present disclosure is directed to a 2.5-inch storage device carrier suitable for accommodating different thicknesses of 2.5-inch storage devices. A rotatable storage device holding element is provided with multiple bearing surfaces of differing heights to come into contact with storage devices of different thicknesses and securely hold the storage device within the storage carrier. | 2019-08-01 |
20190237111 | Routing Structures for Memory Applications - Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines. | 2019-08-01 |
20190237112 | INTEGRATED CIRCUIT DEVICES HAVING STROBE SIGNAL TRANSMITTERS WITH ENHANCED DRIVE CHARACTERISTICS - An integrated circuit device includes a read strobe signal transmitter including a main output drive circuit and a victim output drive circuit having an output terminal electrically coupled to an output terminal of the main output drive circuit. The read strobe signal transmitter is configured to: (i) generate a periodic active read strobe signal during a read time interval, in response to a pair of periodic drive signals, which are 180° out-of-phase relative to each other during the read time interval, and (ii) generate a disabled read strobe signal at a fixed logic level during a non-read time interval, in response to an active victim control signal. The main output drive circuit is responsive to the pair of periodic drive signals during the read time interval, and the victim output drive circuit is responsive to the active victim control signal during the non-read time interval. | 2019-08-01 |
20190237113 | DIFFERENTIAL READ-ONLY MEMORY (ROM) DEVICE - A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a | 2019-08-01 |
20190237114 | MULTI-LEVEL SENSING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A multi-level sensing circuit for a multi-level memory device configured to “recognize” more than two different voltages. The multi-level voltage sensing circuit may include a pre-charge controller configured to pre-charge a pair of bit lines with a bit-line pre-charge voltage level in response to an equalizing signal during a sensing mode. The multi-level voltage sensing circuit may include a read controller configured to maintain a voltage of the pair of bit lines at the bit-line pre-charge voltage level in response to a read control signal during a sensing operation. The multi-level voltage sensing circuit may include a sense-amplifier configured to generate data of the pair of bit lines during the sensing mode. The multi-level voltage sensing circuit may include a voltage sensor configured to generate the equalizing signal by comparing a bit-line voltage with a reference voltage. | 2019-08-01 |
20190237115 | SEMICONDUCTOR APPARATUS AND METHOD OF OPERATING THE SAME - A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the to second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command. | 2019-08-01 |
20190237116 | STACK ACCESS CONTROL FOR MEMORY DEVICE - Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function. | 2019-08-01 |
20190237117 | APPARATUSES AND METHODS FOR PROVIDING INTERNAL CLOCK SIGNALS OF DIFFERENT CLOCK FREQUENCIES IN A MEMORY DEVICE - Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command. buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes. | 2019-08-01 |
20190237118 | READ LATENCY REDUCTION IN A MEMORY DEVICE - A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface. | 2019-08-01 |
20190237119 | DATA WRITING METHOD AND MAGNETIC MEMORY - A data writing method according to an aspect is configured such that a spin-orbit torque-type magnetoresistance effect element includes: a spin-orbit torque wire extending in a first direction; and a functional portion having a first ferromagnetic layer, a non-magnetic layer, and a second ferromagnetic layer stacked on one surface of the spin-orbit torque wire in that order from the spin-orbit torque wire, wherein a voltage applied in the first direction of the spin-orbit torque wire is equal to or higher than a critical writing voltage at an environmental temperature and is equal to or lower than a predetermined value. | 2019-08-01 |
20190237120 | CAPACITIVE MATRIX ARRANGEMENT AND METHOD FOR ACTUATION THEREOF - The invention relates to a capacitive matrix arrangement that comprises an active medium, which is arranged in a layer between word lines and bit lines whose crossing points have capacitor cells, selectable by actuation of the word lines and bit lines, arranged at them with the interposed active medium, and to an actuation method, wherein the invention is based on the object of combining active actuation of capacitive elements in a matrix with the advantages of passive actuation. This is achieved by virtue of the word lines having a specific variable Debye length, i.e. consisting of a material with a variable mobile charge carrier concentration, and being arranged between the active medium and a non-active dielectric. The actuation is effected by controlling the action of an electrical field. | 2019-08-01 |
20190237121 | FERROELECTRIC MEMORY AND CAPACITOR STRUCTURE THEREOF - A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line. | 2019-08-01 |
20190237122 | APPARATUSES AND METHODS FOR ACCESSING FERROELECTRIC MEMORY INCLUDING PROVIDING REFERENCE VOLTAGE LEVEL - Apparatuses and methods are disclosed that include ferroelectric memory and for refreshing ferroelectric memory. An example apparatus includes: a word line; a first memory cell coupled to a first digit line and stores a first data on the first digit line responsive to the word line in an active state; a second memory cell coupled to a second digit line and stores a second data on the second digit line responsive to the word line in the active state. The first digit line is coupled to a first power potential and the second digit line is coupled to a second power potential in a refresh operation. | 2019-08-01 |
20190237123 | PSEUDO STATIC RANDOM ACCESS MEMORY AND CONTROL METHOD THEREOF - In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal. | 2019-08-01 |
20190237124 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor memory device includes a memory including a plurality of units, and a controller. Under control of the controller, a power for an operation of the memory is independently supplied to each of the plurality of units or is independently blocked with respect to each of the plurality of units. | 2019-08-01 |
20190237125 | APPARATUSES AND METHODS FOR PROVIDING ADDITIONAL DRIVE TO MULTILEVEL SIGNALS REPRESENTING DATA - Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other. | 2019-08-01 |
20190237126 | SEMICONDUCTOR DEVICE HAVING MODE REGISTER - Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command und activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal. | 2019-08-01 |
20190237127 | MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME - A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller. | 2019-08-01 |
20190237128 | APPARATUSES AND METHODS FOR PROVIDING DRIVING SIGNALS IN SEMICONDUCTOR DEVICES - Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats. | 2019-08-01 |
20190237129 | LOGICAL OPERATIONS USING MEMORY CELLS - The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell. | 2019-08-01 |
20190237130 | REDUCED TRANSPORT ENERGY IN A MEMORY SYSTEM - A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level. | 2019-08-01 |
20190237131 | APPARATUSES AND METHODS FOR DETECTING A ROW HAMMER ATTACK WITH A BANDPASS FILTER - Apparatuses and methods for executing row hammer (RH) refresh are described. An example apparatus includes a RH control circuit to provide a row hammer address, and a refresh control circuit to perform a RH refresh operation on a memory address array related to the RH address. The RH control circuit includes first latches each to store an old row address used to access the memory and second latches provided correspondingly to the first latches each set to a state indicating whether the old row address stored in one of the first latches is valid. The RH control circuit further including a signal generator configured to assert a sample signal when a new row address to be used to access the memory array matches the old row address stored in any one of the first latches is valid based on a state of one of the second latches. | 2019-08-01 |
20190237132 | SEMICONDUCTOR DEVICE PERFORMING ROW HAMMER REFRESH OPERATION - Disclosed herein is an apparatus that includes a memory cell array including a normal memory region assigned to first value of a redundant signal and a redundancy memory region assigned to a second value of the redundant signal; a first circuit configured to receive a row address signal, produce the first value of the redundant signal if the first circuit detects that the row address signal is inconsistent to any of redundancy information, and produce the second value of the redundant signal and additional row address signal if the first circuit detects that the row address signal is consistent to any of the redundancy information; and a second circuit configured to produce further additional row address signal based on the row address signal and the first value of the redundant signal or based on the additional row address signal and the second value of the redundant signal. | 2019-08-01 |
20190237133 | VOLATILE MEMORY DEVICE AND ELECTRONIC DEVICE COMPRISING REFRESH INFORMATION GENERATOR, INFORMATION PROVIDING METHOD THEREOF, AND REFRESH CONTROL METHOD THEREOF - A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time. | 2019-08-01 |
20190237134 | SRAM CELL FOR INTERLEAVED WORDLINE SCHEME - Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail. | 2019-08-01 |
20190237135 | Write Assist Circuitry - Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells. | 2019-08-01 |
20190237136 | Neural Network Classifier Using Array Of Two-Gate Non-volatile Memory Cells - A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines. | 2019-08-01 |
20190237137 | MEMRISTIVE ARRAYS WITH OFFSET ELEMENTS - In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements. | 2019-08-01 |
20190237138 | RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS - The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor. | 2019-08-01 |
20190237139 | HYBRID CONFIGURATION MEMORY CELL - A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device. | 2019-08-01 |
20190237140 | SINGLE POLY MULTI TIME PROGRAM CELL AND METHOD OF OPERATING THE SAME - A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well. | 2019-08-01 |
20190237141 | METHOD FOR PROGRAMMING A SPLIT-GATE MEMORY CELL AND CORRESPONDING MEMORY DEVICE - A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value. | 2019-08-01 |
20190237142 | Neural Network Classifier Using Array Of Four-Gate Non-volatile Memory Cells - A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines. | 2019-08-01 |
20190237143 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M2019-08-01 | |
20190237144 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY SYSTEM - Provided herein may be a memory device, a memory system including the memory device, and a method of operating the memory system. The memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a program operation and an erase operation on any of the plurality of memory blocks; and a logic group configured to control the peripheral circuit to perform the program operation and the erase operation. The logic group may control the peripheral circuit to perform, during the program operation on a first memory block, selected as a current open block among the plurality of memory blocks, sub-operations of an erase operation on a second memory block to be selected as a subsequent open block. | 2019-08-01 |
20190237145 | MEMORY DEVICE AND OPERATING METHOD THEREOF - There are provided a memory device and an operating method thereof. The memory device includes: a memory cell; a bit line and a word line, coupled to the memory cell; and a page buffer configured to perform a read operation on the memory cell, wherein the page buffer senses a program state of the memory cell as one of at least three program states by performing a first evaluation operation, a first sensing operation, a second evaluation operation, and a second sensing operation when one read voltage is applied to the word line during the read operation. | 2019-08-01 |
20190237146 | PREEMPTIVE IDLE TIME READ SCANS - Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan. | 2019-08-01 |
20190237147 | SEMICONDUCTOR MEMORY DEVICE - A voltage generation circuit, having a circuit scale significantly reduced as compared with the related art, is provided. The voltage generation circuit of the disclosure includes a charge pump outputting a boosted voltage to an output node, a resistor connected between the output node and another output node, and a current source circuit having first and second current paths connected in parallel between the another output node and a reference potential. The first current path includes a resistor and a first DAC. The first DAC generates a first constant current corresponding to a voltage generation code. The second current path includes a second DAC. The second DAC generates a second constant current corresponding to a code obtained by inverting the voltage generation code. Thereby, a driving voltage obtained by lowering the boosted voltage is generated at the other output node. | 2019-08-01 |
20190237148 | SEMICONDUCTOR MEMORY DEVICE AND METHODS FOR OPERATING A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again. | 2019-08-01 |
20190237149 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved. | 2019-08-01 |
20190237150 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block. | 2019-08-01 |
20190237151 | MEMORY CONTROLLER AND MEMORY SYSTEM HAVING THE SAME - There are provided a memory controller and a memory system having the same. A memory controller includes: an internal memory for storing error injection information for an error test operation and error test information that is a result of the error test operation; and a central processing unit for receiving first sector data from a host, and performing an error test operation on a memory device according to the error injection information, when the error injection information is included in the first sector data. | 2019-08-01 |
20190237152 | METHOD AND SYSTEM FOR MONITORING INFORMATION OF A MEMORY MODULE IN REAL TIME - A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation comprises receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel. | 2019-08-01 |
20190237153 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks. | 2019-08-01 |
20190237154 | SEMICONDUCTOR MEMORY DEVICE AND REPAIR METHOD THEREOF - A repair method of a semiconductor memory device which includes a memory cell array including a main and a redundant cell array and error correction code (ECC) logic includes detecting a fail bit of each of a main repair unit of the main cell array and a redundant repair unit of the redundant cell array, determining whether the fail bit detected from each of the main and redundant repair units is correctable, by using the ECC logic and determining a first or a second correctable status, calculating a first cumulative correctable fail bit count of each of the main repair unit and the redundant repair unit, and determining whether to replace the main repair unit with the redundant repair unit depending on the first correctable status, the second correctable status, and the first and second cumulative correctable fail bit counts and performing a repair operation depending on the determination result. | 2019-08-01 |
20190237155 | MEMORY INTEGRATED CIRCUIT WITH A PAGE REGISTER/STATUS MEMORY CAPABLE OF STORING ONLY A SUBSET OF ROW BLOCKS OF MAIN COLUMN BLOCKS - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 2019-08-01 |
20190237156 | COMPUTATIONAL ANALYSIS OF BIOLOGICAL DATA USING MANIFOLD AND A HYPERPLANE - A method of analyzing biological data containing expression values of a plurality of polypeptides in the blood of a subject. The method comprises: calculating a distance between a segment of a curved line and an axis defined by a direction, the distance being calculated at a point over the curved line defined by a coordinate along the direction. The method further comprises correlating the distance to the presence of, absence of, or likelihood that the subject has, a bacterial infection. The coordinate is defined by a combination of the expression values, wherein at least 90% of the segment is between a lower bound line and an upper bound line. | 2019-08-01 |
20190237157 | Quantitation and Modeling of Quality Attributes of Therapeutic Monoclonal Antibodies - Methods of predicting an in vivo serum concentration of an antibody with a post-translational modification of interest after administration of the antibody are provided, as are methods for predicting a subject's exposure to post-translational variants of the antibody. The methods include predicting a percentage of the antibody with the post-translational modification of interest using an in vivo rate constant determined for the post-translational modification, and multiplying the predicted percentage of the antibody with the post-translational modification of interest by the in vivo concentration of the antibody to determine the concentration of the antibody with the post-translational modification of interest. | 2019-08-01 |
20190237158 | METHODS TO ANALYZE GENETIC ALTERATIONS IN CANCER TO IDENTIFY THERAPEUTIC PEPTIDE VACCINES AND KITS THEREFORE - The invention describes a method for identifying T-cell activating neo-epitopes from all genetically altered proteins. The mutated proteins contribute to neo-epitopes after they are proteolytically degraded within antigen presenting cells, such as dendritic cells and macrophages. | 2019-08-01 |
20190237159 | METHOD AND SYSTEM FOR FRAGMENT ASSEMBLY AND SEQUENCE IDENTIFICATION - Embodiments of a method and/or system for improving fragment assembly and/or sequence identification includes: collecting a sample including a set of nucleic acid components associated with a set of microorganisms; generating a set of tagged sequence fragments; amplifying the set of tagged sequence fragments and sequencing the set of tagged sequence fragments; based upon the set of identifier tags, generating a set of branched assemblies of candidate sequence fragments, wherein each of the set of branched assemblies includes a set of ordered nodes and a set of branches distributed across the set of nodes; implementing a threshold criterion to reduce the set of branched assemblies to a set of branch-reduced assemblies; and identifying a set of sequences corresponding to the set of branch-reduced assemblies and/or generating an analysis informative of the set of microorganisms associated with the sample. | 2019-08-01 |