| 31st week of 2013 patent applcation highlights part 21 |
| Patent application number | Title | Published |
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| 20130193956 | METHODS AND APPARATUS FOR SENSING A SUBSTRATE IN A LOAD CUP - Methods, apparatus, and systems are provided for detecting the presence of a substrate in a load cup. The invention includes a proximity sensor having a detection pad disposed below a contact surface of a load cup assembly and a target disposed on a lever member and adapted to move toward the detection pad when a substrate is placed on the lever member and adapted to move away from the detection pad when a substrate is removed from the lever member. Numerous additional aspects are disclosed. | 2013-08-01 |
| 20130193957 | RESOLVER - A brushless axial flux electromagnetic resolver comprising a stator carrying output and excitation windings and an inductive rotor having two substantially annular members arranged substantially perpendicular to the axis of rotation of the rotor, wherein each of the annular members has a lobe which is helically skewed along the rotor and wherein the lobes of the annular members are angularly offset from one another to provide a discontinuity in the helical skew between the annular members. | 2013-08-01 |
| 20130193958 | SPINDLE FORCE ACTUATOR - An apparatus includes a circuit, a code modulator, and an actuator. The circuit is operable to detect displacements of a rotating object while in motion. The circuit is operable to detect a position of the displacements and to generate a signal associated therewith. The code modulator is operable to generate a modulated signal based on the position and the displacements. The actuator is operable to apply a force to the rotating object, wherein the force is based on the modulated signal. | 2013-08-01 |
| 20130193959 | Detection of a Metal or Magnetic Object - A measuring device for detecting a metal object includes two emission coils configured to produce superimposed magnetic fields, a receiving coil in the region of both magnetic fields, and a control device configured to control the emission coils such that a value of a voltage, which is clock synchronized with alternating voltages and which is induced in the emission coils, is minimized. The control device is configured to detect the metal object when a ratio of the alternating voltages does not correspond to a ratio of distances between the receiving coils and the emission coils. | 2013-08-01 |
| 20130193960 | Eddy Current Flaw Detection System and Eddy Current Flaw Detection Method - An eddy current flaw detection system includes an eddy current flaw detection probe having a substrate facing an inspection surface, and at least one exciting coil and at least two detecting coils provided on the substrate, a scanning device which scans the probe on the inspection surface, a scan control device which drives and controls the scanning device, an eddy current flaw detection device which acquires results of detection of a plurality of detection points corresponding to combinations of the exciting and detecting coils for each scan position of the probe, and a data processing/display device which processes data from the scan control device and the eddy current flaw detection device and thereby displays a result of flaw detection. The data processing/display device acquires three-dimensional coordinates of the detection points for each scan position of the probe and thereby creates three-dimensional flaw detection data. | 2013-08-01 |
| 20130193961 | SYSTEM AND METHOD FOR MEASURING PERTURBATIONS USING A SLOW-LIGHT FIBER BRAGG GRATING SENSOR - An optical device, a method of configuring an optical device, and a method of using a fiber Bragg grating is provided. The optical device includes a fiber Bragg grating, a narrowband optical source, and at least one optical detector. The fiber Bragg grating has a power transmission spectrum as a function of wavelength with one or more resonance peaks, each comprising a local maximum and two non-zero-slope regions with the local maximum therebetween. The light generated by the narrowband optical source has a wavelength at a non-zero-slope region of a resonance peak that is selected such that one or more of the following quantities, evaluated at the resonance peak, is at a maximum value: (a) the product of the group delay spectrum and the power transmission spectrum and (b) the product of the group delay spectrum and one minus the power reflection spectrum. | 2013-08-01 |
| 20130193962 | HALL ELECTROMOTIVE FORCE SIGNAL DETECTION CIRCUIT AND CURRENT SENSOR THEREOF - A Hall electromotive force signal detection circuit combines offset cancellation means by a spinning current method of a Hall element with a continuous-time signal processing circuit. A first Hall element includes first to fourth terminals, and generates a Hall electromotive force signal voltage Vhall | 2013-08-01 |
| 20130193963 | SURFACE SCANNING RADIO FREQUENCY ANTENNA FOR MAGNETIC RESONANCE FORCE MICROSCOPY - A probe for scanning a surface of an arbitrarily sized sample in magnetic resonance force microscopy comprising a magnetic sensor having a support element coupled to a magnetic particle, an RF antenna, at least partially circumscribing the magnetic sensor, for emitting an RF magnetic field across a portion of the sample and an optical sensor, positioned proximate the magnetic sensor, for detecting displacement of the support element. | 2013-08-01 |
| 20130193964 | METHOD FOR DETECTING OIL AND GAS FROM THE SURFACE BY NUCLEAR MAGNETIC RESONANCE IMAGING - A process using Nuclear Magnetic Resonance (NMR) with pre-determined oil specimens at the earth's surface by which to match the location and lateral boundaries of any and every producible oil reservoir responsive to NMR technology, to provide estimates to useable industry standards of porosity and permeability of said reservoirs for exploration purposes by NMR, to detect and identify depth and direction of faults in any given oil area by NMR, to provide mapping of surveyed areas prior to drilling either offset or wildcat ventures resulting from NMR testing, to evaluate reservoir and production potential in existing oil fields by NMR, to detect the existence of natural gas by NMR, and the ability to condemn any proposed drilling location in view of failure. | 2013-08-01 |
| 20130193965 | BODY/HEAD COIL SWITCHING METHOD, A POWER AMPLIFIER COMPONENT AND A MRI SYSTEM - A method for implementing a switching between a body coil and a head coil in a nuclear magnetic resonance imaging system comprising the body coil, the head coil and a power amplifier component, wherein the power amplifier component comprises sets of power amplifiers, each set of power amplifiers comprising channels of power amplifiers combined by a Wilkinson circuit, a combiner configured to combine signals from the sets of power amplifiers and to connect the sets of power amplifiers to the body coil, a first switching device comprising a first terminal configured to be grounded, a second switching device connected in series in a resistor branch of the Wilkinson circuit, and a ¼ wavelength transformation transmission line located between the second switching device and the head coil, the method comprising connecting the power amplifier component to the body coil or the head coil by setting states of both switching devices. | 2013-08-01 |
| 20130193966 | PHASE-SENSITIVE IMAGING OF MAGNETIZATION EXCHANGE AND ISOTOPE FLUX - A method for imaging a substrate and product over time is provided. The substrate and product are magnetically tagged with at least one magnetic gradient where magnetically tagging provides a tag-dependent signal phase for the substrate and a different tag-dependent signal phase for the product. At least one readout of magnetically tagged substrate and product is provided over time. The tag-dependent signal phase is used to determine product that has been transformed from magnetically tagged substrate and substrate that has been transformed from magnetically tagged product over time. | 2013-08-01 |
| 20130193967 | METHOD FOR TAKING DATA FROM A RESONANCE FORCE MICROSCOPY PROBE - A control apparatus for extracting data from an MRFM system in accordance with exemplary embodiments of the present invention comprising a visualization controller for controlling operation of the MRFM system, an initialization module, coupled to the visualization controller, for retrieving initialization data from a data source, a data collection module, coupled to the visualization controller, for extracting data from the MRFM system and an imaging module for generating image data based on the extracted data. | 2013-08-01 |
| 20130193968 | LOCAL COIL WITH A NUMBER OF SEPARATELY SWITCHABLE LOCAL COIL SHIM COILS - A local coil for an imaging system includes a number of shim coils. A current for generating a shim field in one of the shim coils may be switched on and switched off. A current for generating a shim field in another of the shim coils may be switched on and switched off. The currents may be switched on and switched off independently of one another for generating a respective shim field in the shim coils. | 2013-08-01 |
| 20130193969 | RELAXATION TIME ESTIMATION IN SURFACE NMR - Technologies including NMR relaxation time estimation methods and corresponding apparatus are disclosed. Example techniques may generate two or more alternating current transmit pulses with arbitrary amplitudes, time delays, and relative phases; apply a surface NMR acquisition scheme in which initial preparatory pulses, the properties of which may be fixed across a set of multiple acquisition sequence, are transmitted at the start of each acquisition sequence and are followed by one or more depth sensitive pulses, the pulse moments of which are varied across the set of multiple acquisition sequences; and apply processing techniques in which recorded NMR response data are used to estimate NMR properties and the relaxation times T | 2013-08-01 |
| 20130193970 | PROBE FOR MAGNETIC RESONANCE FORCE MICROSCOPY AND METHOD THEREOF - A probe for use in Magnetic Resonance Force Microscopy (MRFM) to provide an image of a sample comprising: a magnetic field source adapted to orient the spin of the nuclei in a sample; a detector capable of detecting a magnetic field comprising an oscillator; at least one conductor substantially surrounding the oscillator for forming a RF antenna for transmitting a radio frequency electromagnetic field; whereby the at least one conductor transmits a radio frequency electromagnetic field that influences the nuclei in the sample, and whereby the detector detects how the nuclei are influenced through the oscillations of the oscillator to provide identification information concerning the content of the sample. Also included is a method for magnetic resonance force microscopy of a sample. | 2013-08-01 |
| 20130193971 | MAGNETIC RESONANCE IMAGING (MRI) USING SPIR AND/OR CHESS SUPPRESSION PULSES - A magnetic resonance imaging (MRI) apparatus includes an MRI imaging condition setting unit configured to set an imaging condition frequency-selectively applying a first suppression pulse for suppressing fat and further frequency-selectively applying a second suppression pulse to the fat after applying the first suppression pulse, a slip angle of the second suppression pulse differing from that of the first suppression angle, and the second suppression pulse further suppressing remaining fat after applying the first suppression pulse. The image data acquisition unit acquires image data according to the imaging condition. | 2013-08-01 |
| 20130193972 | MAGNETIC RESONANCE IMAGING APPARATUS - A magnetic resonance imaging apparatus of an embodiment has a setting unit configured to set a pulse sequence having a pre-pulse for fat suppression and a pulse train for data acquisition for acquiring echo data for image reconstruction, the pulse sequence being provided with a plurality of dummy pulses between the pre-pulse for fat suppression and the head of the pulse train for data acquisition, a data acquisition unit configured to apply an RF pulse and a gradient magnetic field pulse based on the pulse sequence set by the setting unit to a test object so as to acquire the echo data, and an image generation unit configured to reconstruct an image of the test object from the acquired echo data, wherein an application time during which the plural dummy pulses are applied or flip angles of the plural dummy pulses can be adjusted. | 2013-08-01 |
| 20130193973 | Permanent Magnet Device for Generating an Offset Uniform Magnetic Field - Disclosed is a device for generating a homogeneous magnetic field component Bz along an axis Oz in a spherical zone of interest of centre O and radius r includes at least one first ring of axis Oz in magnetic material with radial magnetization oriented in a first direction and extending around an opening giving access to the zone of interest ZI, a second ring of axis Oz in magnetic material with radial magnetization oriented in the first direction and offset along axis Oz from the first ring and the zone of interest ZI, the inner radius and the outer radius of the second ring respectively being smaller than the inner radius and outer radius of the first ring. | 2013-08-01 |
| 20130193974 | RADIO FREQUENCY (RF) BODY COIL ASSEMBLY FOR DUAL-MODALITY IMAGING - A radio frequency (RF) body coil assembly includes a coil support structure including an inner tubular member, an outer tubular member disposed radially outwardly from the inner tubular member, and a structural material disposed between the inner and outer tubular members, an RF coil mounted to an inner surface of the coil support structure, and a positron emission tomography (PET) detector assembly mounted to an outer surface of the coil support structure. A dual-modality imaging system is also described. | 2013-08-01 |
| 20130193975 | ELECTROLOCATION APPARATUS AND METHODS FOR PROVIDING INFORMATION ABOUT ONE OR MORE SUBTERRANEAN FEATURE - In some embodiments, a method of approximating or determining at least one dimension of at least one underground geological feature in a zone of interest proximate to a well bore includes generating an electric field in the zone of interest while the well bore and geological feature at least partially contain conductive fluid. At least two sensing electrodes are provided in the well bore and configured to detect differences therebetween in electric potential caused by at least one target object in the zone of interest and provide data relating thereto to at least one data processing system. The data processing system(s) approximates or determines the dimension(s) of the geological feature(s) based at least partially upon data provided by the sensing electrodes. | 2013-08-01 |
| 20130193976 | LABEL WITH ON-BATTERY VOLTAGE INDICATOR - The present invention is a shrink label with a die cut voltage indicator device integrated therewith. | 2013-08-01 |
| 20130193977 | VOLTAGE AND TEMPERATURE SENSING OF BATTERY CELL GROUPS - The embodiments described herein include a system and a method. One embodiment provides a sensing apparatus for a battery system having a plurality of cells. The sensing apparatus includes an elongated substrate configured to extend along one side of the plurality of cells and a plurality of sensors, each corresponding to a respective one of the plurality of cells, and each configured to contact its respective cell. | 2013-08-01 |
| 20130193978 | Aerosol Detection - Aerosol detection apparatus comprises an aircraft having a dielectric member, such as a window ( | 2013-08-01 |
| 20130193979 | DEVICE AND METHOD FOR DETECTING A GROUND FAULT - An arrangement to detect a ground fault in an AC electric circuit including an electric machine having a neutral point connecting to a neutral point and a terminal side, and a unit transformer connected to the terminal side of the machine, wherein the arrangement includes a signal injection unit, a voltage transformer having a primary winding connected to the terminal side of the electric machine and a secondary winding that is open delta-connected, an instrument transformer having a primary winding connected to the neutral point of the electric machine and a secondary winding, and a ground fault detecting unit. The signal injection unit is configured to inject a signal to the secondary winding of the voltage transformer. The instrument transformer is configured to measure the resultant injected signal at its secondary winding The ground fault detecting unit is configured to detect a ground fault based on the measured signal. | 2013-08-01 |
| 20130193980 | SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs - A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance. | 2013-08-01 |
| 20130193981 | SWITCHED CAPACITOR COMPARATOR CIRCUIT - A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal. | 2013-08-01 |
| 20130193982 | TECHNIQUES FOR CALIBRATING MEASUREMENT SYSTEMS - Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response. | 2013-08-01 |
| 20130193983 | JIG FOR MEASURING EMC OF SEMICONDUCTOR CHIP AND METHOD FOR MEASURING EMC OF SEMICONDUCTOR CHIP USING THE SAME - Disclosed are a jig for measuring EMC of a semiconductor chip and a method for measuring EMC that can accurately measure the EMC at a semiconductor chip level. The jig for measuring EMC of a semiconductor chip according to the exemplary embodiment of the present disclosure includes: a chip mount unit on which the semiconductor chip for which the EMC is to be measured is mounted; a memory unit configured to store EMC information of components in a system in which the semiconductor chip is used; and a measurement control unit configured to extract the EMC information stored in the memory unit and provide the extracted EMC information to the chip mount unit at the time of measuring the EMC of the semiconductor chip. | 2013-08-01 |
| 20130193984 | TEST APPARATUSES FOR MEASURING ELECTROMAGNETIC INTERFERENCE OF IMAGE SENSOR INTEGRATED CIRCUIT DEVICES - A test apparatus for measuring electromagnetic interference (EMI) of an image sensor integrated circuit (IC) device may include an EMI test jig configured to drive a mounted image sensor IC device on one or more test conditions; an electromagnetic (EM) shielding box configured to shield external EM waves from other directions except an upper direction, the EM shielding box accepting the EMI test jig; an EM emission sensing probe configured to sense EM emissions from the image sensor IC device, the EM emission sensing probe being separated from and adjacent to the image sensor IC device in the upper direction when sensing EM emissions; and a spectrum analyzer configured to connect to the EM emission sensing probe, the spectrum analyzer configured to evaluate the EM emissions from the image sensor IC device. | 2013-08-01 |
| 20130193985 | TEMPERATURE COMPENSATED PROXIMITY SENSOR - A proximity sensor includes a relatively simple temperature compensation circuit, and includes a variable gain oscillator, a temperature sensor circuit, and a proximity determination circuit. The variable gain oscillator has a gain that varies with the proximity of a target to a sensor coil, generates an oscillating electrical signal having a substantially constant amplitude magnitude, and generates an energy signal representative of the electrical energy needed to sustain oscillations. The temperature compensation circuit senses proximity sensor temperature and supplies a temperature signal representative thereof, and the proximity determination circuit, based on the energy signal, supplies a proximity signal representative of target proximity to the sensor coil. The proximity determination circuit includes a comparator and a fixed resistor network. The comparator circuit supplies the proximity signal. The fixed resistor network is coupled between the temperature sensor circuit and comparator circuit and supplies a temperature compensation signal to the comparator circuit. | 2013-08-01 |
| 20130193986 | DELAY LINE SCHEME WITH NO EXIT TREE - A measure initialization path for a delay line structure includes: a forward path, comprising a plurality of delay stages coupled in series; a first output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path; and a second output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path. When a signal is propagated through the measure initialization path, the signal successively propagates through a delay stage of the forward path, a delay stage of the first output path and a delay stage of the second output path for performing measure initialization. | 2013-08-01 |
| 20130193987 | DEVICE FOR MEASURING ELECTRICAL CURRENT AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are embodiments of devices for measuring electrical current and related systems and methods for forming and using such devices. According to certain embodiments, devices according to the present disclosure may comprise Rogowski coils. Also disclosed are systems and methods for forming a current measuring device using a bobbin that may allow for the use of a continuous length of wire for all windings associated with the current measuring device. Automated manufacturing techniques may be utilized to facilitate the manufacture of devices for measuring electrical current and/or may reduce the cost of such devices. Various embodiments disclosed herein include the use of a bobbin that may be selectively configured between a linear configuration and a closed configuration. One or more current sensors disclosed herein may be utilized in connection with a motor management relay or other type of intelligent electronic device. | 2013-08-01 |
| 20130193988 | Electronic Imager Using an Impedance Sensor Grid Array and Method of Making - An novel impedance sensor is provided having a plurality of substantially parallel drive lines configured to transmit a signal into a surface of a proximally located object, and also a plurality of substantially parallel pickup lines oriented substantially perpendicular to the drive lines and separated from the pickup lines by a dielectric to form intrinsic electrode pairs that are impedance sensitive at each of the drive and pickup crossover locations. | 2013-08-01 |
| 20130193989 | CAPACITIVE DISTANCE SENSOR - A capacitive distance sensor is provided. The distance sensor includes a sensor element having an electrically conductive, elongated, flat sensor area which in turn contains a number of holes. The sensor area is completely surrounded by an electrically non-conductive insulating body, with the result that the insulating body completely covers the edge regions of the holes. The sensor element is produced, in particular, by first of all making the holes in the sensor area. In a subsequent step, the sensor area is completely encased by the insulating body which also completely fills the holes in the sensor area. | 2013-08-01 |
| 20130193990 | SERVO TECHNIQUES FOR APPROXIMATION OF DIFFERENTIAL CAPACITANCE OF A SENSOR - Techniques and circuits are described for approximation of the differential capacitance of a capacitive sensor to, among other things, optimize device operation and power consumption. In particular, feedback techniques are utilized for measurement and approximation of the differential capacitance of the capacitive sensor. In accordance with the disclosure, the capacitance approximation value for a test cycle preceding a given test cycle is utilized to reduce the number of iterations to be performed in a continuous series of test cycles. The capacitance approximation value for the given test cycle is reported as being equivalent to that of the preceding test cycle if the variance between the selected capacitance and the unselected capacitance is less than or equal to a first predefined value. | 2013-08-01 |
| 20130193991 | High Voltage Sensing Capacitor and Indicator Device - A high-voltage sensing capacitor as an interface apparatus that may be used to attach an indicator unit to a high-voltage AC electrical bus and to provide safety to maintenance personnel. The high-impedance nature of the sensing capacitor effectively isolates the indicator unit from the high-voltage source to which it is connected. The sensing capacitor can be directly mounted between a high-voltage busbar and an indicator unit to provide visual and/or audible alerts to maintenance personnel when high voltage conditions are detected on the busbar. The sensing capacitor is comprised of a portable, unitary capacitive structure that includes a molded insulator body encapsulating two electrodes. The electrodes only partially or incompletely overlap within the insulator body. The electrode spacing and configuration is structured to provide a deliberate amount of coupling between the two electrodes in the presence of an AC electric field. | 2013-08-01 |
| 20130193992 | Current Detection Circuit - A current detection circuit comprises: a series circuit of a first current detection part series to a first semiconductor and a second current detection part, which detects current having a smaller range than the first current detection part; a second semiconductor device, which is provided with a second drive circuit, connected in parallel with the second current detection part; and a current determination circuit configured to switch between the first current detection part and the second current detection part, based on the magnitude of the detection current of the first current detection part, wherein, when the detection current of the first current detection part is larger than a predetermined value, the voltage from the first current detection part is output, and wherein, when the detection current of the first current detection part is smaller than the predetermined value, the voltage from the second current detection part is output. | 2013-08-01 |
| 20130193993 | METHOD AND APPARATUS FOR TESTING A DEVICE-UNDER-TEST - A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource. | 2013-08-01 |
| 20130193994 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 2013-08-01 |
| 20130193995 | METHODS AND DEVICES FOR STRESSING AN INTEGRATED CIRCUIT - Disclosed is in particular a device ( | 2013-08-01 |
| 20130193996 | Semiconductor Package with Improved Testability - An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball. | 2013-08-01 |
| 20130193997 | SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER - System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit. | 2013-08-01 |
| 20130193998 | Default Current Test Method of Impulse Voltage Mixed High Voltage Direct Current Converter Valve - The test method of this invention is comparatively simpler without high voltages in normal default current tests, high voltages have been replaced by impulse generator employing positive and negative symmetrical voltages mixed with impulse voltages to form asymmetrical forward and reverse high voltages, meanwhile the timing for impulse voltage is flexible, the amplitudes could be continuously adjustable according to specific needs, to make test voltage exactly reach climax upon certain timing, the test is flexible and safe, to be applied to converter valves in different direct currents. | 2013-08-01 |
| 20130193999 | SEQUENTIAL CIRCUIT WITH CURRENT MODE ERROR DETECTION - A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals. | 2013-08-01 |
| 20130194000 | ELECTROMAGNETIC RADIATION DISSIPATING DEVICES - Electromagnetic radiation (“EMR”) dissipating devices. One example embodiment includes an electrical circuit including an EMR source configured to generate an output signal at an operating bit rate. The output signal may include an EMR component. The electrical circuit may also include an EMR dissipating device electrically coupled to the EMR source and configured to have a resonance frequency corresponding to the operating bit rate. | 2013-08-01 |
| 20130194001 | DATA OUTPUT CIRCUIT - A data output circuit includes a pre-code generation unit configured to generate one of a pre-pull-up code and a pre-pull-down code according to a calibration code in response to a voltage level of input data; and a plurality of main driving units configured to be selectively activated in response to an on-die termination code, wherein respective outputs of the plurality of main driving units are commonly connected to an output node, and wherein activated main driving units drive the output node in response to the pre-pull-up code or the pre-pull-down code. | 2013-08-01 |
| 20130194002 | RE-CONFIGURABLE MIXED-MODE INTEGRATED CIRCUIT ARCHITECTURE - An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells. | 2013-08-01 |
| 20130194003 | DRIVER CIRCUIT - The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal. | 2013-08-01 |
| 20130194004 | INTEGRATED CIRCUIT HAVING INPUT/OUTPUT CELL ARRAY HAVING SINGLE GATE ORIENTATION - An integrated circuit (IC) including a core area containing active devices and at least one input/output (I/O) cell configured to transfer signals into and out of the core area. The at least one I/O cell includes a gate orientation, a pre-driver module, and at least one post-driver module. The pre-driver module and the at least one post-driver module are offset from each other by an angle between zero and ninety degrees with respect to the gate orientation. The gate orientation for every one of the at least one I/O cell is substantially the same. | 2013-08-01 |
| 20130194005 | GENERATION OF DIFFERENTIAL SIGNALS - The invention relates to an apparatus comprising a differential driver module configured to generate at least one differential signal having steep rise and fall times for at least partially reducing common-mode noise. The invention also relates to a method for causing the differential driver to generate the signal and a system comprising the differential driver and a conductor module for transmission of the generated differential signal. A computer program for performing the method and a computer-readable medium is also part of the invention. | 2013-08-01 |
| 20130194006 | DEAD TIME GENERATION CIRCUIT AND LOAD DRIVING APPARATUS - A dead time generation circuit includes a high-side control signal generation circuit and a low-side control signal generation circuit which are separate circuits. The high-side control signal generation circuit inverts a level of a high-side control signal from a driving prohibition level to a driving permission level when a time corresponding to a first clock number has elapsed in a state where a control signal keeps a first level after the control signal transitions from a second level to the first level. The low-side control signal generation circuit inverts a level of a low-side control signal from the driving prohibition level to the driving permission level when a time corresponding to a second clock number has elapsed in a state where the control signal keeps the second level after the control signal transitions from the first level to the second level. | 2013-08-01 |
| 20130194007 | ASYNCHRONOUS SAMPLING FREQUENCY CONVERSION DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT - An asynchronous sampling frequency conversion device includes: a storage unit configured to store input digital signals; a data specifying unit configured to specify first data and second data based on a ratio of a sampling frequency of the input digital signal to a sampling frequency of an output digital signal, the first data being sampled at a sampling timing immediately before an i | 2013-08-01 |
| 20130194008 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal. | 2013-08-01 |
| 20130194009 | POWER ON RESET APPARATUS - A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven. | 2013-08-01 |
| 20130194010 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor. | 2013-08-01 |
| 20130194011 | POWER-ON RESET CIRCUIT - The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output. | 2013-08-01 |
| 20130194012 | PHASE-LOCKED LOOP SYSTEM - A phase-locked loop system is provided. The system includes a charge pump, a voltage-controlled oscillator (VCO) and a bias converter. The charge pump outputs a control voltage according to a phase frequency detection signal, and generates an output current according to a bias signal. The VCO generates an output signal according to the control voltage. The bias converter is coupled between the VCO and the charge pump and for generating the bias signal according to the control voltage. | 2013-08-01 |
| 20130194013 | APPARATUSES AND METHODS FOR ALTERING A FORWARD PATH DELAY OF A SIGNAL PATH - Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay. | 2013-08-01 |
| 20130194014 | RECEIVER CIRCUIT - A receiver circuit includes a buffering unit configured to buffer an input signal and generate a buffering signal; a variation detection unit configured to generate a control signal according to a level of a reference voltage; a driving unit configured to drive the buffering signal and generate an output signal; and a compensation unit configured to control a slew rate of the output signal in response to the control signal. | 2013-08-01 |
| 20130194015 | METHOD FOR THE OPERATION OF ELECTROSTATIC PRECIPITATORS - The disclosure relates to a method for the scheduling and/or the operation of a system of at least two power supplies ( | 2013-08-01 |
| 20130194016 | SYSTEM AND METHOD FOR GENERATING A CLOCK GATING NETWORK FOR LOGIC CIRCUITS - A system and method for generating a power efficient clock gating network for a Very Large Scale Integration (VLSI) circuit. Statistical analysis is performed upon the activity of component registers of the circuit and registers having correlated toggling behavior are clustered into sets and provided with common clock gaters. The clock gating network may be generated independently from the logical structure of the circuit. | 2013-08-01 |
| 20130194017 | DELAY LINE PHASE SHIFTER WITH SELECTABLE PHASE SHIFT - A phase shifter with selectable phase shift and comprises a switchable phase shifting element that includes a first and second signal path coupled between an input and an output and providing a, respective, first and second phase shift for a signal coupled through the respective signal paths; a switch circuit for selecting between the first and second signal paths where the first and second signal paths and the switch circuit are configured to equalize the insertion loss for the first and second signal path, the phase shifter further including control circuit for controlling the switch circuit. | 2013-08-01 |
| 20130194018 | Method for Selecting Natural Frequency in Resonant Clock Distribution Networks with no Inductor Overhead - An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels. | 2013-08-01 |
| 20130194019 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING DEVICE INCLUDING THE SAME - The semiconductor integrated circuit includes a clock tree that transmits a clock signal to a plurality of tree branches, a plurality of pulse generators, and a plurality of pulse distribution networks. Each pulse generator generates a pulse in response to the clock signal transmitted through the tree branches. Each pulse distribution network is in communication with a pulse generator of the plurality of pulse generators, and is constructed and arranged to transmit the pulse generated by each pulse generator to a plurality of pulse sinks. | 2013-08-01 |
| 20130194020 | LEVEL SHIFTING CIRCUIT - An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter. | 2013-08-01 |
| 20130194021 | CAPACITIVE COUPLING, ASYNCHRONOUS ELECTRONIC LEVEL SHIFTER CIRCUIT - An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal. | 2013-08-01 |
| 20130194022 | SWITCH MODE CIRCULATOR ISOLATED RF MIXER - The present invention relates to a radio frequency mixer circuit comprising a first terminal ( | 2013-08-01 |
| 20130194023 | ADJUSTABLE POWER SPLITTER AND CORRESPONDING METHODS & APPARATUS - An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; and a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output. | 2013-08-01 |
| 20130194024 | SEMICONDUCTOR DEVICE AND COMMUNICATION INTERFACE CIRCUIT - A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors. | 2013-08-01 |
| 20130194025 | DRIVING METHOD AND DRIVING CIRCUIT OF SCHOTTKY TYPE TRANSISTOR - A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal. | 2013-08-01 |
| 20130194026 | Half Bridge Flyback and Forward - A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off. | 2013-08-01 |
| 20130194027 | Cascode Switch with Robust Turn On and Turn Off - A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current. | 2013-08-01 |
| 20130194028 | SPRING, PARTICULARLY FOR A PUSH BUTTON - The invention relates to a spring ( | 2013-08-01 |
| 20130194029 | INPUT APPARATUS - An input apparatus includes a touch plate, a decoration layer, a film sensor, an electrode portion, a wire portion, and a guard layer. The touch plate is a basal plate for finger manipulation. The decoration layer is on a front side of the touch plate to decorate the front side. The film sensor is bonded to a rear side of the touch plate. The electrode portion is on the film sensor. The wire portion is on the film sensor and connected to the electrode portion to transmit a signal outputted from the electrode portion. The guard layer contains a guard layer formation material to suppress an electrostatic capacity between the finger and the wire portion. The guard layer formation material is combined into the decoration layer such that the decoration layer and the guard layer are provided as a single integrated member. | 2013-08-01 |
| 20130194030 | Method and Apparatus for Tap-Sensing Electronic Switch to Trigger a Function in An Electronic Equipment - An electronic switch, or an electronic equipment having such switch that has a tap-sensing detection region for a user to perform finger-tapping, foot-tapping, or other finger movements on a contact surface in this region and effectuate sending of a signal to turn on, turn off, or perform other contemplated functions of the electronic equipment. This switch emits a radiation, such as infrared light, towards the detection region. The reflection of the radiation off of an object is collected and compared to a predetermined value. If there is a match, the switch would send a signal to the device to perform the predetermined function. In operation, the switch would allow an electrical equipment to have a “virtual switch” where the user can control the device by manipulating his finger or his foot in the designated detection region. The equipment may optionally have a LED illuminator to shine a lit marking indicating where the contact surface is and how it is to be used. | 2013-08-01 |
| 20130194031 | DATA-DRIVEN CHARGE-PUMP TRANSMITTER FOR DIFFERENTIAL SIGNALING - One embodiment of the present invention sets forth a mechanism for transmitting and receiving differential signals. A transmitter combines a direct current (DC) to DC converter including a capacitor with a 2:1 multiplexer to drive a pair of differential signaling lines. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different differential signaling pairs. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit. | 2013-08-01 |
| 20130194032 | APPARATUSES AND METHODS FOR PROVIDING CAPACITANCE IN A MULTI-CHIP MODULE - Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors. | 2013-08-01 |
| 20130194033 | SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE - A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off. | 2013-08-01 |
| 20130194034 | UNIVERSAL FILTER IMPLEMENTING SECOND-ORDER TRANSFER FUNCTION - An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks. | 2013-08-01 |
| 20130194035 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V | 2013-08-01 |
| 20130194036 | ENVELOPE DETECTION APPARATUS DYNAMICALLY CONTROLLED IN RESPONSE TO INPUT SIGNAL AND ENVELOPE DETECTION METHOD THEREOF - An envelope detection apparatus dynamically controlled in response to an input signal and an envelope detection method thereof are provided. The envelope detection apparatus includes an envelope detector configured to output an envelope of an input signal. The envelope detection apparatus further includes a detection band determination unit configured to determine a detection band based on the input signal. The envelope detection apparatus further includes a detection band controller configured to control a detection band of the envelope detector based on the determined detection band. | 2013-08-01 |
| 20130194037 | POWER AMPLIFIER, RADIO-FREQUENCY POWER AMPLIFICATION DEVICE, AND AMPLIFICATION CONTROL METHOD - The present invention allows amplification with low distortion and high efficiency. | 2013-08-01 |
| 20130194038 | SIGNAL PROCESSING APPARATUS AND AMPLIFICATION APPARATUS - A signal processing apparatus includes a corrector that corrects a digital signal in accordance with a correction value, a converter that converts the digital signal corrected by the corrector into an analog signal, a sample-and-hold unit that holds an instantaneous value of the analog signal that has been obtained by the converter and that has been amplified by an amplifier for a certain frequency that is smaller than twice a maximum frequency of the analog signal, a digitizer that converts the instantaneous value held by the sample-and-hold unit into a digital value when the digitizer received an operation clock having the certain frequency, and an updater that updates, on the basis of the digital value obtained by the digitizer, the correction value of the corrector such that the correction value becomes a correction value that reduces nonlinear distortion in the analog signal amplified by the amplifier. | 2013-08-01 |
| 20130194039 | DIFFERENTIAL AMPLIFIER CIRCUIT WITH ULTRALOW POWER CONSUMPTION PROVIDED WITH ADAPTIVE BIAS CURRENT GENERATOR CIRCUIT - A differential amplifier circuit includes a differential operational amplifier that includes a differential pair circuit and operates based on a constant bias current supplied from a bias current source circuit, and the differential amplifier circuit includes a bias current generator circuit. A current monitor circuit detects two currents flowing through the differential pair circuit in correspondence with differential input voltages inputted to the differential pair circuit, and detect a minimum current of the two currents for a difference voltage of the differential input voltages as a monitored current. A current comparator circuit compares the monitored current with the constant bias current. A current amplifier circuit amplifies a voltage corresponding to the comparison result, and controls currents flowing through the differential pair circuit based on an amplified voltage, and the bias current generator circuit performs negative feedback adaptive control such that the bias current increases as the monitored current decreases. | 2013-08-01 |
| 20130194040 | Limiting Amplifier And Method Thereof - A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage. | 2013-08-01 |
| 20130194041 | AUTOMATIC GAIN CONTROL DEVICE AND METHOD, POWER ADJUSTING DEVICE AND RADIO TRANSMITTING SYSTEM - An automatic gain control device includes: a variable gain adjusting unit, for adjusting an input signal by a variable gain and outputting an adjustment result; an analog-digital converting unit, for performing analog-digital conversion on the adjustment result to obtain an analog-digital conversion result; and a gain determining unit, for determining a distribution status over a predetermined period of time of a maximum or a minimum of the analog-digital conversion result, comparing the distribution status with a first distribution condition, and if the distribution status meets the first distribution condition, then keeping the variable gain unchanged, otherwise changing the variable gain and determining newly a distribution status until the newly determined distribution status meets a second distribution condition which is at least as strict as the first distribution condition. | 2013-08-01 |
| 20130194042 | Multi-Stage Amplifier Using Tunable Transmission Lines and Frequency Response Calibration of Same - A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria. | 2013-08-01 |
| 20130194043 | LOW-POWER VOLTAGE-CONTROLLED OSCILLATOR - In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit. | 2013-08-01 |
| 20130194044 | Phase Interpolator with Voltage-Controlled Oscillator Injection-Lock - In one embodiment, one or more circuits convert an n-bit control code of a phase interpolator to a coupling control signal of k-bit wide. The one or more circuits couple one or more output signals of the phase interpolator to a reference clock of the phase interpolator based on the coupling control signal. | 2013-08-01 |
| 20130194045 | Fine Tuning of Electronic Oscillators - According to the invention there is provided a method of producing an output signal including the steps of: providing an electronic oscillator having a switching arrangement allowing the oscillator to be switched between at least a first configuration having an associated first oscillator frequency and period, and a second configuration having an associated second oscillator frequency and period, and a control arrangement for controlling the switching arrangement; dithering the oscillator between at least the first configuration and the second configuration to produce the output signal, having an intermediate frequency and period, in which the dithering is performed by switching from the first configuration to the second configuration for a pre-determined subset of each output signal period over successive cycles of the output signal frequency. | 2013-08-01 |
| 20130194046 | SYSTEMS AND METHODS FOR EXTERNAL FRIT MOUNTED COMPONENTS - Embodiments of the present invention provide improved systems and methods for external frit mounted components on a sensor device. In one embodiment, a method for fabricating a sensor device comprises securing at least one component stack on a sensor body over at least one opening in the sensor body, wherein the at least one component stack comprises a plurality of components and applying a frit to the plurality of components in the at least one component stack and the sensor body. The method further comprises heating the frit, the at least one component stack, and the sensor body such that the frit melts and cooling the frit, the at least one component stack, and the sensor body such that the at least one component stack is secured to the sensor body. | 2013-08-01 |
| 20130194047 | CLOCK DISTRIBUTOR AND ELECTRONIC DEVICE - A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part. | 2013-08-01 |
| 20130194048 | ELECTROMECHANICAL OSCILLATORS, PARAMETRIC OSCILLATORS, AND TORSIONAL RESONATORS BASED ON PIEZORESISTIVE NANOWIRES - Doubly-clamped nanowire electromechanical resonators that can be used to generate parametric oscillations and feedback self-sustained oscillations. The nanowire electromechanical resonators can be made using conventional NEMS and CMOS fabrication methods. In very thin nanowire structures (sub-micron-meter in width), additive piezoresistance patterning and fabrication can be highly difficult and thus need to be avoided. This invention shows that, in piezoresistive nanowires with homogeneous material composition and symmetric structures, no conventional and additive piezoresistance loops are needed. Using AC and DC drive signals, and bias signals of controlled frequency and amplitude, output signals having a variety of frequencies can be obtained. Various examples of such resonators and their theory of operation are described. | 2013-08-01 |
| 20130194049 | VIBRATOR ELEMENT, VIBRATOR, OSCILLATOR, AND ELECTRONIC DEVICE - A vibrator element includes: a base having a mounting surface; a vibrating arm which is extended from the base and has a first surface and a second surface that faces the first surface and is positioned on the mounting surface side, and which performs flexural vibration in a direction normal to the first and second surfaces; and a laminated structure which is provided on at least one of the first and second surfaces of the vibrating arm, and which includes at least a first electrode, a second electrode, and a piezoelectric layer disposed between the first and second electrodes, in which the vibrating arm is warped toward the mounting surface side. | 2013-08-01 |
| 20130194050 | VOLTAGE CONTROLLED OSCILLATOR USING VARIABLE CAPACITOR AND PHASE LOCKED LOOP USING THE SAME - A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL). | 2013-08-01 |
| 20130194051 | ANALOG-DIGITAL PULSE WIDTH MODULATOR (ADPWM) - Analog-to-digital pulse width modulation circuitry includes thermometer code generator circuitry, clock generator circuitry, delay selection circuitry, and an output stage. The thermometer code generator circuitry is adapted to generate a digital thermometer code based upon a received analog input voltage. The clock generator circuitry is adapted to generate a reference clock and a plurality of delayed clock signals. The delay selection circuitry is connected between the thermometer code generator circuitry and the clock generator circuitry, and is adapted to select one of the delayed clock signals to present to the output stage based upon the generated thermometer code. The selected delayed clock signal is delayed by an amount of time that is proportional to the generated thermometer code. The reference clock signal and the selected delayed clock signal are delivered to the output stage where they are used to generate a pulse width modulated output signal. | 2013-08-01 |
| 20130194052 | COMPACT ROTMAN LENS USING METAMATERIALS - Apparatus for receiving and transmitting electromagnetic signals are disclosed herein. In some embodiments, an apparatus includes a positive refractive index (PRI) medium; a negative refractive index (NRI) medium having a first side and a second side disposed in the PRI medium; a plurality of first transmission lines, each first transmission line having a first end extending toward the first side of the NRI medium; and a plurality of second transmission lines, each second transmission line having a second end extending toward the second side of the NRI medium, wherein a plurality of electromagnetic signals travelling in a first direction, enters the PRI medium and travels along the plurality of first transmissions lines and exits into first side of the NRI medium, passes through the NRI medium and exits through the second side of the NRI medium into the PRI medium along a first one of the second transmission lines. | 2013-08-01 |
| 20130194053 | Integrated Combiner with Common Mode Correction - A circuit can include multiple data input ports and data output ports, pickoff tees coupled therebetween, and a resistive network coupled between the pickoff tees. A differential signal generator can be coupled with the resistive network and the pickoff tees. Resistances of the pickoff tees and resistive network can be selected such that impedances looking into the data input ports and data output ports are matched to a desired system impedance. | 2013-08-01 |
| 20130194054 | COMBINED DIRECTIONAL COUPLER AND IMPEDANCE MATCHING CIRCUIT - An output circuit with an integrated directional coupler and impedance matching circuit is disclosed. In an exemplary design, an apparatus includes a switchplexer and an output circuit. The switchplexer is coupled to at least one power amplifier. The output circuit is coupled to the switchplexer and a load (e.g., an antenna) and includes a directional coupler and an impedance matching circuit sharing at least one inductor. The output circuit performs impedance matching for the load. The output circuit also acts as a directional coupler and provides an input radio frequency (RF) signal as an output RF signal and further couples a portion of the input RF signal as a coupled RF signal. Reusing the at least one inductor for both the directional coupler and the impedance matching circuit may reduce circuitry, size, and cost of the wireless device and may also improve performance. | 2013-08-01 |
| 20130194055 | DIRECTIONAL COUPLER - A directional coupler has a first line capable of transmitting a high-frequency signal therethrough and a second line arranged for electromagnetic coupling with the first line in a laminated board. The first line and the second line are routed on a first conductor layer to extend in close proximity to and in parallel with each other, to form an intra-layer coupling zone for developing electromagnetic coupling between the first line and the second line. The second line is routed on a second conductor layer such that the second line partially overlaps with the first line disposed on the first conductor layer with respect to a length-wise direction, when viewed in plan, to form an inter-layer coupling space for developing electromagnetic coupling between the second line on the second conductor layer and the first line on the first conductor layer. | 2013-08-01 |
