| 31st week of 2013 patent applcation highlights part 16 |
| Patent application number | Title | Published |
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| 20130193456 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate, a white pixel and a color pixel, each including an emission area, a non-emission area, a thin film transistor on the substrate, and an organic light emitting element on the substrate and electrically connected to the thin film transistor and configured to emit light at the emission area, a color filter layer between the organic light emitting element of the color pixel and the substrate at the emission area of the color pixel, and an overcoat layer having an overcoat opening corresponding to the emission area of the white pixel, and covering the color filter layer between the organic light emitting element of the color pixel and the color filter layer. | 2013-08-01 |
| 20130193457 | Light-Emitting Circuit, Luminaire, and Manufacturing Method for the Light-Emitting Circuit - According to one embodiment, a light-emitting circuit includes: a plurality of substrates in which wiring pattern layers are formed, the substrates including light-emitting elements connected to and mounted on the wiring pattern layers; and a linear conductor having electric conductivity, the linear conductor including linear joining sections at both ends electrically connected to the wiring pattern layers of the substrates and a convex section formed to be bent in a convex shape in an intermediate section between the joining sections, and the joining sections being respectively joined to the wiring pattern layers among the plurality of substrates adjacent to one another. | 2013-08-01 |
| 20130193458 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD - A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer located on at least one semiconductor light-emitting chip in order to emit various colored lights including white light. The semiconductor light-emitting device can include a casing having a cavity and a mounting surface, the chip mounted on the mounting surface, a transparent plate mounted on the wavelength converting layer within a top surface of the chip and a reflective layer located in the cavity so as to surround the transparent plate, the wavelength converting layer and the chip. The semiconductor light-emitting device can be configured to improve light-colored variability and light-emitting efficiency of the chip by using the reflective layer as a reflector, and therefore can emit a wavelength-converted light having a substantially uniform color tone and a high light-emitting efficiency from a smaller light-emitting surface than the top surface of the chip. | 2013-08-01 |
| 20130193459 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a substrate; a light-emitting element formed on the substrate; a seal member sealing the light-emitting element, the seal member formed of a transparent dry film resist laminated on the substrate with the light-emitting element interposed therebetween. | 2013-08-01 |
| 20130193460 | LIGHT EMITTING DEVICE - A light emitting device includes a plurality of light emitting elements, a plurality of lead frames, and a package. The light emitting elements are mounted on the lead frames. The package is made of resin. The package has an opening. A part of the lead frames is embedded in an inner portion of the package and another part of the lead frames is exposed on a bottom surface of the opening. A resin bottom surface on which the resin is exposed is provided on the bottom surface of the opening of the package. The package includes a wall portion projecting from the bottom surface of the opening between the light emitting elements in the opening. The light emitting elements are connected by wire that straddles the wall portion. | 2013-08-01 |
| 20130193461 | ARRAY SUBSTRATE AND DISPLAY DEVICE HAVING THE SAME - An array substrate includes a lower substrate, a switching element and a pixel electrode. In the lower substrate, unit pixel areas are each divided into a plurality of domains. The switching element is disposed on the lower substrate and transmits a pixel signal. The pixel electrode is disposed on the unit pixel area and is electrically connected to the switching element. The pixel electrode includes a plurality of slit portions disposed thereon. A portion of the slit portions is longitudinally extended in a zigzag shape along different directions in correspondence with the domains. | 2013-08-01 |
| 20130193462 | LIGHT EMITTING DEVICE - A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a dam resin made of a resin having a low optical transmittance; a fluorescent-material-containing resin layer; and an anode-side electrode and a cathode-side electrode, (a) which are provided on a primary surface of the ceramic substrate so as to face each other along a first direction on the primary surface and (b) which are disposed below at least one of the dam resin and the fluorescent-material-containing resin layer. With the configuration in which a plurality of LEDs, which are connected in a series-parallel connection, are provided on a substrate, it is possible to provide a light emitting device which can achieve restraining of luminance unevenness and an improvement in luminous efficiency. | 2013-08-01 |
| 20130193463 | Methods Of Integrating LED Chips With Heat Sinks, And Led-Based Lighting Assemblies Made Thereby - An LED-based lighting assembly includes a heat sink having at least one pedestal with an upwardly facing, upper planar surface that is raised in a vertical direction relative to an upwardly facing, lower planar surface of the heat sink. A PCB forms an aperture corresponding to the pedestal, includes electrical conductors on an upper surface thereof, and is attached to the lower planar surface. The upper planar surface extends into the aperture, and one or more LED chips attach directly to the upper planar surface and connect to the conductors such that light emits upwardly. A method of integrating LEDs with a heat sink includes mounting a PCB to a planar surface of the heat sink, mounting one or more LED chips to a raised surface of the heat sink that is not covered by the PCB, and electrically connecting the LED chips to conductors on the PCB. | 2013-08-01 |
| 20130193464 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHT EMITTING MODULE - Disclosed are a light emitting device, a light emitting device package and a light emitting module. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers; a support member under the light emitting structure; a reflective electrode layer between the second conductive semiconductor layer and the support member; and first to third connection electrodes spaced apart from each other in the support member. The second connection electrode is disposed between the first and third connection electrodes, the first and third connection electrodes are electrically connected with each other, and the support member is disposed at a peripheral portion of the first to third connection electrodes. | 2013-08-01 |
| 20130193465 | PHOSPHOR PLACEMENT IN WHITE LIGHT EMITTING DIODE ASSEMBLIES - A white LED assembly includes a blue LED die attached to a substrate. A first volume of a first luminescent material surrounds the blue LED die in a lateral dimension such that none of the first luminescent material is disposed directly over the blue LED die. The first luminescent material includes a relatively inefficient phosphor having a peak emission wavelength longer than 620 nm and includes substantially no phosphor having a peak emission wavelength shorter than 620 nm. A second volume of a second luminescent material is disposed over the first volume and the blue LED die. The second luminescent material includes a relatively efficient phosphor having a peak emission wavelength shorter than 620 nm and includes substantially no phosphor having a peak emission wavelength longer than 620 nm. Placement of the first and second luminescent materials in this way promotes removal of heat from the inefficient phosphor and reduces the likelihood of interabsorption. | 2013-08-01 |
| 20130193466 | METHOD OF FORMING A LIGHT EMITTING DIODE STRUCTURE AND A LIGHT DIODE STRUCTURE - A method of forming a vertical III-nitride based light emitting diode structure and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-on-insulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based substrate of the light emitting structure. | 2013-08-01 |
| 20130193467 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND LIGHT-EMITTING APPARATUS INCLUDING THE SAME - A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency. | 2013-08-01 |
| 20130193468 | SUBMOUNT BASED SURFACE MOUNT DEVICE (SMD) LIGHT EMITTER COMPONENTS AND METHODS - Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In some aspects, light emitter components can include a submount with a first side having a first surface area, first and second electrical contacts disposed on the first side of the submount, and at least one light emitter chip on the first side. In some aspects, the electrical contact area can be less than half of the first surface area of the first side of the submount. Components disclosed herein can include low profile parts or domes where a ratio between a dome height and a dome width is less than 0.5. A method of providing components can include providing a panel of material and LED chips, dispensing a liquid encapsulant material over the panel, and singulating the panel into individual submount based components after the encapsulant material has hardened. | 2013-08-01 |
| 20130193469 | OPTOELECTRONIC COMPONENT - An optoelectronic component includes a semiconductor chip, and a phosphor at least partly surrounding the semiconductor chip, wherein 1) the semiconductor chip emits a primary radiation in a short-wave blue spectral range at a dominant wavelength of less than approximately 465 nm, and wherein the phosphor converts at least part of the primary radiation into a longer-wave secondary radiation in a green spectral range at a dominant wavelength of approximately 490 nm to approximately 550 nm, and 2) a mixed light composed of primary radiation and secondary radiation has a dominant wavelength at wavelengths of approximately 460 nm to approximately 480 nm such that luminous flux of the mixed light is up to 130% greater than luminous flux of an optoelectronic component without a phosphor having the same dominant wavelength of 460 nm to 460 nm. | 2013-08-01 |
| 20130193470 | Optoelectronic Component and Method for Producing an Optoelectronic Component - An optoelectronic component includes a protective layer including a material containing hydrophobic groups. Furthermore, a method is described, by means of which an optoelectronic component can be produced, and in which a protective layer including hydrophobic groups is applied. | 2013-08-01 |
| 20130193471 | III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A III nitride semiconductor light emitting device with improved light emission efficiency achieved without significantly increasing forward voltage by achieving both good ohmic contact between an electrode and a semiconductor layer, and sufficient functionality of a reflective electrode layer, and a method for manufacturing the same. The III nitride semiconductor light emitting device has a III nitride semiconductor laminate including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer; an n-side electrode, a p-side electrode; and a composite layer having a reflective electrode portion and a contact portion made of Al | 2013-08-01 |
| 20130193472 | MN-ACTIVATED PHOSPHORS - The invention relates to compounds of the general formula (I): Lu | 2013-08-01 |
| 20130193473 | Lighting Device - An object of the present invention is to reduce the thickness of a lighting device using an electroluminescent material. Another object of the present invention is to simplify the structure of a lighting device using an electroluminescent material to reduce cost. A light-emitting element having a stacked structure of a first electrode layer, an EL layer, and a second electrode layer is provided over a substrate having an opening in its center, and a first connecting portion and a second connecting portion for supplying electric power to the light-emitting element are provided in the center of the substrate (in the vicinity of the opening provided in the substrate). | 2013-08-01 |
| 20130193474 | LIGHT EMITTING ELEMENT WITH IMPROVED LIGHT EXTRACTION EFFICIENCY, LIGHT EMITTING DEVICE COMPRISING THE SAME, AND FABRICATING METHOD OF THE LIGHT EMITTING ELEMENT AND THE LIGHT EMITTING DEVICE - Provided is a light emitting element, a light emitting device including the same, and fabrication methods of the light emitting element and light emitting device. The light emitting device comprises a substrate, a light emitting structure including a first conductive layer of a first conductivity type, a light emitting layer, and a second conductive layer of a second conductivity type which are sequentially stacked, a first electrode which is electrically connected with the first conductive layer; and a second electrode which is electrically connected with the second conductive layer and separated apart from the first electrode, wherein at least a part of the second electrode is connected from a top of the light emitting structure, through a sidewall of the light emitting structure, and to a sidewall of the substrate. | 2013-08-01 |
| 20130193475 | SEMIFINISHED PRODUCT AND METHOD FOR PRODUCING A LIGHT-EMITTING DIODE - The invention relates to a method and a semifinished product for producing a light-emitting diode including: a flexible supporting material; a first and a second contact area, arranged on the supporting material, for producing electrical connections; a light-emitting diode chip or a holder for a light-emitting diode chip, arranged on the supporting material; a foldable flap, formed into the supporting material, the flap being arranged in such a way that it can be folded towards and/or onto the light-emitting diode chip. Arranged on the foldable flap is at least a first electrical connecting web, which is connected to the first contact area and can be connected to a first terminal of the light-emitting diode chip by folding of the flap. | 2013-08-01 |
| 20130193476 | LIGHT EMITTING DEVICE WITH REDUCE EPI STRESS - Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling. | 2013-08-01 |
| 20130193477 | LIGHT EMITTING DIODE DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a light emitting diode device includes preparing an encapsulating resin layer; embedding a light emitting diode element in the encapsulating resin layer; and heating while pressing with gas the encapsulating resin layer having the light emitting diode element being embedded therein. | 2013-08-01 |
| 20130193478 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, METHOD FOR PRODUCING SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - In a semiconductor light emitting element having a sapphire substrate, and a lower semiconductor layer and an upper semiconductor layer laminated on the sapphire substrate, the sapphire substrate includes a substrate top surface, a substrate bottom surface, first substrate side surfaces and second substrate side surfaces; plural first cutouts and plural second cutouts are provided at border portions between the first substrate side surface and the substrate top surface and between the second substrate side surface and the substrate top surface; the lower semiconductor layer includes a lower semiconductor bottom surface, a lower semiconductor top surface, first lower semiconductor side surfaces and second lower semiconductor side surfaces; plural first projecting portions and plural first depressing portions are provided on the first lower semiconductor side surface; and plural second protruding portions and second flat portions are provided on the second lower semiconductor side surface. | 2013-08-01 |
| 20130193479 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CHIP - A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n | 2013-08-01 |
| 20130193480 | Epitaxy Technique for Reducing Threading Dislocations in Stressed Semiconductor Compounds - A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers. | 2013-08-01 |
| 20130193481 | FIELD EFFECT TRANSISTOR AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region. | 2013-08-01 |
| 20130193482 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 2013-08-01 |
| 20130193483 | Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. | 2013-08-01 |
| 20130193484 | FIELD-EFFECT TRANSISTOR ON A SELF-ASSEMBLED SEMICONDUCTOR WELL - A device including at least one transistor on a substrate in a first semiconductor material, each transistor including a gate electrode as a gate, two conductor electrodes, an island in a second semiconductor material inlaid in the substrate, defining a region capable of forming a channel as a channel region, and an insulating layer separating the gate from the two electrodes and the channel region. The channel region is inside the island and is in direct electrical contact with at least one of the two conductor electrodes. | 2013-08-01 |
| 20130193485 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; a two-dimensional electron gas suppressing layer formed over the electron supply layer; an insulating film formed over the two-dimensional electron gas suppressing layer and the electron transit layer; and a gate electrode formed over the insulating film. The gate electrode is electrically connected with the two-dimensional electron gas suppressing layer. | 2013-08-01 |
| 20130193486 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface. | 2013-08-01 |
| 20130193487 | HIGH ELECTRON MOBILITY TRANSISTORS WITH FIELD PLATE ELECTRODE - A high electron mobility transistor comprising:
| 2013-08-01 |
| 20130193488 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error. | 2013-08-01 |
| 20130193489 | INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors. | 2013-08-01 |
| 20130193490 | Semiconductor Structure and Method for Manufacturing the Same - The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process. | 2013-08-01 |
| 20130193491 | Field Controlled Diode with Positively Biased Gate - An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described. | 2013-08-01 |
| 20130193492 | SILICON CARBON FILM STRUCTURE AND METHOD - An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors. | 2013-08-01 |
| 20130193493 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - In a semiconductor device including a transistor using an oxide semiconductor film, stable electric characteristics can be provided and high reliability can be achieved. A structure of the semiconductor device, which achieves high-speed response and high-speed operation, is provided. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in order and a sidewall insulating layer is provided on the side surface of the gate electrode layer, the sidewall insulating layer has an oxygen-excess regions, which is formed in such a manner that a first insulating film is formed and then is subjected to oxygen doping treatment, a second insulating is formed over the first insulating film, and a stacked layer of the first insulating film and the second insulating film are etched. | 2013-08-01 |
| 20130193494 | TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT - The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern. | 2013-08-01 |
| 20130193495 | LIGHT RECEIVING CIRCUIT - According to an embodiment, a light-receiving circuit includes a MOSFET, a first light-receiving element and a second light-receiving element. The first light-receiving element controls a state of the MOSFET between ON state and OFF state by applying a voltage induced by a light signal between a gate of the MOSFET and a source of the MOSFET; and a second light-receiving element controls a threshold voltage of the MOSFET. | 2013-08-01 |
| 20130193496 | IMAGE SENSORS - In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern. | 2013-08-01 |
| 20130193497 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME - A photoelectric conversion apparatus includes: a first semiconductor region forming a part of a photoelectric conversion element; a second semiconductor region stacked on the first semiconductor region, and forming a part of the photoelectric conversion element; a third semiconductor region to which a signal charge transferred from the photoelectric conversion element; a fourth semiconductor region of the first conductivity type having an higher impurity concentration, between the first and third semiconductor region and between the second and third semiconductor regions, closer to a main surface than the first semiconductor region, and connected to the first semiconductor region; a first gate electrode over the fourth semiconductor region, an insulating film on the main surface and between the first gate electrode and the fourth semiconductor region; and a second gate electrode between the third and fourth semiconductor regions, and over the insulating film. | 2013-08-01 |
| 20130193498 | Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 2013-08-01 |
| 20130193499 | DECOUPLING CAPACITOR AND LAYOUT FOR THE CAPACITOR - A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region. | 2013-08-01 |
| 20130193500 | DECOUPLING FINFET CAPACITORS - A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material. | 2013-08-01 |
| 20130193501 | Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 2013-08-01 |
| 20130193502 | MEDIUM VOLTAGE MOSFET DEVICE - A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches. | 2013-08-01 |
| 20130193503 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity. | 2013-08-01 |
| 20130193504 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a plurality of interconnects, and a plurality of gap control units. The substrate includes silicon. The plurality of interconnects is provided above the substrate. The plurality of gap control units is provided respectively on the plurality of interconnects to have width dimensions greater than width dimension of the plurality of interconnects. A gap is provided between adjacent interconnects of the plurality of interconnects. An apical portion of the gap is provided between adjacent gap control units of the plurality of gap control units and between a lower surface position and an upper surface position of each of the adjacent gap control units. | 2013-08-01 |
| 20130193505 | Memory Devices and Methods of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 2013-08-01 |
| 20130193506 | SEMICONDUCTOR DEVICE HAVING DIFFERENT NON-VOLATILE MEMORIES HAVING NANOCRYSTALS OF DIFFERING DENSITIES AND METHOD THEREFOR - A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density. | 2013-08-01 |
| 20130193507 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate. | 2013-08-01 |
| 20130193508 | SEMICONDUCTOR DEVICE WITH SUPER JUNCTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer. | 2013-08-01 |
| 20130193509 | SOI LATERAL MOSFET DEVICES - The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits. | 2013-08-01 |
| 20130193510 | SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING - A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension. | 2013-08-01 |
| 20130193511 | VERTICAL TRANSISTOR STRUCTURE - A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation. | 2013-08-01 |
| 20130193512 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. | 2013-08-01 |
| 20130193513 | Multi-Gate Field Effect Transistor with a Tapered Gate Profile - A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin. | 2013-08-01 |
| 20130193514 | METHOD TO ENABLE THE FORMATION OF SILICON GERMANIUM CHANNEL OF FDSOI DEVICES FOR PFET THRESHOLD VOLTAGE ENGINEERING - An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks. | 2013-08-01 |
| 20130193515 | SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS - An SRAM structure and method which includes a semiconductor on insulator (SOI) substrate which includes a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer. The SOI layer has a first thickness. The SRAM structure further includes a FinFET transistor formed on the SOI substrate including a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer and a planar transistor formed on the SOI substrate including a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer. The first thickness is greater than the second thickness. Also included is a gate electrode on the FinFET transistor and the planar transistor. | 2013-08-01 |
| 20130193516 | SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION - SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors. | 2013-08-01 |
| 20130193517 | SEMICONDUCTOR DEVICE WITH LATERAL AND VERTICAL CHANNEL CONFINEMENT AND METHOD OF FABRICATING THE SAME - Semiconductor devices and methods of making semiconductor devices are provided. Boron diffusion into source/drain regions is restricted by a vertical and lateral confinement area formed on the surfaces of the source/drain regions. In an aspect, a silicon-carbon layer formed on the surface of the channel region suppresses boron diffusion toward a first source/drain region and toward at least a second source/drain region. | 2013-08-01 |
| 20130193518 | SEMICONDUCTOR DEVICES HAVING DOUBLE-LAYERED METAL CONTACTS AND METHODS OF FABRICATING THE SAME - Semiconductor devices are provided. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, first and second conductive line extending onto the semiconductor substrate to constitute a peripheral circuit, a first interlayer insulation layer on the first and second conductive lines, a first peripheral interconnection pattern on the first interlayer insulation layer of the peripheral region, a first contact plug disposed in the first interlayer insulation layer, second peripheral interconnection patterns on the second interlayer insulation layer of the peripheral region, a second contact plug disposed in the second interlayer insulation layer to electrically connect the first peripheral interconnection pattern to one of the second peripheral interconnection patterns, and a third contact plug penetrating the first and second interlayer insulation layers to electrically connect the second conductive line to another one of the second peripheral interconnection patterns. | 2013-08-01 |
| 20130193519 | END-TO-END GAP FILL USING DIELECTRIC FILM - A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures. | 2013-08-01 |
| 20130193520 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 2013-08-01 |
| 20130193521 | Modifying Work Function in PMOS Devices by Counter-Doping - A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode. | 2013-08-01 |
| 20130193522 | REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT - The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures. | 2013-08-01 |
| 20130193523 | STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET - An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation , GIDL and junction leakage. | 2013-08-01 |
| 20130193524 | Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 2013-08-01 |
| 20130193525 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices. | 2013-08-01 |
| 20130193526 | FinFET Body Contact and Method of Making Same - A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate. | 2013-08-01 |
| 20130193527 | MICRO-ELECTRO MECHANICAL SYSTEM (MEMS) STRUCTURES WITH THROUGH SUBSTRATE VIAS AND METHODS OF FORMING THE SAME - The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded together by fusion bonding at high processing temperatures, which enables more complete removal of chemical species from the dielectric materials in the substrates prior to sealing cavities of the MEMS structures. Fusion bonding of MEMS structures reduces outgassing of chemical species and is compatible with the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to eutectic bonding due to a higher bonding ratio. In addition, fusion bonding enables the formation of through substrate vias (TSVs) in the MEMS structures. | 2013-08-01 |
| 20130193528 | SYSTEMS AND METHODS FOR CONDUCTIVE PILLARS - Systems and methods for conductive pillars are provided. In one embodiment, a system comprises an electrical board comprising an electrical device, and a packaged die, the packaged die bonded to the electrical board. The packaged die comprises a substrate layer, the substrate layer comprising a recessed area, a conductive trace, wherein a portion of the conductive trace is formed in the recessed area, and an epitaxial device layer bonded to the substrate layer. The device layer comprises a MEMS device, and an epitaxial conductive pillar, wherein a first side of the epitaxial conductive pillar is electrically connected to the conductive trace and the second side of the epitaxial conductive pillar is electrically connected to the electrical board, wherein the epitaxial conductive pillar extends through the epitaxial device layer to electrically couple the conductive trace to an interface surface on the epitaxial device layer. | 2013-08-01 |
| 20130193529 | MICRO-ELECTROMECHANICAL SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - The micro-electromechanical semiconductor component is provided with a first semiconductor substrate, which has an upper face, and a second semiconductor substrate, which has an upper face. Both semiconductor substrates are bonded resting on the upper faces thereof. A cavity is introduced into the upper face of at least one of the two semiconductor substrates. The cavity is defined by lateral walls and opposing top and bottom walls, which are formed by the two semiconductor substrates. The top or the bottom wall acts as a reversibly deformable membrane and an opening extending through the respective semiconductor substrate is arranged in the other of said two walls of the cavity. | 2013-08-01 |
| 20130193530 | Semiconductor Component and Corresponding Production Method - A semiconductor component includes a substrate, a molded package, and a semiconductor chip. The semiconductor chip is suspended on the molding compound above the substrate in the molded package in such a way that a cavity mechanically decouples the semiconductor chip from the substrate. The cavity extends along an underside facing the substrate. | 2013-08-01 |
| 20130193531 | PHYSICAL QUANTITY SENSOR WITH SON STRUCTURE, AND MANUFACTURING METHOD THEREOF - Provided by some aspects of the invention is a relatively low-cost, relatively highly accurate physical quantity sensor, and a manufacturing method thereof, that relaxes thermal stress from an outer peripheral portion of a diaphragm in a silicon-on-nothing (“SON”) structure. By providing a stress relaxation region (trench groove) in an outer peripheral portion of a diaphragm in a SON structure, there can be, in some aspects of the invention, a benefit of relaxing the transmission to the diaphragm of thermal stress generated by the difference in linear expansion coefficient between a package and chip, and it is possible to relax the transmission to an electronic circuit disposed in an outer peripheral portion of mechanical stress generated by a measured pressure. As a result of this, it is possible to provide a highly accurate physical quantity sensor. | 2013-08-01 |
| 20130193532 | CAPACITIVE PRESSURE SENSING SEMICONDUCTOR DEVICE - A capacitive pressure sensing semiconductor device is provided, which has pressure resistance against pressure applied by a pressing member and can detect the pressure surely and efficiently. The pressure sensing semiconductor device includes a pressure detecting part, which detects pressure as a change in capacitance, and a package that receives the pressure detecting part within. The pressure detecting part includes a first electrode and a second electrode disposed to oppose the first electrode, with a determined distance therebetween. Capacitance is formed between the first electrode and the second electrode, and changes according to a change in said distance caused by pressure transmitted to the first electrode by a pressing member. The package also includes a pressure transmitting member that transmits, to the first electrode of the pressure detecting part, the pressure applied by the pressing member. | 2013-08-01 |
| 20130193533 | EMBEDDED CIRCUIT IN A MEMS DEVICE - A Microelectromechanical System (MEMS) microphone includes a printed circuit board, a MEMS die, and an integrated circuit. The MEMS die is disposed on a top surface of the printed circuit board. The integrated circuit is disposed at least partially within the printed circuit board and produces at least one output signal. The output signals of the integrated circuit are routed directly into at least one conductor to access pads at the printed circuit board and the access pads are disposed on a bottom surface of the printed circuit board that is opposite the top surface. | 2013-08-01 |
| 20130193534 | CAPACITIVE PRESSURE SENSOR AND METHOD OF MANUFACTURING THE SAME - A capacitive pressure sensor includes: a semiconductor substrate having a reference pressure chamber formed therein; a diaphragm which is formed in a front surface of the semiconductor substrate and has a ring-like peripheral through hole penetrating between the front surface of the semiconductor substrate and the reference pressure chamber and defining an upper electrode and a plurality of central through holes; a peripheral insulating layer which fills the peripheral through hole and electrically isolates the upper electrode from other portions of the semiconductor substrate; and a central insulating layer which fills the central through holes. | 2013-08-01 |
| 20130193535 | MICRO-ELECTROMECHANICAL DEVICE AND USE THEREOF - The micro-electromechanical device has a substrate. Integrated into the substrate is a micromechanical component that has a bending element which can be bent reversibly and which has a first end connected to the substrate and extends from the first end over a free space. The bending element has at least one web having two side edges, the course of which is defined by depressions introduced into the bending element and adjacent to the side edges. In order to form a homogenization region located within the web, in which mechanical stresses occurring during bending of the bending element are substantially equal, the mutual spacing of the side edges of the web decreases, as viewed from the first end of the bending element. The device further comprises at least one microelectronic component that is sensitive to mechanical stresses and embedded in the web in the homogenization region of the latter. | 2013-08-01 |
| 20130193536 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A MEMS ELEMENT - In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer. | 2013-08-01 |
| 20130193537 | SYSTEM AND METHOD FOR DETECTING PARTICLES WITH A SEMICONDUCTOR DEVICE - Systems and methods are described herein for detecting particles emitted by nuclear material. The systems comprise one or more semiconductor devices for detecting particles emitted from nuclear material. The semiconductor devices can comprise a charge storage element comprising several layers. A non-conductive charge storage layer enveloped on top and bottom by dielectric layers is mounted on a substrate. At least one top semiconductor layer can be placed on top of the top dielectric layer. A reactive material that reacts to particles, such as neutrons emitted from nuclear material, can be incorporated into the top semiconductor layer. When the reactive material reacts to a particle emitted from nuclear material, ions are generated that can alter the charge storage layer and enable detection of the particle. | 2013-08-01 |
| 20130193538 | Methods and Apparatus for an Improved Reflectivity Optical Grid for Image Sensors - An improved reflectivity optical grid for image sensors. In an embodiment, a backside illuminated CIS device includes a semiconductor substrate having a pixel array area comprising a plurality of photosensors formed on a front side surface of the semiconductor substrate, each of the photosensors forming a pixel in the pixel array area; an optical grid material disposed over a backside surface of the semiconductor substrate, the optical grid material patterned to form an optical grid that bounds each of the pixels in the pixel array area and extending above the semiconductor substrate, the optical grid having sidewalls and a top portion; and a highly reflective coating formed over the optical grid, comprising a pure metal coating of a metal that is at least 99% pure, and a high-k dielectric coating over the pure metal coating that has a refractive index of greater than about 2.0. Methods are also disclosed. | 2013-08-01 |
| 20130193539 | Method for Increasing Photodiode Full Well Capacity - A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency. | 2013-08-01 |
| 20130193540 | Apparatus and Method for Reducing Dark Current in Image Sensors - A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer. | 2013-08-01 |
| 20130193541 | UV Radiation Recovery of Image Sensor - A method of an embodiment comprises forming a dielectric layer on a first side of an image sensor substrate, and exposing the dielectric layer to ultraviolet (UV) radiation. The image sensor substrate comprises a photo diode. A structure of an embodiment comprises a substrate and a charge-less dielectric. The substrate comprises a photo diode. The charge-less dielectric layer is on a first side of the substrate, and a total charge of the charge-less dielectric results in an average voltage drop of less than 0.2 V across the charge-less dielectric layer. | 2013-08-01 |
| 20130193542 | IMAGE SENSOR, PRODUCTION APPARATUS, PRODUCTION METHOD, AND IMAGING APPARATUS - An image sensor includes a substrate formed of a material having a light absorption coefficient higher than that of silicon, and a photoelectric conversion element formed on the substrate for photoelectrically converting incident light. | 2013-08-01 |
| 20130193543 | SEMICONDUCTOR OPTOELECTRONICS DEVICES - A semiconductor device comprising a semiconductor substrate with a plurality of photo-diodes arranged in the semiconductor substrate with interconnect layers defining apertures at the photo-diodes and a first polymer which fills the gaps such as to cover the photo-diode. Further, layers of color filters are arranged on top the gap filling polymer layer opposite to the photo-diodes and a second polymer arranged on the interconnect layers covers and planarizes and passivates the color filter layers. On top of the planarizing polymer there is a plurality of micro-lenses opposite to the color filters, and a third polymer layer is deposited on the micro-lenses for passivating the micro-lenses. According to the invention the polymer materials are comprised of a siloxane polymer which gives thermally and mechanically stable, high index of refraction, dense dielectric films exhibiting high-cracking threshold, low pore volume and pore size. | 2013-08-01 |
| 20130193544 | MICROSCOPY METHOD AND SYSTEM INCORPORATING NANOFEATURES - A lensfree imaging and sensing device includes an image sensor comprising an array of pixels and a substantially optically transparent layer disposed above the image sensor. Nano-sized features that support surface plasmon waves are populated on the substantially optically transparent layer separating the image sensor from the nano-sized features. The nano-sized features may include apertures through a substantially optically opaque layer (e.g., metal layer) or they may include antennas. An illumination source is provided that is configured to illuminate a sample. At least one processor is operatively coupled to the image sensor. Changes to the detected transmission pattern at the image sensor are used to sense conditions at or near the surface containing the nano-sized features. Conditions may include binding events or other changes to the index of refraction occurring near the surface of the device. | 2013-08-01 |
| 20130193545 | SEMICONDUCTOR APPARATUS AND IMAGE SENSOR PACKAGE USING THE SAME - A semiconductor apparatus and a method of fabricating the same are provided. The semiconductor apparatus includes a body part having a first surface and a second surface facing each other, a first trench formed into the first surface of the body part, a second trench formed into the second surface of the body part, an opening connecting the first trench and the second trench to each other, a first adhesion enhancer, such as a rough surface, formed on a bottom surface of the first trench, and a second adhesion enhancer, such as a rough surface, formed on the second surface of the body part. | 2013-08-01 |
| 20130193546 | SINGLE PHOTON AVALANCHE DIODE FOR CMOS CIRCUITS - A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region. | 2013-08-01 |
| 20130193547 | SOLID-STATE IMAGING ELEMENT, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE - Disclosed herein is a solid-state imaging element including: a semiconductor layer; a plurality of photoelectric conversion sections arranged within the semiconductor layer; and a pixel separating section disposed in a shape of a same width from a light receiving surface of the semiconductor layer to an opposite surface of the semiconductor layer from the light receiving surface in a position of separating the photoelectric conversion sections from each other for each pixel, the pixel separating section being formed by a material including an impurity. | 2013-08-01 |
| 20130193548 | SEMICONDUCTOR DEVICES HAVING A TRENCH ISOLATION LAYER AND METHODS OF FABRICATING THE SAME - Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided. | 2013-08-01 |
| 20130193549 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUGS AND METHODS OF MANUFACTURING THE SAME - Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided. | 2013-08-01 |
| 20130193550 | 3D INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer. | 2013-08-01 |
| 20130193551 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist. | 2013-08-01 |
| 20130193552 | INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES - A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer. | 2013-08-01 |
| 20130193553 | High performance system-on-chip inductor using post passivation process - A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. | 2013-08-01 |
| 20130193554 | Cell Array with Density Features - A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit. | 2013-08-01 |
| 20130193555 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor within a trench in a workpiece, the capacitor comprising a bottom electrode, a dielectric layer disposed over the bottom electrode, and a top electrode disposed over the dielectric layer. A cap layer is formed over the capacitor. Forming the capacitor and forming the cap layer comprise optimizing at least one of: a width of the trench, a thickness of the bottom electrode, a thickness of the dielectric layer, a thickness of the top electrode, and a thickness of the cap layer, so that the cap layer completely covers the top electrode. | 2013-08-01 |
