31st week of 2014 patent applcation highlights part 67 |
Patent application number | Title | Published |
20140215088 | METHOD AND SYSTEM FOR PACING, ACKING, TIMING, AND HANDICAPPING (PATH) FOR SIMULTANEOUS RECEIPT OF DOCUMENTS - A method for facilitating substantially simultaneous receipt of content included in at least one document by a plurality of intended recipients is disclosed. At least one portion of impactful content is delimited in the at least one document to define at least one impactful block (IBlock). A remaining portion of content is delimited to define at least one non-impactful block (NIBlock). The least one IBlock is transmitted to be received substantially simultaneously by the plurality of intended recipients. | 2014-07-31 |
20140215089 | SYSTEMS AND METHODS FOR DYNAMIC DATA TRANSFER MANAGEMENT ON A PER SUBSCRIBER BASIS IN A COMMUNICATIONS NETWORK - A method of dynamically managing transmission of packets is disclosed. The method, in some embodiments, may comprise establishing a network session over a communication link between a network and a user device of a user and associating a data transmission parameter with the user device. The method may further comprise receiving a packet and calculating a delay period associated with the packet based on the data transmission parameter and delaying transmission of the packet based on the delay period. | 2014-07-31 |
20140215090 | DFA SUB-SCANS - In a DFA, a sub-scan is executed during a DFA scan. The sub-scan consumes input symbols out of sequence relative to the DFA scan, either forward or in reverse. An input symbol in the DFA scan is matched. A sub-scan command is supplied to the DFA. The sub-scan command is executed and at least one symbol is consumed in the sub-scan. | 2014-07-31 |
20140215091 | RECOVERING LOST DEVICE INFORMATION IN CABLE NETWORKS - In one embodiment, methods are described for recovering lost customer premises equipment (CPE) information on a cable modem termination system (CMTS) in the presence of only Dynamic Host Control Protocol Version 6 (DHCPv6) CONFIRM. A CMTS purges routing information for an Internet Protocol Version 6 (IPv6) node, such as a CPE router, in response to detecting an interface reset for the IPv6 node. IPv6 addresses and prefixes information for the IPv6 node is gleaned from a DHCPv6 CONFIRM message received from the IPv6 node. By sending portions of the IPv6 addresses and prefixes information within a DHCPv6 LEASEQUERY message, a DHCPv6 CONFIRM message with an embedded DHCPv6 LEASEQUERY message, or a DHCPv6 CONFIRM message with an Interface-ID option, a reply message can be received that contains the purged routing information for the IPv6 node. | 2014-07-31 |
20140215092 | Selective Proxying In Domain Name Systems - Systems and methods for processing requests for domain name information in accordance with subscriber information are provided. A request for domain name information can be correlated with subscriber preferences to resolve the domain name information. Domain names may be flagged for blocking or proxying by one or more subscriber preferences. In response to a flagged domain name, a client device can be redirected to a web server that can function as proxy on behalf of the user for accessing the flagged domain. In one example, user preferences and/or network preferences can be used to determine whether a particular user can bypass a blocking preference and access the flagged domain using the proxy. | 2014-07-31 |
20140215093 | System and Method of Formatting Data - A system and method of formatting data. The system accounts for the user's current device and current activity in order to determine the appropriate format for presenting data. | 2014-07-31 |
20140215094 | METHOD AND SYSTEM FOR DATA COMPRESSION - Interrelated methods for compression and decompression within a common context provides mapping of each index of a sequence of indexes to an index value. The method comprises decomposing a data set into a sequence of chunks, wherein each chunk is associated with a bit pattern and an index unique within the sequence. For a certain bit pattern a value sum is created of all index values mapped to each index of every chunk associated with the bit pattern. The decompression method comprises retrieving a value sum associated with a certain bit pattern; selecting a set of indexes, such that the sum of all index values mapped to indexes comprised in the selected set of indexes equals the retrieved index value sum; and recomposing a sequence of chunks such that each chunk is further associated with the unique bit pattern. | 2014-07-31 |
20140215095 | COMMUNICATION SYSTEM AND ITS METHOD AND COMMUNICATION APPARATUS AND ITS METHOD - This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means. | 2014-07-31 |
20140215096 | METHOD AND SYSTEM FOR A CONFIGURABLE HARDWARE MODULE - Provided is a programmable logic system for controlling an external device including a first processor and one or more system input/output (I/O) modules coupled to the processor via an interface. The programmable logic system also includes a configurable hardware module coupled to the processor and the I/O modules via the interface. | 2014-07-31 |
20140215097 | PRINT CONTROL DEVICE, CONTROL METHOD OF A PRINT CONTROL DEVICE, AND RECORDING MEDIUM STORING A PROGRAM - A print control device, a control method of a print control device, and a recording medium storing a program enable easily configuring a peripheral device connected to a printer. A POS terminal that configures peripheral devices connected to a receipt printer has a device configuration selection unit for selecting a configuration of peripheral devices; and a device configuration screen display unit that displays a configuration screen for the peripheral devices based on the selected device configuration. Because a configuration screen for a peripheral device that is not connected to the receipt printer (a configuration screen that is not needed) is not displayed, the risk of creating confusion regarding the configuration of a peripheral device for the user can be reduced. | 2014-07-31 |
20140215098 | DOCKING DISPLAY ADAPTER WITH AUTOMATIC MODE SWITCHING - A display adapter for docking one or more clients to a display and providing automatic mode switching of the display. The display adapter including a client interface circuit configured to receive client data from the one or more clients; a processing circuit configured to determine a display mode based on the client data; and a display interface circuit configured to transmit the display mode to the display. | 2014-07-31 |
20140215099 | Systems and Methods for Providing a Wireless Computer Control Link - Systems and methods are provided for wirelessly controlling a client computer system from a host computer system. A HID class command is received from a host computer system that is generated by an application executing on the host computer system in order to control a client computer system using a first wireless transceiver device that connects to a USB port of the host computer system. The HID class command is transmitted across a wireless channel using the first wireless transceiver device. The HID class command is received from the wireless channel using a second wireless transceiver device that is connected to a USB port of the client computer system and is configured by the client computer system as a HID. The HID class command is sent to the client computer system in order to control the client computer system using the second wireless transceiver device. | 2014-07-31 |
20140215100 | SYSTEM FOR MANAGING DOMESTIC PERIPHERALS - The present invention relates to a system for managing a plurality of peripherals ( | 2014-07-31 |
20140215101 | DISPLAY DEVICE - A displaying device includes a first storing portion that stores first connection data indicating connection statuses of a plurality of instruments and a controlling system, a second storing portion that stores second connection data indicating connection statuses of a plurality of instruments and an instrument controlling device, a displaying portion that displays the first connection statuses through the first connection data and the second connection statuses through the second connection data, and a display controlling portion that causes the first connection statuses and the second connection statuses to be displayed separately on the displaying portion. | 2014-07-31 |
20140215102 | STATE-BASED AUXILIARY DISPLAY OPERATION - Described is a technology by which the operation of an auxiliary computing device, comprising a display and/or actuator set, may be automatically modified based on detected state data. For example, user input may be routed from the actuator set to the host computer system when the host computer system is in an online state, or to the auxiliary computing device when the host computer system is offline. State may be determined based on one or more various criteria, such as online or offline, laptop lid position, display orientation, current communication and/or other criteria. The auxiliary display and/or actuator set may be embedded in the host computer system, or each may be separable from it or standalone, such as a remote control or cellular phone. | 2014-07-31 |
20140215103 | DECOUPLED LOCKING DMA ARCHITECTURE - A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device. | 2014-07-31 |
20140215104 | Crosstalk Mitigation in On-Chip Interfaces - A system and method to reduce and/or eliminate crosstalk between various data paths of a data bus within integrated circuits (i.e., chips). The system and method can transmit both delayed and non-delayed data in respective transmission paths, store the delayed and non-delayed data upon receipt, and delay the reading of the delayed and non-delayed data from the storage unit to compensate for the delay implemented on the transmission of the delayed data. | 2014-07-31 |
20140215105 | MOUSE WITH A REPLACEABLE SENSING UNIT - A mouse with a replaceable sensing unit comprises a main body, a processor unit and a sensing unit. The main body has a containing slot and a first electrical interface. The first electrical interface is disposed in the containing slot. The processor unit is disposed in the main body, and coupled to the first electrical interface. The sensing unit is replaceably disposed in the containing slot of the main body, and the sensing unit is coupled to the first electrical interface when the sensing unit is disposed in the containing slot. The processor unit gets via the first electrical interface an input signal generated when the sensing unit senses the movement of the main body, and then relatively outputs a cursor control signal to a computer apparatus. | 2014-07-31 |
20140215106 | SVID DATA TEST SYSTEM AND METHOD - An SVID data test system is applied on a test device and a display device, and the test device is electrically connected to a tested device via an SVID interface, and the display device via a serial interface. The system receives SVID signals, analyzes the SVID signals to obtain nine bit real signals, and performs parallel encoding on the nine bit real signals to obtain nine bit parallel signals. The system further converts the nine bit parallel signals to nine bit serial signals, transmits the serial signals in sequence to the display device, and parses the nine bit serial signals to obtain a packet in hexadecimal and controls the display device to display the packet in response to the display command. | 2014-07-31 |
20140215107 | Expander Bypass - An expander including an IN port, an OUT port and expander logic circuitry. A bypass path is provided to bypass the expander logic circuitry when power to the expander is off. | 2014-07-31 |
20140215108 | REDUCING WRITE I/O LATENCY USING ASYNCHRONOUS FIBRE CHANNEL EXCHANGE - A FCP initiator sends a FCP write command to a FCP target within a second FC Exchange, and the target sends one or more FC write control IUs to the initiator within a first FC Exchange to request a transfer of data associated with the write command. The first and second FC exchanges are distinct from one another. A payload of each write control IU includes an OX_ID value with which the initiator originated the second Exchange and a RX_ID value assigned by the FCP target for the second exchange. The two Exchanges yield a full-duplex communication environment between the initiator and target that enables the reduction or elimination of latencies incurred in a conventional FCP write I/O operation due to the half-duplex nature of a single FC Exchange. The write control IU may be an enhanced FCP_XFER_RDY IU or a new FC IU previously undefined by the FCP standard. | 2014-07-31 |
20140215109 | Compatible Network Node, in Particular, For Can Bus Systems - A network node is provided, including a device, in particular, an error detection logic, which is deactivated if it is detected that a signal according to a first protocol or a first version of a first protocol is received, and which is not deactivated if it is detected that a signal according to a second, different protocol or a second, different version of the first protocol is received. | 2014-07-31 |
20140215110 | DRIVING INTEGRATED CIRCUIT AND UPATE METHOD THEREOF - A driving IC is being controlled by a host IC to update a driving program stored in a storage with a SPI interface. The driving IC includes a IIC interface, an identifying module, and a calculating module. The IIC interface receives an instruction from the host IC in the IIC protocol format. The identifying module determines whether the received instruction is an update instruction, and generates a converting instruction when the received instruction is the update instruction. The calculating module converts the received instruction into a SPI format according to a predetermined converting rule. The SPI interface transmits the converted instruction in the SPI format to the storage. | 2014-07-31 |
20140215111 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 2014-07-31 |
20140215112 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a predefined sequence on each of the lanes. | 2014-07-31 |
20140215113 | HDMI-CEC DEVICE AND ADDRESS ALLOCATION METHOD OF HDMI-CEC DEVICE NETWORK - A method allocates physical addresses HDMI-CEC devices within an HDMI-CEC device network. The HDMI-CEC device network includes a plurality of HDMI-CEC devices consisting of at least two root devices, a plurality of parent devices, and a plurality of slave devices. Each of the root devices has a root ID. When a slave device is plug into an HDMI interface of a parent device, the parent device allocates a root ID and a physical address for the slave device. The slave device creates a route table according to the allocated root ID and physical address, to establish a serial communication with the parent device. | 2014-07-31 |
20140215114 | Base for a Tablet Computer - An example of a base apparatus for use by a tablet computer is disclosed. The base apparatus can include a first peripheral device capable of operating according to a first wireless communication protocol; a first demultiplexer coupled to the first peripheral device; and a first wireless communication module coupled to the first demultiplexer. The first demultiplexer is to transmit signals received from the first peripheral device to the tablet computer in a wired way or transmit signals received from the first peripheral device to the first wireless communication module based on whether the tablet computer is connected to or detached from the base apparatus. The first wireless communication module is to transmit wirelessly signals received from the first demultiplexer to the tablet computer. | 2014-07-31 |
20140215115 | Device for Distributing Data About a Vehicle - A device for distributing data about a vehicle, has a first sensor data reception interface for receiving first sensor data from a first sensor, a second sensor data reception interface for receiving second sensor data from a second sensor, and a transmission interface for transmitting the data about the vehicle on the basis of the first sensor data and the second sensor data to a receiver. A vehicle and an on-board system which incorporate the devise are also encompassed herein. | 2014-07-31 |
20140215116 | MULTI-BUS SYSTEM - A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path. | 2014-07-31 |
20140215117 | ELECTRONIC DEVICE AND METHOD FOR CONTROLLING STATUS OF PCI INTERFACES - An electronic device includes a main board. The main board includes a number of PCI interfaces, an addressing unit, a determination unit, and a control unit. The addressing unit is configured for addressing addresses of each of the PCI interfaces of the main board from an address bus of the electronic device. The determination unit is configured for determining whether any PCI interfaces are not connected to corresponding PCI devices according to a value at the addressed addresses. The control unit is configured to turn off the PCI interfaces that are not connected to corresponding PCI devices. A method for controlling status of the PCI interfaces is also provided. | 2014-07-31 |
20140215118 | SWITCHING CIRCUIT, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - According to one embodiment, a switching circuit includes a device, a load switch, a device bus to which the device is connected, a device bus terminating resistor, a bus switch, and a host bus terminating resistor. The load switch feeds power to the device when a control signal is active. The device bus terminating resistor terminates the device bus. The bus switch connects a host bus and the device bus when the control signal is active or when the load switch is in a feed state. The host bus terminating resistor terminates the host bus when the host bus and the device bus are disconnected. | 2014-07-31 |
20140215119 | STORAGE CONTROL DEVICE, ELECTRONIC APPARATUS, STORAGE MEDIUM, AND STORAGE CONTROL METHOD - A storage control device includes a first storage unit, a write control unit, and a read control unit. The first storage unit includes a plurality of storage areas corresponding to a plurality of addresses. The write control unit performs a write process to sequentially designate one of the plurality of addresses and write data to the storage area corresponding to the designated address, in a predetermined first order. The read control unit performs a read process to sequentially designate one of the plurality of addresses and read data stored in the storage area corresponding to the designated address, in a second order opposite to the first order, starting with the address corresponding to the storage area in which data has been stored immediately near a predetermined start timing after the beginning of execution of the write process, the read process being started at the predetermined start timing. | 2014-07-31 |
20140215120 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR GENERATING CHRONOLOGICALLY ORDERED GLOBALLY UNIQUE IDENTIFIERS - A computer-based system, method and computer program product for generating chronologically based globally unique identifiers. | 2014-07-31 |
20140215121 | MEMORY CONTROLLER USING CRISSCROSS ERROR-CORRECTING CODES - A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array. | 2014-07-31 |
20140215122 | NON-VOLATILE MEMORY PROGRAMMING DATA PRESERVATION - A system and methods for programming a set of data onto non-volatile memory elements, maintaining copies of the data pages to be programmed, as well as surrounding data pages, internally or externally to the memory circuit, verifying programming correctness after programming, and upon discovering programming error, recovering the safe copies of the corrupted data to be reprogrammed in alternative non-volatile memory elements. Additionally, a system and methods for programming one or more sets of data across multiple die of a non-volatile memory system, combining data pages across the multiple die by means such as the XOR operation prior to programming the one or more sets of data, employing various methods to determine the correctness of programming, and upon identifying data corruption, recovering safe copies of data pages by means such as XOR operation to reprogram the pages in an alternate location on the non-volatile memory system. | 2014-07-31 |
20140215123 | Controller-Opaque Communication with Non-Volatile Memory Devices - The disclosure is directed to a system and method for controlling a non-volatile memory (NVM) device with controller-opaque commands issued by a host. A device controller is configured to receive a command script from a host. The device controller executes one or more commands of the command script including sending one or more operations of the command script to a NVM device in communication with the device controller. The device controller is enabled to provide at least a portion of the one or more operations from the command script to be executed by the NVM device without any embedded knowledge by the device controller of the actions of and/or consequences of the operations, thereby allowing the host to access NVM commands that are not necessarily supported by the device controller. | 2014-07-31 |
20140215124 | SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE - The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source. | 2014-07-31 |
20140215125 | LOGICAL BLOCK ADDRESS REMAPPING - A method and system is disclosed that remaps logical block addresses (LBAs) for defragmentation that is managed at the storage device level. The remapping may include sequentially remapping LBAs where individual files are remapped so that each file is referenced by sequential LBAs. The remapping of LBAs may be performed without changes to the physical location of data. | 2014-07-31 |
20140215126 | Data Randomization in 3-D Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings. | 2014-07-31 |
20140215127 | APPARATUS, SYSTEM, AND METHOD FOR ADAPTIVE INTENT LOGGING - A system and method is provided for implementing adaptive intent logging in a file system of a computing device. The file system receives an I/O request from one more applications executing on the computing device. The file system includes one or more intent logging modules that adaptively and/or selectively write detail data included in an I/O request directly to storage pool device or an intent log that based on logging rules and/or the detail data associated with the request. The intent logging modules minimizes processing delays when an application issues multiple synchronous requests, such as small write request. | 2014-07-31 |
20140215128 | ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY - When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines. | 2014-07-31 |
20140215129 | COOPERATIVE FLASH MEMORY CONTROL - This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage. | 2014-07-31 |
20140215130 | CLOCK SWITCHING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state. | 2014-07-31 |
20140215131 | CONTROLLING METHOD, MEMORY CONTROLLER, AND DATA TRANSMISSION SYSTEM - A controlling method of a rewritable non-volatile memory module, and a memory controller and a data transmission system using the same are provided. The controlling method includes following steps. A command is received from a host system. Whether the command is a configuration command is determined according to a command code of the command. A plurality of action information in the configuration command and an execution sequence corresponding to the action information are analyzed. The action information is executed according to the execution sequence. Each action information is configured to request the rewritable non-volatile memory module to execute a predetermined action. Thereby, the functionality of a memory storage device can be dynamically extended. | 2014-07-31 |
20140215132 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A data writing method, a memory controller, and a memory storage device are provided. The method is applied to control a rewritable non-volatile memory module that includes two memory units. The method includes: configuring a plurality of logical addresses and mapping the logical addresses to at least parts of physical erasing units in the two memory units; receiving a writing command from a host system to instruct to write data into one of the logical addresses; writing the data into a physical erasing unit in the two memory units; determining one of the memory units where the physical erasing unit belongs to; if the physical erasing unit belongs to one of the memory units, erasing another physical erasing unit in the other memory unit while writing the data into the physical erasing unit. Accordingly, a speed of writing data into the memory storage device by the host system is accelerated. | 2014-07-31 |
20140215133 | MEMORY SYSTEM AND RELATED BLOCK MANAGEMENT METHOD - A memory system manages memory blocks of a nonvolatile memory device by determining at least one memory block property of a selected memory block among the multiple memory blocks in the nonvolatile memory device, storing memory block property information indicating the at least one memory block property, arranging a free memory block list based on the stored memory block property information, and designating a free memory block from the arranged free memory block list as an active memory block, wherein the designation of the free memory block as an active memory block is based on an ordering of the free memory block list. | 2014-07-31 |
20140215134 | MAINBOARD AND METHOD OF BACKING UP OF BASEBOARD MANAGEMENT CONTROLLER - A mainboard includes a selecting module, a calculating module, and a backup module. The selecting module selects a highest backup sequence group. The calculating module checks whether current backup time arrives, and calculates memory space of partitions belonging to the highest backup sequence group when the current backup time arrives. The backup module checks whether residual space in a first flash is enough according to the calculated memory space, and backs up the partitions belonging to the highest backup sequence group originally in a second flash to the first flash if the residual space in the first flash is enough. A method of the mainboard backing up of a baseboard management controller is also provided, which provides backing up for the baseboard management controller. | 2014-07-31 |
20140215135 | MEMORY DEVICE, MEMORY SYSTEM, AND CONTROL METHOD PERFORMED BY THE MEMORY SYSTEM - Provided are a memory device, a memory system, and a control method performed by the memory system. The control method includes operations of generating, by a first function block of the memory system, a main request comprising a first sub-request for a first operation that is requested by an external source and a second sub-request for a second operation that is dependent upon a processing result of the first operation; processing, by a second function block of the memory system, the first sub-request or the second sub-request; and when a processing result of the first sub-request performed by the second function block is a fail, transmitting, by a third function block of the memory system, abortion information to the first function block in response to the main request, regardless of processing the second sub-request. | 2014-07-31 |
20140215136 | METHODS AND APPARATUS FOR STORING DATA TO A SOLID STATE STORAGE DEVICE BASED ON DATA CLASSIFICATION - Systems and methods for storing data to a non-volatile storage device are provided. A request to store data to the storage device at a given address corresponding to one of a plurality of regions of the storage device is received. A region classification map associated with the storage device associates a classification with each of the plurality of regions. A determination is made based on the region classification map as to which classification is associated with the one of the plurality of regions corresponding to the given address. The data is stored at the given address in response to determining that the one of the plurality of regions is associated with a first classification. The data is stored to an alternate location in response to determining that the one of the plurality of regions is associated with a second classification. | 2014-07-31 |
20140215137 | METHODS FOR IMPLEMENTATION OF AN ARCHIVING SYSTEM WHICH USES REMOVABLE DISK STORAGE SYSTEM - According to the disclosure, embodiments of archival storage system are disclosed. The archival storage system includes two or more removable disk drives that provide random access and are readily expandable. One or more application servers can store archival data to the one or more removable disk drives. Further, the archival storage system provides intelligent archiving by adapting storage requirements to the type of data being archived by the application servers. Methods for storing archival data are also provided that store archival information in removable disk drives. | 2014-07-31 |
20140215138 | MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES - The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface. | 2014-07-31 |
20140215139 | MEMORY DEVICES HAVING SPECIAL MODE ACCESS - Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode. | 2014-07-31 |
20140215140 | Data Mask Encoding in Data Bit Inversion Scheme - Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte. | 2014-07-31 |
20140215141 | High-Speed Processor Core Comprising Mapped Auxilliary Component Functionality - A high-speed processor core having a plurality of individual FPGA-based processing elements configured in a synchronous or asynchronous pipeline architecture with direct processor-to-memory interconnectivity and having an auxiliary component functionality mapped into at least one of the processing elements. | 2014-07-31 |
20140215142 | DRAM REFRESH METHOD AND SYSTEM - A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times. | 2014-07-31 |
20140215143 | CROSSBAR MEMORY TO PROVIDE CONTENT ADDRESSABLE FUNCTIONALITY - Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar. | 2014-07-31 |
20140215144 | ARCHITECTURE FOR TCAM SHARING - Aspects of the disclosure provide a packet processing system. The packet processing system includes a plurality of processing units, a ternary content addressable memory (TCAM) engine, and an interface. The plurality of processing units is configured to process packets received from a computer network, and to perform an action on a received packet. The action is determined responsively to a lookup in a table of rules to determine a rule to be applied to the received packet. The TCAM engine has a plurality of TCAM banks defining respective subsets of a TCAM memory space to store the rules. The interface is configured to selectably associate the TCAM banks to the processing units. The association is configurable to allocate the subsets of the TCAM memory space to groups of the processing units to share the TCAM memory space by the processing units. | 2014-07-31 |
20140215145 | TAPE DRIVE CACHE MEMORY - A system including a tape drive having cache memory to detect a smaller partition and a larger partition in a tape and load stored information in the smaller partition into the cache memory to access the cache memory instead of the smaller partition on the tape. | 2014-07-31 |
20140215146 | APPARATUS, METHOD AND PROGRAM PRODUCT FOR DETERMINING THE DATA RECALL ORDER - To provide a technique for optimizing the processing order of recall requests in which the average latency time of a host apparatus is minimized. A storage manager accepts a request of the host apparatus for the recalling data from a tape library, and stores the request in a queue table. In response to storage of the request, the storage manager calculates the latency time for each request in all the conceivable execution orders for all the requests stored in the queue table. The storage manager determines the execution order which minimizes the total calculated latency time for all the requests including the active request, and rearranges the requests in the queue table. | 2014-07-31 |
20140215147 | RAID STORAGE REBUILD PROCESSING - A storage management module configured to identify storage volumes to be rebuilt and remaining storage volumes that are not to be rebuilt, calculate rebuild priority information for the identified storage volumes to be rebuilt based on storage information of the identified storage volumes, and generate rebuild requests to rebuild the identified storage volumes to be rebuilt and process host requests directed to the remaining and to be rebuilt storage volumes based on the rebuild priority information and amount of host requests, wherein with relative high amount of host requests, generate relative less rebuild requests but not less than a minimum rebuild traffic percentage or more than a maximum rebuild traffic percentage. | 2014-07-31 |
20140215148 | LIMITING THE EXECUTION OF BACKGROUND MANAGEMENT OPERATIONS IN A DRIVE ARRAY - Limiting the execution of background management operations in a drive array, including: receiving a read instruction to read data from a memory drive in the drive array; determining whether the read instruction is associated with a write instruction to write data to a memory drive in the drive array; responsive to determining that the read instruction is associated with the write instruction, restricting performance of background management operations on the memory drive targeted by the write instruction; determining whether the write instruction has completed; and responsive to determining that the write instruction has completed, removing restrictions associated with the performance of background management operations on the memory drive targeted by the write instruction. | 2014-07-31 |
20140215149 | FILE-SYSTEM AWARE SNAPSHOTS OF STORED DATA - Methods and structure are provided for utilizing file-system aware backups for a Redundant Array of Independent Disks (RAID) storage system. The backup system comprises a backup storage device that includes one or more Copy-On-Write snapshots of a RAID logical volume that implements a file system. The backup system also comprises a backup controller operable to determine that a write operation is pending for an extent of the logical volume, to access allocation data for the file system to determine whether the extent was allocated to a file of the file system when a snapshot was created, and to copy the extent to the snapshot responsive to determining that the extent was allocated when the snapshot was created. | 2014-07-31 |
20140215150 | Limiting The Execution Of Background Management Operations In A Drive Array - Limiting the execution of background management operations in a drive array, including: receiving a read instruction to read data from a memory drive in the drive array; determining whether the read instruction is associated with a write instruction to write data to a memory drive in the drive array; responsive to determining that the read instruction is associated with the write instruction, restricting performance of background management operations on the memory drive targeted by the write instruction; determining whether the write instruction has completed; and responsive to determining that the write instruction has completed, removing restrictions associated with the performance of background management operations on the memory drive targeted by the write instruction. | 2014-07-31 |
20140215151 | STORAGE SYSTEM - In order to enhance the accuracy of problem analysis in a disk subsystem, the present invention suspends system trace and writing of system trace information to a storage area at the timing of occurrence of a problem. The suspension of system trace and the writing of system trace information to the storage area is executed not only in the disk subsystem where the problem failure has occurred, but also in all the other connected disk subsystems. Then, a maintenance terminal is used to collect dump information including the system trace information. | 2014-07-31 |
20140215152 | EXPANDABLE MULTIMEDIA STORAGE SYSTEM, MULTIMEDIA DISTRIBUTION DEVICE, AND RELEVANT COMPUTER PROGRAM PRODUCT - A multimedia storage system includes a multimedia distribution device and a plurality of storage devices. The multimedia distribution device splits a multimedia file into a plurality of multimedia segments and monitors the operation statuses of the storage devices. The multimedia distribution device further configures each of the multimedia segments to be stored in at least two of the storage devices according to the available storage devices in the multimedia storage system. The storage device comprises a network access device for receiving the multimedia segments and a redundant array of inexpensive disks for storing the received multimedia segments. | 2014-07-31 |
20140215153 | STORAGE SYSTEM, DISK ARRAY APPARATUS AND CONTROL METHOD FOR STORAGE SYSTEM - Provided is a storage system which is configured such that, when high-load processing is carried out by each of at least one of the storage nodes, an access is made in a method in which the access is made asynchronously with other nodes, and a completion of the access is not waited for, and in each of the at least one storage node other than the at least one storage node carrying out the high-load processing, an access is made in a method in which the access is made synchronously with any other one of the at least one storage node other than the storage node carrying out the high-load processing, and a completion of the access is waited for. | 2014-07-31 |
20140215154 | SYSTEM AND METHOD FOR FILE PROCESSING FROM A BLOCK DEVICE - An example system and method includes an electronic memory configured to store electronic data. The system further includes a controller coupled to an electronic storage device including electronic data storage locations arranged in a consecutive sequence on a storage medium and configured to store electronic data corresponding to electronic files in the electronic storage locations and access the electronic storage locations serially according to the consecutive sequence. The controller may be configured to cause the electronic storage device to serially access and transmit to the electronic memory, according to the consecutive sequence, at least some electronic data, cause the electronic memory to store the electronic data as received so that the electronic data of the file forms a complete file, and cause a processor to access the files from the electronic memory upon all electronic data associated with ones of the files having been stored in the electronic memory. | 2014-07-31 |
20140215155 | FRACTAL LAYOUT OF DATA BLOCKS ACROSS MULTIPLE DEVICES - A system, method, and computer-readable storage medium for mapping block numbers within a region to physical locations within a storage system. Block numbers are mapped within a region according to a fractal-based space-filling curve. If the region is not a 2 | 2014-07-31 |
20140215156 | PRIORITIZED DUAL CACHING METHOD AND APPARATUS - Provided are a prioritized dual caching method and apparatus. The dual caching apparatus includes a content cache unit configured to store a content cache separated into a first (premium) cache and a second (general) cache, a pointer storage unit configured to store a pointer for variably separating the first and second caches, a threshold value storage unit configured to store a first threshold value and a second threshold value that is less than the first threshold value, and a cache policy execution unit configured to receive a request for content, manage a request count value for the content, and execute a cache policy based on results of comparing the request count value to the first threshold value and the second threshold value and whether there is requested content in the content cache. | 2014-07-31 |
20140215157 | MONITORING MULTIPLE MEMORY LOCATIONS FOR TARGETED STORES IN A SHARED-MEMORY MULTIPROCESSOR - A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. More specifically, the disclosed embodiments provide a system that notifies a waiting thread when a targeted store is directed to monitored memory locations. During operation, the system receives a targeted store which is directed to a specific cache in a shared-memory multiprocessor system. In response, the system examines a destination address for the targeted store to determine whether the targeted store is directed to a monitored memory location which is being monitored for a thread associated with the specific cache. If so, the system informs the thread about the targeted store. | 2014-07-31 |
20140215158 | Executing Requests from Processing Elements with Stacked Memory Devices - Executing requests from processing elements with stacked memory devices includes receiving a request from a processing element, determining which of multiple memory devices contains information pertaining to the request, forwarding the request to a selected memory device of the memory devices, and responding to the processing element with the information in response to receiving the information from the selected memory device. | 2014-07-31 |
20140215159 | MANAGING CONCURRENT ACCESSES TO A CACHE - Various embodiments of the present invention allow concurrent accesses to a cache. A request to update an object stored in a cache is received. A first data structure comprising a new value for the object is created in response to receiving the request. A cache pointer is atomically modified to point to the first data structure. A second data structure comprising an old value for the cached object is maintained until a process, which holds a pointer to the old value of the cached object, at least one of one of ends and indicates that the old value is no longer needed. | 2014-07-31 |
20140215160 | METHOD OF USING A BUFFER WITHIN AN INDEXING ACCELERATOR DURING PERIODS OF INACTIVITY - A method of using a buffer within an indexing accelerator during periods of inactivity, comprising flushing indexing specific data located in the buffer, disabling a controller within the indexing accelerator, handing control of the buffer over to a higher level cache, and selecting one of a number of operation modes of the buffer. An indexing accelerator, comprising a controller and a buffer communicatively coupled to the controller, in which, during periods of inactivity, the controller is disabled and a buffer operating mode among a number of operating modes is chosen under which the buffer will be used. | 2014-07-31 |
20140215161 | BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways. | 2014-07-31 |
20140215162 | RETRIEVAL OF PREVIOUSLY ACCESSED DATA IN A MULTI-CORE PROCESSOR - A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory. | 2014-07-31 |
20140215163 | PROCESSING READ AND WRITE REQUESTS IN A STORAGE CONTROLLER - Provided are a method, system, and computer program product for processing read and write requests in a storage controller. A host adaptor in the storage controller receives a write request from a host system for a storage address in a storage device. The host adaptor sends write information indicating the storage address updated by the write request to a device adaptor in the storage controller. The host adaptor writes the write data to a cache in the storage controller. The device adaptor indicates the storage address indicated in the write information to a modified storage address list stored in the device adaptor, wherein the modified storage address list indicates modified data in the cache for storage addresses in the storage device. | 2014-07-31 |
20140215164 | Multiport Memory Architecture - The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory. | 2014-07-31 |
20140215165 | MEMORY MANAGEMENT IN A STREAMING APPLICATION - One embodiment is directed to a method for processing a stream of tuples. The method may include receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors. Each of the processing elements has an associated memory space. In addition, the method may include monitoring the plurality of processing elements. The monitoring may include identifying a first performance metric for a first processing element. The method may include modifying the first processing element based on the first performance metric. The modifying of the first processing element may include employing memory management of the associated memory space. | 2014-07-31 |
20140215166 | APPARATUS FOR STORING/READING DATA IN A MEMORY ARRAY OF A TRANSPONDER - An apparatus for storing or reading data in a memory array of a transponder and a corresponding transponder, read/write device and program element is described. Therein, a data file system for storing data within the memory array is defined by a predetermined protocol. The storing additional data includes checking whether a memory size of the application data file is larger than the memory size indicated by the application data length indicator; and storing second application data in a partial memory area of the application data file not occupied by the first application data. Thereby, memory areas which, according to the predetermined protocol, are not used can be used for new applications, data can be hidden in these areas such that they can not be read by protocol compliant reader devices and the data structure read or written is compatible with the former predetermined protocol. | 2014-07-31 |
20140215167 | FIELD APPARATUS - A field apparatus includes a first memory that stores a program specifying an operation of the field apparatus; a second memory that stores parameters to be used in the field apparatus; a log generation unit configured to generate an operating log in which first information representing a type of an event generated within the field apparatus, second information representing a time at which the event was generated, and third information related to the event are associated; and a control unit that includes the log generation unit, the control unit storing the operating log in a log storage region secured in a free space in one of the first memory and the second memory. | 2014-07-31 |
20140215168 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first semiconductor chip which includes a first data input-output circuit connected to a plurality of output lines including first and second output lines and configured to output a status signal onto the first output line, and a second semiconductor chip which includes a second data input-output circuit connected to the plurality of output lines including the first and second output lines and configured to output a status signal onto the second output line. | 2014-07-31 |
20140215169 | APPARATUS AND METHOD FOR MANAGING DATA ACCESS COUNT - An apparatus counts, for each piece of data, an access count indicating a number of times of access to the each piece of data for every unit time so as to store a management information element including the access count and identification information identifying the each piece of data. The apparatus deletes, from the plurality of management information elements stored in a memory, a management information element that includes the access count having a value minimum among the plurality of management information elements, when a number of the plurality of management information elements reaches a predetermined number. The apparatus determines whether there is a piece of data that satisfies a condition related to rapid increase of access, based on the access counts included in the plurality of management information elements. | 2014-07-31 |
20140215170 | Block Compression in a Key/Value Store - System and method embodiments are provided for improving the performance of data compression for storage systems. The embodiments enable selectively compressing data for storage on a block by block basis to save resources and computation time and cost. The system and method also handle the compression of different types of data blocks using different targeted algorithms. In an embodiment, a method for compressing data in a storage system includes receiving one or more data blocks for storage, determining whether to compress one or more data blocks according to attributes of the one or more data blocks, upon determining to compress a data block from the one or more data blocks, compressing the data block, and storing the compressed data block. The attributes include at least one of a name of the data block, a file type of the data block, and information in the data block. | 2014-07-31 |
20140215171 | VIRTUAL STORAGE SYSTEM AND METHODS OF COPYING ELECTRONIC DOCUMENTS INTO THE VIRTUAL STORAGE SYSTEM - A virtual storage system in data communication with a user computing device via a communication network and methods of selectively or automatically copying electronic documents to a virtual storage system where the virtual storage system includes at least one processor configured to process, encrypt and copy electronic documents retrieved from an external system, and a plurality of redundant physical storage devices in data communication with the at least one processor and each configured to store the electronic documents retrieved from the external system. | 2014-07-31 |
20140215172 | PROVIDING VIRTUAL MACHINE MIGRATION RELIABILITY USING AN INTERMEDIARY STORAGE DEVICE - Systems and methods for live migration of a virtual machine are provided. A migration manager can send a request to a source host machine to migrate a virtual machine to a first destination host machine. The migration manager can determine that the migration of the virtual machine from the source host machine to the first destination host machine has failed. The migration manager can identify an intermediary storage device used during the migration to store a state of the virtual machine. The migration manager identifies a second destination host machine for the virtual machine migration. The migration manager causes the second destination host machine to obtain the state of the virtual machine from the intermediary storage device to migrate the virtual machine to the second destination host machine. | 2014-07-31 |
20140215173 | LOW-COST BACKUP AND EDGE CACHING USING UNUSED DISK BLOCKS - A designated storage system receives a request to store data in the local storage as a backup copy. The designated storage system requests a file system in the computer system to store the backup copy as a file in the local storage and maintains a record describing storage locations for each of the one or more sets of contiguous available file system data blocks. The storage system may transmit the record to a management computer configured to track which of the computer systems has stored the backup copy. The storage system then requests the file system to delete the file, whereupon the file system removes the file descriptor and frees the one or more file system data blocks in order to satisfy the deletion request but does not delete the data stored in the one or more file system data blocks. | 2014-07-31 |
20140215174 | Accessing Memory with Security Functionality - A memory device includes a first memory portion and a second memory portion. The second memory portion includes a security functionality. The size of the first memory portion and the size of the second memory portion are adjustable. | 2014-07-31 |
20140215175 | EFFICIENT SUSPEND-RESUME OPERATION IN MEMORY DEVICES - A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first memory access operation, is obtained from the memory. Based on the progress indication, a decision is made whether to suspend the execution of the first memory access operation in order to execute a second memory access operation. | 2014-07-31 |
20140215176 | MEMORY ALLOCATION CONTROL METHOD, RECORDING MEDIUM, AND INFORMATION PROCESSING DEVICE - A method executed by a processor in a computer including the processor and memory includes: trying to allocate a block of the memory by the processor at a request for memory allocation, in a first case in which a result of a judgment on a probability of success or failure of the memory allocation based on a time taken for the processor to perform each of one or more specific procedures indicates that there is a high probability that the memory allocation succeeds; and either trying to allocate the block of the memory by the processor with a delay with respect to the first case, or returning by the processor, without trying to allocate the block of the memory, a reply that the memory allocation has failed, in a second case in which the result of the judgment indicates that there is a high probability that the memory allocation fails. | 2014-07-31 |
20140215177 | Methods and Systems for Managing Heterogeneous Memories - A system includes a processor and first and second memories coupled to the processor. The first and second memories have a hardware attribute, such as bandwidth, latency and/or power consumption, wherein a first value of the hardware attribute of the first memory is different from a second value of the hardware attribute of the second memory. The system further includes a memory management module configured to receive a memory allocation request. The memory management module is configured to allocate memory space in the first memory or the second memory in response to the memory allocation request based on the values of the hardware attribute of the first memory and the second memory. | 2014-07-31 |
20140215178 | RESOURCE MANAGEMENT IN MAPREDUCE ARCHITECTURE AND ARCHITECTURAL SYSTEM - A method for resource management in MapReduce architecture. The method includes: determining a ratio r of an input data amount of a Map task and an output data amount of the Map task and an average size R of a record in Map output results; determining a memory size Memory_size that can be allocated to the Map task corresponding to a Map slot; according to the determined r, R and Memory_size, determining an input split size appropriate for the Map task; and allocating an input split with the input split size in a MapReduce job to be processed to the Map task occupying the Map slot. An apparatus for same is also provided. | 2014-07-31 |
20140215179 | ADDRESS GENERATOR, ADDRESS GENERATION METHOD, AND ENCAPSULATION-DECAPSULATION DEVICE - An address generator includes a storage device in which one or more second-protocol-family address prefixes are stored, the one or more second-protocol-family address prefixes each corresponding to a corresponding combination of at least a multiplexing identifier and a first-protocol-family address, and a controller configured to read, from the storage device, the second-protocol-family address prefix corresponding to a combination of at least the multiplexing identifier and the first-protocol-family address that is contained in a data block to be transferred via a backbone network to a destination network which uses the first protocol family, the read second-protocol-family address prefix serving as an address prefix for a network that is overlaid with the destination network, and configured to generate a second-protocol-family address containing the first-protocol-family address, the multiplexing identifier, and the read second-protocol-family address prefix, the generated second-protocol-family address serving as a destination address within the backbone network. | 2014-07-31 |
20140215180 | ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 2014-07-31 |
20140215181 | QUEUE REQUEST ORDERING SYSTEMS AND METHODS - The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In one embodiment, the storage component maintains a request without stalling a request in an aliasing condition. | 2014-07-31 |
20140215182 | Persistent Relocatable Reset Vector for Processor - In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time. | 2014-07-31 |
20140215183 | HARDWARE AND SOFTWARE SOLUTIONS TO DIVERGENT BRANCHES IN A PARALLEL PIPELINE - A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler arranges instructions within the identified loop into very large instruction words (VLIW's). At least one VLIW includes instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The compiler generates code wherein when executed assigns at runtime instructions within a given VLIW to multiple parallel execution lanes within a target processor. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The target processor includes a vector register for storing indications indicating which given instruction within a fetched VLIW for an associated lane to execute. | 2014-07-31 |
20140215184 | MEMORY MANAGEMENT IN A STREAMING APPLICATION - One embodiment is directed to a method for processing a stream of tuples. The method may include receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors. Each of the processing elements has an associated memory space. In addition, the method may include monitoring the plurality of processing elements. The monitoring may include identifying a first performance metric for a first processing element. The method may include modifying the first processing element based on the first performance metric. The modifying of the first processing element may include employing memory management of the associated memory space. | 2014-07-31 |
20140215185 | FETCHING INSTRUCTIONS OF A LOOP ROUTINE - In one aspect, a processor is configured to store instructions fetched from a program memory in an instruction queue, determine that an instruction to be decoded defines a beginning of a loop routine, and determine whether the instruction is stored in the instruction queue. In response to determining that the instruction is stored in the instruction queue, the processor disables fetching of instructions from the program memory, fetches instructions of the loop routine from the instruction queue, and stores the instructions of the loop routine in an instruction register. In response to determining that the instruction is not stored in the instruction queue, the processor fetches the instruction from the program memory, stores the instruction in the instruction queue, and stores the instruction in the instruction register. | 2014-07-31 |
20140215186 | SYSTEMS, APPARATUSES, AND METHODS FOR MAPPING A SOURCE OPERAND TO A DIFFERENT RANGE - Embodiments of systems, apparatuses, and methods for performing a range mapping instruction in a computer processor are described. In some embodiments, the execution of a range mapping instruction maps a data element having a source data range to a destination data element having a destination data range and storage of the of the destination data element. | 2014-07-31 |
20140215187 | SOLUTION TO DIVERGENT BRANCHES IN A SIMD CORE USING HARDWARE POINTERS - A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler generates code wherein when executed determines a size of a next very large instruction world (VLIW) to process and determine multiple pointer values to store in multiple corresponding PC registers in a target processor. The updated PC registers point to instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The processor includes a vector register for mapping PC registers to execution lanes. | 2014-07-31 |