31st week of 2014 patent applcation highlights part 21 |
Patent application number | Title | Published |
20140210476 | MAGNETIC RESONANCE IMAGING DEVICE - A device includes: a static magnetic field generating device including static magnetic field generating sources generating a homogeneous magnetic field in a space; gradient magnetic field generating sources superimposing a gradient magnetic field on the homogeneous magnetic field, and conductor rings arranged between the static magnetic field generating sources and the gradient magnetic field generating sources in a pair of arranging regions on both sides in a direction of the homogeneous magnetic field in a region where the homogeneous magnetic field is generated (imaging region), respectively, the conductor rings being separated from each other and making a pair. The conductor rings are mechanically connected to the gradient magnetic field generating device or the static magnetic field generating device. This provides an MRI device 1 capable of reduction in vibration with suppression of the image quality deterioration of the tomographic images. | 2014-07-31 |
20140210477 | DISTINGUISHING FALSE SIGNALS IN CABLE LOCATING - Discriminating between a cable locating signal and a false cable locating signal is described. A reference signal, which contains a locating signal frequency impressed on it, is transmitted in a way which provides for detection of a phase shift between the locating signal and the false locating signal. Based on the phase shift, a receiver is used to distinguish the locating signal from the false locating signal. | 2014-07-31 |
20140210478 | BORING TECHNIQUE USING LOCATE POINT MEASUREMENTS FOR BORING TOOL DEPTH PREDICTION - A method is disclosed as part of an overall process in which a boring tool is moved through the ground within a given region along a particular path in an orientation which includes pitch. A locating signal is transmitted from the boring tool which signal exhibits a field defined forward point within a reference surface which field defined forward point is vertically above an inground forward point on the particular path through which the boring tool is likely to pass. The method establishes a predicted depth of the boring tool at the inground forward point by first identifying the field defined forward point. The signal strength of the locating signal is then measured at the field defined forward point as being representative of the depth of the boring tool at an inground upstream point which is the current location of the boring tool. With the boring tool at the upstream inground point, the pitch of the boring tool is determined. Using the measured signal strength and the determined pitch, the predicted depth of the boring tool is determined for the inground forward point based on the boring tool moving along an approximately straight path to the inground forward point. | 2014-07-31 |
20140210479 | DEVICE FOR MEASURING AN ELECTRIC CURRENT - The invention relates to a device for measuring an electric current between a vehicle battery and an electrical consumer connected to the vehicle battery. The claimed device includes a bus bar which picks up the electric current in the vehicle battery and guides it further to the electrical consumer, on which a first current sensor and a second current sensor which is different from the first current sensor are arranged, the current sensors being designed to measure, independently from each other, the electric current circulating in the bus bar. | 2014-07-31 |
20140210480 | METHOD OF TESTING SECONDARY BATTERY - A method of testing a secondary battery includes step A of charging the secondary battery to a predetermined charge voltage, step B of setting aside the secondary battery for a predetermined time (tb) after the step A, step C of discharging the secondary battery to a predetermined discharge voltage after the step B, and step D of detecting a battery voltage increase for a preset time (t2) after a predetermined time (t1) has elapsed after the step C. This method of testing a secondary battery can evaluate a measurement of how much the negative electrode active material layer covers the positive electrode active material layer based on the battery voltage increase detected in the step D. | 2014-07-31 |
20140210481 | BATTERY TARGET TEMPERATURE METHODS AND SYSTEMS - Methods and systems for determining a target temperature and/or adjusting a temperature associated with a battery, such as a vehicle battery. In some implementations of such methods, a temperature-scaled battery capacity of at least a portion of a battery may be determined at a measured temperature. The temperature-scaled battery capacity may be compared with a capacity threshold and, upon determining that the temperature-scaled battery capacity is below the capacity threshold, a target battery temperature for the at least a portion of the battery may be determined and/or set. | 2014-07-31 |
20140210482 | METHOD AND APPARATUS FOR REDUCING COMMON MODE VARIATIONS IN A VOLTAGE SENSING COMPONENT - A method and apparatus that reduce common mode variations experienced by a voltage sensing component. A measurement component such as a BATFET or an external sensing resistor, receives, at its source, a voltage from the top of a battery having a voltage VPH_PWR. A voltage sensing component, such as an ADC, is powered by the voltage from the battery. A power referenced component, such as a power referenced LDO, tracks the voltage from the battery and outputs the tracked voltage minus a predetermined voltage amount to a negative side of the voltage sensing component. | 2014-07-31 |
20140210483 | PROCESSING DEVICE FOR BATTERY PACK AND PROCESSING METHOD THEREFOR - A processing device for a battery pack including a plurality of batteries has a voltage detection section configured to detect the voltage of each of the batteries, a first processing section configured to perform first processing for discharging the battery pack, and a second processing section configured to perform second processing for individually charging the batteries. The second processing section is configured to suppress a voltage drop by performing the second processing on the battery of which the voltage value has been reduced to a first predetermined value during the discharging in the first processing. | 2014-07-31 |
20140210484 | METHOD FOR DETERMINING A CIRCUIT ELEMENT PARAMETER - A method for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter. | 2014-07-31 |
20140210485 | METHOD AND APPARATUS FOR DETECTING AN ARC IN A DC CIRCUIT - The disclosure relates to a method for detecting an arc in a DC circuit. The method includes measuring and analyzing an AC component (I | 2014-07-31 |
20140210486 | ANTENNA SYSTEM - Broadband antenna system comprising a plurality of antenna elements and a plurality of amplifiers; wherein every antenna element of said plurality of antenna elements is configured for operating in a predetermined frequency range and is associated with an amplifier of said plurality of amplifiers which is configured for said predetermined frequency range; said plurality of antenna elements covering a broadband range. | 2014-07-31 |
20140210487 | ANTENNA DEVICE - An antenna device includes a sensor electrode having a capacitance configured to change upon an object approaching or contacting the sensor electrode, a sensor circuit electrically connected to the sensor electrode, an antenna section, and a substrate having the sensor circuit mounted thereon and having the sensor electrode fixed thereto. The sensor circuit is configured to detect the capacitance. The substrate is inserted into the antenna section. This antenna device allows components to be easily positioned during assembly. | 2014-07-31 |
20140210488 | METHOD OF FILLING LEVEL MEASUREMENT OF LAYERED MEDIA - A method of filling level measurement in a container ( | 2014-07-31 |
20140210489 | Sensor and Method for Detecting a Number of Objects - A sensor device for detecting a number of objects, has a number of electrode configurations forming a sensor surface, each electrode configuration having a number of measurement electrodes and each electrode configuration being associated with at least one transmitter electrode, and an evaluation device coupled to the measurement electrodes and the transmitter electrodes, which is adapted for using a time multiplexing method for applying an alternating signal to one of the transmitter electrodes, and to apply a predetermined constant electrical potential to the remaining transmitter electrodes, and tapping an electrical signal indicating the position of the object relative to the sensor surface at the measurement electrodes associated with the transmitter electrode having the electrical alternating signal applied. | 2014-07-31 |
20140210490 | HYBRID SENSOR - A hybrid sensor includes a proximity sensor section and a load sensor section. The proximity sensor section includes a first base material, a plurality of first front-side electrodes, a plurality of first back-side electrodes, and a protective layer. Each of these members is made of an elastomer. The proximity sensor section detects the approach and coordinates of an object to be detected, based on a change in capacitance between the first front-side electrode and the first back-side electrode which is caused by the approach of the object to be detected. The load sensor section detects pressing and coordinates of the object to be detected, based on a load that is applied from the object to be detected via the proximity sensor section. | 2014-07-31 |
20140210491 | Current-Based Charge Compensation in a Touch Sensor - In one embodiment, a method comprises generating a first current at a current source having a magnitude based on the magnitude of a second current flowing from a capacitive node of a touch sensor in the absence of a touch with respect to the capacitive node. The method further includes generating a third current from the capacitive node of the touch sensor in the presence of a touch with respect to the capacitive node. The first current and the third current are summed to cancel out at least a portion of the third current. The method further includes integrating, by an integrator, the sum of the first current and the third current to generate an output voltage. | 2014-07-31 |
20140210492 | Moisture Meter for Determining the Moisture Content of Particulate Material - A moisture meter for determining the moisture content of particulate material is provided. The moisture meter comprises a frame part, a space, a measuring cup disposed within said space for receiving a sample of the particulate material which moisture is to be measured, and moisture measuring means. The moisture meter comprises a swiping means for removing at least partly a part of a sample of particulate material which moisture is to be measured, which part of the sample of particulate material extends out of the inner space of the measuring cup through the open end of the measuring cup. The swiping means are movably attached to the frame part for movement in a swiping path where a swiping member of the swiping means is configured to move essentially along the open end of the measuring cup. | 2014-07-31 |
20140210493 | HANDHELD AND MOBILE IMPEDANCE SENSOR PLATFORM FOR DETECTION OF E-COLI AND OTHER PATHOGENS WITH IMMOBILIZED PEPTIDE/ANTIBODY - A handheld device to detect pathogens may include a handheld impedance sensor to measure impedance of the pathogen having a socket and a sensing circuit being positioned in the socket to provide the pathogen. | 2014-07-31 |
20140210494 | ELECTRICAL METHODS AND SYSTEMS FOR CONCRETE TESTING - Hundreds of thousands of concrete bridges and hundreds of billions of tons of concrete require characterization with time for corrosion. Accordingly, protocols for rapid testing and improved field characterization systems that automatically triangulate electrical resistivity and half-cell corrosion potential measurements would be beneficial allowing discrete/periodic mapping of a structure to be performed as well as addressing testing for asphalt covered concrete. Further, it is the low frequency impedance of rebar in concrete that correlates to corrosion state but these are normally time consuming vulnerable to noise. Hence, it would be beneficial to provide a means of making low frequency electrical resistivity measurements rapidly. Further, prior art techniques for electrical rebar measurements require electrical connection be made to the rebar which increases measurement complexity/disruption/repair/cost even when no corrosion is identified. Beneficially a method of determining the state of a rebar without electrical contact is taught. | 2014-07-31 |
20140210495 | LOAD TESTING MACHINE - A load testing machines includes: six resistance units; six cooling fans; insulators between the resistance units and the cooling fans; and connection cables, in which: each of the resistance units includes a plurality of steps of resistor groups arranged in a z-direction and each formed of a plurality of rod-shaped resistors parallel to a x-direction connected together in series arranged at predetermined intervals in a y-direction; the six cooling fans face the resistance units, respectively, in the z-direction; the connection cables are cables used for serially and detachably connecting resistor groups next to each other in the y-direction of two resistance units next to each other in the y-direction with an interval of not smaller than a second distance in between; and the insulators each have a size corresponding to the rated voltage of a target power supply of a power supply load test to be conducted using a resistance unit group. | 2014-07-31 |
20140210496 | CHIP-TO-CHIP SIGNAL TRANSMISSION SYSTEM AND CHIP-TO-CHIP CAPACITIVE COUPLING TRANSMISSION CIRCUIT - A chip-to-chip signal transmission system is provided, which includes a first chip, a second chip, and a dielectric layer. A signal transmission is performed between a transmitter of the first chip and a receiver of the second chip through a transmission-metal-pad unit and a receiving-metal-pad unit. The transmitter transmits a transmission-testing-coupling signal through the transmission-metal-pad unit according to a driving-testing signal when the transmitter receives the driving-testing signal. A first testing unit receives the transmission-testing-coupling signal and outputs a transmission-testing signal according to the transmission-testing-coupling signal. A second testing unit transmits a receiving-testing-coupling signal through the receiving-metal-pad unit according to the driving-testing signal when the second testing unit receives the driving-testing signal. The receiver receives the receiving-testing-coupling signal and outputs a receiving-testing signal according to the receiving-testing-coupling signal. | 2014-07-31 |
20140210497 | STACK INCLUDING INSPECTION CIRCUIT, INSPECTION METHOD AND INSPECTION APPARATUS - According to one embodiment, a stack includes first and second wiring structures and an inspection circuit. The inspection circuit includes a switching circuit having an input terminal, a drive terminal, and an output terminal electrically connected with a discharge mechanism. The inspection circuit is configured such that, in a state where a first electric connection is made in the first wiring structure and a second electric connection is made in the second wiring structure, at the time of applying charges to first and second electrodes, the charge applied to the second electrode flows to the drive terminal through the second wiring structure to bring the input terminal and the output terminal of the switching circuit into an electrically conducted state, and the charge applied to the first electrode flows to the discharge mechanism through the first wiring structure and the switching circuit. | 2014-07-31 |
20140210498 | ELECTRONIC APPARATUS HAVING IC TEMPERATURE CONTROL - The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins. | 2014-07-31 |
20140210499 | INCREASING CURRENT CARRYING CAPABILITY THROUGH DIRECT LIQUID COOLING OF TEST CONTACTS - Testing methods and systems are described. One method for testing an electronic device includes providing a probe in electrical contact with a device. The method also includes positioning an interface of the probe and the device in a liquid medium. The method also includes transmitting a current from the probe through the interface while the interface is in the liquid medium. Other embodiments are described and claimed. | 2014-07-31 |
20140210500 | SEMICONDUCTOR EVALUATING DEVICE AND SEMICONDUCTOR EVALUATING METHOD - A semiconductor evaluating device includes a chuck stage for holding a semiconductor device serving as a measuring object, a contact probe for evaluating an electrical characteristic of the semiconductor device by getting contact with the semiconductor device held on the chuck stage, and a fluid spraying portion for spraying a fluid onto the semiconductor device. | 2014-07-31 |
20140210501 | TEST APPARATUS HAVING A PROBE CARD AND CONNECTOR MECHANISM - A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder. | 2014-07-31 |
20140210502 | ENHANCED REVERBERATION CHAMBER - A method and apparatus for an enhanced reverberation chamber are disclosed. In one embodiment, one or more positioners are coupled to a tuner, such that when the tuner moves, the positioner moves. A device involved with a test may be mounted to the positioner so that when the positioner moves, the device moves. | 2014-07-31 |
20140210503 | STARTUP BOOT CYCLE TESTING OF A MOBILE DEVICE AT DIMINISHED POWER SUPPLY CURRENT - A startup boot cycle test system for testing a mobile multi-function device under test (DUT) that has a power manager and a main system processor is described. The system includes an external power source and a tester device. The external power source provides an input current to the power manager, which in turn provides a boot current, drawn from the input current, to the main system processor. The tester device connects to a test point in the DUT using a contact test probe to draw a margin current from the boot current. The resulting diminished boot current is used by the processor to boot. The tester device detects whether the processor successfully boots using the diminished boot current using a data input connector connected between the DUT and tester device. Other embodiments are also described and claimed. | 2014-07-31 |
20140210504 | TESTING DEVICE FOR ELECTRONIC DEVICE TESTING - A testing device includes a test board, a number of locating pins, a pin holder, a number of metal pins, a connector holder, a connector, a number of elastic elements, and a pressure block. The test board is electrically connected with a testing circuit. The locating pins are fixed on the testing board to guide the connector holder. Bottoms of the number of metal pins are vertically fixed in the pin holder. The elastic elements are arranged between the pin holder and the connector holder for pushing the connector holder back to its original position after testing. The connector is set in the connector holder and connected with an electronic device to be tested. The pressure block is positioned above the connector holder and used to push the connector holder down to the pin holder to make the testing contacts in the connector contact the metal pins. | 2014-07-31 |
20140210505 | WAFER TESTING PROBE CARD - A wafer testing probe card includes a printed circuit board, a flexible circuit board, an elastic piece, and a probe unit. The flexible circuit board is electrically connected to the printed circuit board. The elastic piece is disposed between the printed circuit board and the flexible circuit board. The probe unit includes a probe head and a plurality of probes. The probe head is fixed on the printed circuit board and has a plurality of through holes. The probes respectively pass through the through holes and move up and down relative to the probe head. | 2014-07-31 |
20140210506 | In-Situ Charging Neutralization - Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided. | 2014-07-31 |
20140210507 | LED FAILURE DETECTION - A fault detecting circuit in a string of LEDs D | 2014-07-31 |
20140210508 | Determining A Malfunctioning Device in A Plasma System - Systems and methods for determining a malfunctioning device in a plasma system, are described. One of the methods includes receiving an indication whether plasma is generated within a plasma chamber of the plasma system. The plasma system includes a processing portion and a power delivery portion. The method further includes determining whether the plasma system operates within constraints in response to receiving the indication that the plasma is generated, determining a value of a variable at an output of the power delivery portion when the processing portion is decoupled from the power delivery portion, and comparing the determined value with a pre-recorded value of the variable. The method includes determining whether the determined value is outside a range of the pre-recorded value and determining that the malfunctioning device within the power delivery portion upon determining that the determined value is outside the range of the pre-recorded value. | 2014-07-31 |
20140210509 | REDRIVER WITH OUTPUT RECEIVER DETECTION THAT MIRRORS DETECTED TERMINATION ON OUTPUT TO INPUT - A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling. | 2014-07-31 |
20140210510 | BYPASSABLE CLOCKED STORAGE CIRCUITRY FOR DYNAMIC VOLTAGE-FREQUENCY SCALING - Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff. | 2014-07-31 |
20140210511 | Error Detection in Nonvolatile Logic Arrays Using Parity - A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected. | 2014-07-31 |
20140210512 | Rescaling - A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits. | 2014-07-31 |
20140210513 | Controllable Storage Elements for an IC - An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC. | 2014-07-31 |
20140210514 | CONFIGURABLE LOGIC BLOCK AND OPERATION METHOD THEREOF - A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit. | 2014-07-31 |
20140210515 | PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS - In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block. | 2014-07-31 |
20140210516 | Level Shifter Circuit Optimized for Metastability Resolution and Integrated Level Shifter and Metastability Resolution Circuit - A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal. | 2014-07-31 |
20140210517 | HIGH-VOLTAGE LEVEL-SHIFTER - Described herein is a high-voltage level-shifter (HVLS) that can be used for both NMOS and PMOS bridges, exhibits a higher voltage tolerance for over-clocking than traditional level-shifters, has reduced crowbar current in its input driver, and no contention in its output driver. The HVLS comprises an input driver including a first signal conditioning unit, the input driver operating on a first power supply level and for conditioning an input signal as a first signal in the first signal conditioning unit; and a circuit to receive the first signal and to provide a second signal based at least in part on the first signal, the second signal being level-shifted from the first power supply level to a second power supply level, wherein the second power supply level is higher than the first power supply level. | 2014-07-31 |
20140210518 | Resonant Inductor Coupling Clock Distribution - The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal. | 2014-07-31 |
20140210519 | Combined Sense Signal Generation and Detection - In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal. | 2014-07-31 |
20140210520 | LOW POWER LOW VOLTAGE DIFFERENTIAL DRIVER - The present invention provides for a differential driver for transmitting a differential signal including: a first power source to supply a first voltage; a second power source to supply a second voltage that is less than the first voltage; a current steering circuit coupled between the first power source and the second power source, the current steering circuit for steering a current into either a positive differential output node or a negative differential output node to transmit the differential signal according to a data signal and a dataN signal; a resistor interposed between the first power source and the current steering circuit; and a constant current sink interposed between the current steering circuit and the second power source, the constant current sink for sinking the current having a substantially constant value, in which, the dataN signal is the inverse of the data signal. | 2014-07-31 |
20140210521 | GATE OR SOURCE DRIVING APPARATUS - A gate/source driving apparatus includes a first gate/source driving chip and a second gate/source driving chip. The first gate/source driving chip includes a plurality of first charge pump circuits, each of which has a voltage input end, a voltage output end, a first capacitor end, and a second capacitor end. The second gate/source driving chip includes a plurality of second charge pump circuits, each of which also has a voltage input end, a voltage output end, a first capacitor end, and a second capacitor end. The voltage output end of at least one of the first charge pump circuits is coupled to the voltage input end of at least one of the second charge pump circuits. | 2014-07-31 |
20140210522 | DRIVE CIRCUITRY COMPENSATED FOR MANUFACTURING AND ENVIRONMENTAL VARIATION - Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process. | 2014-07-31 |
20140210523 | ELECTRONIC DEVICE WITH POWER MODE CONTROL BUFFERS - An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation. | 2014-07-31 |
20140210524 | USING HIGH FREQUENCY CRYSTAL FROM EXTERNAL MODULE TO TRIM REAL TIME CLOCK - Techniques including methods and apparatus for calibrating a local clock are provided in an implantable medical device. The implantable medical device includes a telemetry module for receiving a remote signal transmitted by an external device. The received signal is provided to a clocking circuit having a clocking circuit for computation of a calibration factor based on a difference between phases of the clock signal generated by the local clock and transitions in the received remote signal. The calibration factor may be derived as a function of an edge of the clock signal lagging or leading relative to a corresponding edge of the remote signal. | 2014-07-31 |
20140210525 | Hitless Switching Phase-Locked Loop - A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless. | 2014-07-31 |
20140210526 | Rotational Synchronizer Circuit for Metastablity Resolution - A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input. | 2014-07-31 |
20140210527 | INDUCTION-COUPLED CLOCK DISTRIBUTION FOR AN INTEGRATED CIRCUIT - An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package. | 2014-07-31 |
20140210528 | PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC) - One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal. | 2014-07-31 |
20140210529 | Phase Locked Loop and Method for Operating the Same - The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response. | 2014-07-31 |
20140210530 | CLOCK RECOVERY CIRCUIT AND CLOCK AND DATA RECOVERY CIRCUIT - A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock. | 2014-07-31 |
20140210531 | DELAY-LOCKED LOOP WITH INDEPENDENT PHASE ADJUSTMENT OF DELAYED CLOCK OUTPUT PAIRS - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 2014-07-31 |
20140210532 | Phase-Locked Loop Apparatus and Method - A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency. | 2014-07-31 |
20140210533 | EDGE RATE CONTROL GATE DRIVE CIRCUIT AND SYSTEM FOR HIGH AND LOW SIDE DEVICES WITH LARGE DRIVER FET - An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET. | 2014-07-31 |
20140210534 | PULSE WIDTH MODULATION SIGNAL GENERATION CIRCUIT AND PULSE WIDTH MODULATION SIGNAL GENERATION METHOD - The present invention discloses a PWM signal generation circuit and a PWM signal generation method. The PWM signal generation circuit includes: a reference signal generation circuit for generating a reference signal according to an input voltage; a variable ramp signal generation circuit for generating a variable ramp signal; and a comparator circuit for comparing the reference signal with the variable ramp signal to generate a PWM signal. A rising slope and/or a falling slope of the variable ramp signal is variable. | 2014-07-31 |
20140210535 | Signal Level Conversion in Nonvolatile Bitcell Array - A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage. | 2014-07-31 |
20140210536 | Technique For Filtering Of Clock Signals - In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC. | 2014-07-31 |
20140210537 | ELECTRONIC DEVICE - An electronic device is powered by a first power supply and connected to an external device powered by a second power supply. The electronic device comprises a master controller, a conversion module, and a detection module. The master controller outputs first information. The conversion module converts the first information into second information based on a first voltage from the first power supply and a second voltage from the second power supply to control the external device to execute corresponding functions. The detection module is connected with the first power supply and the conversion module, and generates a pull-up voltage when the voltage of the second power supply is in an abnormal state. The conversion module further converts the first information into a second information based on the voltage of the first power supply and the pull-up voltage. The pull-up voltage is larger than the first voltage. | 2014-07-31 |
20140210538 | MULTIPLE RAMP VARIABLE ATTENUATOR - The present disclosure provides an attenuator and associated methods of operations. An exemplary attenuator includes an input terminal, an output terminal, a voltage reference terminal, a first attenuation segment coupled with the input terminal and the output terminal, and a second attenuation segment coupled with the first attenuation segment and the voltage reference terminal. The attenuator further includes at least two switches coupled with the input terminal and the output terminal in parallel with the first attenuation segment, where at least some of the at least two switches have an associated voltage control terminal. For example, the attenuator includes a first switch and a second switch coupled with the input terminal and the output terminal in parallel with the first attenuation segment, wherein a first voltage control terminal is coupled with the first switch and a second voltage control terminal is coupled with the second switch. | 2014-07-31 |
20140210539 | Low Distortion MOS Attenuator - An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion. | 2014-07-31 |
20140210540 | POWER LINE CARRIER COMMUNICATION RECEPTION CIRCUIT - A power line carrier communication reception circuit which can precisely receive a signal to be superimposed at such a signal level that leakage of an electromagnetic wave does not cause a problem while employing a simplified configuration is provided. | 2014-07-31 |
20140210541 | SYSTEMS AND METHODS OF LEVEL SHIFTING FOR VOLTAGE DRIVERS - System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal. | 2014-07-31 |
20140210542 | POWER SPLITTER AND COMBINER - An electronic device is described, the device including a first circuit arranged to transfer a signal with a first predetermined phase shift, a second circuit, connected in series with the first circuit, arranged to transfer a signal with a second predetermined phase shift, and a resistance connected in parallel with the first and second circuits, wherein the first circuit includes a first capacitance connected between a first pair of nodes, a second capacitance connected between a second pair of nodes, and a first transformer having a first winding connected between the first pair of nodes and a second winding connected between the second pair of nodes. | 2014-07-31 |
20140210543 | HIGH FREQUENCY SEMICONDUCTOR SWITCH - A switch circuit, a control circuit, a grounding wire and a control wire are formed on a substrate. The switch circuit connects an antenna terminal with one of multiple high frequency terminals. The control circuit outputs a control signal to the switch circuit. The grounding wire is disposed between the switch circuit and the control circuit and extends from a location proximate to an edge of the substrate to a location proximate to an opposite edge of the substrate. The control wire that carries the control signal is disposed between one end of the grounding wire and an edge of the semiconductor substrate. | 2014-07-31 |
20140210544 | MONITOR CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING POWER SUPPLY VOLTAGE OF SEMICONDUCTOR DEVICE - A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result. | 2014-07-31 |
20140210545 | ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATION - An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current. | 2014-07-31 |
20140210546 | TUNING CIRCUITRY AND METHOD FOR ACTIVE FILTERS - Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency. | 2014-07-31 |
20140210547 | OPERATIONAL AMPLIFIER CIRCUIT - Provided is an operational amplifier circuit having a high tolerance for clock phase difference fluctuations. An FIR filter is used to add an input signal of the FIR filter to a signal obtained by delaying the input signal of the FIR filter. In this manner, chopper noise can be removed. Thus, the operational amplifier circuit may have a high tolerance for clock phase difference fluctuations regardless of the phase difference between clocks for controlling a chopper circuit and the FIR filter. | 2014-07-31 |
20140210548 | SOFT TURN-OFF FOR BOOST CONVERTERS - Techniques for reducing ringing arising from L-C coupling in a boost converter circuit during a transition from a boost ON state to a boost OFF state. In an aspect, during an OFF state of the boost converter circuit, the size of the high-side switch coupling a boost inductor to the load is gradually increased over time. In this manner, the on-resistance of the high-side switch is decreased from a first value to a second (lower) value over time, which advantageously reduces ringing (due to high quality factor or Q) when initially entering the OFF state, while maintaining low conduction losses during the remainder of the OFF state. Further techniques are provided for implementing the high-side switch as a plurality of parallel-coupled transistors. | 2014-07-31 |
20140210549 | METHOD AND APPARATUS FOR USING A PROCESSOR CONTROLLED SWITCHER WITH A POWER AMPLIFIER - Aspects disclosed herein relate to using a processor controlled switcher architecture with a high-efficiency PA control. A wireless communications device may be include a processor, a power amplifier and a processor controller PA switcher. In an aspect, the processor may be a modem, a RF chip, etc. In one example, the PA switcher may be configured to receive a switcher control signal on the control line. In an aspect, the switcher control signal may be based on future characteristics of an input signal. The PA switcher may be further configured to select a voltage path from among a plurality of voltage paths based on the switcher control signal to provide a supply voltage to the lower pass filter associated with the PA. | 2014-07-31 |
20140210550 | REVERSE CURRENT PREVENTION - Techniques for preventing reverse current in applications wherein a tracking supply voltage is placed in parallel with a switching power stage. The tracking supply voltage may be boosted to a level higher than a battery supply voltage using, e.g., a boost converter. In an aspect, a negative current detection block is provided to detect negative current flow from the boosted tracking supply voltage to the battery supply voltage. A high-side switch of the switching power stage may be disabled in response to detecting the negative current. To prevent false tripping, the tracking supply voltage may be further compared with the battery supply voltage, and a latch may be provided to further control the high-side switch. | 2014-07-31 |
20140210551 | VARIABLE-CLASS AMPLIFIER, SYSTEM, AND METHOD - A method and generator for modifying interactions between a load and the generator are described. The method includes applying output power to the load using a power amplifier, controlling a level of the output power responsive to a power control setting, and adjusting a conduction angle of the power amplifier to reduce a level of sensitivity of the power amplifier to variations of an impedance of the load. The generator includes a compensation subsystem coupled to the power amplifier that controls a conduction angle of the power amplifier to enable a sensitivity of the power amplifier to be adjusted. | 2014-07-31 |
20140210552 | APPARATUS AND METHODS FOR BIASING A POWER AMPLIFIER - Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled. | 2014-07-31 |
20140210553 | Dynamic current source for zero-crossing amplifier units for use in high-speed communication circuits - A zero-crossing amplifier unit for use in high speed analog-digital-converters. A gain stage compares a sampling voltage at an input node with a provided threshold voltage to obtain a gain stage output signal. A voltage controlled current source provides a load current depending on a time window between an initial slope and an end slope of the gain stage output signal. A slope control means increases a duration of a rise and/or fall time of at least one of the initial and end slopes of the gain stage output signal. | 2014-07-31 |
20140210554 | AMPLIFIERS WITH IMPROVED ISOLATION - Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled. | 2014-07-31 |
20140210555 | RADIO FREQUENCY SIGNAL AMPLIFIER AND AMPLIFYING SYSTEM - The present disclosure provides a radio frequency signal amplifier and amplifying system using coaxial cables to apply bias voltages to the control terminals of the transistors. The radio frequency signal amplifier includes a transistor connected between an input terminal and an output terminal, a first coaxial cable configured to couple a bias voltage to a control terminal of the transistor, a feed line connected between the bias voltage and the first coaxial cable, and a second coaxial cable connected between an open stub and the control terminal of the transistor. | 2014-07-31 |
20140210556 | HIGH-FREQUENCY AMPLIFIER - Since a high-frequency signal that is output from a high-frequency oscillator circuit section is detected in a detector circuit and a bias of a negative voltage is supplied from a bias circuit section to the high-frequency amplifier circuit section with a detection voltage that is detected, a negative power supply circuit such as a DC/DC converter or a peripheral circuit is not required, and since a negative bias voltage can be supplied to a high-frequency amplifier circuit, downsizing can be achieved with a low cost. | 2014-07-31 |
20140210557 | BIAS CIRCUIT - Proposed is a bias circuit for a transistor in a C class amplifier. The bias circuit comprises: a class AB amplifier bias voltage generating means adapted to generate a bias voltage at an output terminal; and a transistor connected between the output terminal and a first reference voltage, the control terminal of the transistor being connected to a second reference voltage via a switch. Closure of the switch connects the second reference voltage to the control terminal of the transistor to cause a shift in the bias voltage generated by the class AB amplifier bias voltage generating means to achieve a predetermined class C bias voltage at the output terminal. | 2014-07-31 |
20140210558 | SYSTEMS AND METHODS FOR BIASING AMPLIFIERS USING ADAPTIVE CLOSED-LOOP CONTROL AND ADAPTIVE PREDISTORTION - Various embodiments described herein provide systems and methods for improved performance for power amplifiers, particularly GaN power amplifiers. According to some embodiments, a power amplifier (e.g., GaN power amplifier) utilizes adaptive predistortion and adaptive closed-loop control of the drain current of the power amplifier to achieve improved power amplifier performance. | 2014-07-31 |
20140210559 | DYNAMIC HEADROOM FOR ENVELOPE TRACKING - Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described. | 2014-07-31 |
20140210560 | TRIPLE CASCODE POWER AMPLIFIER - A triple cascode power amplifier is provided. The triple cascode power amplifier includes a first-stage transistor pair, a second-stage transistor pair and a third-stage transistor pair. The first-stage transistor pair comprises two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities. The second-stage transistor pair is coupled with the first-stage transistor pair to form a first node and comprise two second-stage transistors coupled with each other to form a second node. The third-stage transistor pair is coupled with the second-stage transistor pair and comprises two third-stage transistors for outputting a differential signal. The first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component. The power amplifier transforms the differential signal into a single-ended signal for output. | 2014-07-31 |
20140210561 | RING OSCILLATOR AND SEMICONDUCTOR DEVICE - There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition. | 2014-07-31 |
20140210562 | SINGLE-ENDED RING OSCILLATOR WITH FULLY DIFFERENTIAL SIGNAL - A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase. | 2014-07-31 |
20140210563 | CRYSTAL CONTROLLED OSCILLATOR AND OSCILLATING DEVICE - A crystal controlled oscillator of the present disclosure includes: an oscillator circuit for oscillator output, a first oscillator circuit, a second oscillator circuit, a heating unit, a pulse generator, a frequency difference detector, an addition unit, a circuit unit, a frequency measuring unit, a determination unit, and a signal selector. The signal selector is configured to: select a control signal where electric power supplied to the heating unit is smaller than supplied electric power in the detection range in a case where a frequency in a set period at the train of pulses is out of the detection range at the high temperature side; select a control signal where electric power supplied to the heating unit becomes a preset value in a case where a frequency in the set period at the train of pulses is out of the detection range at the low temperature side. | 2014-07-31 |
20140210564 | RELAXATION OSCILLATOR WITH SELF-BIASED COMPARATOR - A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal. | 2014-07-31 |
20140210565 | AMPLITUDE LOOP CONTROL FOR OSCILLATORS - Systems and methods for amplitude loop control for oscillators. In some embodiments, an electronic circuit may include oscillator circuitry configured to produce a periodic signal, and control circuitry operably coupled to the oscillator circuitry, the control circuitry including switched capacitor circuitry configured to determine a difference between maximum and minimum peak voltage values of the periodic signal, the control circuit configured to control a voltage amplitude of the periodic signal based upon the difference. In other embodiments, a method may include receiving a clock signal from a clock generator, determining, using a switched capacitor circuit, a first peak voltage value of the clock signal, determining, using the switched capacitor circuit, a second peak voltage value of the clock signal, and controlling a bias current applied to the clock generator based upon a difference between the first and second peak voltage values. | 2014-07-31 |
20140210566 | CRYSTAL RESONATOR, CRYSTAL RESONATOR PACKAGE, AND CRYSTAL OSCILLATOR - A crystal resonator includes a crystal element and excitation electrodes. The crystal element includes an α crystal region and a β crystal region that have mutually different positive/negative directions along an X-axis. Each two or more of the α crystal regions and the β crystal regions are alternately formed along a direction perpendicular to the X-axis. The excitation electrodes are formed on both surfaces of the respective α crystal region and β crystal region other than crystal regions positioned at both end portions of a row of the α crystal regions and the β crystal regions. | 2014-07-31 |
20140210567 | CRYSTAL RESONATOR, CRYSTAL RESONATOR PACKAGE, AND OSCILLATOR - A crystal resonator includes a plate-shaped crystal element, excitation electrodes, and a second crystal region. The plate-shaped crystal element is supported to a supporting portion. The crystal element is configured to vibrate at a thickness shear vibration. The excitation electrodes are disposed at both surfaces of a first crystal region of the crystal element. The second crystal region is positioned outside with respect to the excitation electrodes. The second crystal region is formed at a peripheral edge portion of the crystal element so as to occupy a region of equal to or more than 75% of a whole circumference of the crystal element. The second crystal region has a positive/negative direction of an X-axis of a crystal different from a positive/negative direction of an X-axis of a crystal of the first crystal region. | 2014-07-31 |
20140210568 | MATCHING NETWORK - A matching network for matching the impedance of a load to an impedance of an electrical energy source has an output, an input, an inductance, a capacitance, and a series connection of a nonlinear impedance and the inductance or the capacitance. The series connection is connected in parallel to the output or parallel to the input. | 2014-07-31 |
20140210569 | MODULE SUBSTRATE AND MODULE - A module substrate includes: a multilayered wiring substrate that includes wiring layers; and embedded duplexers that are embedded in the multilayered wiring substrate and electrically connected to the wiring layers, wherein the embedded duplexers include duplexers supporting at least two bands of Band1, Band2, Band5, and Band8. | 2014-07-31 |
20140210570 | PIEZOELECTRIC THIN FILM RESONATOR, FILTER, AND DUPLEXER - A piezoelectric thin film resonator includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; and an insertion film that is inserted into the piezoelectric film, is located in at least a part of an outer periphery region in a resonance region in which the lower electrode and the upper electrode face each other across the piezoelectric film, and is not located in a center region of the resonance region. | 2014-07-31 |
20140210571 | TRANSFORMER FILTER ARRANGEMENT - A transformer filter arrangement including a transformer having a first winding and a second winding is provided. Both of the first and the second windings are located between an outer border and an inner border, which is inside the outer border. The transformer filter arrangement further includes at least one reactive sub circuit, each including at least one inductor. The first winding of the transformer is divided into a plurality of winding segments. At least a first one of the at least one reactive sub circuit being connected in series with the winding segments of the first winding between two such winding segments, and having at least one of the at least one inductor located inside said inner border. | 2014-07-31 |
20140210572 | MULTI-LAYER DIGITAL ELLIPTIC FILTER AND METHOD - The present invention relates generally to digital elliptic filters, and more particularly, but not exclusively to multi-layer digital elliptic filters and methods for their fabrication. | 2014-07-31 |
20140210573 | BLEND STRIP AND FILTER USING SAME - A filter includes a case, a number of resonant columns received in the case, a partition walls received in the case and located between the adjacent resonant columns, a number of blend strips fastened on the partition walls, and a cover covering on the case. The cover defines a number of regulating through hole corresponding to the resonant columns and the blend strips and includes a number of regulating bolts passing through the regulating through hole to couple with the resonant columns and the blend strips. The regulating bolts move upwards and downwards in the regulating through holes to regulate a transmission zero of the filter. | 2014-07-31 |
20140210574 | STRUCTURE OF BATTERY RELAY FOR VEHICLE - A structure of a battery relay is provided comprising a plunger movable upward and downward. The plunger comprises a lower portion, an upper portion, and an intermediate portion. A guide is fixed to a housing and supports the intermediate portion. A return spring is disposed on the lower portion and supports the plunger. A traveling contact is integrally formed with the plunger and movable upward and downward. A stationary contact is fixedly disposed at a lower side of the traveling contact. An exciting coil is connected to a battery switch and moves the plunger downward by being excited when the battery switch is turned on. A movable spring formed as a compression spring, is disposed on an upper portion of the traveling contact, and has one end fixed to an upper end of the plunger and another end fixed to an upper end of the guide. | 2014-07-31 |
20140210575 | ELECTRICALLY OPERATED BRANCH CIRCUIT PROTECTOR - Electrical operation of circuit breakers utilizing a straight pull dc magnet system with positive means of locking in OFF position is provided. The operating dynamics have advantages in fault coordination and discrimination for motor branch circuits. The construction offers physical and economic advantages in control solutions. | 2014-07-31 |