31st week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140209976 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (Si | 2014-07-31 |
20140209977 | DOPED AND STRAINED FLEXIBLE THIN-FILM TRANSISTORS - Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer. | 2014-07-31 |
20140209978 | DEVICES WITH STRAINED SOURCE/DRAIN STRUCTURES - A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions. | 2014-07-31 |
20140209979 | Metamorphic Growth Of III-V Semiconductor On Silicon Substrate By MOCVD for High Speed III-V Transistors - A III-V semiconductor device on a silicon substrate is constructed with a silicon (Si) substrate onto which gallium arsenide (GaAs) indium phosphide (InP) and aluminum indium arsenide (AlInAs) to form a structure of AlInAs over InP over GaAs over Si. The GaAs is applied in at least one layer over the Si, followed by at least one layer of InP and at least one layer of AlInAs. A portion of the structure is doped and a cap or passivation layer is applied. | 2014-07-31 |
20140209980 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer. | 2014-07-31 |
20140209981 | Semiconductor Device - Disclosed is a semiconductor device including transistors B on an output side of a current mirror, arranged uniformly in a surrounding area of a transistor A on an input side of the current mirror. The transistors B are arranged at equal distances, adjacently to the transistor A, on both sides of the transistor A. | 2014-07-31 |
20140209982 | SELF-ALIGNED WELL STRUCTURES FOR LOW-NOISE CHEMICAL SENSORS - In one implementation, a chemical detection device is described. The device includes a chemically-sensitive field effect transistor including a floating gate conductor coupled to a gate dielectric and having an upper surface, and a sensing material on the upper surface. The device also includes a fill material defining a reaction region extending above the sensing material, the reaction region overlying and substantially aligned with the floating gate conductor. | 2014-07-31 |
20140209983 | INTEGRATED METAL OXIDE CHEMICAL SENSOR - A chemical sensor is described with at least one layer of metal oxide arranged between two electrodes with the length of the layer of metal oxide between the electrodes being less than 50 microns, wherein at least one interface layer is formed between the surface of at least one of the electrodes and the layer of metal oxide and wherein the interface layer lowers the contact resistance between the electrodes and the layer of metal oxide by facilitating transport of charge carriers across layer boundaries. | 2014-07-31 |
20140209984 | Semiconductor Device With Multi Level Interconnects And Method Of Forming The Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure. | 2014-07-31 |
20140209985 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 2014-07-31 |
20140209986 | PHOTOCONDUCTOR-ON-ACTIVE PIXEL DEVICE - A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer. | 2014-07-31 |
20140209987 | MEMORY DEVICE - It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer. | 2014-07-31 |
20140209988 | NONVOLATILE MEMORY BITCELL - A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention. | 2014-07-31 |
20140209989 | ANTI-FUSE MEMORY CELL - An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area. | 2014-07-31 |
20140209990 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A memory device is provided having an improved gate coupling ratio, substantial suppression of p-type dopant segregation, and reduction in inter-poly dielectric current leakage. The memory device may be substantially free of any void spaces in a second conductive layer. Methods of manufacturing such a memory device are also provided. | 2014-07-31 |
20140209991 | CONVEX SHAPED THIN-FILM TRANSISTOR DEVICE - The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed. | 2014-07-31 |
20140209992 | FABRICATING METHOD OF NON-VOLATILE MEMORY STRUCTURE - A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer. | 2014-07-31 |
20140209993 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 2014-07-31 |
20140209994 | Embedded Cost-Efficient SONOS Non-Volatile Memory - A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI). | 2014-07-31 |
20140209995 | Non-Volatile Memory Cells Having Carbon Impurities and Related Manufacturing Methods - Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced. | 2014-07-31 |
20140209996 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region. | 2014-07-31 |
20140209997 | THIN FILM TRANSISTOR - A thin film transistor based on carbon nanotubes includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The work-functions of the source electrode and of the drain electrode are different from that of the semiconductor layer, enabling the creation of both p-type and n-type field-effect transistors. | 2014-07-31 |
20140209998 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 10 | 2014-07-31 |
20140209999 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductivity-type drain layer, a first conductivity-type drift layer formed on the drain layer, a second conductivity-type base layer formed on the drift layer, a first conductivity-type source layer which is selectively formed on a surface of the base layer, a trench region formed through a surface of the source layer such that the trench region reaches the drift layer from the surface of the source layer, a gate electrode formed adjacent to the base layer and inside the trench region, and surrounded by a first insulation film, a field plate electrode formed in the trench region below the gate electrode and surrounded by a second insulation film having a higher dielectric constant than the first insulation film, a drain electrode which is electrically connected to the drain layer, and a source electrode electrically connected to the source layer. | 2014-07-31 |
20140210000 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first lower insulating film (LIL | 2014-07-31 |
20140210001 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film. A thickness of the second region in a depth direction is gradually increased from the peripheral part of the element region to the central part thereof | 2014-07-31 |
20140210002 | N-CHANNEL DOUBLE DIFFUSION MOS TRANSISTOR, AND SEMICONDUCTOR COMPOSITE DEVICE - The n-channel double diffusion MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the p-type semiconductor substrate and the p-type epitaxial layer. In a p-type body layer provided in a surface portion of the p-type epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the p-type epitaxial layer in spaced relation from the p-type body layer. An n-type drain layer is provided in a surface portion of the p-type epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the p-type epitaxial layer between the n-type drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer. | 2014-07-31 |
20140210003 | DIODE, ESD PROTECTION CIRCUIT AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode. | 2014-07-31 |
20140210004 | SELF-ADJUSTING GATE HARD MASK - A method provides an intermediate semiconductor device structure and includes providing a water having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non planar wafer surface topography due at least to a presence of the fist dummy gate plugs; depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition. | 2014-07-31 |
20140210005 | SELF-ADJUSTING GATE HARD MASK - An intermediate wafer includes a substrate having a surface and a first dummy gate plug disposed upon a structure, e.g., a FIN, supported by the substrate surface; a second dummy gate plug disposed upon the substrate surface; and a first layer in which the first dummy gate plug and the second dummy gate plug are embedded. The first layer exhibits a non-planar surface topography characterized by a depression due at least to a presence of the first dummy gate plug. The structure further includes a second layer that fills the depression to the surface of the first layer, and a third layer that overlies the first layer and the second layer. The third layer is formed of a hard mask material and has a substantially planar surface topography over the first and second dummy gate plugs and over the depression that is filled with the material of the second layer. | 2014-07-31 |
20140210006 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY DEVICE - Embodiments of the invention provide an array substrate and a fabrication method thereof, and a liquid crystal display device. The array substrate comprises: a gate line, a data line, and a pixel unit formed by the gate line and the data line intersecting with each other. A first thin-film transistor and a pixel electrode are formed in the pixel unit, and the pixel electrode has slits. The pixel unit further comprises a second thin-film transistor, a first common electrode and a second common electrode, and the second thin-film transistor is configured to turn on and transmit a signal of the first common electrode to the second common electrode when a data line signal is at a high level. | 2014-07-31 |
20140210007 | ESD-Protection Circuit for Integrated Circuit Device - A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections. | 2014-07-31 |
20140210008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an n-type drift layer formed on a main surface of a semiconductor substrate, a plurality of p-type well regions formed selectively in an upper layer portion of the drift layer, an n-type source region formed in a surface of the p-type well region, and a p-type contact region which is shallower than the source region formed in the surface of the p-type well region adjacent to the source region. Moreover, the semiconductor device includes an n-type additional region formed in contact with a bottom surface of the p-type well region in a position corresponding to below the contact region and deeper than the p-type well region. | 2014-07-31 |
20140210009 | HIGH VOLTAGE FINFET STRUCTURE - Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region. | 2014-07-31 |
20140210010 | METHOD TO FORM FINFET/TRIGATE DEVICES ON BULK SEMICONDUCTOR WAFERS - A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices. | 2014-07-31 |
20140210011 | Dual Silicide Process - In one aspect, a method for silicidation includes the steps of: (a) providing a wafer having at least one first active area and at least one second active area defined therein; (b) masking the first active area with a first hardmask; (c) doping the second active area; (d) forming a silicide in the second active area, wherein the first hardmask serves to mask the first active area during both the doping step (c) and the forming step (d); (e) removing the first hardmask; (f) masking the second active area with a second hardmask; (g) doping the first active area; (h) forming a silicide in the first active area, wherein the second hardmask serves to mask the second active area during both the doping step (g) and the forming step (h); and (i) removing the second hardmask. | 2014-07-31 |
20140210012 | Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions - Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing. | 2014-07-31 |
20140210013 | SEMICONDUCTOR DEVICES HAVING A NANOWIRE CHANNEL STRUCTURE - A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different. | 2014-07-31 |
20140210014 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION - An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor. | 2014-07-31 |
20140210015 | Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure. | 2014-07-31 |
20140210016 | IMPLANT FOR PERFORMANCE ENHANCEMENT OF SELECTED TRANSISTORS IN AN INTEGRATED CIRCUIT - A first implant is performed into a substrate to form a well in which a plurality of transistors will be formed. Each transistor of a first subset of the plurality of transistors to be formed has a width that satisfies a predetermined width constraint and each transistor of a second subset has a width that does not satisfy the constraint. A second implant is performed at locations in the well in which transistors of the first subset will be formed and not at locations in the well in which transistors of the second subset will be formed. The transistors are formed, wherein a channel region of each transistor of the first subset is formed in a portion of the substrate which received the second implant and a channel region of each transistor of the second subset is formed in a portion of the substrate which did not receive the second implant. | 2014-07-31 |
20140210017 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes. | 2014-07-31 |
20140210018 | MICROELECTROMECHANICAL SYSTEM DEVICES HAVING CRACK RESISTANT MEMBRANE STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation. | 2014-07-31 |
20140210019 | LOW-COST PACKAGE FOR INTEGRATED MEMS SENSORS - An integrated MEMS sensor package is disclosed. The package comprises a sensor chip with a top surface and a bottom surface. The top surface comprises an opening. The bottom surface is attached to a substrate with electrical inter-connects. A lid is coupled to the top surface with an adhesive material. The lid may have an opening to expose the sensor chip to ambient environment. | 2014-07-31 |
20140210020 | MEMS Device and Method of Manufacturing a MEMS Device - MEMS devices with a rigid backplate and a method of making a MEMS device with a rigid backplate are disclosed. In one embodiment, a device includes a substrate and a backplate supported by the substrate. The backplate includes elongated protrusions. | 2014-07-31 |
20140210021 | METHOD AND APPARATUS FOR AMELIORATING PERIPHERAL EDGE DAMAGE IN MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) DEVICE FERROMAGNETIC LAYERS - An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same. | 2014-07-31 |
20140210022 | Magnetic Seed for Improving Blocking Temperature and Shield to Shield Spacing in a TMR Sensor - The blocking temperature of the AFM layer in a TMR sensor has been raised by inserting a magnetic seed layer between the AFM layer and the bottom shield. This gives the device improved thermal stability, including improved SNR and BER. | 2014-07-31 |
20140210023 | Vertical Hall Effect Element with Improved Sensitivity - A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity. | 2014-07-31 |
20140210024 | TUNNELING MAGNETORESISTANCE (TMR) READ SENSOR WITH AN INTEGRATED AUXILLIARY FERROMAGNETIC SHIELD - The invention provides a tunneling magnetoresistance (TMR) read sensor with an integrated auxiliary shield comprising buffer, parallel-coupling, shielding and decoupling layers for high-resolution magnetic recording. The buffer layer, preferably formed of an amorphous ferromagnetic Co—X (where X is Hf, Y, Zr, etc.) film, creates microstructural discontinuity between a lower ferromagnetic shield and the TMR read sensor. The parallel-coupling layer, preferably formed of a polycrystalline nonmagnetic Ru film, causes parallel coupling between the buffer and shielding layers. The shielding layer, preferably formed of a polycrystalline ferromagnetic Ni—Fe film exactly identical to that used as the lower ferromagnetic shield, shields magnetic fluxes stemming from a recording medium into the lower edge of the TMR read sensor. The decoupling layer, preferably formed of another polycrystalline nonmagnetic Ru film, causes decoupling between the shielding layer and a pinning layer preferably formed of a polycrystalline antiferromagnetic Ir—Mn film. | 2014-07-31 |
20140210025 | SPIN TRANSFER MRAM ELEMENT HAVING A VOLTAGE BIAS CONTROL - A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention. | 2014-07-31 |
20140210026 | SHORT CIRCUIT REDUCTION IN A FERROELECTRIC MEMORY CELL COMPRISING A STACK OF LAYERS ARRANGED ON A FLEXIBLE SUBSTRATE - A ferroelectric memory cell ( | 2014-07-31 |
20140210027 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - There is provided an image sensor module, including: an image sensor having a small thickness of 175 μm or less and having a first coefficient of thermal expansion; a substrate having the image sensor mounted thereon and having a second coefficient of thermal expansion higher than the first coefficient of thermal expansion; and an adhesive layer disposed between the image sensor and the substrate and including an adhesive having a third coefficient of thermal expansion of 130 ppm/° C. or more at a glass transition temperature Tg or more. | 2014-07-31 |
20140210028 | COLOR FILTER INCLUDING CLEAR PIXEL AND HARD MASK - Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed. | 2014-07-31 |
20140210029 | Backside Illumination Image Sensor Chips and Methods for Forming the Same - A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die. | 2014-07-31 |
20140210030 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a photoelectric conversion section made of semiconductor; a color filter made of an inorganic material to which a metal ion is added; and a getter film formed between the photoelectric conversion section and the color filter and configured to trap the metal ion. | 2014-07-31 |
20140210031 | VARIABLE OPTICAL FILTER AND A WAVELENGTH-SELECTIVE SENSOR BASED THEREON - A variable optical filter is disclosed including a bandpass filter and a blocking filter. The bandpass filter includes a stack of alternating first and second layers, and the blocking filter includes a stack of alternating third and fourth layers. The first, second and fourth materials each comprise different materials, so that a refractive index of the first material is smaller than a refractive index of the second material, which is smaller than a refractive index of the fourth material; while an absorption coefficient of the second material is smaller than an absorption coefficient of the fourth material. The materials can be selected to ensure high index contrast in the blocking filter and low optical losses in the bandpass filter. The first to fourth layers can be deposited directly on a photodetector array. | 2014-07-31 |
20140210032 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - The present invention relates to a solid-state imaging device having good focusing properties, a method for manufacturing such a solid-state imaging device, and an electronic apparatus. The solid-state imaging device has a semiconductor substrate | 2014-07-31 |
20140210033 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a pixel unit of a solid-state imaging device, a semiconductor substrate is provided with a plurality of photodiodes, a first insulating film includes a recess in a portion above each of the photodiodes, a second insulating film embeds the recess, a plurality of color filters is formed on the second insulating film, the color filters each corresponding to one of the photodiodes, a partition is provided between adjacent ones of the color filters, the partition being a part of a third insulating film, and in an area outside of the pixel unit, (i) a conductive film at least partially covered by the third insulating film is formed on the second insulating film, and (ii) the third insulating film formed on the conductive film and on the second insulating film near the conductive film has a film thickness smaller than a film thickness of the partition. | 2014-07-31 |
20140210034 | NEAR-INFRARED ABSORBING FILM COMPOSITIONS - A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film. | 2014-07-31 |
20140210035 | DIGITAL SILICON PHOTOMULTIPLIER DETECTOR CELLS - A silicon photomultiplier detector cell may include a photodiode region and a readout circuit region formed on a same substrate. The photodiode region may include a first semiconductor layer exposed on a surface of the silicon photomultiplier detector cell and doped with first type impurities; a second semiconductor layer doped with second type impurities; and/or a first epitaxial layer between the first semiconductor layer and the second semiconductor layer. The first epitaxial layer may contact the first semiconductor layer and the second semiconductor layer. The first epitaxial layer may be doped with the first type impurities at a concentration lower than a concentration of the first type impurities of the first semiconductor layer. | 2014-07-31 |
20140210036 | MEMBRANE-BASED SENSOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A sensing device has a semiconductor substrate with an opening and a membrane spanning the opening. A heater is arranged on the membrane. To reduce the thermal conductivity of the membrane, a recess is etched into the membrane from below. | 2014-07-31 |
20140210037 | SEMICONDUCTOR DEVICE - A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate electrode when turning on a power diode, an inversion layer is formed in a front surface layer of an n drift region sandwiched between a p guard ring region and a p anode region, and the p guard ring region and p anode region are connected by the inversion layer, thereby causing one portion or all of the p guard ring region to function as an active region together with the anode region, and expanding an energization region, thus lowering on-voltage. | 2014-07-31 |
20140210038 | SOI RF DEVICE AND METHOD FOR FORMING THE SAME - A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at least a part of the non-doped polysilicon layer is covered by an above metal layer. With effects of the metal layer which is applied with a RF signal or a superposed signal, and fixed charges in the BOX layer, an inversion layer may be formed at a surface of the non-doped polysilicon layer. Since carriers may easily recombine at the grain boundaries of polysilicon, eddy current generated on a surface of the high resistivity silicon base is reduced, loss of the RF signal is reduced, and linearity of the RF signal device is improved. | 2014-07-31 |
20140210039 | METHOD OF FABRICATING ISOLATED CAPACITORS AND STRUCTURE THEREOF - A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors. | 2014-07-31 |
20140210040 | ELECTRONIC FUSE LINE WITH MODIFIED CAP - An electronic fuse structure having an M | 2014-07-31 |
20140210041 | ELECTRONIC FUSE HAVING AN INSULATION LAYER - An electronic fuse structure including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the dielectric layer and the seed layer causing the seed layer to reflow and fill the first via opening, the second via opening, and partially filling the trench opening to form a fuse line, a first via, and a second via. The structure further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening. | 2014-07-31 |
20140210042 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which prevents deterioration of the long-term reliability caused by entry of moisture owing to a fuse opening in a multilayer wiring process. In order to prevent entry of moisture through the fuse opening, interlayer insulating films which are oxide films are etched so as to leave a part of a plasma TEOS oxide film layer. After that, a passivation nitride film is deposited and patterned, and then, the passivation nitride film is partly removed, thereby obtaining a structure in which side walls and a side bottom surface of the interlayer insulating films in the fuse opening are covered with the passivation nitride film. This enables inhibition of entry of moisture through an interface among the stacked interlayer insulating films and through an SOG layer, and deterioration of the IC characteristics owing to moisture can be prevented. | 2014-07-31 |
20140210043 | INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME - One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage V | 2014-07-31 |
20140210044 | SEMICONDUCTOR DEVICE HAVING INDUCTOR - A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines. | 2014-07-31 |
20140210045 | INDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An inductor device includes an insulation layer, an inductor, fixed electrodes, and a movable electrode. The inductor is formed on the insulation layer. The fixed electrodes are provided in positions which do not overlap with the inductor in a planar view. The movable electrode overlaps with the inductor and the fixed electrodes in the planar view, and is separated from the inductor and the fixed electrodes. Further, the movable electrode includes first openings. | 2014-07-31 |
20140210046 | SEMICONDUCTOR DEVICE HAVING HIGH FREQUENCY WIRING AND DUMMY METAL LAYER AT MULTILAYER WIRING STRUCTURE - A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor. | 2014-07-31 |
20140210047 | SEMICONDUCTOR DEVICE - A semiconductor device including: first and second semiconductor chips mounted on a base substrate; a third semiconductor chip, which is mounted on the base substrate, and outputs control signals controlling operations of the first and second semiconductor chips; a first transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the first semiconductor chip; and a second transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the second semiconductor chip, wherein the control signals are transmitted from the third semiconductor chip to the first semiconductor chip and the second semiconductor chip individually through the first transmission transformer and the second transmission transformer. | 2014-07-31 |
20140210048 | LAMINATE TYPE SEMICONDUCTOR CERAMIC CAPACITOR WITH VARISTOR FUNCTIONALITY AND METHOD FOR MANUFACTURING THE SAME - A semiconductor ceramic having a compounding molar ratio m between a Sr site and a Ti site that satisfies 1.000≦m≦1.020, has a donor element present as a solid solution in crystal grains, has an acceptor element present in a grain boundary layer in the range of 0.5 mol or less with respect to 100 mol of the Ti element, contains a Zr element in the range of 0.15 mol or more and 3.0 mol or less with respect to 100 mol of the Ti element, and has the crystal grains of 1.5 μm or less in average grain size. | 2014-07-31 |
20140210049 | METHODS OF FORMING CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL - Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material. | 2014-07-31 |
20140210050 | METHOD OF MANUFACTURING CAPACITOR AND DISPLAY APPARATUS INCLUDING THE SAME - Provided is a method of manufacturing a capacitor of a display apparatus, the display apparatus being formed on a substrate and including a thin film transistor, which includes an active layer, a gate electrode, and source and drain electrodes, a display device connected to the thin film transistor, and the capacitor, the method including: forming an electrode layer on the substrate; forming a passivation layer on the electrode layer; patterning the passivation layer to form a first pattern including first branch patterns parallel to each other, and a second pattern including second branch patterns parallel to each other and interposed between the first branch patterns; and forming first and second electrodes by etching the electrode layer using the first and second patterns as masks. | 2014-07-31 |
20140210051 | METHOD FOR IMPLEMENTING DEEP TRENCH ENABLED HIGH CURRENT CAPABLE BIPOLAR TRANSISTOR FOR CURRENT SWITCHING AND OUTPUT DRIVER APPLICATIONS - A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions. | 2014-07-31 |
20140210052 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region. | 2014-07-31 |
20140210053 | BI-DIRECTIONAL ESD PROTECTION CIRCUIT - A structure is designed with an external terminal ( | 2014-07-31 |
20140210054 | Semiconductor Devices and Methods of Producing These - A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip. | 2014-07-31 |
20140210055 | METHOD OF FORMING MICROPATTERN, METHOD OF FORMING DAMASCENE METALLIZATION, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED USING THE SAME - According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines. | 2014-07-31 |
20140210056 | SEMICONDUCTOR DEVICE - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 2014-07-31 |
20140210057 | METHOD OF APPLYING PHOTORESIST TO A SEMICONDUCTOR SUBSTRATE - A method comprises dispensing a first solvent on a semiconductor substrate; dispensing a first layer of a high-viscosity polymer on the first solvent; dispensing a second solvent on the first layer of high-viscosity polymer; and spinning the semiconductor substrate after dispensing the second solvent, so as to spread the high-viscosity polymer to a periphery of the semiconductor substrate. | 2014-07-31 |
20140210058 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer. | 2014-07-31 |
20140210059 | ORGANIC MODULE EMI SHIELDING STRUCTURES AND METHODS - Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An electromagnetic interference (EMI) shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material. | 2014-07-31 |
20140210060 | SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing resin, wherein: an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin is used as the sealing resin; and a copper member made of copper or a copper alloy and having an oxide film formed in the surface with a film thickness in a color indicated by an L* value in the range of 48 to 51, an a* value in the range of 40 to 49 and a b* value in the range of 24 to 40 is used as the leadframe and the wiring pattern. | 2014-07-31 |
20140210061 | CHIP ARRANGEMENT AND CHIP PACKAGE - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion. | 2014-07-31 |
20140210062 | Leadframe-Based Semiconductor Package Having Terminals on Top and Bottom Surfaces - A semiconductor device ( | 2014-07-31 |
20140210063 | SEMICONDUCITIVE CATECHOL GROUP ENCAPSULANT ADHESION PROMOTER FOR A PACKAGED ELECTRONIC DEVICE - A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant. | 2014-07-31 |
20140210064 | WIRE BONDING METHOD AND STRUCTURE - An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires. | 2014-07-31 |
20140210065 | SEMICONDUCTOR PACKAGE - A semiconductor package having a metal frame includes a frame-shaped conductive member which has an opening portion, mounted on a substrate, and a semiconductor element disposed within the opening. A ring-shaped wiring pattern is provided on a portion of the substrate outwards from the opening portion of the conductive member. The electrostatic coupling capacity of the ring-shaped wiring pattern and the conductive member is not less than the electrostatic coupling capacity of a semiconductor metal wiring layer and the conductive member. The ring-shaped wiring pattern and the ground wiring of the semiconductor metal wiring layer are electrically connected. | 2014-07-31 |
20140210066 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other. | 2014-07-31 |
20140210067 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate joined with a semiconductor chip, a case covering a surface of the insulating substrate where the semiconductor chip is joined, and a control terminal in which one end portion is electrically connected to the semiconductor chip, and another end portion passes through the case and is exposed to outside of the case. A portion of the control terminal exposed to the outside of the case includes a cut-out section where a part of the exposed portion is cut out, and a blocking section formed by bending a portion surrounded by the cut-out section and remaining on the control terminal. The blocking section contacts the case from the outside of the case and blocks a movement of the control terminal. | 2014-07-31 |
20140210068 | HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN ETCHED SILICON WAFER TROUGHS FOR ENHANCED THERMAL PERFORMANCE - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad. | 2014-07-31 |
20140210069 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - The present invention discloses a chip package and a manufacturing method thereof. The chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; and a bond pad formed on the upper surface, for electrically connecting to a circuit in the semiconductor chip. | 2014-07-31 |
20140210070 | Friction Stir Welding Structure and Power Semiconductor Device - A friction stir welding structure is comprised of a first and a second member integrated into one piece by friction stir welding, and in which a thin section is formed along the friction stir weld section on at least one of either of the first and the second member. | 2014-07-31 |
20140210071 | INTEGRATED STRUCTURE WITH IMPROVED HEAT DISSIPATION - An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material. | 2014-07-31 |
20140210072 | SEMICONDUCTOR MODULE - A semiconductor module includes a control board, and a shield plate arranged opposing the control board. A metal first heat dissipating portion is provided on a surface of the control board. A metal second heat dissipating portion is provided on a first surface of the shield plate, opposing the surface of the control board. A dielectric body is arranged between the first heat dissipating portion and the second heat dissipating portion. | 2014-07-31 |
20140210073 | CONDUCTIVE PASTE, ELECTRODE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a conductive paste, an electrode for a semiconductor device manufactured by using the conductive paste, a semiconductor device and a method for manufacturing the semiconductor device. The conductive paste includes conductive powder made of a plurality of conductive particles and silver powder made of a plurality of silver particles. The conductive particles includes a base material made of ceramics and a conductive layer configured to cover at least a part of an outer surface of the base material. The ratio of the mass of the conductive layer relative to the total mass of the conductive particles is 10% or more by mass, and the ratio of the mass of the conductive powder relative to the total mass of the conductive powder and the silver powder is 25% or less by mass. | 2014-07-31 |
20140210074 | Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages - Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. | 2014-07-31 |
20140210075 | METHODS FOR PROCESSING SUBSTRATES - A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer. | 2014-07-31 |