31st week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150214083 | PLASMA PROCESSING APPARATUS - In a plasma processing apparatus, an additional viewing window is disposed between an infrared temperature sensor and a view window, and the additional viewing window is cooled to be retained at room temperature (20° C. to 25° C.), to reduce and to stabilize electromagnetic waves emitted from the viewing window. By correcting the value of the electromagnetic waves, the measurement precision of the temperature monitor is increased and it is possible to measure and to control the dielectric window temperature in a stable state. | 2015-07-30 |
20150214084 | FRAME CASSETTE - According to various embodiments, a frame cassette may include: a housing; a mounting structure inserted in the housing, the mounting structure including a plurality of tape-frame slots, wherein each tape-frame slot is configured to receive a tape-frame, wherein the housing includes an opening to introduce a tape-frame into a tape-frame slot of the plurality of tape-frame slots or to remove a tape-frame from a tape-frame slot of the plurality of tape-frame slots, and a door mounted at the housing, wherein the door is configured to close the opening of the housing to seal the interior of the housing from the exterior of the housing. | 2015-07-30 |
20150214085 | MULTIFUNCTION WAFER AND FILM FRAME HANDLING SYSTEM - A multifunction wafer and film frame handling system includes a wafer table assembly having a wafer table providing an ultra-planar wafer table surface configured for carrying a wafer or a film frame, and at least one of: a flattening apparatus configured for automatically applying a downward force to portions of a warped or non-planar wafer in a direction normal to the wafer table surface; a displacement limitation apparatus configured for automatically constraining or preventing uncontrolled lateral motion of a wafer relative to the wafer table surface after cessation of an applied negative pressure and application of a positive pressure to the underside of the wafer via the wafer table; and a rotational misalignment compensation apparatus configured for automatically compensating for a rotational misalignment of a wafer mounted on a film frame. | 2015-07-30 |
20150214086 | Substrate Transport Vacuum Platform - An apparatus including a first device configured to support at least one substrate thereon; and a first transport having the device connected thereto. The transport is configured to carry the device. The transport includes a plurality of supports which are movable relative to one another along a linear path; at least one magnetic bearing which at least partially couples the supports to one another. A first one of the magnetic bearings includes a first permanent magnet and a second magnet. The first permanent magnet is connected to a first one of the supports. A magnetic field adjuster is connected to the first support which is configured to move the first permanent magnet and/or vary influence of a magnetic field of the first permanent magnet relative to the second magnet. | 2015-07-30 |
20150214087 | DIFFUSION RESISTANT ELECTROSTATIC CLAMP - In one embodiment, a method of fabricating an electrostatic clamp includes forming an insulator body, forming an electrode on the insulator body, and depositing a layer stack on the electrode, the layer stack comprising an aluminum oxide layer that is deposited using atomic layer deposition (ALD). | 2015-07-30 |
20150214088 | PICKUP METHOD AND PICKUP DEVICE - Disclosed is a pickup method in which a first suction unit is caused to approach and come into contact with a chip adhered to an adhesive sheet, and a second suction unit which is formed with a concavity on a contact surface configured to come into contact with the adhesive sheet is caused to approach and come into contact with the adhesive sheet in such a manner as to be opposite to the first suction unit. The adhesive sheet is sucked by the second suction unit that is in contact with the adhesive sheet, and a fluid is injected between the adhesive sheet and the chip by an injection unit. As a result, the adhesive sheet is detached from a portion of the chip opposite to the concavity, and in the state where the chip is being sucked by the first suction unit, the first suction unit is caused to be spaced away from the adhesive sheet that is being sucked by the second suction unit. In this manner, the chip is detached and picked up from the adhesive sheet. | 2015-07-30 |
20150214089 | METHODS FOR PROCESSING SUBSTRATES - A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer. | 2015-07-30 |
20150214090 | SINGLE ULTRA-PLANAR WAFER TABLE STRUCTURE FOR BOTH WAFERS AND FILM FRAMES - A wafer table structure providing a single wafer table surface suitable for handling both wafers and film frames includes a base tray having a set of compartments formed therein by way of a set of ridges formed in or on an interior base tray surface; a hardenable fluid permeable compartment material disposed within the set of base tray compartments; and a set of openings formed in the base tray interior surface by which the hardened compartment material is exposable to negative or positive pressures. The base tray includes a first ceramic material (e.g., porcelain), and the hardenable compartment material includes a second ceramic material. The base tray and the compartment material are simultaneously machinable by way of a standard machining process to thereby planarize exposed outer surfaces of the base tray and the hardened compartment material at an essentially identical rate for forming a highly or ultra-planar wafer table surface. | 2015-07-30 |
20150214091 | WAFER HANDLING TRACTION CONTROL SYSTEM - A wafer handling traction control system is provided that is able to detect slippage of a semiconductor wafer with respect to an end effector and is able to adjust the end effector's movement in order to minimize further slippage. Upon the detection of relative motion of the semiconductor wafer with respect to the end effector past a threshold amount, the end effector's movements are adjusted to minimize slippage of the semiconductor wafer. The wafer handling traction control system may include a sensor that detects relative motion between the semiconductor wafer and the end effector. | 2015-07-30 |
20150214092 | AIR GAPS BETWEEN COPPER LINES - Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The common name “air gap” will be used interchangeably the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The gas pockets may be one or more pores within dielectric material located between copper lines. Adjacent copper lines may be bordered by a lining layer and air gaps may extend from one lining layer on one copper line to the lining layer of an adjacent copper line. The gas pockets can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-K dielectric materials. | 2015-07-30 |
20150214093 | PROCESSES AND SYSTEMS FOR ENGINEERING A BARRIER SURFACE FOR COPPER DEPOSITION - A method for processing an interconnect structure on a substrate is provided, including: depositing a metallic barrier layer to line the interconnect structure, the metallic barrier layer configured to prevent diffusion of copper into the dielectric layer; depositing a thin copper seed layer over the metallic barrier layer in the interconnect structure; depositing a gap-fill copper layer over the thin copper seed layer; removing copper overburden and metallic barrier overburden, wherein removing copper overburden and metallic barrier overburden creates a planarized copper surface on the gap-fill copper layer; selectively depositing a thin layer of a cobalt-containing material on the reduced planarized copper surface; wherein the substrate is processed and transferred in controlled environments to minimize exposure to oxygen, the controlled environments defined by one or more controlled ambient environments and/or one or more vacuum environments. | 2015-07-30 |
20150214094 | METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES - Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization. | 2015-07-30 |
20150214095 | Method for Producing a Copper Layer on a Semiconductor Body Using a Printing Process - A method for producing a metal layer on a wafer is described. In one embodiment the method comprises providing a semiconductor wafer including a coating, printing a metal particle paste on the semiconductor wafer thereby forming a metal layer and heating the metal layer in a reductive gas for sintering the metal particle paste or for annealing a sintered metal particle paste in an oven. | 2015-07-30 |
20150214096 | SINKER WITH A REDUCED WIDTH - The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion. | 2015-07-30 |
20150214097 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION - The present invention provides a method for manufacturing a shallow trench isolation, comprising: forming a hard mask layer on the substrate; phottoetching/etching the hard mask layer and the substrate to form a plurality of first trenches along a first direction and a plurality of second trenches along a second direction perpendicular to the first direction, wherein the volume of the second trench is greater than that of the first trench; depositing an insulating material in the first and second trenches; planarizing the insulating material and the hard mask layer until the substrate is exposed so as to form a shallow trench isolation. According to a method of the present invention, the shallow trench isolation is allowed by etch-filling to be deep and wide in the channel width direction and shallow and narrow in the channel length direction, and stress is applied to NMOS and PMOS simultaneously to increase the carrier mobility of the channel region, thereby improving the overall driving capability of the device. | 2015-07-30 |
20150214098 | PROCESSING FOR FABRICATION OF A STRUCTURE WITH A VIEW TO A SUBSEQUENT SEPRATION - A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of said parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface. | 2015-07-30 |
20150214099 | METHOD OF ETCHING A CRYSTALLINE SEMICONDUCTOR MATERIAL BY ION IMPLANTATION AND THEN CHEMICAL ETCHING BASED ON HYDROGEN CHLORIDE - The invention provides a method of etching a crystalline semiconductor material ( | 2015-07-30 |
20150214100 | Methods of Forming a Substrate Opening - A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls. | 2015-07-30 |
20150214101 | METHODS FOR ETCHING A DIELECTRIC BARRIER LAYER IN A DUAL DAMASCENE STRUCTURE - Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer. | 2015-07-30 |
20150214102 | Interconnect Structures Comprising Flexible Buffer Layers - A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer. | 2015-07-30 |
20150214103 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a stack of conductive films, the stack of conductive films having a stairway portion located at an end portion thereof; an insulating layer disposed above the stack of conductive films; contact electrodes having different depths extending from an upper surface of the insulating layer to establish connection with upper surfaces of the conductive films in the stairway portion, the contact electrodes having different depths being arranged into at least a first contact group and a second contact group; an adjustment film disposed in the insulating layer; the contact electrodes in the second contact group extending through the adjustment film, a contact electrode having the smallest depth in the first contact group being deeper than a contact electrode having the greatest depth in the second contact group. | 2015-07-30 |
20150214104 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a plurality of metal terminals that are formed on a surface of the semiconductor substrate on the opposite side to a circuit-forming surface; and a resin that is formed on the surface of the semiconductor substrate on the opposite side to the circuit-forming surface, and covers at least part of side surfaces of the metal terminals, wherein upper surfaces of the metal terminals are exposed from the resin. | 2015-07-30 |
20150214105 | STRUCTURE AND METHOD OF FORMING SILICIDE ON FINS - Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET. | 2015-07-30 |
20150214106 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to increase the reliability of a semiconductor device. A manufacturing method of a semiconductor device according to the present invention includes a step of removing a patterned resist film and the step of removing a patterned resist film includes the steps of: (A) introducing at least a gas containing oxygen into a processing room; (B) starting electric discharge for transforming the gas containing oxygen into plasma; and (C) introducing a water vapor or an alcohol vapor into the processing room. On this occasion, the step (C) is applied either simultaneously with or after the step (B). | 2015-07-30 |
20150214107 | APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME - Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed. | 2015-07-30 |
20150214108 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions. | 2015-07-30 |
20150214109 | WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH WITH MASK PLASMA TREATMENT FOR IMPROVED MASK ETCH RESISTANCE - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits. | 2015-07-30 |
20150214110 | Structure and Approach to Prevent Thin Wafer Crack - A semiconductor structure and a method of manufacture are provided. Devices, such as integrated circuit dies, are mounted on a substrate, such as another die, packaging substrate, interposer, or the like, and recesses are formed in the substrate along the scribe lines. One or more molding compound layers are formed in the recesses and between adjacent dies. A backside thinning process may be performed to expose the molding compound in the recesses. A singulation process is performed in the molding compound layer in the recesses. In an embodiment, a first molding compound layer is formed in the recess, and a second molding compound is formed over the first molding compound layer and between adjacent dies. The devices may be placed on the substrate before or after forming the recesses. | 2015-07-30 |
20150214111 | WATER SOLUBLE MASK FORMATION BY DRY FILM VACUUM LAMINATION FOR LASER AND PLASMA DICING - Methods and systems for dicing a semiconductor wafer including a plurality of integrated circuits (ICs) are described. In one embodiment, a method involves adhering an adhesive tape to a thin water soluble dry film. The method involves applying the thin water soluble dry film adhered to the adhesive tape over a surface of the semiconductor wafer. The method involves removing the adhesive tape from the thin water soluble dry film. The thin water soluble dry film is patterned with a laser scribing process, exposing regions of the semiconductor wafer between the ICs. The method involves etching the semiconductor wafer through gaps in the patterned thin water soluble dry film, and removing the thin water soluble dry film. | 2015-07-30 |
20150214112 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor devices and methods for forming the same. A substrate having a dielectric layer formed thereon is provided. The dielectric layer has six openings. A gate dielectric layer and a cap layer are sequentially formed in each opening of the six openings. A first work function layer is formed in a first opening and a second opening. A diffusion layer is formed in the first opening, a fifth opening, and a sixth opening. A material of the diffusion layer is diffused into the first work function layer and the cap layer, to form a doped work function layer in the first opening and a doped cap layer in the fifth opening and in the sixth opening. A second work function layer is formed in a fourth opening and the fifth opening. A third work function layer and a metal gate are formed in the each opening. | 2015-07-30 |
20150214113 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS - A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings. | 2015-07-30 |
20150214114 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches. | 2015-07-30 |
20150214115 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate. | 2015-07-30 |
20150214116 | LOW LEAKAGE PMOS TRANSISTOR - A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices. | 2015-07-30 |
20150214117 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS - Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer. | 2015-07-30 |
20150214118 | Forming Arsenide-Based Complementary Logic On A Single Substrate - In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed. | 2015-07-30 |
20150214119 | FORMATION OF FINS HAVING DIFFERENT HEIGHTS IN FIN FIELD EFFECT TRANSISTORS - A method includes forming at least two fins of a fin field effect transistor (finFET) on a substrate and forming an insulator layer on the at least two fins. A portion of the insulator layer at a top of a first fin of the at least two fins is removed and a sacrificial layer is formed in a top end of the first fin. The method includes etching the sacrificial layer to remove the sacrificial layer to form the first fin having a different fin height than a second fin of the at least two fins. | 2015-07-30 |
20150214120 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE - A method for manufacturing an array substrate includes: forming a shielding layer, an insulating buffer layer, active layers, a gate insulating layer and NMOS gate electrodes in a display area and a drive area on a substrate in sequence; forming a PMOS gate electrode in the drive area on the foregoing substrate, in which the NMOS gate electrodes and the PMOS gate electrode are provided on the same layer; meanwhile forming a first through hole in a common electrode connecting area, in which the first through hole is configured to connect the shielding layer and a source/drain electrode layer; forming an intermediate insulating layer on the foregoing substrate, forming a second through hole in the common electrode connecting area and third through holes in the display area and the drive area, in which the second through hole is formed at a same position as the first through hole and configured to connect the shielding layer and a source/drain electrode layer, and the third through holes are configured to connect the active layers and the source/drain electrode layer; and forming the source/drain electrode layer on the foregoing substrate. | 2015-07-30 |
20150214121 | ULTRATHIN BODY FULLY DEPLETED SILICON-ON-INSULATOR INTEGRATED CIRCUITS AND METHODS FOR FABRICATING SAME - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body fully depleted silicon-on-insulator substrate. The method forms a temporary gate structure over the substrate and forms lightly doped source/drain extension areas around the gate structure. Further, the method includes performing an annealing process on the lightly doped source/drain extension areas. Outdiffusion from the lightly doped source/drain extensions is less than 5 nm during the annealing process. The method includes forming a strain region around the gate structure. | 2015-07-30 |
20150214122 | WAFER-SCALE TESTING OF PHOTONIC INTEGRATED CIRCUITS USING HORIZONTAL SPOT-SIZE CONVERTERS - Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits. | 2015-07-30 |
20150214123 | SEMICONDUCTOR WAFER EVALUATION METHOD AND SEMICONDUCTOR WAFER MANUFACTURING METHOD - A semiconductor-wafer evaluation method includes: before the mirror-polishing step, measuring warp data of displacement of the surface of the semiconductor wafer with a capacitive shape measurement device; setting a prescribed width of an outer circumferential portion of the semiconductor wafer as a sampling range; performing fitting of the warp data within the sampling range with a fitting function in a predetermined fitting range; calculating a difference (Range) between a maximum and a minimum of the warp data after the fitting within the sampling range; and, after the mirror-polishing step, evaluating the nanotopography of the surface of the semiconductor wafer on the basis of the calculated difference (Range). | 2015-07-30 |
20150214124 | Surface Delayering with a Programmed Manipulator - A method and apparatus for use in surface delayering for fault isolation and defect localization of a sample work piece is provided. More particularly, a method and apparatus for mechanically peeling of one or more layers from the sample in a rapid, controlled, and accurate manner is provided. A programmable actuator includes a delayering probe tip with a cutting edge that is shaped to quickly and accurately peel away a layer of material from a sample. The cutting face of the delayering probe tip is configured so that each peeling step peels away an area of material having a linear dimension substantially equal to the linear dimension of the delayering probe tip cutting face. The surface delayering may take place inside a vacuum chamber so that the target area of the sample can be observed in-situ with FIB/SEM imaging. | 2015-07-30 |
20150214125 | SCRIBE LINE STRUCTURE - A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other. | 2015-07-30 |
20150214126 | POWER SEMICONDUCTOR MODULE - Disclosed herein is a power semiconductor module. The power semiconductor module includes: a printed circuit board (PCB); first and second heat spreaders mounted on the PCB and having one surface arranged with terminal slots; power devices mounted on the first heat spreader and connected to one another in parallel and electrically connected to the second heat spreader; and first and second terminals provided with protrusion inserted into the terminal slots and provided with connection terminals for connecting external terminals. Therefore, it is possible to improve heat radiating properties of the power semiconductor module and improve a reliability problem such as solder crack or delamination in connection with terminal connection. | 2015-07-30 |
20150214127 | INTEGRATED DEVICE COMPRISING A SUBSTRATE WITH ALIGNING TRENCH AND/OR COOLING CAVITY - Some features pertain to an integrated device that includes a substrate. The substrate includes a first cavity (e.g., trench). The first cavity includes a first edge that is non-vertical. The first cavity is configured to align a die towards a center of the first cavity when the die is placed off-center of the first cavity. The integrated device also includes a first die positioned in the first cavity. The integrated device further includes a redistribution portion coupled to the first die. In some implementations, the first edge is a first wall of the first cavity. In some implementations, the first cavity includes a first opening and a first base portion. The first opening of the first cavity is greater than the first base portion of the first cavity. | 2015-07-30 |
20150214128 | System and Method for Bonding Package Lid - Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill. | 2015-07-30 |
20150214129 | ELECTRONIC COMPONENT PACKAGE AND METHOD FOR MANUFACTURING THE SAME - There is provided a method for manufacturing an electronic component package, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. In the manufacturing method of the present invention, a combination of a formation process of a plurality of metal plating layers and a patterning process of the metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, the patterning process being performed by a patterning of at least two of the metal plating layers. | 2015-07-30 |
20150214130 | STACKED INTERCONNECT HEAT SINK - A method is provided. The method includes providing an integrated circuit having a substrate. The method also includes locating a via within the substrate. The method further includes connecting the via to a corresponding heat spreader via. The corresponding heat spreader via may pass through a thermally conductive core of a heat spreader. | 2015-07-30 |
20150214131 | HEAT SINK AND SEMICONDUCTOR DEVICE - A heat sink includes a frame having an opening, the opening extending in a thickness direction of the frame, the opening having a first opening part and a second opening part, the second opening part being larger than the first opening part in a plan view perpendicular to the thickness direction, a wall standing on the frame at an edge of the opening, a groove formed in the frame beside the wall, and a plate member including a first plate disposed in the first opening part and a second plate disposed in the second opening part and larger than the first plate in the plan view, wherein the second opening part is larger than the second plate in the plan view to leave a gap therebetween, and the wall is bent toward the opening to be in contact with an edge along a perimeter of the second plate. | 2015-07-30 |
20150214132 | Low-Profile Heat Sink with Fine-Structure Patterned Fins for Increased Heat Transfer - In one embodiment, a device for transferring heat comprises a base member and a first array of pin fins supported by the base member, the pin fins having an aspect ratio of not less than about 10, and the pin fins being not more than about 0.3 mm in equivalent diameter and not more than about 3 mm in length, either one or both of the base member and pin fins comprising a metallic or semiconductor material. To form this device, a substrate is provided. A pattern is formed on the substrate, the pattern having holes therein or in the form of dots with cross-sectional dimensions of not more than about 0.3 mm. Pin fins supported by the substrate are formed, where the pin fins have an aspect ratio of not less than about 10, and not more than about 0.3 mm in equivalent diameter and not more than about 3 mm in length. Either one or both of the base member and pin fins comprise a metallic or semiconductor material. The pattern is then removed. | 2015-07-30 |
20150214133 | Electronic Device and Method for Fabricating an Electronic Device - An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element. | 2015-07-30 |
20150214134 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein. | 2015-07-30 |
20150214135 | Semiconductor Device Including Conductive Layer with Conductive Plug - Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected to the first conductive layer. The first conductive layer includes a plurality of loops of conductive material over the semiconductor substrate. Each of the plurality of loops comprises a first opening and a second opening, a first portion and a second portion sandwiching the first opening, a third portion and a fourth portion sandwiching the second opening, a first tab portion connected to the first portion and the third portion and having a first length in a first direction and a first width in a second direction perpendicular to the first direction, and a second tab portion connected to the second portion and the fourth portion and having a second length in the first direction and a second width in the second direction. | 2015-07-30 |
20150214136 | SEMICONDUCTOR DEVICE HAVING LEADFRAME WITH PRESSURE-ABSORBING PAD STRAPS - A leadframe ( | 2015-07-30 |
20150214137 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device may include a frame portion on which at least one semiconductor chip is arranged; a plurality of leads electrically connected to the semiconductor chip; and a mold portion formed on the frame portion to surround a part of the frame portion on which the semiconductor chip and the plurality of leads are arranged, wherein a gap between closest portions of the respective leads is at least 2.9 mm. | 2015-07-30 |
20150214138 | SEMICONDUCTOR DEVICE - According to one embodiment, the connector includes a first portion and a second portion. The first portion is provided on the second surface of the semiconductor chip and bonded to the second electrode. The first portion has a bonding surface, a heat dissipation surface, and a side surface. The bonding surface is bonded to the second electrode of the semiconductor chip. The heat dissipation surface is opposite to the bonding surface and exposed from the resin. The side surface is tilted with respect to the bonding surface and the heat dissipation surface, and covered with the resin. The second portion protrudes from the first portion toward the second leadframe side. The second portion is thinner than the first portion and bonded to the second leadframe. | 2015-07-30 |
20150214139 | SEMICONDUCTOR DEVICE - According to one embodiment, the connector has a first portion and a second portion. The first portion is provided on the second surface of the semiconductor chip and bonded to the second electrode. The first portion has a first bonding surface bonded to the second electrode of the semiconductor chip, and a heat dissipation surface opposite the first bonding surface and exposed from the resin. The second portion protrudes from the first portion toward the second lead frame side and thinner than the first portion. The second portion has a second bonding surface bonded to the second lead frame and a level difference portion provided near the second bonding surface at the first portion side. | 2015-07-30 |
20150214140 | LEADLESS PACKAGE TYPE POWER SEMICONDUCTOR MODULE - There is provided a leadless package type power semiconductor module. According to an exemplary embodiment of the present disclosure, the leadless package type power semiconductor module includes: connection terminals of a surface mounting type (SMT) formed at edges at which respective sides of four surfaces meet each other; a first mounting area connected to the connection terminals through a bridge to be disposed at a central portion thereof and mounted with power devices or control ICs electrically connected to the power devices to control the power devices; and second mounting areas formed between the connection terminals and mounted with the power devices or the control ICs, wherein the first mounting area is disposed at a different height from the second mounting area through the bridge to generate a phase difference from the second mounting area. Therefore, it is possible to implement a high-integration, high-performance, and small power semiconductor module by applying a three-dimensional structure deviating from a one-dimensional flat structure. | 2015-07-30 |
20150214141 | INTEGRATED PACKAGE ASSEMBLY FOR SWITCHING REGULATOR - In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate. | 2015-07-30 |
20150214142 | SEMICONDUCTOR DEVICE - To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire | 2015-07-30 |
20150214143 | Semiconductor Integrated Circuit With Nano Gap - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap. | 2015-07-30 |
20150214144 | NANOTUBE STRUCTURE BASED METAL DAMASCENE PROCESS - In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes. | 2015-07-30 |
20150214145 | Interconnect Structure and Method of Fabricating Same - An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump. | 2015-07-30 |
20150214146 | SEMICONDUCTOR DEVICE INCLUDING LANDING PAD - A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures. | 2015-07-30 |
20150214147 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance. | 2015-07-30 |
20150214148 | Inductor for Post Passivation Interconnect and A Method of Forming - An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member. | 2015-07-30 |
20150214149 | E-FUSE STRUCTURE WITH METHODS OF FUSING THE SAME AND MONITORING MATERIAL LEAKAGE - The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link. | 2015-07-30 |
20150214150 | Capacitor with Fuse Protection - An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node. | 2015-07-30 |
20150214151 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening. | 2015-07-30 |
20150214152 | SEMICONDUCTOR DEVICE INCLUDING LANDING PAD - The semiconductor device includes a plurality of conductive line structures including a plurality of conductive lines spaced apart from a substrate with an insulating film there between and insulating capping layers that are formed on each of plurality of conductive lines; an insulating spacer that is disposed between the plurality of conductive line structures and covers both side walls of each of the plurality of conductive line structures to define a contact hole having a first width in a first direction parallel to an upper surface of the substrate; a contact plug filling a portion of the contact hole; and a landing pad that is connected to the contact plug and vertically overlapping with one of the plurality of conductive line structures. | 2015-07-30 |
20150214153 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other. | 2015-07-30 |
20150214154 | Semiconductor Device and IO-Cell - According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction. | 2015-07-30 |
20150214155 | PACKAGES FOR THREE-DIMENSIONAL DIE STACKS - Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity. | 2015-07-30 |
20150214156 | MANUFACTURABLE SPIN AND SPIN-POLARON INTERCONNECTS - Manufacturable spin and spin-polaron interconnects are disclosed that do not exhibit the same increase in resistivity shown by Cu interconnects associated with decreasing linewidth. These interconnects rely on the transmission of spin as opposed to charge. Two types of graphene based interconnect approaches are explored, one involving the injection and diffusive transport of discrete spin-polarized carriers, and the other involving coherent spin polarization of graphene charge carriers due to exchange interactions with localized substrate spins. Such devices are manufacturable as well as scalable (methods for their fabrication exist, and the interconnects are based on direct growth, rather than physical transfer or metal catalyst formation). Performance at or above 300 K, as opposed to cryogenic temperatures, is the performance criteria. | 2015-07-30 |
20150214157 | ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS - An electrical device comprising including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers. | 2015-07-30 |
20150214158 | GATE METAL STRUCTURE AND FORMING METHID OF THE SAME - A gate metal structure and a forming method of the same are provided. The gate metal structure includes: a substrate and a copper metal layer; and a barrier layer disposed between the substrate and the copper metal layer, the barrier layer being formed of silicon oxynitride SiON or silicon oxide SiOx. By disposing a SiON or SiOx barrier layer between the substrate and the copper metal layer, conductivity and adhesion can be enhanced while reducing diffusion of copper when copper is used as the conductive metal layer material. | 2015-07-30 |
20150214159 | Interconnect Structure for Semiconductor Devices - A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. | 2015-07-30 |
20150214160 | Semiconductor structures comprising at least one through-substrate via filled with conductive materials - A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF | 2015-07-30 |
20150214161 | SEMICONDUCTOR STRUCTURE - A semiconductor structure comprising a tray, a chip, a first grounding wire and a second grounding wire is provided. The tray has a first surface and a second surface, and there is a height difference existing between the first surface and the second surface. The chip is disposed on the first surface of the tray and has an active surface. The first grounding wire connects the active surface and the second surface. The second grounding wire connects the first surface and the second surface. | 2015-07-30 |
20150214162 | PASSIVE COMPONENT STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump. | 2015-07-30 |
20150214163 | CHIP AND METHOD FOR DETECTING AN ATTACK ON A CHIP - According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal. | 2015-07-30 |
20150214164 | SEMICONDUCTOR DEVICES COMPRISING GETTER LAYERS AND METHODS OF MAKING AND USING THE SAME - Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material. | 2015-07-30 |
20150214165 | BONDING PAD STRUCTURE WITH DENSE VIA ARRAY - A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate. | 2015-07-30 |
20150214166 | System and Method for 3D Integrated Circuit Stacking - A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit. | 2015-07-30 |
20150214167 | SEMICONDUCTOR DIE WITH VARIABLE LENGTH BOND PAD - A semiconductor die has elongate, adjacent external interface cells that form an interface cell row. Each of the external interface cells provides an external interface for a circuit node of the die. Bond pads are disposed on a surface of the die, with each of the bond pads being electrically connected to a directly underlying one of the interface cells of the interface cell row. Each of the bond pads has a longitudinal axis aligned with a lengthwise axis of its respective directly underlying interface cell. Each of the bond pads also has a multiple potential wire bond site locations along its respective longitudinal axes. | 2015-07-30 |
20150214168 | SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF - A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer. | 2015-07-30 |
20150214169 | METHOD OF FABRICATING CONNECTION STRUCTURE FOR A SUBSTRATE - A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads. | 2015-07-30 |
20150214170 | SEMICONDUCTOR DEVICE WITH BUMP STOP STRUCTURE - A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided. | 2015-07-30 |
20150214171 | Substrates with Protruding Copper Termination Posts - A multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising at least one copper post that is only partially embedded in an outer layer of dielectric such that part of the at least one copper post protrudes beyond surface of the outer layer of dielectric. | 2015-07-30 |
20150214172 | MEMORY AND LAYOUT METHOD OF MEMORY BALL PADS - A memory comprises a substrate and memory ball pads. The memory ball pads are disposed around the substrate so as to form a ring pattern which show a bilateral symmetry by reflection, wherein the memory ball pads of left-half part of the ring pattern are divided into a first main area, a second main area, a third main area and a fourth main area. The memory ball pads in the first main area are divided into a first sub-region, a second sub-region and a third sub-region, and a plurality of input/output data pins and electricity power pins are disposed in the first sub-region and the third sub-region, wherein the input/output data pins are not adjacent to each other and at least one power voltage pin and at least one ground voltage pin are disposed next to each of the input/output data pins. | 2015-07-30 |
20150214173 | PACKAGE SUBSTRATE STRUCTURE FOR ENHANCED SIGNAL TRANSMISSION AND METHOD - In one embodiment, an electronic package structure includes a substrate having one or more conductive plane layers formed therein. The substrate also includes a plurality of conductive pads on major surface configured to provide electrical interconnects to a next level of assembly. At least one conductive plane layer is configured to have cut-outs above the solder pads so that at least portions of the solder pad are not overlapped by the conductive plane layer. | 2015-07-30 |
20150214174 | SEMICONDUCTOR MODULE - A semiconductor module includes a first semiconductor chip including a first signal line and a first ground, a mounting board or a second semiconductor chip including a second signal line and a second ground, a signal line coupling bump that couples the first signal line and the second signal line with each other, a first ground coupling bump that couples the first ground and the second ground with each other, a signal line side insulating film including a capacitance that causes a series resonance with an inductance by the signal line coupling bump at a target frequency and a ground side insulating film including a capacitance that causes a series resonance with an inductance by the first ground coupling bump at a target frequency. | 2015-07-30 |
20150214175 | CHIP MOUNTING STRUCTURE AND MANUFACTURING METHOD THEREFOR - Chip mounting is provided in which the pitch between bumps can be further narrowed without establishing contact between bumps. In a chip mounting structure in which a flip-chip bond has been established between a chip and a board via bumps, the bumps are provided so that the height position of the bumps from the connection surface of the chip or the connection surface of the board has a difference in height exceeding the thickness of adjacent bumps. This further narrows the pitch between bumps without establishing contact between the bumps. | 2015-07-30 |
20150214176 | ANISOTROPIC CONDUCTIVE FILM AND METHOD OF PRODUCING THE SAME - An anisotropic conductive film has a three-layer structure in which a first connection layer is sandwiched between a second connection layer and a third connection layer that each are formed mainly of an insulating resin. The first connection layer has a structure in which conductive particles are arranged in a single layer in the plane direction of an insulating resin layer on a side of the second connection layer, and the thickness of the insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than that of the insulating resin layer in regions in proximity to the conductive particles. | 2015-07-30 |
20150214177 | COATING LAYER FOR A CONDUCTIVE STRUCTURE - A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer. | 2015-07-30 |
20150214178 | MICROELECTRONIC UNIT AND PACKAGE WITH POSITIONAL REVERSAL - A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip package such as a two-chip package having a first chip facing upwardly and a second chip facing downwardly towards a package substrate, disposed below the chips. The reversed connections simplify routing, particularly where corresponding contacts of the two chips are to be connected to common terminals on the package substrate. | 2015-07-30 |
20150214179 | SEMICONDUCTOR DEVICE INCLUDING FLEXIBLE LEADS - A semiconductor device includes a semiconductor chip including a transistor. A first flexible lead is electrically coupled to a first electrode on a first surface of the semiconductor chip. A second flexible lead is electrically coupled to a second electrode on the first surface of the semiconductor chip. A third flexible lead is electrically coupled to a third electrode on a second surface of the semiconductor chip, the second surface opposite to the first surface. | 2015-07-30 |
20150214180 | ANTIOXIDANT GAS BLOW-OFF UNIT - An antioxidant gas blow-off unit includes: a base portion configured as a hollow plate having an antioxidant gas flow passage formed therein; a hole that is provided in the base portion to allow a capillary to be inserted therein or removed therefrom and that communicates with the antioxidant gas flow passage; and a heater mounted on an outer surface of the base portion. The antioxidant gas flow passage includes a first flow passage provided in the vicinity of the outer surface of the base portion on which the heater is mounted. This antioxidant gas blow-off unit to be installed in a wire bonding apparatus heats free air balls effectively with a compact structure. | 2015-07-30 |
20150214181 | METHODS FOR FORMING A SEMICONDUCTOR DEVICE PACKAGE - A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector. | 2015-07-30 |
20150214182 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate. | 2015-07-30 |