31st week of 2015 patent applcation highlights part 44 |
Patent application number | Title | Published |
20150212877 | APPARATUS AND METHOD FOR IMPROVING DATA STORAGE BY DATA INVERSION - An apparatus includes a processing unit and a memory. The processing unit is configured to encode a plurality of bits to obtain a plurality of encoded bits, the processing unit is configured to determine an inversion decision. When the inversion decision indicates that the subset of the encoded bits shall not be inverted, the processing unit is configured to store, as a stored word, bits of the first codeword into the memory. When the inversion decision indicates that the subset of the encoded bits shall be inverted, the processing unit is configured to invert each encoded bit of a subset of the encoded bits to obtain a second codeword and to store the second codeword into the memory. | 2015-07-30 |
20150212878 | NON-BLOCKING COMMANDS - Methods, systems, and devices are provided that processes storage commands. Data may be read from a storage memory at a storage device based on a read command received at the storage device from a host. An error may be detected in the data read from the storage memory at the storage device. In response to the error, placeholder data may be transmitted from the storage device to the host without transmitting an indication that the read command failed or succeeded. Corrected data may be transmitted from the storage device to the host, where the host replaces the placeholder data with the corrected data. | 2015-07-30 |
20150212879 | SEMICONDUCTOR DEVICE PERFORMING ERROR CORRECTION OPERATION - A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region. | 2015-07-30 |
20150212880 | ERROR CORRECTION IN DIFFERENTIAL MEMORY DEVICES WITH READING IN SINGLE-ENDED MODE IN ADDITION TO READING IN DIFFERENTIAL MODE - A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word. | 2015-07-30 |
20150212881 | ERROR CORRECTION IN MEMORY DEVICES BY MULTIPLE READINGS WITH DIFFERENT REFERENCES - A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word. | 2015-07-30 |
20150212882 | PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE - The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory. | 2015-07-30 |
20150212883 | ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE - Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches. | 2015-07-30 |
20150212884 | MEMORY CONTROLLER, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a storage device includes an encoder, a nonvolatile memory that stores user data and a parity, a magnetic disk, and a management unit that holds correspondence between a logical address and a first physical address as first conversion information, and holds correspondence between the first physical address and a second physical address as second conversion information, with the second physical address including media information indicating a medium of a storage destination and information indicating a storage position. When the user data stored in the nonvolatile memory is to be moved to the magnetic disk, the management unit updates the second physical address of the user date in the second conversion information, to a value indicating a storage destination after the movement. | 2015-07-30 |
20150212885 | ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC) - Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency. | 2015-07-30 |
20150212886 | ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC) - Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency. | 2015-07-30 |
20150212887 | REBUILDING A DATA REVISION IN A DISPERSED STORAGE NETWORK - A method begins by a processing module storing a set of encoded data slices in storage units. A data segment of data is encoded, in accordance with dispersed storage error encoding parameters, to produce the set of encoded data slices. The dispersed storage error encoding parameters include a decode threshold number and a pillar width number, which is at least twice the decode threshold number. The method continues with the processing module processing a first request for retrieval of the data segment by retrieving a first sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a first recovered data segment. The method continues with the processing module processing a second request for retrieval of the data segment by retrieving a second sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a second recovered data segment. | 2015-07-30 |
20150212888 | MEMORY SYSTEM - According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table. | 2015-07-30 |
20150212889 | TECHNIQUES FOR SERVING ARCHIVED ELECTRONIC MAIL - A system for providing user access to electronic mail includes an email client and an email server. The email client receives and communicates a user interaction with an email message The email server that receives the communication, determines whether the email message stored in a live database or in a backup storage. Upon determination that the email message is stored in a backup storage, the email server performs a message exchange with a backup storage system to perform the user-requested action. | 2015-07-30 |
20150212890 | GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR RECOVERING A VIDEO BASIC INPUT/OUTPUT SYSTEM - A graphics processing subsystem and a method for recovering a video basic input/output system (VBIOS). One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a VBIOS, and (2) a processor coupled to the memory and configured to employ a bridge to gain access to the VBIOS and cause the VBIOS to be written to the memory. | 2015-07-30 |
20150212891 | RESTARTING PROCESSES - Techniques are disclosed that include a computer-implemented method, including storing information related to an initial state of a process upon being initialized, wherein execution of the process includes executing at least one execution phase and upon completion of the executing of the execution phase storing information representative of an end state of the execution phase; aborting execution of the process in response to a predetermined event; and resuming execution of the process from one of the saved initial and end states without needing to shut down the process. | 2015-07-30 |
20150212892 | CAPTURING SNAPSHOTS OF OFFLOAD APPLICATIONS ON MANY-CORE COPROCESSORS - Methods are provided. A method includes capturing a snapshot of an offload process being executed by one or more many-core processors. The offload process is in signal communication with a host process being executed by a host processor. At least the offload is in signal communication with a monitoring process. The method further includes terminating the offload process on the one or more many-core processors, by the monitor process responsive to a communication between the monitor process and the offload processing being disrupted. The snapshot includes a respective predetermined minimum set of information required to restore a same state of the process as when the snapshot was taken. | 2015-07-30 |
20150212893 | SINGLE SNAPSHOT FOR MULTIPLE APPLICATIONS - An information management system according to certain aspects may be configured to generate a snapshot of data relating to a plurality of applications. The system may include a plurality of data agents, wherein each data agent is associated with at least one of a plurality of applications, and data generated by the plurality of applications is stored in a logical volume in primary storage. The system may also include a snapshot manager configured to detect the plurality of applications; check with the plurality of data agents whether the associated applications are in consistent states; obtain a snapshot of the logical volume in response to receiving notifications from the plurality of data agents that the associated applications are in consistent states; and generate mapping information between a particular one of the plurality of applications and a portion of the snapshot relating to the particular one of the plurality of applications. | 2015-07-30 |
20150212894 | RESTORING APPLICATION DATA FROM A SINGLE SNAPSHOT FOR MULTIPLE APPLICATIONS - An information management system according to certain aspects may be configured to restore data of an application from a snapshot including data of a plurality of applications. The system may include a snapshot manager configured to: receive instructions to restore data of a first application from a snapshot in secondary storage, the snapshot comprising data of a plurality of applications stored in a logical volume in primary storage at a first time, the plurality of applications comprising the first application and executing on a client computing device at the first time, the plurality of applications being in consistent states at the first time; access mapping information that maps data of the first application in the snapshot to the first application; locate a portion of the snapshot corresponding to the data of the first application to be restored; and copy the portion of the snapshot from the secondary storage. | 2015-07-30 |
20150212895 | GENERATING MAPPING INFORMATION FOR SINGLE SNAPSHOT FOR MULTIPLE APPLICATIONS - An information management system according certain aspects may be configured to generate a snapshot of data relating to a plurality of applications. The system may include first and second data agents associated with first and second applications, respectively. The system may also include a snapshot manager configured to: in response to receiving notifications from the first and second data agents that the first and second applications are in consistent states: obtain a snapshot of the logical volume including data generated by the first and second applications; generate mapping information between the first application and a portion of the snapshot relating to the first application based at least in part on metadata obtained by the first data agent; and generate mapping information between the second application and a portion of the snapshot relating to the second application based at least in part on metadata obtained by the second data agent. | 2015-07-30 |
20150212896 | DATABASE APPLICATION BACKUP IN SINGLE SNAPSHOT FOR MULTIPLE APPLICATIONS - An information management system according to certain aspects may be configured to generate a snapshot of data relating to a plurality of applications. Data generated by the plurality of applications may be stored in a logical volume in primary storage. The system may include a plurality of data agents including a database data agent associated with a database application that can be configured to back up one or more log files of a database log separately from data of the database application. The system may also include a snapshot manager configured to: in response to receiving notifications from the plurality of data agents that the associated applications are in consistent states, obtain a snapshot of the logical volume; generate mapping information between a particular application of the plurality of applications and a portion of the snapshot relating to the particular application; and truncate the database log of the database application. | 2015-07-30 |
20150212897 | SNAPSHOT READINESS CHECKING AND REPORTING - An information management system according to certain aspects may determine whether snapshot operations will work prior to executing them. The system may check various factors or parameters relating to a snapshot storage policy to verify whether the storage policy will work at runtime without actually executing the policy. Some examples of factors can include: availability of primary storage devices for which a snapshot should be obtained, availability of secondary storage devices, license availability for snapshot software, user credentials for connecting to primary and/or second storage devices, available storage capacity, connectivity to storage devices, etc. The system may also check whether a particular system configuration is supported in connection with snapshot operations. The result of the determination can be provided in the form of a report summarizing any problems found with the snapshot storage policy. The report can include recommended courses of action or solutions for resolving any identified issues. | 2015-07-30 |
20150212898 | DATA MIGRATION METHOD AND SYSTEMS - The invention relates to a method and system for migrating data stored in a second computing system to a first computing system, particularly wherein the first computing system is a local file system and the second computing system is a backup file system storing files to be transferred to the local file system. The method comprises pre-allocating a primary file matching a corresponding secondary file the second computing system. In response to receiving a read request for a data block not yet stored in the primary file, method comprises retrieving the requested data block from the secondary file and storing same locally in the primary file such that it is usable in the local system. The primary file is automatically populated with data blocks from the secondary file until it is complete in respect of data blocks stored. The system substantially carries out the method of the invention. | 2015-07-30 |
20150212899 | GRAPHICAL USER INTERFACE RELATIONSHIP GRAPH FOR DISPLAYING RELATIONSHIPS BETWEEN IMAGE BACKUP FILES IN A BACKUP JOB - Graphical user interface relationship graph for displaying relationships between image backup files in a backup job. In one example embodiment, one or more non-transitory computer-readable media store a program that causes a processor to generate and visually present, on an electronic display device associated with the processor, a graphical user interface (GUI) relationship graph for displaying relationships between image backup files in a backup job. The GUI relationship graph includes multiple image nodes each representing an image backup file of a source storage and a chain path including multiple links. Each of the links represents a parent-child relationship between one of the image nodes and another of the image nodes. | 2015-07-30 |
20150212900 | STORAGE SYSTEM AND METHOD OF CONTROLLING STORAGE SYSTEM - In a storage system for backing up data of an external apparatus, the external apparatus and a storage apparatus collaboratively perform efficient de-duplication. A storage system stores data from the external apparatus in a unit of content, and includes a backup apparatus configured to execute backup processing to create backup data of the data from the external apparatus in the unit of content; and a storage apparatus coupled to the backup apparatus in a communication-enabled manner and configured to store the backup data received from the backup apparatus. A first backup processing part of the backup apparatus determines whether or not a content is already stored in the storage apparatus by using first redundancy determination information that is information for determining whether or not each of contents of the backup data is already stored in the storage apparatus. | 2015-07-30 |
20150212901 | HEALTH MONITORING AND RECOVERY FOR INFRASTRUCTURE DEVICES - Automated health monitoring and recovery is provided for infrastructure devices supporting server devices in a data center. Health analysis operations may be selected to be performed on an infrastructure device based on the capabilities of the infrastructure device and/or how the infrastructure device is being used to support server devices in the data center. If the infrastructure device is unhealthy, an automated recovery operation may be performed. The automated recovery operation may include recovery actions selected based on the capabilities of the infrastructure device, the failure mode of the infrastructure device, and/or how the infrastructure device is being used to support server devices in the data center. | 2015-07-30 |
20150212902 | NETWORK ATTACHED STORAGE DEVICE WITH AUTOMATICALLY CONFIGURED DISTRIBUTED FILE SYSTEM AND FAST ACCESS FROM LOCAL COMPUTER CLIENT - A network attached storage device that has dual network ports and internal network bridge with a method for automatically configuring a distributed file system allowing multiple devices to be connected directly to computer clients while presenting an amalgamation of all the devices into a single large storage element. Electronic files stored on the storage element are automatically replicated so that a failure of one of the network attached storage devices will not result in the loss of data, and the multiple devices will automatically incorporate additional units to present a larger amalgamated storage element to the computer clients. These methods simplify the use of the storage devices and allow multiple computer clients simultaneous very fast access to files on the local devices. | 2015-07-30 |
20150212903 | MANAGEMENT COMPUTER USED TO CONSTRUCT BACKUP CONFIGURATION OF APPLICATION DATA - According to the present invention, it is possible to construct a backup configuration of a particular application data, without influencing data of another application. A management computer is coupled to a host computer on which an application operates, and to a storage apparatus that includes a plurality of volume groups each having one or more logical volumes. At least one of the logical volumes is allocated to the application. The management computer includes a volume group overlapping use determination part and a backup policy determination part. When the backup of the volume group to which one logical volume belongs is configured, the volume group overlapping use determination part determines whether there is another application that uses the volume group. The backup policy determination part determines whether there is set, for another volume group, backup policy information same as that set for the application. | 2015-07-30 |
20150212904 | METHOD AND COMPUTING DEVICE FOR RECORDING LOG ENTRIES - A method, computing device and computer program product are provided to maintain a comprehensive record of log entries, even in an instance in which the recordation of log entries to the primary log temporarily fails. In the context of a method, one or more log entries are written to a primary log. The method also includes determining that writing a log entry to the primary log has failed and writing the log entry to a fallback log in an instance in which writing the log entry to the primary log has failed. The method further includes performing a restoration process. The restoration process includes determining whether the log entry written to the fallback log is able to be written to the primary log. If so, the restoration process writes one or more log entries written to the fallback log to the primary log. If not, the restoration process is repeated. | 2015-07-30 |
20150212905 | TRANSACTIONAL EXECUTION DIAGNOSTICS USING DIGESTS - Gathering diagnostics during a transactional execution in a transactional memory environment, a transactional memory environment for performing transactional executions is provided. Included is identifying a first indicator, by a computer system, signaling a beginning instruction of a transaction comprising a plurality of instructions; generating, by the computer system, a computed digest based on the execution of at least one of the plurality of instructions; accumulating, by the computer system, a diagnostic data of the transaction based on the execution of the plurality of instructions; identifying, by the computer system, a second indicator associated with the plurality of instructions signaling an ending instruction of the transaction comprising the plurality of instructions; and based on an abort of the transaction, not saving the memory store data of the transaction to memory. | 2015-07-30 |
20150212906 | USING TRANSACTIONAL EXECUTION FOR RELIABILITY AND RECOVERY OF TRANSIENT FAILURES - Executing each portion of a stream of program instructions as a transaction for reliability, a computer system supporting transactional execution mode processing is provided. Included is determining that an instruction in a portion of the stream of program instructions begins a transaction; based on beginning the transaction, saving a snapshot of system state information and executing the portion of the stream of program instructions as a transaction until an end-mode test point in the stream of program instruction is reached. Based on reaching the end-mode test point, committing store data of the transaction to memory; and based on the stream of program instructions not being complete, automatically beginning a new transaction of a next portion of the stream of program instructions or based on aborting the transaction, re-executing the transaction based on the saved snapshot of the system state information. | 2015-07-30 |
20150212907 | MOBILE AGENT BASED MEMORY REPLICATION - Embodiments of the present invention disclose a method, computer program product, and system for memory replication. In one embodiment, in accordance with the present invention, the computer implemented method includes the steps of executing a mobile agent on a server node, wherein the server node is within a cluster of server nodes connected via network communications, capturing a memory state of the server node during operation of the server node, wherein the memory state includes session information stored on computer memory of the server node, which is captured and stored by the mobile agent, monitoring the server node to determine whether the server node has failed, and responsive to determining that the server node has failed, migrating the mobile agent to an active server node within the cluster of server nodes, wherein the mobile agent carries the captured memory state. | 2015-07-30 |
20150212908 | INTELLIGENT ROLLING UPGRADE FOR DATA STORAGE SYSTEMS - Various method, system, and computer program product embodiments for facilitating upgrades in a computing storage environment are provided. In one such embodiment, one of an available plurality of rolling upgrade policies is defined by specifying the at least one selectable upgrade parameter, including specifying one of a commencement time and duration of an upgrade procedure. A node down tolerance factor is set for at least one node in the computing storage environment. The node down tolerance factor specifies a percentage of elements of the at least one node taken offline to apply the selected one of the available plurality of rolling upgrade policies during the upgrade window. | 2015-07-30 |
20150212909 | METHOD AND APPARATUS FOR FAILOVER DETECTION AND RECOVERY - An approach for efficient failover detection includes detecting an attempt by a first server to transition from a standby mode to an active mode, diagnosing a loss of connectivity to the first server in a control plane as a cause of the attempt, and transitioning to a standby mode based on the diagnosed cause of the attempt. | 2015-07-30 |
20150212910 | HIGH AVAILABILITY ACROSS GEOGRAPHICALLY DISJOINT CLUSTERS - Exemplary methods, apparatuses, and systems include a first virtual infrastructure management (VIM) server monitoring a first host device to determine if the first host device receives one or more messages within an interval of time from a first storage device indicating a failure of one or more logical disks within the first storage device. The first VIM server manages a first virtual datacenter including the first host device and the first storage device. A second VIM server manages a second virtual datacenter including a second host device and a second storage device. The logical disk is replicated on the second storage device. The first VIM server determines, that a plurality of virtual machines running on the first host device is dependent upon the logical disk(s). The first VIM server performs, in response to the dependency upon the logical disk, a failover of the virtual machines to the second host device. | 2015-07-30 |
20150212911 | DYNAMIC USE OF RAID LEVELS RESPONSIVE TO PREDICTED FAILURE OF A DATA STORAGE DEVICE - Data associated with a workload is stored in a first composite array of data storage devices, and is automatically stored in a second composite array in response to predicting failure of one of the data storage devices in the first composite array. The data may be stored in the second composite array by either converting the first composite array or migrating the data to the second composite array. One of the data storage devices may predict its own failure and issue a predictive failure alert. | 2015-07-30 |
20150212912 | PERFORMANCE MITIGATION OF LOGICAL UNIT NUMBERS (LUNS) USING SMALL COMPUTER SYSTEM INTERFACE (SCSI) INBAND MANAGEMENT - A computer system for providing small computer system interface inband of storage area network computing environment is provided. The computer system comprises selecting signals of a primary path group that corresponds to a primary logical unit number of a primary device of a storage area network computing environment. The computer system further comprises detecting signal failures of the primary path group that corresponds to the primary logical unit number. The computer system further comprises initiating failover of the failed signals of the primary logical unit number from the primary device to a secondary logical unit number of a secondary device or a tertiary logical unit number of a tertiary device. The computer system further comprises registering, one or more applications of the storage area network computing environment for failover event notifications based on signal failures of the primary logical unit number of the primary device. | 2015-07-30 |
20150212913 | PERFORMANCE MITIGATION OF LOGICAL UNIT NUMBERS (LUNS) USING SMALL COMPUTER SYSTEM INTERFACE (SCSI) INBAND MANAGEMENT - A method for providing small computer system interface inband of storage area network computing environment is provided. The method comprises selecting signals of a primary path group that corresponds to a primary logical unit number of a primary device of a storage area network computing environment. The method further comprises detecting signal failures of the primary path group that corresponds to the primary logical unit number. The method further comprises initiating failover of the failed signals of the primary logical unit number from the primary device to a secondary logical unit number of a secondary device or a tertiary logical unit number of a tertiary device. The method further comprises registering, one or more applications of the storage area network computing environment for failover event notifications based on signal failures of the primary logical unit number of the primary device. | 2015-07-30 |
20150212914 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR TESTING NETWORK DEVICES USING SIMULATED APPLICATION TRAFFIC - Methods, systems, and computer readable media for testing network devices using simulated application traffic are disclosed. One method includes steps implemented in a network equipment test device including at least one processor. The method includes emulating data transfer operations of a plurality of server applications. The method further includes receiving application traffic from a plurality of different client applications. The method further includes queuing incoming connections received from the client applications. The method further includes, for each of the connections, attempting to correlate application-level data with one of the emulated server applications. The method further includes, in response to successful correlation of the received application-level data one of the emulated server applications, performing application-specific processing for the emulated server application. Performing application-specific processing includes sending data from an emulated server application to a client application through a device under test. | 2015-07-30 |
20150212915 | REMOTE CONTROLLABLE MEASURING APPARATUS AND MEASURING SYSTEM - A remote controllable measuring system includes a remote controllable measuring apparatus having a communication terminal having instant messaging; an input/output for exchanging signals with the communication terminal; a measurer (measuring apparatus main body); and a controller (computation apparatus) causing the measurer to operate according to an instruction from the communication terminal. The remote controllable measuring system also includes a mobile terminal capable of transmitting and receiving signals with the communication terminal. | 2015-07-30 |
20150212916 | OPERATION RECORDING CIRCUIT AND OPERATION METHOD THEREOF - An operation recording circuit and an operation method thereof are provided. The operation recording circuit includes a pin monitor unit, a memory unit, a data writing unit, a mode verification unit and a data dumping unit. The pin monitor unit monitors at least one first type pin of an integrated circuit (IC) to correspondingly provide a monitor signal. The data writing unit writes at least one monitor records into the memory unit according the monitor signal. When receiving a test dump command through at least one second type pin of the IC, the mode verification unit correspondingly provides a dump control signal. The data dumping unit determines whether to output the at least one monitor records from the memory unit through the at least one second type pin or not according to the dump control signal. | 2015-07-30 |
20150212917 | STATISTICAL POWER INDICATION MONITOR - A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. A user may use the statistical monitoring information to adjust system or application operation. The random pattern generator may be a pseudo-random pattern generator including a linear feedback shift register and may have programmable seed and sample rate. | 2015-07-30 |
20150212918 | REMINDING APPARATUS IN DATA PROCESSING DEVICE, REMINDING METHOD AND STORAGE MEDIUM - A reminding apparatus includes: a reminding module, configured to determine reminding time of the reminding apparatus and a reminding event corresponding to the reminding time, and trigger the reminding event when the reminding time is up; a background miming module, configured to indicate an operation system of the data processing device to trigger the reminding apparatus to enter a background running state after detecting a switch instruction; a battery level checking module, configured to check battery level of the data processing device when the reminding apparatus runs in the background; and a battery level protecting module, configured to write a local notification into the operation system when the battery level is lower than a predefined threshold, set triggering time of the local notification as the reminding time, and trigger the reminding apparatus to enter a pending state. The local notification can be triggered automatically by the operation system. | 2015-07-30 |
20150212919 | Policy Based Application Suspension and Termination - In accordance with one or more aspects, an application that is to be suspended on a computing device is identified based on a policy. The policy indicates that applications that are not being used are to be suspended. The application is automatically suspended, and is allowed to remain in memory but not execute while suspended. Additionally, when memory is to be freed one or more suspended applications to terminate are automatically selected based on the policy, and these one or more selected applications are terminated. | 2015-07-30 |
20150212920 | SOFTWARE SYSTEM VALIDITY TESTING - Data is identified that represents a path of a transaction that includes a plurality of transaction fragments associated with a plurality of software components. The transaction returns a particular value and a particular one of the plurality of software components is identified as a source of the particular value. A test action is generated that, when executed, is to attempt to verify the particular value from the particular software component. | 2015-07-30 |
20150212921 | DEBUG TRACE STREAM TIMESTAMPING USING DOWNSTREAM CORRELATION - A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a synchronization point. When a synchronization point is detected a time stamp value is inserted into the trace stream along with any relevant identification markers available in the detected synchronization point. | 2015-07-30 |
20150212922 | DATA ANALYSIS APPARATUS, METHOD AND PROGRAM - According to one embodiment, a data analysis apparatus includes a first acquisition unit, a second acquisition unit, an analysis unit and a totaling unit. The first acquisition unit acquires, for each of a plurality of target contents, a content information item including a broadcast time of one of the target contents and information which relates to a broadcast channel on which the one of the target contents is broadcasted. The second acquisition unit acquires viewing log information items each including an identification number, a viewing time and a viewing channel. The analysis unit calculates a viewing state with the identification number for each of the target contents and obtains a viewing pattern. The totaling unit totals the viewing pattern by the numbers of identification numbers. | 2015-07-30 |
20150212923 | NONTRANSITORY PROCESSOR READABLE RECORDING MEDIUM HAVING FAULT INJECTION PROGRAM RECORDED THEREIN AND FAULT INJECTION METHOD - According to one embodiment, a program causes a processor to perform providing, by a fault injection module, cooperation information to a debug function. The program causes a processor to perform receiving, by the fault injection module, a notification of at least one of condition related information and action related information as a response to the cooperation information from the debug function. The program causes a processor to perform determining, by the fault injection module, at least one of a fault injection condition and a fault injection action based on the notification. The program causes a processor to perform creating, by the fault injection module, a fault injection scenario that defines a fault injection procedure with respect to the fault injection target based on at least one of the determined fault injection condition and fault injection action. | 2015-07-30 |
20150212924 | INTERMEDIATE REPRESENTATION CONSTRUCTION FOR STATIC ANALYSIS - The analysis of an intermediate representation of source or program code. An initial version of an initial representation of the source or program code is accessed and statically analyzed. For one or more portions of this initial version, the analysis component queries an analysis-time resolution component that provides supplemental intermediate representations corresponding to the portion. This supplemental intermediate representation provides further clarity regarding the portion, and is analyzed. If defects are found, they may be reported. | 2015-07-30 |
20150212925 | SOFTWARE TRACING USING EXTENSIBLE MARKUP LANGUAGE MESSAGES - Software is traced using Extensible Markup Language (XML) messages. A trace command, which includes one or more specified fields to be traced and a trace output file location, is defined. A determination is made as to whether the trace command is for a full trace or a differential trace, where the full trace traces all the one or more specified fields, and the differential trace traces specified fields only in response to the specified fields having a value that has changed during processing. The trace command is added to an XML input message for propagation through one or more products. Trace data is collected from the full trace or the differential trace for defined fields at each product, and then stored at the trace output file location. | 2015-07-30 |
20150212926 | APPARATUS, SYSTEM, AND METHOD OF ACTIVATION CONTROL, AND MEDIUM STORING ACTIVATION CONTROL PROGRAM - An activation control apparatus stores first association information that associates, for each application, application identification information for identifying an application with terminal identification information for identifying a communication terminal permitted to debug the application. When a first communication terminal is provided with a debugger, the activation control apparatus determines whether any candidate application available for use by the first communication terminal is associated with terminal identification information of the first communication terminal using the first association information, and excludes from the candidate applications one or more applications that are not associated with the terminal identification information of the first communication terminal to generate an application list of one or more applications that can be activated. When the first communication terminal is not provided with a debugger, the activation control apparatus generates the application list that includes all of the one or more candidate applications as applications that can be activated. | 2015-07-30 |
20150212927 | Application Testing Automation - According to one embodiment of the present invention, a test for an application is created. An application is identified with functionality applied through a graphical user interface. A determination is made of expected characteristics of an application object that will be included in a version of the application once the version of the application becomes available for testing through the graphical user interface. A virtual object is created according to the expected characteristics of the application object. A step associated with the virtual object is incorporated into a test case to be used on the version of the application. The test case that includes the virtual object is executed on the version of the application when the version of the application becomes available for testing through the graphical user interface. | 2015-07-30 |
20150212928 | INTERACTIVE GRAPH FOR NAVIGATING APPLICATION CODE - Code elements may be selected from a graph depicting an application. The graph may show code elements as nodes, with edges representing connections between the nodes. The connections may be messages passed between code elements, code flow relationships, or other relationships. When a code element or group of code elements are selected from the graph, the corresponding source code may be displayed. The code may be displayed in a code editor or other mechanism by which the code may be viewed, edited, and manipulated. | 2015-07-30 |
20150212929 | SYSTEMS AND METHODS FOR PROCESSING SOFTWARE APPLICATION METADATA ASSOCIATED WITH A SOFTWARE APPLICATION - Systems and methods for processing software application metadata associated with a software application are provided. A representative method includes the step of collecting software application metadata associated with a software application. The software application metadata includes a first set of information related at least one of the following: screens, paths, and layers associated with the software application. The method further includes the step of storing the software application metadata in a data repository. | 2015-07-30 |
20150212930 | APPLICATION TEST SYSTEM, APPLICATION TEST METHOD AND STORAGE MEDIUM - An application test system includes a management server for managing an operation status of an operating terminal that is operated to test an application and an operation status of an operated terminal that is remotely operated in accordance with the operation of the operating terminal, wherein the management server includes operation information reception means for receiving, from the operating terminal in which a processed application obtained by injecting a terminal operation monitor program for monitoring the operation of the operating terminal into an application under test is installed, operation information of the operating terminal that is monitored by the terminal operation monitor program, and operation information transmission means for transmitting the operation information to the operated terminal in which the application under test and an operation program for operating the operated terminal based on the operation information are installed. | 2015-07-30 |
20150212931 | SYSTEM AND METHOD TO TEST EXECUTABLE INSTRUCTIONS - This document discusses, among other things, a method of testing an Application Programming Interface (API) call that includes receiving data identifying a schema associated with web services together with an API call. Various example embodiments may relate to accessing a data repository associated with the schema to identify an API response corresponding to the API call. In some example embodiments, a message is returned that is based on a determination of whether the API call is valid. The example message may simulate an API response from web services. | 2015-07-30 |
20150212932 | ASYNCHRONOUS CODE TESTING - A method and system for asynchronous code testing. Test cases are generated from an input code that includes code blocks organized in a hierarchy of nesting levels characterized by respective nesting level numbers that increase with increasing separation of each respective nesting level from a reference level of the total input code. Each test case includes a respective launching priority that quantifies how strongly each test case is associated with at least one modified code block of the input code. Generating the test cases determines the respective launching priority for each test case by (i) determining an association strength of each modified code block as measured by the nesting level in the hierarchy of each modified code block and (ii) computing the launching priority as a sum of the association strengths of the modified code blocks. The test cases are run to produce a test result. | 2015-07-30 |
20150212933 | METHODS FOR REDUCING MEMORY SPACE IN SEQUENTIAL OPERATIONS USING DIRECTED ACYCLIC GRAPHS - Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data. | 2015-07-30 |
20150212934 | SYSTEM AND METHOD TO CONVERT LOCK-FREE ALGORITHMS TO WAIT-FREE USING A HARDWARE ACCELERATOR - A method to convert lock-free algorithm to wait-free using a hardware accelerator includes (i) executing a plurality of software threads by a plurality of processing units associated, the plurality of software threads is associated with at least one operation, (ii) generating at least one of a read request or a write request at the hardware accelerator based on the execution, (iii) generating at least one operation includes PARAM and read request or the write request at the hardware accelerator, (iv) checking, an operation specific condition of at least one software thread of the plurality of software threads, and (v) updating, at least one read value or write value and at least one state variable upon the operation specific condition being an operation success. The operation specific condition includes an operation success or an operation failure based on the PARAM, the read request, or the write request. | 2015-07-30 |
20150212935 | METHOD FOR RELIABLY ADDRESSING A LARGE FLASH MEMORY AND FLASH MEMORY - A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area. | 2015-07-30 |
20150212936 | APPARATUS, SYSTEMS, AND METHODS FOR NAMELESS WRITES - An apparatus, system, and method are disclosed for implementing nameless storage operations. Storage clients can access and allocate portions of an address space of a non-volatile storage device to a nameless storage request. The methods include receiving from a storage client, a nameless storage request configured for storing data in an unspecified, available address of a logical block address of a non-volatile storage device, determining whether there exists enough logical capacity in the logical address space to satisfy the nameless storage request, allocating a logical identifier to the nameless storage request, and sending the allocated logical identifier to the storage client. Other embodiments are described. | 2015-07-30 |
20150212937 | STORAGE TRANSLATION LAYER - Method and systems for distributing the translation layer of storage media (such as NAND Flash or Storage Class Memory Storage) system across various storage system components are described herein. Non-limiting examples of storage system components include a Persistent Storage Device (PSD), a Storage Aggregation Controller (SAC), and a Storage Management Writer (SMW). The SMW may be configured to maintain a table of the logical address of each page it writes to a PSD via a SAC. The SAC may maintain the status of the validity of previously written pages with the SMW informing the SAC when any page is no longer valid. The PSD may handle device specific issues including error correction and block-level mapping for management of block-level failures and internal wear-leveling. The SAC may handle garbage collection of the physical pages within the PSDs it is managing, while the SMW may maintain the actual page-level tables. | 2015-07-30 |
20150212938 | GARBAGE COLLECTION AND DATA RELOCATION FOR DATA STORAGE SYSTEM - Managing data in a data storage system including at least one Data Storage Device (DSD) and a host. An initial location is determined for data to be stored in the at least one DSD based on at least one attribute defined by the host. A source portion is identified from a plurality of source portions in the at least one DSD for a garbage collection operation based on the at least one attribute defined by the host. A destination portion is identified in the at least one DSD for storing data resulting from the garbage collection operation based on the at least one attribute defined by the host. Garbage collection of the data in the source portion is performed into the destination portion, and after completion of garbage collection, the source portion is designated as a new destination portion for a new garbage collection operation. | 2015-07-30 |
20150212939 | ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD THEREFOR - An arithmetic processing apparatus has OS arithmetic processing unit executing instruction of OS, general-purpose arithmetic processing units each executing an instruction other than OS, a shared cache unit including a shared cache memory, a cache control unit and a request selection circuit which selects a memory access request from the arithmetic processing units, and a data buffer temporarily storing data of the memory access request, and a memory access control unit controlling a memory access to a main memory. The shared cache unit has a memory access band control register to which either one or both of a first set value, which includes an entry criterion for the request selection circuit to enter the memory access request from OS arithmetic processing unit, and a second set value which sets a capacity of a storage area in the data buffer for storing the data are set. | 2015-07-30 |
20150212940 | Identifying Performance Limiting Internode Data Sharing on NUMA Platforms - Methods, systems, and computer program products for identifying performance limiting internode data sharing on Non-Uniform Memory Access (NUMA) platforms are provided. A computer-implemented method may include receiving event records collected by a performance monitoring unit (PMU) during event tracing, associating the event records with corresponding operating system information observed during the event tracing, analyzing the event records to identify shared cache line utilization, and generating a shared cache line utilization report in view of the analyzing. | 2015-07-30 |
20150212941 | MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY - Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries. | 2015-07-30 |
20150212942 | ELECTRONIC DEVICE, AND METHOD FOR ACCESSING DATA IN ELECTRONIC DEVICE - A method for accessing data in an electronic device is provided. The method includes receiving a request for the data from at least one processor by a first cache memory among a plurality of cache memories, transmitting the requested data to the at least one processor, and transmitting access-related information regarding the request to a second cache memory among the plurality of cache memories. | 2015-07-30 |
20150212943 | METHODS FOR COMBINING ACCESS HISTORY AND SEQUENTIALITY FOR INTELLIGENT PREFETCHING AND DEVICES THEREOF - A method, non-transitory computer readable medium, and device that prefetchs includes identifying a candidate data block from one of one or more immediate successor data blocks. The identified candidate data block has a historical access probability value from an initial accessed data block which is higher than a historical access probability value for each of the other immediate successor data blocks and is above a prefetch threshold value. The identifying is repeated until a next identified candidate data block has the historical access probability value below the prefetch threshold value. In the repeating, the identifying next immediate successor data blocks is from the previously identified candidate data block and the historical access probability value for each of the next immediate successor data blocks is determined from the originally accessed data block. The identified candidate data block with the historical access probability value above the prefetch threshold value is fetched. | 2015-07-30 |
20150212944 | Method and Apparatus for Pushing Memory Data - A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage. | 2015-07-30 |
20150212945 | CACHE MEMORY SYSTEM WITH SIMULTANEOUS READ-WRITE IN SINGLE CYCLE - A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read. | 2015-07-30 |
20150212946 | INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD THAT ENSURES EFFECTIVE CACHING - An information processor includes a CPU, a primary storage unit, a secondary storage unit, a cache memory, and a cache controller. The primary storage unit stores the at least one program and data. The data is used by at least one process generated by execution of the at least one program in the CPU. The secondary storage unit stores the at least one programs and the data. The secondary storage unit has a lower access speed than an access speed of the primary storage unit. The cache memory caches the data. The at least one process exchanges the data between the primary storage unit and the secondary storage unit. The cache controller controls the caching of the data based on caching necessity information, the caching necessity information being determined for each of the processes and indicating whether the caching of the data is necessary or not. | 2015-07-30 |
20150212947 | DYNAMIC CACHE ENLARGING BY COUNTING EVICTIONS - A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions. | 2015-07-30 |
20150212948 | LAZY MEMORY TRANSFORMATION IN VIRTUAL MACHINE LIVE MIGRATION - Systems and methods for lazy memory transformation in virtual machine live migration. An example method may comprise: receiving, by a computer system, a plurality of transformed memory blocks, each transformed memory block comprising one or more memory pages mapped into an address space of a virtual machine being migrated to the computer system; storing, in a memory data structure, one or more mappings, each mapping comprising a guest virtual address of a memory page and an identifier of a transformed memory block containing the memory page; responsive to detecting an access to a memory page by the virtual machine, identifying, using the memory data structure, a transformed memory block containing the memory page being accessed; and storing in a memory mapped into the address space of the virtual machine the memory page produced by performing a reverse transformation of the transformed memory block. | 2015-07-30 |
20150212949 | STORAGE CONTROL DEVICE AND STORAGE CONTROL METHOD - A storage control device capable of avoiding a decrease in performance related to accesses to a storage device from a start time of a certain time zone is provided. A schedule information storing unit | 2015-07-30 |
20150212950 | MICROCOMPUTER AND METHOD FOR CONTROLLING MEMORY ACCESS - A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state. | 2015-07-30 |
20150212951 | LOW-LATENCY, LOW-OVERHEAD HYBRID ENCRYPTION SCHEME - A hybrid encryption scheme for storing data lines in a memory includes identifying data lines determined to be frequently accessed, and encrypting the data lines using a first encryption scheme. The hybrid encryption scheme also includes encrypting data lines determined not to be frequently accessed using a second encryption scheme. | 2015-07-30 |
20150212952 | METHOD FOR THE COEXISTENCE OF SOFTWARE HAVING DIFFERENT SAFETY LEVELS IN A MULTICORE PROCESSOR SYSTEM - A method for the coexistence of software having different safety levels in a multicore processor which has at least two processor cores ( | 2015-07-30 |
20150212953 | SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING - A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams. | 2015-07-30 |
20150212954 | CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO TRANSMISSION PARAMETER - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 2015-07-30 |
20150212955 | Programmable Interrupt Routing in Multiprocessor Devices - A multiprocessor device is provided that includes a plurality of processors in which each processor of the plurality of processors includes an interrupt controller, and a symmetric interrupt crossbar having a plurality of interrupt inputs in which each interrupt input that is not reserved is coupled to a respective interrupt output of an interrupt source of a plurality of interrupt sources, and a plurality of interrupt outputs in which each interrupt output is coupled to a respective interrupt input of an interrupt controller of one of the plurality of processors, in which the symmetric interrupt crossbar is programmable to map an interrupt signal from any interrupt source of the plurality of interrupt sources coupled to the symmetric interrupt crossbar to any interrupt input of any interrupt controller coupled to the symmetric interrupt crossbar. | 2015-07-30 |
20150212956 | UPDATING VIRTUAL MACHINE MEMORY BY INTERRUPT HANDLER - Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory context on the computer system matches a memory context of the virtual machine, writing, by the interrupt handling routine, the data frame into a memory of the virtual machine. | 2015-07-30 |
20150212957 | Supply Assembly Of Imaging Device, Chip Thereon, And Method For Updating Slave Address - The present disclosure discloses a supply assembly of an imaging device, a chip thereof, and a method for updating a slave address of the supply assembly. The method comprises: receiving, by the supply assembly, an address change instruction from the imaging device, the address change instruction including the slave address of the supply assembly; and gathering, by the supply assembly, upon first monitoring an addressing instruction after detection of the address change instruction, a second slave address contained in the addressing instruction first monitored, updating the slave address of the supply assembly into the second slave address, and sending acknowledging data to the imaging device. The supply assembly and its chip according to the present disclosure can rapidly respond to the instructions from the imaging device so as to perform the address change, and manufacturing costs thereof are also reduced. | 2015-07-30 |
20150212958 | DATA TRANSMISSION APPARATUS, COMMUNICATION CONTROL METHOD, AND COMMUNICATION CONTROL PROGRAM - A data transmission apparatus includes an output unit, when outputting data on a bus, to determine whether to output the data on the bus based on a result of a communication arbitration performed with competing data to be output on the bus, using priority information attached to the data; a storage unit to have areas set, the areas having respective priorities set for the communication arbitration, and to store a group of data having the consecutive priority information attached, in the respective areas; and a distribution unit to write the data having a transmission request received, in one of the areas in the storage unit, based on the priority information attached to the data. The output unit prioritizes outputting the data on the bus, the data being stored in the one of the areas having a higher priority, among the data stored in the areas. | 2015-07-30 |
20150212959 | INTER-COMPONENT COMMUNICATION INCLUDING SLAVE COMPONENT INITIATED TRANSACTION - Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed. | 2015-07-30 |
20150212960 | SS HUB, USB 3.0 HUB, AND INFORMATION PROCESSING INSTRUMENT - The power consumption of a USB 3.0 hub is reduced, and the interconnection between the USB 3.0 hub and USB 3.0 devices is improved. On receiving a data transfer request packet, which is transferred by a DS port in a low power consumption state, from a host, an SS controller of an SS hub makes the DS port transmit an LFPS for returning a destination device of the data transfer request packet to U0 state, and transmits a transfer enable packet, which is generated by the SS controller itself and shows that the destination device has become ready to correspond to the data transfer, to the host after transmitting a transfer deferment packet to the host. The SS controller does not execute a process that is specified in USB 3.0, and in which a transfer deferment packet is transmitted to the destination device after the DS port return to U0 state. | 2015-07-30 |
20150212961 | USB SERVER - A USB server includes a casing, a motherboard, a PCIe switch host card, a USB to PCIe control card, and a connecting cable. The PCIe control card is inserted on the motherboard and includes a first PCIe bus connecting port. The USB to PCIe control card includes a second PCIe bus connecting port and a plurality of USB receptacle ports. The connecting cable is connected between the first PCIe bus connecting port and the second PCIe bus connecting port, and the USB receptacle ports are located on a front side of the casing. | 2015-07-30 |
20150212962 | Servo Drive Device - A device is provided in which messages are received from a backplane through backplane connectors. Switching circuitry identifies which messages received from the backplane are intended for the operational circuitry of the device and interprets the input/output protocol of such messages while returning messages not intended for the operational circuitry to the backplane. The switching circuitry is removable from the device independently of the backplane connectors, allowing it to be changed for use with different backplane protocols without affecting other device elements. | 2015-07-30 |
20150212963 | Connecting Apparatus and System - Embodiments of the present invention provide a connecting apparatus and a system. The connecting apparatus includes N interconnection units, M line processing units, and X switch processing units, where each interconnection unit is connected to at least one switch processing unit, each switch processing unit is connected to only one interconnection unit, each interconnection unit is connected to the M line processing units, each line processing unit is connected to the N interconnection units, M is a positive integer, N is a positive integer, and X is greater than or equal to N. In addition, the embodiments of the present invention further provide another connecting apparatus and system. According to the foregoing technical solutions, a connecting mode between an LPU and an SPU is relatively flexible. | 2015-07-30 |
20150212964 | HIGH PERFORMANCE COMPUTING (HPC) NODE HAVING A PLURALITY OF SWITCH COUPLED PROCESSORS - A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard. | 2015-07-30 |
20150212965 | COMBINATION OF BUSES FOR A HAZARD MANAGEMENT SYSTEM, HAZARD MANAGEMENT SYSTEM, AND METHOD OF OPERATING THE HAZARD MANAGEMENT SYSTEM - A hazard management system is provided with a field bus and a broadband bus. The field bus is configured to connect at least two units of the hazard management system for sending alarm signals among the units of a hazard management system. The broadband bus, which is separate from the field bus, is configured to connect at least two units of a hazard management system, so that these units may exchange data through the broadband bus. The broadband bus is configured to stream audio and/or video data from one unit to other units or to deploy software updates among the units of the hazard management system. | 2015-07-30 |
20150212966 | CROSS-OVER AND BYPASS CONFIGURATIONS FOR HIGH-SPEED DATA TRANSMISSION - Circuits, methods, and apparatus that may improve networking techniques for transferring data among various electronic devices. One example may provide sharing data among various devices by daisy-chaining devices together. That is, several devices may be connected to each other through a series of cables to form a chain of devices. In this physical configuration, data may be shared among multiple devices using a series of single-hop virtual tunnels. Alternatively, a number of tunnels may be formed by a host device, each having a target device in the daisy chain. Each tunnel may originate at the host device and terminate at their target device. Each tunnel may bypass devices between the host device and the tunnel's target device. These two techniques may also be combined. Another example may provide a method of simplifying the routing of high-speed data signals through a network topology. | 2015-07-30 |
20150212967 | Wireless Communication Adaptor And Receiver Device With Integrated Speakers - A wireless communication adaptor and receiver device (WCARD) including a communication unit, electrical connectors, an authentication module, an acoustic unit, a recording unit, and a power charging unit is provided. The communication unit wirelessly communicates with a portable electronic device (PED). The electrical connectors connect the WCARD to a docking station and/or the PED. The authentication module authenticates the PED. The acoustic unit plays media received wirelessly from the PED. The acoustic unit configured as a speaker and/or a microphone establishes a duplex communication. The recording unit, through a wired connection or a wireless connection, receives and records input data from the PED. A device management system provided on the PED remotely manages the WCARD by configuring the WCARD to connect to a wireless network, wirelessly transmitting an authentication code, media, and input data to the WCARD, and activating the power charging unit to transmit power to the PED. | 2015-07-30 |
20150212968 | CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVER PARAMETER - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 2015-07-30 |
20150212969 | CONFIGURING A REMOTE M-PHY - An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode. | 2015-07-30 |
20150212970 | SYSTEM AND METHOD FOR COMMUNICATION BETWEEN A DATA-ACQUISITION CIRCUIT AND A DATA-PROCESSING CIRCUIT - The present invention relates to a communication system coupled to a data-acquisition circuit and to a data-processing circuit, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in said shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. The present invention also relates to methods for communication between a data-acquisition circuit and a data-processing circuit. | 2015-07-30 |
20150212971 | SYSTEM AND METHOD FOR REGISTERING AN ELECTRONIC DEVICE - A system and a method for registering an electronic device are provided. An auto-enrollment status of an electronic device by an enterprise is determined based on hash information associated with an identifier for the electronic device. In a case where the auto-enrollment status of the electronic device is determined to require auto-enrollment of the electronic device by the enterprise, one or more configuration settings for the electronic device as designated by the enterprise are identified, and the electronic device is requested to adopt the one or more configuration settings as designated by the enterprise in response to providing the auto-enrollment login interface to the electronic device. | 2015-07-30 |
20150212972 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING SCAN OPERATIONS - A data processing apparatus and method are provided for executing a vector scan instruction. The data processing apparatus comprises a vector register store configured to store vector operands, and processing circuitry configured to perform operations on vector operands retrieved from said vector register store. Further, control circuitry is configured to control the processing circuitry to perform the operations required by one or more instructions, said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements and defining a scan operation to be performed on a sequence of vector elements within the vector operand. The control circuitry is responsive to the vector scan instruction to partition the N vector elements of the specified vector operand into P groups of adjacent vector elements, where P is between 2 and N/2, and to control the processing circuitry to perform a partitioned scan operation yielding the same result as the defined scan operation. The processing circuitry is configured to perform the partitioned scan operation by performing separate scan operations on those vector elements of the sequence contained within each group to produce intermediate results for each group, and to perform a computation operation to combine the intermediate results into a final result vector operand containing a sequence of result vector elements. The partitioned scan operation approach of the present invention enables a balance to be achieved between energy consumption and performance. | 2015-07-30 |
20150212973 | INTEGRATED UTILITY BASED DATA PROCESSING METHODS - A method for processing integrated utility based data includes: obtaining a first integrated utility value according to an association relationship between parameters of a cloud-based media task request and attribute parameters of current cloud-based media resources; allocating the cloud-based media resources according to the first integrated utility value; wherein the association relationship is obtained by calculating: U=ω | 2015-07-30 |
20150212974 | FAST AND AUTOMATED ARIMA MODEL INITIALIZATION - The present disclosure relates generally to the field of ARIMA model initialization (e.g., fast and automated ARIMA model initialization). The ARIMA model initialization may be implemented in the form of systems, methods and/or algorithms. The process of one example begins by first trying to find a pure auto-regressive only model for the time-series data, then a pure moving-average only model and finally a mixed-model. At each step, if a model is found, the process exits, thus enabling a fast and automated initialization procedure. | 2015-07-30 |
20150212975 | ENERGY EFFICIENCY EVALUATION SUPPORT DEVICE, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM STORING COMPUTER PROGRAM, AND METHOD FOR SUPPORTING ENERGY EFFICIENCY EVALUATION - An energy efficiency evaluation support device according to one aspect of the present invention includes a data collector configured to collect actual values of an energy consumption index to be evaluated and actual values of at least one relevant variable and an evaluation display image generator configured to generate a display image for evaluating energy efficiency. The display image includes one axis for the actual values of the energy consumption index and the other axis for model calculated values of the energy consumption index. The model calculated values are calculated from the actual values of the at least one relevant variable using a model representing a correlation between the energy consumption index and the at least one relevant variable. | 2015-07-30 |
20150212976 | SYSTEM AND METHOD FOR RULE BASED CLASSIFICATION OF A TEXT FRAGMENT - A method for classifying a text fragment by applying one or more rule functions is provided. The method includes (i) obtaining a set of words from one or more sentences of the text fragment obtained from a multimedia content, (ii) mapping each word from the set of words with one or more category map tables to obtain a set of candidate vector, each candidate vector includes at least one category associated with each word, (iii) generating one or more category vectors based on the at least one category, (iv) applying rule functions on the one or more category vectors, (v) generating a candidate classification decision matrix based on the rule functions, and (vi) classifying the text fragment based on the candidate classification decision matrix. The candidate classification matrix includes results of each rule function applied on each of the category vector. | 2015-07-30 |