30th week of 2021 patent applcation highlights part 62 |
Patent application number | Title | Published |
20210233858 | APPARATUSES INCLUDING CONDUCTIVE STRUCTURE LAYOUTS - Embodiments of the disclosure are drawn to arrangements of one or more “cuts” or pattern of cuts in conductive structures. Wiring layers may each include a cut pattern including a set of cuts through conductive structures of the wiring layers where each of the cuts is offset from the other in a direction orthogonal to the cut. The cut pattern in a wiring layer may be orthogonal to the cut pattern in another wiring layer. In some examples, the cut pattern may be a stair-step pattern. In some examples, the cut pattern may be interrupted by other conductive structures. | 2021-07-29 |
20210233859 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug. | 2021-07-29 |
20210233860 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal. | 2021-07-29 |
20210233861 | Liner-Free Conductive Structures with Anchor Points - The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric. | 2021-07-29 |
20210233862 | SEMICONDUCTOR DEVICE - A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics. | 2021-07-29 |
20210233863 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area and in a material layer through a first mask. Second features are formed in a second product region of each die area and in the material layer through a second mask. Third features are formed in a third product region of each die area and in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area and in the material layer through a fourth mask. Fifth features are formed in an alignment region between the first, second, third and fourth product regions of each die area and in the material layer through the first, second, third and fourth masks. The first product region is free of the second, third, and fourth features. | 2021-07-29 |
20210233864 | SEMICONDUCTOR DEVICE WITH OXIDE-NITRIDE STACK - A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight. | 2021-07-29 |
20210233865 | MICROWAVE DEVICE AND ANTENNA - A microwave device includes: a first multilayer resin substrate including a ground via hole; a semiconductor substrate provided at the first multilayer resin substrate and including a high frequency circuit; and a conductive heat spreader provided at an opposite face of the semiconductor substrate from a face of the semiconductor substrate facing the first multilayer resin substrate. The microwave device includes: a resin provided over the first multilayer resin substrate and covering the semiconductor substrate and the heat spreader such that an opposite face of the heat spreader from a face of the heat spreader facing the semiconductor substrate is exposed as an exposed face; and a conductive film covering the resin and the heat spreader and touching the exposed face. The semiconductor substrate includes a ground through hole extending through the semiconductor substrate. The conductive film is electrically connected to the ground via hole via the heat spreader and the ground through hole. | 2021-07-29 |
20210233866 | Controlled Induced Warping of Electronic Substrates - An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via thin film deposition (TFD) instrumentation and techniques in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree. | 2021-07-29 |
20210233867 | KEEP OUT ZONE WITH HYDROPHOBIC SURFACE FOR INTEGRATED CIRCUIT (IC) PACKAGE - Embodiments herein describe techniques for an IC package including a supporting layer having a first zone and a second zone. An electronic component is placed above the first zone of the supporting layer. An underfill material is formed above the first zone of the supporting layer, around or below the electronic component to support the electronic component. The second zone of the supporting layer includes a base area and multiple micro-pillars above the base area, where any two micro-pillars of the multiple micro-pillars are separated by a gap in between. The second zone has a hydrophobic surface including surfaces of the multiple micro-pillars and surfaces of the base area. The second zone is a keep out zone to prevent the underfill material from entering the second zone. Other embodiments may be described and/or claimed. | 2021-07-29 |
20210233868 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package and method of manufacturing the same are provided. The semiconductor device package includes a substrate, a semiconductor die and a first encapsulant. The substrate includes a first surface, a second surface opposite to the first surface, and a first edge and a second edge connecting the first surface to the second surface. The first edge is shorter than the second edge. The semiconductor die is disposed on the first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate and encapsulates the semiconductor die. The first encapsulant includes at least one first lock portion extending from the first surface to the second surface and penetrating through the substrate via the first edge. | 2021-07-29 |
20210233869 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having an electrode, material of which is first metal, a lead frame through which a plurality of holes extend with an outer contour of the electrode being avoided in a first portion, and having the first portion, material of which is second metal, a bonding layer interposed between the first portion and the electrode, and solder being inside the plurality of holes and adjoining the bonding layer, the solder being thicker than the bonding layer. The plurality of holes have a plurality of first holes extending through the first portion in a thickness direction of the first portion. The bonding layer has a first bonding layer located on the electrode side and being an alloy of the first metal and tin, and a second bonding layer located on the first portion side and being an alloy of the second metal and tin. The plurality of first holes are located in an annular region inside the outer contour of the electrode. | 2021-07-29 |
20210233870 | VERTICAL MEMORY DEVICES - A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer. | 2021-07-29 |
20210233871 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink. | 2021-07-29 |
20210233872 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms. | 2021-07-29 |
20210233873 | SEMICONDUCTOR DEVICE - An oxide film ( | 2021-07-29 |
20210233874 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, INTEGRATED SUBSTRATE, AND ELECTRONIC DEVICE - The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, an integrated substrate, and an electronic device capable of improving moisture resistance of the semiconductor device. The semiconductor device includes a semiconductor chip and a protective member which is a transparent member having moisture resistance and covers at least one of a first surface perpendicular to a side surface of the semiconductor chip or a second surface opposite to the first surface and the side surfaces. The electronic device includes the semiconductor device and the signal processing unit. The present technology is applied to, for example, an imaging element and an electronic device including an imaging element. | 2021-07-29 |
20210233875 | CAPACITOR LOOP STRUCTURE - A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package. | 2021-07-29 |
20210233876 | MODULE AND ELECTRONIC APPARATUS - A module of an embodiment of the present disclosure includes a first substrate including a first wiring pattern and a second substrate having a second wiring pattern with a wiring density different from that of the first wiring pattern, in which the second substrate is bonded to the first substrate. At least one of the first substrate or the second substrate has visible light transmittance. | 2021-07-29 |
20210233877 | PACKAGE WITH DIFFERENT TYPES OF SEMICONDUCTOR DIES ATTACHED TO A FLANGE - A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described. | 2021-07-29 |
20210233878 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness. | 2021-07-29 |
20210233879 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness. | 2021-07-29 |
20210233880 | SEMICONDUCTOR DEVICES INCLUDING ARRAY POWER PADS, AND ASSOCIATED SEMICONDUCTOR DEVICE PACKAGES AND SYSTEMS - Semiconductor devices are disclosed. According to some embodiments, a semiconductor device may include a memory array area and a peripheral area. The memory array area may include a number of memory cells and a number of array pads configured to receive an input voltage. The peripheral area may include a number of peripheral pads for interfacing with the memory array area. In these or other embodiments, the peripheral area may be arranged adjacent to a first edge of the semiconductor device and the number of array pads may be arranged proximate to a second edge of the semiconductor device. The second edge may be perpendicular to the first edge. The memory array area may also include an array distribution conductor configured to variously electrically connect the number of memory cells to the number of array pads. A semiconductor-device package and system are also disclosed. | 2021-07-29 |
20210233881 | BONDED ASSEMBLY CONTAINING METAL-ORGANIC FRAMEWORK BONDING DIELECTRIC AND METHODS OF FORMING THE SAME - A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices and bonded to a respective one of the first bonding pads, and at least one metal-oxide framework (MOF) dielectric layer that laterally surrounds at least one of the first bonding pads and the second bonding pads. | 2021-07-29 |
20210233882 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. | 2021-07-29 |
20210233883 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region. | 2021-07-29 |
20210233884 | METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD - A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material. | 2021-07-29 |
20210233885 | SEMICONDUCTOR DEVICE AND LEAD FRAME MEMBER - A semiconductor device includes: an inner substrate on which a semiconductor chip is mounted, and has a surface on which terminals including electric path terminals are formed; a lead frame which has a chip connecting electrode portion which is electrically connected to a surface of the semiconductor chip via a conductive bonding member, substrate connecting electrode portions which are electrically connected to the electric path terminals of the inner substrate, and horizontal surface support portions which bulge to the outside from the chip connecting electrode portion or the substrate connecting electrode portions; and pin terminals which are mounted upright over the inner substrate in a direction perpendicular to flat surfaces of the substrate connecting electrode portions of the lead frame, wherein the horizontal surface support portions bulge to the outside of the inner substrate. | 2021-07-29 |
20210233886 | SEMICONDUCTOR DEVICE - A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed. | 2021-07-29 |
20210233887 | THERMOCOMPRESSION BOND TIPS AND RELATED APPARATUS AND METHODS - A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed. | 2021-07-29 |
20210233888 | DIE PROCESSING - Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously. | 2021-07-29 |
20210233889 | DBI TO SI BONDING FOR SIMPLIFIED HANDLE WAFER - Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components. | 2021-07-29 |
20210233890 | PACKAGING STRUCTURES - Packaging structure includes a substrate; a bonding layer on the substrate; and an improvement layer on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are located in the openings. The chips include functional surfaces that bond to the bonding layer, and top surfaces of the chips are lower than or flush with a top surface of the improvement layer. Another packaging structure includes chips and an improvement layer. The chips are interspersed in the improvement layer. Each chip includes a functional surface coplanar with a first surface of the improvement layer, and another surface lower than or flush with a second surface of the improvement layer. A gap is formed between each sidewall of the chips and the improvement layer. An encapsulation layer is formed in the gap between each chip and the improvement layer. | 2021-07-29 |
20210233891 | SEMICONDUCTOR PACKAGES INCLUDING CHIPS STACKED ON A BASE MODULE - A semiconductor package includes a package substrate, a base module disposed on the package substrate and configured to include an intermediate chip, bonding wires connecting the intermediate chip to the package substrate, a lower-left chip disposed between the base module and the package substrate, and an upper-left chip disposed on the base module. The base module further includes an encapsulant encapsulating the intermediate chip, through vias electrically connected to the upper-left chip, and redistributed lines (RDLs) connecting the intermediate chip to the through vias and extending to provide connection parts which are spaced apart from the through vias and are connected to the lower-left chip. | 2021-07-29 |
20210233892 | Mixed Under Bump Metallurgy (UBM) Interconnect Bridge Structure - An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads. | 2021-07-29 |
20210233893 | FACE-TO-FACE DIES WITH ENHANCED POWER DELIVERY USING EXTENDED TSVS - A TSV of a first semiconductor die may extend from a semiconductor substrate of the first semiconductor die through at least one metallization layer of the die to connect to a metallization layer to supply power to the second semiconductor die. By extending the TSV, resistance may be reduced, allowing for enhanced power delivery to the second semiconductor die. Resistance may be further reduced by allowing for the TSV to connect to a thicker metallization layer than would otherwise be possible. Also, in some embodiments, the TSV may connect to a metallization layer that is suitable for supplying power to both semiconductor dies. The first semiconductor die may be a top die or a bottom die in a face-to-face arrangement. Disclosed concepts may be extended to any number of dies included in a die stack that includes the face-to-face arrangement. | 2021-07-29 |
20210233894 | THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS - Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure. | 2021-07-29 |
20210233895 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other. When a distance between the first conductive layer and the second conductive layer in the first direction is a first distance, a distance between the third conductive layer and the fourth conductive layer in the first direction is a second distance, and a distance between the fifth conductive layer and the sixth conductive layer in the first direction is a third distance, the second distance is smaller than the first distance, and the third distance is smaller than the second distance. | 2021-07-29 |
20210233896 | REDUCING LOSS IN STACKED QUANTUM DEVICES - A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element. | 2021-07-29 |
20210233897 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package. | 2021-07-29 |
20210233898 | IMAGE DISPLAY DEVICE - An image display device according to the present disclosure includes: a display panel; a frame unit; and a driver. The display panel is switchable between an image display mode in which an image is displayed and a transmissive mode in which the display panel is in a transmissive state where an object behind the display panel is visible in a front view of the display panel. The frame unit includes an upper plate disposed along an upper edge of the display panel and protruding rearward. The driver includes a circuit unit which drives the display panel. The driver is supported by the upper plate on a bottom side of the upper plate. | 2021-07-29 |
20210233899 | DISPLAY PANEL, MANUFACTURING METHOD OF SAME, AND TILED DISPLAY PANEL - A display panel comprises a plurality of light-emitting components, an array substrate, and a driver chip. The array substrate comprises: a base substrate; a plurality of signal lines disposed on a first surface of the base substrate; and a fanout circuit disposed on a second surface of the base substrate; the driver chip is disposed on a second surface side, and is electrically connected to the fanout circuit; a plurality of openings are provided on the array substrate, the plurality of openings are located on an edge of the array substrate and penetrate the array substrate, the array substrate comprises a plurality of electrical connection parts, and the plurality of electrical connection parts are electrically connected to the plurality of signal lines and the fanout circuit. | 2021-07-29 |
20210233900 | BONDED ASSEMBLY WITH VERTICAL POWER AND CONTROL SIGNAL CONNECTION ADJACENT TO SENSE AMPLIFIER REGIONS AND METHODS OF FORMING THE SAME - A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region. | 2021-07-29 |
20210233901 | METHOD TO CONSTRUCT 3D DEVICES AND SYSTEMS - A method to construct a 3D system, the method including: providing a base wafer; and then transferring a memory control on top; and then thinning the memory control, transferring a first memory wafer on top; and then thinning the first memory wafer; and then transferring a second memory wafer on top; and then thinning the second memory wafer. A 3D device, the device including: a first stratum including first bit-cell memory arrays; a second stratum including second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the first stratum overlays the third stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays. | 2021-07-29 |
20210233902 | SEMICONDUCTOR CHIP - A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row. | 2021-07-29 |
20210233903 | Integrated Fluxgate Device - An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers. | 2021-07-29 |
20210233904 | DECOUPLING CAPACITOR - A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates. | 2021-07-29 |
20210233905 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device. | 2021-07-29 |
20210233906 | ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES - A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures. | 2021-07-29 |
20210233907 | FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap. | 2021-07-29 |
20210233908 | THROUGH GATE FIN ISOLATION - Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes. | 2021-07-29 |
20210233909 | FLEXIBLE GAA NANOSHEET HEIGHT AND CHANNEL MATERIALS - Certain aspects of the present disclosure relate to a gate-all-around (GAA) semiconductor device. One example GAA semiconductor device includes a plurality of nanosheet stack structures disposed vertically above a horizontal plane of a substrate, wherein: each nanosheet stack structure of the plurality of nanosheet stack structures comprises one or more nanosheets; the one or more nanosheets of a first nanosheet stack structure of the plurality of nanosheet stack structures comprise a first semiconductor material; and the one or more nanosheets of a second nanosheet stack structure of the plurality of nanosheet stack structures comprise a second semiconductor material different from the first semiconductor material. | 2021-07-29 |
20210233910 | NANOSHEET DEVICE INTEGRATED WITH A FINFET TRANSISTOR - A semiconductor device includes a nanosheet device and a gate-all-around FIN-shaped (GAA-FIN) device. The nanosheet device includes n- and p-type field effect transistor (nFET and pFET) sections, each of which includes nanosheet stacks and work function metal (WFM). Each nanosheet stack includes lowermost and uppermost spacers, intermediate semiconductor layers and dielectric material surrounding the lowermost and uppermost spacers and the intermediate semiconductor layers. The WFM surrounds the nanosheet stacks and entirely fills suspension regions thereof. The GAA-FIN device includes nFET and pFET sections, each of which includes fin elements and WFM. Each fin element includes a lower spacer, a secondary intermediate layer of semiconductor material and dielectric material surrounding the lower spacer and the secondary intermediate layer of semiconductor material. The WFM surrounds each of the fin elements. A thickness of the WFM entirely filling the suspension regions exceeds a thickness of the WFM of the fin elements. | 2021-07-29 |
20210233911 | GATE-ALL-AROUND DEVICES WITH REDUCED PARASITIC CAPACITANCE - Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure. | 2021-07-29 |
20210233912 | Multi-Layer Thyristor Random Access Memory with Silicon-Germanium Bases - A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described. | 2021-07-29 |
20210233913 | DRAM WITH SELECTIVE EPITAXIAL CELL TRANSISTOR - A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer. | 2021-07-29 |
20210233914 | Integrated Transistors and Methods of Forming Integrated Transistors - Some embodiments include an integrated device having a first transistor gate over a first region of a semiconductor base, and having a second transistor gate over a second region of the semiconductor base. First sidewall spacers are along sidewalls of the first transistor gate. The first sidewall spacers include SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry. The first sidewall spacers have a first thickness. Second sidewall spacers are along sidewalls of the second transistor gate. The second sidewall spacers have a second thickness which is less than the first thickness. First source/drain regions are within the semiconductor base and are operatively proximate the first transistor gate. Second source/drain regions are within the semiconductor base and are operatively proximate the second transistor gate. Some embodiments include methods of forming integrated devices. | 2021-07-29 |
20210233915 | SEMICONDUCTOR STRUCTURE - Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. Height of the second via is greater than height of the first via. The local interconnect line and the bit line are formed in the same metal layer. The bit line is thicker than the local interconnect line. | 2021-07-29 |
20210233916 | BONDED SEMICONDUCTOR DEVICES HAVING PROCESSOR AND NAND FLASH MEMORY AND METHODS FOR FORMING THE SAME - First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures. | 2021-07-29 |
20210233917 | 3D VERTICAL NAND MEMORY DEVICE INCLUDING MULTIPLE SELECT LINES AND CONTROL LINES HAVING DIFFERENT VERTICAL SPACING - Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a pillar including a length, a memory cell string and control lines located along a first segment of the pillar, and select lines located along a second segment of the pillar. The control lines include at least a first control line and a second control line. The first control line is adjacent the second control line. The first control line is separated from the second control line by a first distance in a direction of the length of the pillar. The select lines include at least a first select line and a second select line. The first select line is separated from the second select line by a second distance in the direction of the length of the pillar. The second distance is less than the first distance. | 2021-07-29 |
20210233918 | METHODS AND APPARATUS FOR THREE DIMENSIONAL NAND STRUCTURE FABRICATION - Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces. | 2021-07-29 |
20210233919 | EMBEDDED FERROELECTRIC MEMORY IN HIGH-K FIRST TECHNOLOGY - In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material. | 2021-07-29 |
20210233920 | Integrated Circuit Constructions Comprising Memory And Methods Used In The Formation Of Integrated Circuitry Comprising Memory - An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed. | 2021-07-29 |
20210233921 | Embedded Flash Memory Device with Floating Gate Embedded in a Substrate - An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack. | 2021-07-29 |
20210233922 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies. | 2021-07-29 |
20210233923 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region. | 2021-07-29 |
20210233924 | SEMICONDUCTOR DEVICE WITH INTEGRATED MEMORY DEVICES AND MOS DEVICES AND PROCESS OF MAKING THE SAME - A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level. | 2021-07-29 |
20210233925 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor storage device includes a substrate; a stacked body provided above the substrate, wherein the stacked body includes a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked on top of one another along a vertical direction; a plurality of columnar portions that penetrate the stacked body; a first slit, provided in the vertical direction, that divides one or more of the plurality of conductive layers at least at an upper portion of the stacked body; and a second insulating layer that overlays an opening of the first slit, which forms a cavity. | 2021-07-29 |
20210233926 | 3-Dimensional NOR Strings with Segmented Shared Source Regions - A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively. | 2021-07-29 |
20210233927 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region. The 3D memory device further includes a plurality of second doped regions in the substrate and separated by the insulating structure. | 2021-07-29 |
20210233928 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING WORD LINE INCLUDING POLYSILICON AND METAL - A 3D memory device and a method of manufacturing the same, the device including a substrate including a cell and an extension region; a cell stack including insulation layers and word lines alternately stacked on the substrate; channel structures vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction; a contact plug vertically connected to the word lines on the extension region; and a bit line extending lengthwise in a second direction on the channel structures, wherein each of the word lines includes an inner pattern including polysilicon; and an outer pattern including metal, the outer pattern surrounds an outer surface of the inner pattern, the channel structures vertically pass through the inner pattern, and the contact plug is on the outer pattern. | 2021-07-29 |
20210233929 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING SAME - A nonvolatile memory device and method of fabricating same are provided. The nonvolatile memory device includes; a substrate, a first semiconductor layer on the substrate, an etching stop film including a metal oxide on the first semiconductor layer, a mold structure on which a second semiconductor layer and an insulating layer are alternately stacked on the etching stop film, a channel hole which penetrates through at least one of the mold structure, the etching stop film, the second semiconductor layer and the substrate, and a channel structure which extends along a side wall of the channel hole, and includes an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film and a channel semiconductor which are sequentially formed along the side wall of the channel hole, wherein the first semiconductor layer contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film. | 2021-07-29 |
20210233930 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer. | 2021-07-29 |
20210233931 | Flash Memory Structure and Method of Forming the Same - Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium. | 2021-07-29 |
20210233932 | INTERCONNECT STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES - Channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers is formed above a substrate. A local dielectric layer is formed on the dielectric stack. A slit opening extending vertically through the local dielectric layer and the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first source contact portion is formed in the slit opening. A channel local contact opening through the local dielectric layer to expose the channel structure, and a staircase local contact opening through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack are simultaneously formed. A channel local contact in the channel local contact opening, a second source contact portion above the first source contact portion in the slit opening, and a staircase local contact in the staircase local contact opening are simultaneously formed. | 2021-07-29 |
20210233933 | Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies - Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies. | 2021-07-29 |
20210233934 | IC PRODUCTS FORMED ON A SUBSTRATE HAVING LOCALIZED REGIONS OF HIGH RESISTIVITY AND METHODS OF MAKING SUCH IC PRODUCTS - One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer. | 2021-07-29 |
20210233935 | SEMICONDUCTOR DEVICE - Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy. A semiconductor device includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor paired with the first MOS transistor, and insulation separation walls which insulate and separate elements from each other, wherein relative characteristics of the first MOS transistor and the second MOS transistor are in a predetermined range, the first MOS transistor and the second MOS transistor are relatively arranged in a gate width direction or a gate length direction, and distances between gate oxide films of the first MOS transistor and the second MOS transistor and the insulation separation walls facing the gate oxide films are the same as each other in a direction perpendicular to the gate width direction or the gate length direction. | 2021-07-29 |
20210233936 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device are disclosed. The array substrate includes: a base substrate; and a first electrically conductive layer and a second electrically conductive layer on the base substrate, wherein the base substrate is provided with at least one TFT, each of the at least one TFT includes a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer, and wherein the drain electrode has a comb shape and includes a plurality of drain electrode sub-portions extending parallel to one another, and the source electrode has a comb shape and includes a plurality of source electrode sub-portions extending parallel to one another, and wherein at least one of the drain electrode and the source electrode includes an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode. | 2021-07-29 |
20210233937 | TRANSISTOR STRUCTURE, DISPLAY DEVICE INCLUDING TRANSISTOR STRUCTURE, AND METHOD OF MANUFACTURING TRANSISTOR STRUCTURE - A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate. | 2021-07-29 |
20210233938 | DISPLAY PANEL AND DISPLAY DEVICE - The present invention discloses a display panel and a display device. By adding a stress adjustment layer having a plurality of patterned structures spaced apart from each other, the stress neutral surface can be effectively adjusted, and the stress of the metal trace is reduced when it is bent, to avoid or mitigate excessive stress causing generation and expansion of cracks in the stress adjustment layer, thereby reducing the probability of breakage of the metal trace when the flexible display is bent, thus reducing the risk of failure of the metal trace. | 2021-07-29 |
20210233939 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, AND MASK - An array substrate, a manufacturing method thereof, a display device, and a mask are provided. The array substrate includes a base substrate; a first conductive layer located on the base substrate; and an organic layer located on a side of the first conductive layer away from the base substrate, the peripheral region includes at least one bonding region in each bonding region, the first conductive layer includes multiple wires arranged at intervals, the organic layer includes a first opening exposing the wires, the first opening includes an edge intersected with an extension direction of each wires, and the organic layer further includes a zigzag-shaped groove connected with the edge; in a direction perpendicular to the base substrate, a depth of the zigzag-shaped groove is less than a thickness of the organic layer, an orthographic projection of the zigzag-shaped groove on a plane parallel with the base substrate is zigzag-shaped. | 2021-07-29 |
20210233940 | CIRCUIT BACKPLANE OF DISPLAY PANEL, METHOD FOR MANUFACTURING THE CIRCUIT BACKPLANE, AND DISPLAY PANEL - A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode. | 2021-07-29 |
20210233941 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - In a method for manufacturing an array substrate, a first photoresist pattern is formed on a buffer layer of a non-display region and the buffer layer uncovered by the first photoresist pattern is removed to form a first via hole in the non-display region. A second via hole is formed on the basis of the first via hole. The second via hole is connected to the first via hole. By forming the first via hole in the non-display region and forming the second via hole on the basis of the first via hole, completeness of film layers is ensured and product yield is improved. | 2021-07-29 |
20210233942 | ARRAY SUBSTRATE, MANUFACTURING METHOD AND DISPLAY THEREOF - An array substrate, a manufacturing method and a display panel thereof are provided. A single mask process is used for completing formation of a flat layer and a pixel definition layer, or the flat layer, the pixel definition layer and a spacer. A light emitting unit is located within an anode so that the light of the emitting unit is reflected by the anode to accumulate. The risk of color mixing on the display panel is reduced, and the light intensity on the light exit side is enhanced. | 2021-07-29 |
20210233943 | MANUFACTURE METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE, AND DISPLAY PANEL - Disclosed is a manufacture method of the array substrate, including: sequentially forming a gate, a gate insulating layer, an active layer, an ohmic contact layer and a metal layer on a substrate, forming a photoetching mask on the metal layer, where thickness of the photoetching mask in a half exposure area of the mask plate is from 2000 Å to 6000 Å; etching the metal layer, the ohmic contact layer and the active layer outside a covering area of the photoetching mask; ashing the photoetching mask for a preset time with an ashing reactant, wherein the ashing reactant comprises oxygen, and the preset time is from 70 seconds to 100 seconds; and sequentially etching the metal layer, the ohmic contact layer and the active layer based on the ashed photoetching mask, and forming a channel region of the array substrate. The present disclosure further discloses an array substrate, and a display panel. | 2021-07-29 |
20210233944 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second, insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film. | 2021-07-29 |
20210233945 | BSI Image Sensor and Method of Forming Same - A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate. | 2021-07-29 |
20210233946 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS - The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor. | 2021-07-29 |
20210233947 | LIGHT ATTENUATION LAYER FABRICATION METHOD AND STRUCTURE FOR IMAGE SENSOR - An image sensor includes a substrate having a plurality of small photodiodes and a plurality of large photodiodes surrounding the small photodiodes. The substrate further includes a plurality of deep trench isolation structures in regions of the substrate between ones of the small photodiodes and the large photodiodes. Each of large photodiodes having a full well capacity larger than each of the small photodiodes. The image sensor further includes an array of color filters disposed over the substrate, a first and second buffer layer disposed between the substrate and the array of color filters, metal grid structures disposed between the color filters and above the first buffer layer, and an attenuation layer portion above a region of the substrate between ones of the large and small photodiodes, the attenuation layer portion is between the first and second buffer layers and normal to an upper surface of the substrate. | 2021-07-29 |
20210233948 | SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD THEREOF - A solid-state imaging element with pixel transistors and wires capable of efficiently outputting and transferring a pixel signal from a stacked photoelectric conversion film while suppressing an increase in manufacturing cost, and a manufacturing method thereof are provided. There is provided a solid-state imaging element which includes a semiconductor substrate; a first photoelectric conversion unit provided on the semiconductor substrate; and a control unit provided stacked with the first photoelectric conversion unit and including a plurality of pixel transistors, in which the first photoelectric conversion unit includes a second electrode, a first photoelectric conversion film provided above the second electrode and converting light into charges, and a first electrode provided on the first photoelectric conversion film, the plurality of pixel transistors include an amplification transistor that amplifies and outputs the charges as a pixel signal, and a channel formation region of the amplification transistor made of an oxide semiconductor layer. | 2021-07-29 |
20210233949 | SEMICONDUCTOR DEVICE, IMAGING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Deformation of a semiconductor chip is to be prevented in a semiconductor device in which a heat releasing plate and a circuit board are disposed. The semiconductor device includes the semiconductor chip, the circuit board, the heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening. | 2021-07-29 |
20210233950 | IMAGING DEVICE INCLUDING SHARED PIXELS AND OPERATING METHOD THEREOF - An operating method of an imaging device comprising a plurality of shared pixels that share a floating diffusion node and each comprising sub-pixels covered by a micro-lens. The method involves generating a capture image from the plurality of shared pixels that receive light reflected from an object; compensating for the capture image using static phase information based on misalignment of the micro lens of each of the plurality of shared pixels; performing auto exposure control based on the compensation of the capture image; performing auto focus control based on the compensated capture image; and generating an output image by processing the compensated capture image. | 2021-07-29 |
20210233951 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE - A solid-state imaging device including: a plurality of pixels; and microlenses. Each of the pixels includes a photoelectric converter. The plurality of pixels is disposed along a first direction and a second direction. The microlenses are provided for respective pixels on light incident sides of the photoelectric converters. The microlenses include lens sections and an inorganic film. The lens sections each have a lens shape and are in contact with each other between the pixels adjacent in the first direction and the second direction. The inorganic film covers the lens sections. The microlenses each include first concave portions between the pixels adjacent in the first direction and the second direction, and second concave portions provided between the pixels adjacent in a third direction. The second concave portions are closer to the photoelectric converter than the first concave portions. | 2021-07-29 |
20210233952 | Semiconductor Device and Electronic Device - A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided. | 2021-07-29 |
20210233953 | IMAGE SENSOR, METHOD FOR OBTAINING IMAGE DATA FROM IMAGE SENSOR, AND CAMERA DEVICE - This application discloses an image sensor, which includes a color film layer. The color film layer includes a plurality of color film units, the color film unit includes at least one color-determined subunit and at least three transparent subunits, and a color of the color-determined subunit is determined. The color-determined subunit is configured to filter out a portion of the received light, and the transparent subunit is configured to allow light to pass through. A ratio of a quantity of the at least one color-determined subunit to a quantity of the plurality of subunits is less than 1/2. Because the transparent subunit can allow light to pass through, and most of light incident to the color film layer can be received by a photodiode, light sensitivity of the image sensor can be effectively increased without increasing an area of the color film layer or increasing a size of the photodiode. | 2021-07-29 |
20210233954 | DETECTION PANEL AND MANUFACTURING METHOD THEREOF - A detection panel and a manufacturing method thereof are disclosed. The detection panel ( | 2021-07-29 |
20210233955 | DISPLAY DEVICE - According to one embodiment, a display device comprises a display portion comprising a plurality of pixels. Each of the pixels comprises an anode, a cathode, and a light-emitting diode disposed between the anode and the cathode. The light-emitting diode comprises an emitting layer and a resistive layer partly overlapping the emitting layer in planar view. A width w of a region of the emitting layer which does not overlap the resistive layer and a thickness d of the light-emitting diode satisfy w/d>1. | 2021-07-29 |
20210233956 | LIGHT EMITTING DEVICE AND BACKLIGHT INCLUDING THE LIGHT EMITTING DEVICE - A light emitting device includes at least three light emitting elements arranged side by side, and one or more light transmissive members each containing a phosphor and covering the light emitting elements. The at least three light emitting elements include two outer light emitting elements arranged on outer sides, and an inner light emitting element arranged between the two outer light emitting elements and having a different peak emission wavelength than a peak emission wavelength of the two outer light emitting elements. The phosphor has a longer peak emission wavelength than the peak emission wavelengths of the outer light emitting elements and the peak emission wavelength of the inner light emitting element. The two outer light emitting elements and the inner light emitting element are connected in series. | 2021-07-29 |
20210233957 | Quantum Computing System and Method of Using Quantum Computing System - A quantum computing system including plural base configurations each configured including a first quantum bit group configured from first quantum bits arranged so as to form a single column without mutual coupling, a second quantum bit group configured from second quantum bits arranged so as to form a single column with adjacent ones of the second quantum bits coupled together and each of the second quantum bits coupled to the first quantum bit that is arranged in a same row, and a third quantum bit coupled to all of the second quantum bits. The plural base configurations are arranged so as to form a single column with the third quantum bits in adjacent ones of the base configurations coupled together. In a quantum computing circuit configuration, a two-dimensional cluster state or a three-dimensional cluster state is accordingly realized with two-dimensional control wiring, or surface code is accordingly realized with a pseudo two-dimensional superconducting circuit. | 2021-07-29 |