30th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100187537 | Thin Film Transistor Array Substrate and Method for Manufacturing the Same - A thin film transistor array structure and a method for manufacturing the same are provided. The thin film transistor array structure comprises a substrate, including a transition area and a pad area. A patterned first metal layer is formed on the substrate, wherein the patterned first metal layer includes a data connecting line disposed in the transition area, and a data pad and a gate pad disposed in the pad area. A patterned first insulation layer is formed on the patterned first metal layer. The patterned first insulation layer at least defines a first opening on the gate pad, a second opening on the data pad, and a third opening in the transition area, so as to simplify following processes to increase the yield. | 2010-07-29 |
20100187538 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material. | 2010-07-29 |
20100187539 | COMPOUND SEMICONDUCTOR EPITAXIAL WAFER AND FABRICATION METHOD THEREOF - The present invention provides a compound semiconductor epitaxial wafer and a fabrication method thereof, a first silicon buffer layer is deposited on a metal substrate, and then a second compound semiconductor buffer layer is deposited on the first silicon buffer layer, and a third compound semiconductor buffer layer is deposited on the second compound semiconductor buffer layer, and a first compound semiconductor epitaxial layer is crystallized on the third compound semiconductor buffer layer, and a first thermal treatment process is applied, and a second compound semiconductor epitaxial layer is crystallized on the first compound semiconductor epitaxial layer, and a second thermal treatment process is applied to obtain a good-quality compound semiconductor epitaxial wafer. | 2010-07-29 |
20100187540 | GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×10 | 2010-07-29 |
20100187541 | Doped Aluminum Nitride Crystals and Methods of Making Them - Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal. | 2010-07-29 |
20100187542 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor light emitting element from a wafer in which a gallium nitride compound semiconductor has been laminated on a sapphire substrate having an orientation flat, comprises of: laminating a semiconductor layer on a first main face of the sapphire substrate having an off angle θ in a direction Xo parallel to the orientation flat; forming a first break groove that extends in a direction Y substantially perpendicular to the direction Xo, on the semiconductor layer side; forming a second break line that is shifted by a predetermined distance in the ±Xo direction from a predicted split line within the first break groove and parallel to the first break groove in the interior of the sapphire substrate and corresponding to the inclination of the off angle θ; and splitting the wafer along the first and/or second break line. | 2010-07-29 |
20100187543 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND THE SILICON CARBIDE SEMICONDUCTOR DEVICE - Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof. | 2010-07-29 |
20100187544 | FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS - In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process to deposit the second diamond layer onto the first diamond layer. | 2010-07-29 |
20100187545 | SELECTIVELY DOPED SEMI-CONDUCTORS AND METHODS OF MAKING THE SAME - The present invention is generally directed to methods of selectively doping a substrate and the resulting selectively doped substrates. The methods include doping an epilayer of a substrate with the selected doping material to adjust the conductivity of either the epilayers grown over a substrate or the substrate itself. The methods utilize lithography to control the location of the doped regions on the substrate. The process steps can be repeated to form a cyclic method of selectively doping different areas of the substrate with the same or different doping materials to further adjust the properties of the resulting substrate. | 2010-07-29 |
20100187546 | VERTICAL GEOMETRY LIGHT EMITTING DIODE PACKAGE AGGREGATE AND PRODUCTION METHOD OF LIGHT EMITTING DEVICE USING THE SAME - There are provided a vertical geometry light emitting diode package aggregate useful for the production of a light emitting device having a vertical geometry light emitting diode as the light source, the light emitting device satisfying requirements in terms of current capacity flowed for light emission, dissipation of heat generated due to flow of a large current, resistance to thermal stress, strength of device and light emission efficiency, and a method for producing a light emitting device having a vertical geometry light emitting diode as the light source by using the package aggregate. The vertical geometry light emitting diode package comprises a metal sheet having formed thereon a number of vertical geometry light emitting diode package units, each package unit comprising two or more substrate portions as a part of the metal sheet, which are separated by a slit, and a reflector having a penetrating opening and being adhered to the two or more substrate portions to cover parts of the slit such that the vertical geometry light emitting diode-mounting position is exposed in the inner side of the opening and at the same time, the end part of the slit is exposed in the outer side of the reflector. | 2010-07-29 |
20100187547 | Image display apparatus - An image display apparatus displaying an image by selectively emitting light from a plurality of semiconductor light emitting elements being regularly arranged, includes a substrate; a first conductive wiring layer being formed on the substrate and supplying a first electric potential; a second conductive wiring layer supplying a second electric potential; the plurality of semiconductor light emitting elements each including a first electrode layer being electrically connected to the first conductive wiring layer and a second electrode layer being electrically connected to the second conductive wiring layer; and a plurality of raised parts being disposed on the substrate, each of the raised parts having an upper surface which is higher than an upper surface of the first conductive wiring layer; wherein the plurality of semiconductor light emitting elements is fixed on the plurality of raised parts respectively. | 2010-07-29 |
20100187548 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME AND MONOLITHIC LIGHT EMITTING DIODE ARRAY - A light emitting device including: at least one light emitting stack including first and second conductivity type semiconductor layers and an active layer disposed there between, the light emitting stack having first and second surfaces and side surfaces interposed between the first and second surfaces; first and second contacts formed on the first and second surface of the light emitting stack, respectively; a first insulating layer formed on the second surface and the side surfaces of the light emitting stack; a conductive layer connected to the second contact and extended along one of the side surfaces of the light emitting stack to have an extension portion adjacent to the first surface; and a substrate structure formed to surround the side surfaces and the second surface of the light emitting stack. | 2010-07-29 |
20100187549 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes a substrate, a plurality of LED chips, and a plurality of electrode pairs. The LED chips are disposed on the substrate, and each of the LED chips is electrically isolated from one another. The electrode pairs are disposed on the substrate, and each of the electrode pairs is electrically isolated from one another. The number of the electrode pairs is equal to the number of the LED chips, and each of the electrode pairs electrically connects one of the LED chips corresponding thereto. | 2010-07-29 |
20100187550 | LIGHT EMITTING DIODE - In a preferred embodiment, a light emitting device comprising: a polar template; a p-type layer grown on the polar template; the p-type layer having a first polarization vector; the first polarization vector having a first projection relative to a growth direction; an n-type layer grown on the p-type layer; the n-type layer having a second polarization vector; the second polarization vector having a second projection relative to said growth direction that is larger than the first projection of the first polarization vector for the p-type layer; the n-type layer and p-type layer forming an interface; whereby the first polarization vector in the p-layer and second polarization vector in the n-layer create a discontinuity at the interface resulting in a negative charge appearing at the interface. In another preferred embodiment, a light emitting device comprising: a polar template; a n-type layer grown on the template; the n-type layer having a first polarization vector; the first polarization vector having a first projection relative to a growth direction; an p-type layer grown on the n-type layer; the p-type layer having a second polarization vector; the second polarization vector having a second projection relative to said growth direction that is larger than the first projection of the first polarization vector for the p-type layer; the n-type layer and p-type layer forming an interface; whereby the first polarization vector in the p-layer and second polarization vector in the n-layer create a discontinuity at the interface resulting in a negative charge appearing at the interface. | 2010-07-29 |
20100187551 | LIGLIGHT EMITTING DIODE PACKAGE STRUCTURE - An LED package structure includes a carrier, a housing, an LED chip, a encapsulant and a surface treatment layer. The housing is disposed on the carrier and has an upper surface, wherein the housing and the carrier together form a chip-containing cavity. The LED chip is disposed on the carrier and located in the chip-containing cavity. The encapsulant is disposed in the chip-containing cavity and encapsulates the LED chip. The surface treatment layer is disposed on the upper surface of the housing to prevent the encapsulant from adhering to the upper surface of the housing. | 2010-07-29 |
20100187552 | HYBRID WHITE ORGANIC LIGHT EMITTTNG DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a hybrid white organic light emitting diode (OLED) and a method of fabricating the same. A HOMO level difference between a fluorescent emission layer and an electron transport layer in an organic emission layer (OLED) becomes higher than that between the other layers or a LUMO level difference between a fluorescent emission layer and a hole transport layer is higher than that between the other layers, so that a recombination region is restricted to a part of an emission layer to obtain high-efficiency fluorescent light emission. In addition, triplet excitons that are not used in a fluorescent emission layer are transferred to an auxiliary emission layer formed to be spaced apart from a recombination region by a predetermined distance to emit light in a different color from the fluorescent emission layer, so that both singlet and triplet excitons formed in the OLED are used to obtain high-efficiency white light emission. | 2010-07-29 |
20100187553 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND METHOD THEREOF - An LED package structure includes a carrier substrate, a reflector and an LED chip. The reflector is disposed on the carrier substrate and includes a base, a magnesium fluoride layer and a cerium dioxide layer. The base has an opening to expose a part of the carrier substrate. The magnesium fluoride layer is disposed on the inside wall of the opening and the cerium dioxide layer is disposed on the magnesium fluoride layer. The LED chip is disposed in the opening and located on the carrier substrate. | 2010-07-29 |
20100187554 | LIGHT EMITTING DEVICE HAVING VERTICAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device having a vertical structure and a method for manufacturing the same, which are capable of increasing light extraction efficiency, are disclosed. The method includes forming a light extraction layer on a substrate, forming a plurality of semiconductor layers on the light extraction layer, forming a first electrode on the semiconductor layers, forming a support layer on the first electrode, removing the substrate, and forming a second electrode on a surface from which the substrate is removed. | 2010-07-29 |
20100187555 | (Al,Ga,In)N AND ZnO DIRECT WAFER BONDED STRUCTURE FOR OPTOELECTRONIC APPLICATIONS, AND ITS FABRICATION METHOD - An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED. | 2010-07-29 |
20100187556 | Light Emitting Device Package And Method For Manufacturing The Same - A light emitting device package capable of emitting uniform white light and a method for manufacturing the same are disclosed. The light emitting device package includes a package body, an electrode formed on at least one surface of the package body, a light emitting device mounted on the package body, and a phosphor layer enclosing the light emitting device while having a uniform thickness around the light emitting device. | 2010-07-29 |
20100187557 | Light Sensor Using Wafer-Level Packaging - The present invention provides systems, devices and methods for fabricating miniature low-power light sensors. With the present invention, a light sensitive component, such as a diode, is fabricated on the front side of a silicon wafer. Connectivity from the front side of the wafer to the back side of the wafer is provided by a through silicon via. Solder bumps are then placed on the back side of the wafer to provide coupling to a printed circuit board. The techniques described in the present invention may also be applied to other types of semiconductor devices, such as light-emitting diodes, image sensors, pressure sensors, and flow sensors. | 2010-07-29 |
20100187558 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises: a light emitting structure comprising a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer; a nitride semiconductor layer on an outer periphery of the second conductive semiconductor layer; and an ohmic layer on the second conductive semiconductor layer. | 2010-07-29 |
20100187559 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises: a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; a second electrode part on the second conductive semiconductor layer; an insulation layer on the second electrode part; and a first electrode part on the insulation layer, a portion of the first electrode part being electrically connected to the first conductive semiconductor layer. | 2010-07-29 |
20100187560 | METHOD FOR BONDING METAL SURFACES, METHOD FOR PRODUCING AN OBJECT HAVING CAVITIES, OBJECT HAVING CAVITIES, STRUCTURE OF A LIGHT EMITTING DIODE - A method for bonding two partially form-fitting surfaces of two metal bodies which contain the same metal is carried out by generating a first layer on the surface of a first one of the two bodies, the first layer containing a mixture of the metal and the oxide of the metal; generating a second layer on the first layer, the second layer containing the metal but less oxide of the metal than does the first layer; placing the partially form-fitting surfaces of the two metal bodies adjacent to each other; heating the bodies placed adjacent to each other to a temperature which lies in a target range below the melting point of the metal and above the eutectic temperature of the eutectic of the metal and the metal oxide; and holding the temperature within the target range over a predetermined or a controllable duration of time. | 2010-07-29 |
20100187561 | ELECTRONIC DEVICE - An electronic device includes a carrier, a surface mounting device, and solders. The carrier has a plurality of bonding pads, and at least one of the bonding pads has a notch, such that the bonding pad has a necking portion adjacent to the notch. The surface mounting device is disposed on the carrier. Besides, the surface mounting device has a plurality of leads, and each of the leads is connected to the necking portion of one of the bonding pads, respectively. The notch of each of the bonding pads is located under one of the leads. The solders connect the bonding pads and the leads. | 2010-07-29 |
20100187562 | LIGHT-EMITTING DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light-emitting device package structure includes a leadframe, a light-emitting device disposed on the leadframe, a plurality of wires electrically connecting the leadframe and the light-emitting device, and an encapsulant covering the light-emitting device, the wires and a part of the leadframe. The encapsulant has a gas space therein, and the gas space is disposed on the light-emitting device, wherein the gas space includes at least one gas. | 2010-07-29 |
20100187563 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, temporarily bonding the semiconductor element and the base by applying a pressure or an ultrasonic vibration to the semiconductor element or the base, and permanently bonding the semiconductor element and the base by applying heat having a temperature of 150 to 900° C. to the semiconductor device and the base. | 2010-07-29 |
20100187564 | Method and Apparatus for Providing a Patterned Electrically Conductive and Optically Transparent or Semi-Transparent Layer over a Lighting Semiconductor Device - A light emitting diode (“LED”) using an electrical conductive and optical transparent or semi-transparent layer to improve overall light output is disclosed. The device includes a first conductive layer, an active layer, a second conductive layer, an electrical conductive and optical transparent or semi-transparent layer, and electrodes. In one embodiment, the electrical conductive and optical transparent or semi-transparent layer has a first surface and a second surface, wherein the first surface is overlain the second conductive layer. The second surface includes a pattern which contains thick regions and thin regions for facilitating light passage. | 2010-07-29 |
20100187565 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND WAFER - There are provided a semiconductor light emitting element which allows an improvement in light extraction efficiency without increasing the number of fabrication steps, and a wafer. In a semiconductor light emitting element | 2010-07-29 |
20100187566 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 2010-07-29 |
20100187567 | Semiconductor device - A semiconductor device includes a semiconductor substrate having a first surface and a second surface. A main region and a sensing region are formed on the first surface side of the semiconductor substrate. A RC-IGBT is formed in the main region and a sensing element for passing electric currents proportional to electric currents flowing through the RC-IGBT is formed in the sensing region. A collector region and a cathode region of the sensing element are formed on the second surface side of the semiconductor substrate. The collector region is located directly below the sensing region in a thickness direction of the semiconductor substrate. The cathode region is not located directly below the sensing region in the thickness direction. | 2010-07-29 |
20100187568 | EPITAXIAL METHODS AND STRUCTURES FOR FORMING SEMICONDUCTOR MATERIALS - Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming a plurality of substantially strain-relaxed island structures and utilizing such island structures for subsequent further growth of strain-relaxed substantial continuous layers of semiconductor material. | 2010-07-29 |
20100187569 | HETERO-STRUCTURE FIELD EFFECT TRANSISTOR, INTEGRATED CIRCUIT INCLUDING A HETERO-STRUCTURE FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING A HETERO-STRUCTURE FIELD EFFECT TRANSISTOR - A hetero-structure field effect transistor (HFET). The HFET may include a first contact and a second contact and a hetero-junction structure. The hetero-junction structure may include a first layer made from a first semiconductor material and a second layer made from a second semiconductor material. An interface at which the first layer and the second layer are in contact with each other may be provided, along which a two dimensional electron gas (2DEG) is formed in a part of the first layer directly adjacent to the interface, for propagating of electrical signals from the first contact to the second contact or vice versa. The transistor may further include a gate structure for controlling a conductance of the channel; a substrate layer made from a substrate semiconductor material, and a dielectric layer separating the first layer from the substrate layer. The second contact may include an electrical connection between the substrate layer and the first layer. The electrical connection may include a passage through the dielectric layer filled with an electrically conducting material which is electrically connected to the first layer. | 2010-07-29 |
20100187570 | Heterojunction Transistors Having Barrier Layer Bandgaps Greater Than Channel Layer Bandgaps and Related Methods - A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed. | 2010-07-29 |
20100187571 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to provide a semiconductor resistive element having excellent linearity. A semiconductor device according to the present invention includes a HBT which is formed on a GaAs substrate and includes a group III-V compound semiconductor, and a semiconductor resistive element made of at least one layer included in a semiconductor epitaxial layer included in the HBT, and the semiconductor resistive element includes helium impurities. | 2010-07-29 |
20100187572 | SUSPENDED MONO-CRYSTALLINE STRUCTURE AND METHOD OF FABRICATION FROM A HETEROEPITAXIAL LAYER - Methods of fabricating a suspended mono-crystalline structure use annealing to induce surface migration and cause a surface transformation to produce the suspended mono-crystalline structure above a cavity from a heteroepitaxial layer provided on a crystalline substrate. The methods include forming a three dimensional (3-D) structure in the heteroepitaxial layer where the 3-D structure includes high aspect ratio elements. The 3-D structure is annealed at a temperature below a melting point of the heteroepitaxial layer. The suspended mono-crystalline structure may be a portion of a semiconductor-on-nothing (SON) substrate. | 2010-07-29 |
20100187573 | Semiconductor integrated circuit - Disclosed herein is a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the standard cells, wherein each of the gate electrodes of the standard cells and the reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance. | 2010-07-29 |
20100187574 | Memory Cell For Modification of Revision Identifier In An Integrated Circuit Chip - A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary. | 2010-07-29 |
20100187575 | Semiconductor Element and a Method for Producing the Same - Some embodiments comprise a plurality of fins, wherein at least a first fin of the plurality of fins comprises a different fin width compared to a fin width of another fin of the plurality of fins. At least a second fin of the plurality of fins comprises a different crystal surface orientation compared to another fin of the plurality of fins. | 2010-07-29 |
20100187576 | Method of processing resist, semiconductor device, and method of producing the same - A surface component film ( | 2010-07-29 |
20100187577 | SCHOTTKY DIODE - Improved Schottky diodes ( | 2010-07-29 |
20100187578 | STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING - Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material. | 2010-07-29 |
20100187579 | TRANSISTOR DEVICES AND METHODS OF MAKING - In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers. | 2010-07-29 |
20100187580 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED INFRARED SENSING DEVICE - Protection for infrared sensing device, and more particularly, to a monolithically integrated uncooled infrared sensing device using IC foundry compatible processes. The proposed infrared sensing device is fabricated on a completed IC substrate. In an embodiment, the infrared sensing device has a single crystal silicon plate with an absorbing layer supported a pair of springs. The absorbing layer absorbs infrared radiation and heats up the underlying silicon layer. As a result, an n well in the silicon layer changes its resistance related to its temperature coefficient of resistance (TCR). In another embodiment, the infrared sensing device has a top sensing plate supported by an underlying spring structures. The top sensing plate has sensing materials such as amorphous silicon, poly silicon, SiC, SiGe, Vanadium oxide, or YbaCuO. Finally, a micro lens array is placed on top of the sensing pixel array with a gap in between. In an embodiment, the micro lens array is fabricated on a silicon substrate and bonded to the sensing pixel array substrate. In another embodiment, the micro lens array is fabricated monolithically using amorphous silicon. The micro lens array layer encapsulates the pixel sensing array hermetically, preferably in a vacuum environment. | 2010-07-29 |
20100187581 | SOLID-STATE IMAGE SENSING DEVICE AND CAMERA SYSTEM USING THE SAME - A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor. | 2010-07-29 |
20100187582 | SOLID-STATE IMAGING DEVICE HAVING TRANSMISSION GATES WHICH PASS OVER PART OF PHOTO DIODES WHEN SEEN FROM THE THICKNESS DIRECTION OF THE SEMICONDUCTOR SUBSTRATE - A solid-state imaging device having a plurality of image pixels arranged along a main surface of a semiconductor substrate, wherein each of the plurality of image pixels includes a photodiode that converts incident light into an electric charge and a transmission gate that is formed so as to have a crossing area that partially passes over the photodiode when seen from the thickness direction of the semiconductor substrate. The transmission gate of the solid-state imaging device is formed in a manner that (i) a first region including a laminated body of a silicon film and a silicide film, and (ii) a second region that includes the silicon film and does not include the silicide film, both arranged along a main surface of the semiconductor substrate, and the second region in the transmission gate is formed in at least one part of the crossing area. | 2010-07-29 |
20100187583 | Reconfigurable Electric Circuitry and Method of Making Same - A reconfigurable electric circuit includes first and second crystalline material layers positioned adjacent to each other and forming a first interface, and a first ferroelectric layer positioned adjacent to the first crystalline material layer and having ferroelectric domains applying an electric field to regions of the first interface to induce a quasi two-dimensional electron gas in the regions, wherein at least one of the regions forms a gate and at least one of the regions forms a channel. | 2010-07-29 |
20100187584 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an interlayer insulating film having an opening, an adhesion layer formed on at least a side wall of the opening, a lower electrode formed on a bottom surface of the opening and at least a side surface of the adhesion layer, a capacitor insulating film made of a ferroelectric formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. The lower electrode, the capacitor insulating film and the upper electrode constitute a capacitor, and the capacitor has a cross-section having a recessed shape in the opening. The lower electrode has a protruding portion protruding from the opening. The capacitor insulating film is formed, covering at least the protruding portion of the lower electrode, of the lower electrode and the adhesion layer. The upper electrode is formed, covering the capacitor insulating film formed on the protruding portion. | 2010-07-29 |
20100187585 | Spin MOS field effect transistor and tunneling magnetoresistive effect element using stack having Heusler alloy - A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer. | 2010-07-29 |
20100187586 | SOI DEVICE AND METHOD FOR ITS FABRICATION - A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor. | 2010-07-29 |
20100187587 | MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF - A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate. | 2010-07-29 |
20100187588 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A CYLINDER TYPE STORAGE NODE AND A METHOD OF FABRICATING THE SAME - Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs. | 2010-07-29 |
20100187589 | DEVICES AND METHODS FOR PREVENTING CAPACITOR LEAKAGE - Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench | 2010-07-29 |
20100187590 | Semiconductor device including metal insulator semiconductor transistor - A semiconductor device includes a plurality of metal insulator semiconductor (MIS) transistors. The plurality of MIS transistors each includes a gate electrode formed above a channel region of a semiconductor substrate via a gate insulating film and source/drain regions formed on both sides of the channel region. The gate electrode is electrically connected to an interconnect via a first plug. The interconnect has a plurality of vias formed thereon. The plurality of MIS transistors have threshold voltages different from one another due to variations in quantities of electric charges trapped by the gate insulating films respectively corresponding to the plurality of MIS transistors. | 2010-07-29 |
20100187591 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction. | 2010-07-29 |
20100187592 | HIGH PERFORMANCE FLASH MEMORY DEVICES - Disclosed herein is a flash memory device comprising: a wafer; a gate oxide layer disposed upon the wafer; a floating gate disposed upon the gate oxide layer, the wafer, or a combination thereof; the floating gate comprising a flat floating gate portion and a generally rectangular floating gate portion disposed upon selected areas of the flat floating gate portion; a high K dielectric material disposed upon the floating gate; and a control gate disposed upon the high K dielectric material; wherein the high K dielectric material forms a zigzag pattern coupling the floating gate with the control gate. | 2010-07-29 |
20100187593 | NAND FLASH MEMORY AND METHOD FOR MANUFACTURING THE SAME - A memory cell of NAND flash memory has a floating gate electrode taking a pillared shape formed on the first element region via a gate insulation film; diffusion layers formed in regions located on both sides of the floating gate electrode in the first element region; an IPD film formed on a top face of the floating gate electrode so as to extend over side faces of the floating gate electrode in a second direction perpendicular to the first direction; and a control gate electrode formed on the floating gate electrode and between adjacent floating gate electrodes via the IPD film so as to be continuous in the second direction. The IPD film is a low-k film. | 2010-07-29 |
20100187594 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction. | 2010-07-29 |
20100187595 | NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer. | 2010-07-29 |
20100187596 | Self-aligned double patterning for memory and other microelectronic devices - A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process. | 2010-07-29 |
20100187597 | METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS - Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon. | 2010-07-29 |
20100187598 | SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENT AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENT - There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein. | 2010-07-29 |
20100187599 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region. | 2010-07-29 |
20100187600 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer. | 2010-07-29 |
20100187601 | SEMICONDUCTOR DEVICE - A hermetic compressor includes a closed vessel for storing lubricating oil, an electric-driving element, and a compressing element driven by the electric-driving element. The compressing element includes a cylinder block forming a compression chamber, a piton that reciprocates inside the compression chamber, and an oiling device for supplying the lubricating oil to an outer circumference of the piston. A first oil groove is concavely formed on the outer circumference of the piston, and a second oil groove is concavely formed on a side opposite to the compression chamber relative to the first oil groove. The second oil groove has a spatial volume same or greater than that of the first oil groove. An expanded clearance portion is provided such that a clearance between the piston and the cylindrical hole portion broadens from a top dead point to a bottom dead point. | 2010-07-29 |
20100187602 | METHODS FOR MAKING SEMICONDUCTOR DEVICES USING NITRIDE CONSUMPTION LOCOS OXIDATION - Semiconductor devices and methods for making such devices using nitride consumption LOCOS oxidation are described. The semiconductor devices contain a planar field oxide structure that has been grown using a nitride layer as an oxidation mask. Once the field oxide structure has been grown, the nitride mask is not etched away, but rather converted to an oxide layer by an oxidation process using radicals of hydrogen and oxygen. The semiconductor devices also contain a shielded gate trench MOSFET that can be created using an oxide layer with an overlying nitride layer as the channel (sidewall) gate dielectric. An inter-poly-dielectric (IPD) layer can be formed from a thermally grown oxide which uses the nitride layer as a oxidation mask. The thickness of the IPD layer can be adjusted to any thickness needed with minimal effect of the channel gate dielectric layer. An oxidation process using radicals of hydrogen and oxygen can be preformed to consume the nitride layer and form the gate oxide in the channel region. Since the gate channel nitride acts as a barrier to the oxidation, the IPD oxide layer can be grown to any needed thickness with minimal oxidation to the channel gate and the nitride layer can be removed without any etching processes. Other embodiments are described. | 2010-07-29 |
20100187603 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which can relax the electric field in the junction termination region, and can achieve a high breakdown voltage. | 2010-07-29 |
20100187604 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane. | 2010-07-29 |
20100187605 | MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING - One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively. | 2010-07-29 |
20100187606 | SEMICONDUCTOR DEVICE THAT INCLUDES LDMOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device including an LDMOS transistor includes: a process (a) of forming a first conductive well diffusion layer in the semiconductor substrate; a process (b) of sequentially forming a gate insulator film, a gate conductive film, and a photoresist film on a region on the semiconductor substrate corresponding to the well diffusion layer; a process (c) of performing photolithography to remove a part of the photoresist film formed in a predetermined region, and etching the gate conductive film using a remaining part of the photoresist film as a mask so as to form an opening in the predetermined region; a process (d) of doping second conductive impurity ions using a remaining part of the gate conductive film and the remaining part of the photoresist film as a mask so as to form the body layer; and a process (e) of removing the remaining part of the gate conductive film except a part corresponding to the gate electrode formed based on a part that constitutes a lateral surface of the gate conductive film facing the opening. | 2010-07-29 |
20100187607 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER - A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed. | 2010-07-29 |
20100187608 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer. | 2010-07-29 |
20100187609 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 2010-07-29 |
20100187610 | SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE - A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO | 2010-07-29 |
20100187611 | Contacts in Semiconductor Devices - Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance. | 2010-07-29 |
20100187612 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate. The device includes the substrate, a first gate insulation film formed on the substrate in the first and second regions, and containing silicon, a second gate insulation film formed on the first gate insulation film in the first region, and containing first metal and oxygen, a third gate insulation film formed on the first gate insulation film in the second region, and containing second metal different from the first metal and oxygen, a fourth gate insulation film formed on the second and third gate insulation films in the first and second regions, and containing hafnium, and a gate electrode layer formed on the fourth gate insulation film in the first and second regions, and containing metal and nitrogen, a thickness of the gate electrode layer formed in the second region being greater than a thickness of the gate electrode layer formed in the first region. | 2010-07-29 |
20100187613 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 2010-07-29 |
20100187614 | SELECTIVE NITRIDATION OF GATE OXIDES - A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen. | 2010-07-29 |
20100187615 | Linear Gate Level Cross-Coupled Transistor Device with Direct Electrical Connection of Cross-Coupled Transistors to Common Diffusion Node - Each of first and second PMOS transistors, and first and second NMOS transistors has a respective diffusion terminal with a direct electrical connection to a common node, and has a respective gate electrode formed from an originating rectangular-shaped layout feature. Centerlines of the originating rectangular-shaped layout features are aligned to be parallel with a first direction. The first PMOS transistor gate electrode is electrically connected to the second NMOS transistor electrode. The second PMOS transistor gate electrode is electrically connected to the first NMOS transistor gate electrode. The first and second PMOS transistors, and the first and second NMOS transistors together define a cross-coupled transistor configuration having commonly oriented gate electrodes formed from respective rectangular-shaped layout features. | 2010-07-29 |
20100187616 | Linear Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. At least a portion of the first p-type diffusion region and at least a portion of the second p-type diffusion region are formed over a first common line of extent that extends perpendicular to the first parallel direction. Also, at least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a second common line of extent that extends perpendicular to the first parallel direction. | 2010-07-29 |
20100187617 | Linear Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes - First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes of cross-coupled transistors are defined to extend over the diffusion regions in only a first parallel direction, with each gate electrode fabricated from a respective originating rectangular-shaped layout feature. The first and second p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. At least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a common line of extent that extends across the substrate perpendicular to the first parallel direction. | 2010-07-29 |
20100187618 | Linear Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. | 2010-07-29 |
20100187619 | Linear Gate Level Cross-Coupled Transistor Device with Different Width PMOS Transistors and Different Width NMOS Transistors - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration. | 2010-07-29 |
20100187620 | Linear Gate Level Cross-Coupled Transistor Device with Connection Between Cross-Coupled Transistor Gate Electrodes Made Utilizing Interconnect Level Other than Gate Electrode Level - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. The electrical connection between the gate electrodes of the first PMOS and second NMOS transistor devices is formed in part by one or more electrical conductors present within at least one interconnect level above the gate electrode level region. | 2010-07-29 |
20100187621 | Linear Gate Level Cross-Coupled Transistor Device with Constant Gate Electrode Pitch - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. A gate electrode level region is formed in accordance with a virtual grate defined by virtual lines that extend in only a first parallel direction, such that an equal perpendicular spacing exists between adjacent ones of the virtual lines. Each of a number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned with a virtual line of the virtual grate. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected, and the gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. | 2010-07-29 |
20100187622 | Linear Gate Level Cross-Coupled Transistor Device with Complimentary Pairs of Cross-Coupled Transistors Defined by Physically Separate Gate Electrodes within Gate Electrode Level - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region. | 2010-07-29 |
20100187623 | Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Two Gate Electrode Tracks with Crossing Gate Electrode Connections - A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2010-07-29 |
20100187624 | Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Three Gate Electrode Tracks with Crossing Gate Electrode Connections - A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2010-07-29 |
20100187625 | Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Four Gate Electrode Tracks with Crossing Gate Electrode Connections - A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2010-07-29 |
20100187626 | Channelized Gate Level Cross-Coupled Transistor Device with Direct Electrical Connection of Cross-Coupled Transistors to Common Diffusion Node - Each of first and second PMOS transistors, and first and second NMOS transistors has a respective diffusion terminal with a direct electrical connection to a common node, and has a respective gate electrode defined within any one gate level channel. Each gate level channel is uniquely associated with and defined along one of a number of parallel oriented gate electrode tracks. The first PMOS transistor gate electrode is electrically connected to the second NMOS transistor electrode. The second PMOS transistor gate electrode is electrically connected to the first NMOS transistor gate electrode. The first and second PMOS transistors, and the first and second NMOS transistors together define a cross-coupled transistor configuration having commonly oriented gate electrodes formed from respective rectangular-shaped layout features. | 2010-07-29 |
20100187627 | Channelized Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features that are each defined within any one gate level channel. At least a portion of the first p-type diffusion region and at least a portion of the second p-type diffusion region are formed over a first common line of extent that extends perpendicular to the first parallel direction. Also, at least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a second common line of extent that extends perpendicular to the first parallel direction. | 2010-07-29 |
20100187628 | Channelized Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes - First and second PMOS transistors are defined over first and second p-type diffusion regions. First and second NMOS transistors are defined over first and second n-type diffusion regions. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. | 2010-07-29 |
20100187629 | TENSILE STRAIN SOURCE USING SILICON/GERMANIUM IN GLOBALLY STRAINED SILICON - By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain. | 2010-07-29 |
20100187630 | Channelized Gate Level Cross-Coupled Transistor Device with Connection Between Cross-Coupled Transistor Gate Electrodes Made Utilizing Interconnect Level Other than Gate Electrode Level - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. The electrical connection between the gate electrodes of the first PMOS and second NMOS transistor devices is formed in part by one or more electrical conductors present within at least one interconnect level above the gate electrode level region. | 2010-07-29 |
20100187631 | Channelized Gate Level Cross-Coupled Transistor Device with Constant Gate Electrode Pitch - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. A gate electrode level region is formed in accordance with a virtual grate defined by virtual lines that extend in only a first parallel direction, such that an equal perpendicular spacing exists between adjacent ones of the virtual lines. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of virtual lines of the virtual grate. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected, and the gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. | 2010-07-29 |
20100187632 | Channelized Gate Level Cross-Coupled Transistor Device with Complimentary Pairs of Cross-Coupled Transistors Defined by Physically Separate Gate Electrodes within Gate Electrode Level - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region. | 2010-07-29 |
20100187633 | Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Two Gate Electrode Tracks with Crossing Gate Electrode Connections - A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2010-07-29 |
20100187634 | Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Four Gate Electrode Tracks with Crossing Gate Electrode Connections - A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2010-07-29 |
20100187635 | SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN - By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced. | 2010-07-29 |
20100187636 | METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS - A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET. | 2010-07-29 |