30th week of 2022 patent applcation highlights part 60 |
Patent application number | Title | Published |
20220238657 | GaN/DIAMOND WAFERS - Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a substrate wafer that includes a glass substrate (or a silicon substrate covered by a protection layer) is glass bonded to the diamond layer. Then, the silicon carrier wafer and the protection layer are removed. | 2022-07-28 |
20220238658 | Integrated Assemblies Having Semiconductor Oxide Channel Material, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies. | 2022-07-28 |
20220238659 | Backside Contact With Air Spacer - A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer. | 2022-07-28 |
20220238660 | Method of Forming Backside Power Rails - A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the semiconductor structure includes forming a fin structure extending from a front side of a substrate, recessing a source region of the fin structure to form a source opening, forming a semiconductor plug under the source opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact. By performing the PAI process, crystalline semiconductor is amorphized and may be substantially removed. Thus, the performance and reliability of the semiconductor structure may be advantageously improved. | 2022-07-28 |
20220238661 | SEMICONDUCTOR DEVICE HAVING CONTACT FEATURE AND METHOD OF FABRICATING THE SAME - A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide. | 2022-07-28 |
20220238662 | METHOD FOR FORMING THIN SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES - Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing. | 2022-07-28 |
20220238663 | ION IMPLANT DEFINED NANOROD IN A SUSPENDED MAJORANA FERMION DEVICE - Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device. | 2022-07-28 |
20220238664 | TRENCH GATE FIELD-EFFECT TRANSISTORS WITH DRAIN RUNNER - In a general aspect, a field-effect transistor (FET) can include a semiconductor region, and a trench disposed in the semiconductor region. The FET can also include a trench gate disposed in an upper portion of the trench in an active region of the FET. The FET can further include a conductive runner disposed in a bottom portion of the trench. The conductive runner can be electrically coupled with a drain terminal of the FET. A portion of the conductive runner can be disposed in the active region below the trench gate. | 2022-07-28 |
20220238665 | SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF - A semiconductor structure and a formation method thereof are provided. The semiconductor structure includes: a semiconductor substrate having a source region or drain region therein. The source region or drain region has a groove. The semiconductor structure can include a metal silicide layer arranged on a surface of a sidewall of the groove and an insulating layer arranged on a bottom surface of the groove. The edge of the insulating layer is in contact with a bottom surface of the metal silicide layer on the sidewall of the groove; and a conducting layer filled in the groove and arranged on the metal silicide layer and the insulating layer. The semiconductor structure of the present disclosure can prevent electric current from leaking into the semiconductor substrate at the bottom of the source/drain region. | 2022-07-28 |
20220238666 | INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction. | 2022-07-28 |
20220238667 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - Disclosed are a semiconductor structure and a forming method thereof. In one form, a semiconductor structure includes: a base; gate structures arranged discretely on the base, including gate contact regions used for contact with gate plugs; source/drain doped regions, including source/drain contact regions and source/drain connection regions; dielectric structure layers, located on the base on sides of the gate structures and covering the source/drain doped regions and the gate structures; source/drain contact structures, being in contact with the source/drain doped regions, where the source/drain contact structures are an integrated structure, and include source/drain plugs penetrating dielectric structure layers of the source/drain contact regions and source/drain contact layers located in dielectric structures of the source/drain connection regions, top surfaces of the source/drain contact layers are lower than top surfaces of the source/drain plugs, and the source/drain contact structures and the dielectric structure layers enclose spaced openings; spaced dielectric layers, filling the spaced openings; and gate plugs, located on tops of the gate structures in the gate contact regions and in contact with the gate structures. The source/drain contact structures of implementations of the present disclosure are an integrated structure, which improves performance of electrical connection between the source/drain plugs and the source/drain contact layers. | 2022-07-28 |
20220238668 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; gate structures and source/drain plugs over the base substrate; source/drain contact structures on the source/drain plugs; gate contact structures on the gate structures; and a dielectric layer on the gate structures and the source/drain plugs. Cavities are formed between the gate structures and the source/drain plugs along a surface of the base substrate. The dielectric layer encloses tops of the cavities. | 2022-07-28 |
20220238669 | SEMICONDUCTOR DEVICE, FINFET DEVICE AND METHODS OF FORMING THE SAME - A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region. | 2022-07-28 |
20220238670 | SEMICONDUCTOR DEVICE AND METHOD OF USING - A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area. | 2022-07-28 |
20220238671 | Double Control Gate Semi-Floating Gate Transistor and Method for Preparing the Same - The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate. | 2022-07-28 |
20220238672 | VERTICAL NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×10 | 2022-07-28 |
20220238673 | HIGH VOLTAGE TRANSISTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other. | 2022-07-28 |
20220238674 | METHODS FOR FORMING PLANAR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS - A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate. | 2022-07-28 |
20220238675 | TRENCH-GATE TRANSISTOR WITH GATE DIELECTRIC HAVING A FIRST THICKNESS BETWEEN THE GATE ELECTRODE AND THE CHANNEL REGION AND A SECOND GREATER THICKNESS BETWEEN THE GATE ELECTRODE AND THE SOURCE/DRAIN REGIONS - The present disclosure provides a transistor, a transistor forming method thereof, and a semiconductor device. The transistor forming method comprises providing a substrate, the substrate comprising a first region for forming a source region and a second region for forming a drain region; forming a gate groove in the substrate to separate the first region and the second region, a part of the substrate along the bottom of the gate groove being used for constituting an embedded channel region of a transistor; forming a gate dielectric layer on the gate groove of the substrate to cover the embedded channel region and to extend to cover a side of the first region and a side of the second region in the gate groove; and forming a gate conductive layer on the gate dielectric layer of the substrate and in the gate groove. | 2022-07-28 |
20220238676 | GATE ALL AROUND DEVICE - A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode. | 2022-07-28 |
20220238677 | NANOWIRE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene. | 2022-07-28 |
20220238678 | DEVICE AND METHOD OF FABRICATING MULTIGATE DEVICES HAVING DIFFERENT CHANNEL CONFIGURATIONS - Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures. | 2022-07-28 |
20220238679 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction. | 2022-07-28 |
20220238680 | THRESHOLD VOLTAGE MODULATION FOR GATE-ALL-AROUND FET ARCHITECTURE - A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer. | 2022-07-28 |
20220238681 | Transistor Gates and Methods of Forming - A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric. | 2022-07-28 |
20220238682 | ENABLING ANNEAL FOR RELIABILITY IMPROVEMENT AND MULTI-VT WITH INTERFACIAL LAYER REGROWTH SUPPRESSION - A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer. | 2022-07-28 |
20220238683 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first device formed over a substrate. The first device includes a first device formed over a substrate, and the first device includes a first gate stack structure encircling a plurality of first nanostructures. The semiconductor device includes a first epitaxy structure wrapping an end of one of the first nanostructures, and a second device formed over the first device, wherein the second device includes a second gate stack structure encircling a plurality of second nanostructures. The semiconductor device includes a second epitaxy structure wrapping an end of one of the second nanostructures, and the second epitaxy structure is directly above the first epitaxy structure. | 2022-07-28 |
20220238684 | ELECTRONIC DEVICES COMPRISING A DIELECTRIC MATERIAL, AND RELATED SYSTEMS AND METHODS - Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed. | 2022-07-28 |
20220238685 | CHANNEL STRUCTURES FOR THIN-FILM TRANSISTORS - Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed. | 2022-07-28 |
20220238686 | Semiconductor Device and Method - In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal. | 2022-07-28 |
20220238687 | Transistor Gate Structures and Methods of Forming the Same - In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer. | 2022-07-28 |
20220238688 | GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A semiconductor device a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material. | 2022-07-28 |
20220238689 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a fin-type active area extending in a first horizontal direction on a substrate, a channel area on the fin-type active area, a gate line surrounding the channel area on the fin-type active area and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer structure covering gate sidewalls of the gate line and channel sidewalls of the channel area, wherein the insulating spacer structure includes an air spacer having a first portion facing the gate sidewalls in the first horizontal direction and a second portion facing the channel sidewalls in the second horizontal direction. | 2022-07-28 |
20220238690 | SEMICONDUCTOR DEVICE, FERROELECTRIC CAPACITOR AND LAMINATED STRUCTURE - A semiconductor device includes a substrate, a gate stack over the substrate, a channel layer over the gate stack, and a source/drain electrode. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The source/drain electrode is formed on the channel layer and disposed on sides of the gate stack. | 2022-07-28 |
20220238691 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR - Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure. | 2022-07-28 |
20220238692 | METHOD OF PATTERNING TWO-DIMENSIONAL MATERIAL LAYER ON SUBSTRATE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region. | 2022-07-28 |
20220238693 | SEMICONDUCTOR DEVICES WITH AIR GATE SPACER AND AIR GATE CAP - A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers. | 2022-07-28 |
20220238694 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FORMING THE SAME - A high electron mobility transistor (HEMT) includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a first passivation layer disposed on the barrier layer, a plurality of trenches through at least a portion of the first passivation layer, and a conductive plate structure disposed on the first passivation layer. The conductive plate structure includes a base portion over the trenches and a plurality of protruding portions extending from a lower surface of the base portion and into the trenches. | 2022-07-28 |
20220238695 | Self-Aligned Source/Drain Metal Contacts and Formation Thereof - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature. | 2022-07-28 |
20220238696 | Fin Field-Effect Transistor Device and Method of Forming the Same - A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate. | 2022-07-28 |
20220238697 | Reducing K Values of Dielectric Films Through Anneal - A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl | 2022-07-28 |
20220238698 | MOS-GATED TRENCH DEVICE USING LOW MASK COUNT AND SIMPLIFIED PROCESSING - A trenched, vertical MOS-gated switch is described that uses only three or four masking steps to fabricate. In one embodiment, one mask is used to form first trenches having a first depth, wherein the first trenches are filled with doped polysilicon to form gates to control the conduction of the switch. A second mask is used to form second trenches having a shallower second depth. The second trenches are filled with the same metal used to form the top source electrode and gate electrode. The metal filling the second trenches electrically contacts a top source layer and a body region. A third mask is used to etch the metal to define the source metal, the gate electrode, and floating rings in a termination region surrounding the active area of the switch. An additional mask may be used to form third trenches in the termination region that are deeper than the first trenches. | 2022-07-28 |
20220238699 | Nanostructures and Method for Manufacturing the Same - Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench. | 2022-07-28 |
20220238700 | Method for Forming Semiconductor Device - Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer. | 2022-07-28 |
20220238701 | SEMICONDUCTOR DEVICE - A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a <100> crystallographic direction. | 2022-07-28 |
20220238702 | PARASITIC CAPACITANCE REDUCTION - The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact. | 2022-07-28 |
20220238703 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove. | 2022-07-28 |
20220238704 | Devices Having a Semiconductor Material That Is Semimetal in Bulk and Methods of Forming the Same - Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure. | 2022-07-28 |
20220238705 | Insulated Gate Bipolar Transistor, Power Module, and Living Appliance - An insulated gate bipolar transistor includes a semiconductor substrate, and the semiconductor substrate includes: a collector region doped in a first type, wherein the collector region includes a bump region; a first drift region doped in a second type and a second drift region doped in the second type; wherein the first drift region and the second drift region locate on a side of the collector region having the bump region, a profile contour of the first drift region matches a profile contour of the bump region, such that the second drift region does not contact the bump region, and a doping concentration of the first drift region is greater than a doping concentration of the second drift region; and a first active region and a second active region, formed at two opposite ends of the second drift region. | 2022-07-28 |
20220238706 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer. | 2022-07-28 |
20220238707 | SEMICONDUCTOR DEVICES - A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction. | 2022-07-28 |
20220238708 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided. The semiconductor structure includes fin structures, a gate structure across the fin structures, and a dielectric layer. The gate structure includes a work function layer over the gate dielectric layer, and a contact layer over the work function layer. A portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A top surface of the work function layer and a top surface of the dielectric layer are substantially on a same level. A method for forming a semiconductor structure is also provided. | 2022-07-28 |
20220238709 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer. | 2022-07-28 |
20220238710 | SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND AN ASYMMETRIC CHANNEL AND RELATED METHODS - A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel. | 2022-07-28 |
20220238711 | SEMICONDUCTOR DEVICE HAVING MOS TRANSISTOR FOR EFFICIENT STRESS TRANSFER - Disclosed herein is a method that includes forming a gate electrode on an active region of a semiconductor substrate surrounded by a STI region; implanting a first dopant into the active region by using the gate electrode as a mask to form LDD regions; forming a liner film on top and side surfaces of the gate electrode, the STI region, and the LDD regions; forming a side wall spacer on the side surfaces of the gate electrode with the liner film interposed therebetween; implanting, with covering the STI region and the LDD regions by the liner film, a second dopant by using the gate electrode, the liner film formed on the side surfaces of the gate electrode, and the side wall spacer as a mask to form source/drain regions; and removing the side wall spacer. | 2022-07-28 |
20220238712 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The gate structure has a first sidewall and a second sidewall. The second sidewall is opposite the first sidewall. The semiconductor device also includes a gate spacer structure having two asymmetrical portions. One of the asymmetrical portions is formed on the first sidewall of the gate structure, and the other asymmetrical portion is formed on the second sidewall of the gate structure. The semiconductor device includes a source region and a drain region formed in the semiconductor substrate and aligned with the outer edges of the asymmetrical portions of the gate spacer structure. In some embodiments, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure. | 2022-07-28 |
20220238713 | Epitaxial Source/Drain Structures for Multigate Devices and Methods of Fabricating Thereof - Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate. | 2022-07-28 |
20220238714 | METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STRUCTURES - Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device. | 2022-07-28 |
20220238715 | Gate Resistance Reduction Through Low-Resistivity Conductive Layer - A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack. | 2022-07-28 |
20220238716 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first, second, third and fourth fin structures over a substrate. The first and the second fin structures have a first and a second sidewall surfaces respectively. The third and the fourth fin structure have a third and a fourth sidewall surfaces respectively. The first and the second sidewall surfaces extend along a first direction. The third and the fourth sidewall surfaces extend along a second direction different from the first direction. A first and a second isolation structures are over the substrate and surrounding the first and the second fin structure and surrounding the third and the fourth fin structures respectively. A distance between top portions of the third and the fourth sidewall surfaces is greater than that between top portions of the first and the second sidewall surfaces. | 2022-07-28 |
20220238717 | Isolation Structures And Methods Of Forming The Same In Field-Effect Transistors - A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers. | 2022-07-28 |
20220238718 | METAL OXIDE AND TRANSISTOR INCLUDING METAL OXIDE - A novel metal oxide is provided. The metal oxide includes a crystal. The crystal has a structure in which a first layer, a second layer, and a third layer are stacked. The first layer, the second layer, and the third layer are each substantially parallel to a formation surface of the metal oxide. The first layer includes a first metal and oxygen. The second layer includes a second metal and oxygen. The third layer includes a third metal and oxygen. The first layer has an octahedral structure. The second layer has a trigonal bipyramidal structure or a tetrahedral structure. The third layer has a trigonal bipyramidal structure or a tetrahedral structure. The octahedral structure of the first layer includes an atom of the first metal at a center. The trigonal bipyramidal structure or the tetrahedral structure of the second layer includes an atom of the second metal at a center. The trigonal bipyramidal structure or the tetrahedral structure of the third layer includes an atom of the third metal at a center. The valence of the first metal is equal to the valence of the second metal. The valence of the first metal is different from the valence of the third metal. | 2022-07-28 |
20220238719 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with less variation in transistor characteristics is provided. The semiconductor device includes a semiconductor film, a pair of blocking films over the semiconductor film, and an insulating film provided over the semiconductor film and between the pair of blocking films. The semiconductor film includes a pair of n-type regions and an i-type region provided between the pair of n-type regions. The n-type regions overlap with the blocking films. The i-type region overlaps with the insulating film. | 2022-07-28 |
20220238720 | THIN FILM TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line. | 2022-07-28 |
20220238721 | SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL - A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material. | 2022-07-28 |
20220238722 | THIN FILM TRANSISTOR AND DISPLAY SUBSTRATE HAVING THE SAME - A display substrate including a base substrate, a first thin film transistor disposed on the base substrate and including a first gate electrode and a first semiconductor active layer; a second thin film transistor electrically connected to the first thin film transistor, the second thin film transistor including a second gate electrode and a second semiconductor active layer; and an organic light emitting device electrically connected to the second thin film transistor. The first semiconductor active layer includes a first material and the second semiconductor active layer includes a second material different from the first material. | 2022-07-28 |
20220238723 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction. | 2022-07-28 |
20220238724 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD OF SAME, AND DISPLAY DEVICE - A thin film transistor | 2022-07-28 |
20220238725 | Self-Aligned Spacers For Multi-Gate Devices And Method Of Fabrication Thereof - A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure. | 2022-07-28 |
20220238726 | QUANTUM DIODE FOR TRANSFORMING AN ALTERNATING CURRENT, IN PARTICULAR HIGH FREQUENCY ALTERNATING CURRENT, INTO A DIRECT CURRENT - The present invention refers to a quantum diode for transforming an alternating current, in particular a high frequency alternating current, into a direct current, comprising: a first conductive metal layer ( | 2022-07-28 |
20220238727 | ZENER DIODE AND MANUFACTURING METHOD THEREOF - The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region. | 2022-07-28 |
20220238728 | DIODE, METHOD FOR PRODUCING DIODE, AND ELECTRONIC DEVICE - This diode is configured by a double gate PSJ-GaN-based FET. This FET has a GaN layer | 2022-07-28 |
20220238729 | FINFET MOS CAPACITOR - Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric. | 2022-07-28 |
20220238730 | CAPPING STRUCTURES FOR GERMANIUM-CONTAINING PHOTOVOLTAIC COMPONENTS AND METHODS OF FORMING THE SAME - At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion. | 2022-07-28 |
20220238731 | SOLAR CELL AND SOLAR CELL PANEL INCLUDING SAME - The present disclosure relates to a solar cell and a solar cell panel including the same, and more particularly, to a solar cell with an improved structure and an improved manufacturing process and a solar cell panel including the same. | 2022-07-28 |
20220238732 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING THE SAME - A method for producing an electronic device having a drive circuit including a solar cell structure, the method including the steps of: having a first wafer having solar cell structures on a starting substrate and a second wafer having drive circuits formed, so that either one of the first wafer or the second wafer has a plurality of independent diode circuits and capacitor-function laminated portions; obtaining a bonded wafer by bonding so that the solar cell structures, the diode circuits, the capacitor-function laminated portions, and the drive circuits are superimposed; wiring; and dicing the bonded wafer; thus creating a method for producing an electronic device including a drive circuit, a solar cell structure, and a capacitor-function portion in one chip and having a suppressed production cost; and such an electronic device. | 2022-07-28 |
20220238733 | SENSOR PACKAGES WITH WAVELENGTH-SPECIFIC LIGHT FILTERS - In examples, a sensor package comprises a die pad and a semiconductor die on the die pad. The semiconductor die has an active surface. The sensor package includes a light sensor on the active surface of the semiconductor die. The sensor package includes a mold compound covering the die pad, the semiconductor die, and a portion of the active surface. The sensor package includes a light filter covering the light sensor and abutting the mold compound. The light filter includes a combination of silicone, metal particles, and an organic dye. The combination is configured to reject light having a wavelength in a target wavelength range. The light filter has a thickness of at least 0.5 millimeters. | 2022-07-28 |
20220238734 | SOLAR CELL MODULE HAVING UPCONVERSION NANO-PARTICLES AND METHOD OF MANUFACTURING THE SOLAR CELL MODULE - Disclosed is a solar cell module. The module includes a solar cell including a plurality of unit battery cells electrically connected to each other via internal connection electrodes; an upper cover disposed on a front face of the solar cell; a light-conversion coating layer coated on an inner face of the upper cover, wherein the light-conversion coating layer includes upconversion nano-particles for absorbing near-infrared rays and emitting light having a wavelength in a visible region; a lower cover disposed on a rear face of the solar cell; a first filling material layer formed between the solar cell and the light-conversion coating layer; and a second filling material layer formed between the solar cell and the lower cover. | 2022-07-28 |
20220238735 | LIGHT DETECTION DEVICE, SUPERCONDUCTING NANOWIRE SINGLE PHOTON DETECTOR COMPRISING THE SAME AND METHOD FOR MANUFACTURING THE SAME - A light detection device having improved self-alignment precision using a hard mask, and a method for manufacturing the same is provided. A method of manufacturing a light detection device includes i) providing a substrate; ii) providing a light reflecting portion on the substrate; iii) providing a light detection portion on the light reflection portion; iv) providing an anti-reflection portion provided on the light reflection portion to cover the light detection portion; v) removing each of the first outer periphery of the light reflection portion and the second outer periphery of the anti-reflection portion, and vi) providing a hard mask formed to correspond to the removed first outer periphery, positioned on the substrate, and spaced apart from the light reflecting portion to surround the light reflecting portion. | 2022-07-28 |
20220238736 | MERCURY CADMIUM TELLURIDE-BLACK PHOSPHOROUS VAN DER WAALS HETEROJUNCTION INFRARED POLARIZATION DETECTOR AND PREPARATION METHOD THEREOF - Disclosed are a mercury cadmium telluride-black phosphorus van der Waals heterojunction infrared polarization detector and a preparation method thereof. The structure of the detector from bottom to top comprises a substrate, a mercury cadmium telluride material, an insulating layer, a two-dimensional semiconductor black phosphorus, and metal electrodes. First, growing the mercury cadmium telluride material on the substrate, removing part of the mercury cadmium telluride by ultraviolet lithography and argon ion etching, filling with aluminum oxide as the insulating layer using an electron beam evaporation method, transferring the two-dimensional semiconductor material black phosphorus at the junction of mercury cadmium telluride and an insulating layer assisted by a polypropylene carbonate film, and preparing the metal source-drain electrodes by electron beam lithography technology combined with the lift-off process to form the mercury cadmium telluride-black phosphorus van der Waals heterojunction infrared polarization detector. | 2022-07-28 |
20220238737 | FABRICATING A SEMICONDUCTOR STRUCTURE WITH MULTIPLE QUANTUM WELLS - A method of fabricating a semiconductor structure with multiple quantum wells, comprising: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing: a first layer on the substrate, the first layer of a first semiconductor alloy, and a second layer in contact with the first layer, the second layer of a second semiconductor alloy, to form a first stack of substantially planar semiconductor layers on the substrate; depositing in contact with the first stack a third layer of a binary semiconductor compound having the first lattice constant; depositing at least: a fourth layer on the third layer, the fourth layer comprising a third semiconductor alloy comprising InP, and a fifth layer in contact with the fourth layer, the fifth layer comprising a fourth semiconductor alloy comprising InP, to form a second stack of substantially planar semiconductor layers on the third layer. | 2022-07-28 |
20220238738 | SILICON CARBIDE ULTRAVIOLET LIGHT PHOTODETECTOR AND MANUFACTURING PROCESS THEREOF - The photodetector is formed in a silicon carbide body formed by a first epitaxial layer of an N type and a second epitaxial layer of a P type. The first and second epitaxial layers are arranged on each other and form a body surface including a projecting portion, a sloped lateral portion, and an edge portion. An insulating edge region extends over the sloped lateral portion and the edge portion. An anode region is formed by the second epitaxial layer and is delimited by the projecting portion and by the sloped lateral portion. The first epitaxial layer forms a cathode region underneath the anode region. A buried region of an N type, with a higher doping level than the first epitaxial layer, extends between the anode and cathode regions, underneath the projecting portion, at a distance from the sloped lateral portion as well as from the edge region. | 2022-07-28 |
20220238739 | STABLE PEROVSKITE MODULE INTERCONNECTS - Thin-film solar cell modules and serial cell-to-cell interconnect structures and methods of fabrication are described. In an embodiment, solar cell module and interconnect includes a conformal transport layer over a subcell layer. The conformal transport layer may also laterally surround an outside perimeter the subcell layer. | 2022-07-28 |
20220238740 | MULTIJUNCTION SOLAR CELLS - A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of the active layer of the one solar subcell. | 2022-07-28 |
20220238741 | MULTIJUNCTION SOLAR CELLS - A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; and a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of its emitter layer and base layer. | 2022-07-28 |
20220238742 | MULTIJUNCTION SOLAR CELLS - A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; and a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of its emitter layer and base layer. | 2022-07-28 |
20220238743 | PHOTOELECTRIC CONVERSION DEVICE, PHOTOELECTRIC CONVERSION SYSTEM, AND MOVING BODY - Photoelectric conversion device includes first region of first conductivity type arranged in semiconductor layer having first second surfaces, second region of second conductivity type arranged between the second surface and the first region and forming avalanche photodiode, separation region of the second conductivity type arranged between the first and second surfaces to surround the second region, contact region of the second conductivity type contacted to the separation region, first contact plug connected to the first region, and second contact plug connected to the contact region. The second region has shape of rectangle, and the second contact plug is arranged in diagonal direction of the rectangle. Distance between center of the first contact plug and center of the second contact plug is larger than distance between center of the second region and the center of the second contact plug. | 2022-07-28 |
20220238744 | SEMICONDUCTOR BODY, AVALANCHE PHOTODIODE AND METHOD FOR FABRICATING A SEMICONDUCTOR BODY - A semiconductor body comprises a buried layer of a first type of conductivity, a first region of the first type of conductivity, a shallow region of a second type of conductivity at a first surface of the semiconductor body, a sinker of the first type of conductivity located at the first surface of the semiconductor body, and a separating region of the first type of conductivity encircling at least one of the sinker and the buried layer. The first region is between the buried layer and the shallow region. | 2022-07-28 |
20220238745 | SEMICONDUCTOR LIGHT-RECEIVING ELEMENT - A semiconductor light-receiving element, includes: a semiconductor substrate; a high-concentration layer of a first conductivity type formed on the semiconductor substrate; a low-concentration layer of the first conductivity type formed on the high-concentration layer of the first conductivity type and in contact with the high-concentration layer of the first conductivity type; a low-concentration layer of a second conductivity type configured to form a PN junction interface together with the low-concentration layer of the first conductivity type; and a high-concentration layer of the second conductivity type formed on the low-concentration layer of the second conductivity type and in contact with the low-concentration layer of the second conductivity type. The low-concentration layers have a carrier concentration of less than 1×10 | 2022-07-28 |
20220238746 | GERMANIUM SINGLE-CRYSTAL WAFER, METHOD FOR PREPARING GERMANIUM SINGLE-CRYSTAL WAFER, METHOD FOR PREPARING CRYSTAL BAR, AND USE OF SINGLE-CRYSTAL WAFER - A germanium single-crystal wafer comprises silicon with an atomic concentration of from 3×10 | 2022-07-28 |
20220238747 | INVERTED METAMORPHIC MULTIJUNCTION SOLAR CELL - A method of manufacturing a solar cell comprising: providing a growth substrate depositing on the growth substrate an epitaxial sequence of layers of semiconductor material forming at least a first and second solar subcells depositing a semiconductor contact layer on top of the second solar subcell depositing a reflective metal layer over said semiconductor contact layer such that the reflectivity of the reflective metal layer is greater than 80% in the wavelength range 850 to 2000 nm depositing a contact metal layer composed on said reflective metal layer mounting and bonding a supporting substrate on top of the contact metal layer and removing the growth substrate. | 2022-07-28 |
20220238748 | SOLAR CELL AND PREPARATION METHOD THEREFOR, METHOD FOR PROCESSING N-TYPE DOPED SILICON FILM, AND SEMICONDUCTOR DEVICE - Embodiments of the present disclosure provide a solar cell and a manufacturing method thereof, a processing method of an n-type doped silicon film, and a semiconductor device. The manufacturing method of the solar cell includes: providing a silicon wafer; forming an n-type doped silicon film on a first main surface of the silicon wafer at a first temperature, and simultaneously forming the n-type doped silicon film on at least a portion of surfaces of the silicon wafer except the first main surface due to wrapping around; performing a heat treatment on the n-type doped silicon film at a second temperature; etching and removing the n-type doped silicon film on the surfaces of the silicon wafer except the first main surface after performing the heat treatment; and preparing the solar cell by using the silicon wafer, the first temperature is lower than the second temperature. | 2022-07-28 |
20220238749 | CONTACT STRUCTURE AND ELECTRONIC DEVICE HAVING THE SAME - The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes: a substrate; a copper layer disposed on the substrate; an adhesion promotion layer disposed on the copper layer, wherein the adhesion promotion layer forms a monomolecular adsorption layer on the surface of the copper layer; and a silver nanowire layer disposed on the adhesion promotion layer, and the adhesive force between the copper layer and the silver nanowire layer is 3B or more. In the present disclosure, by disposing the adhesion promotion layer on the copper layer, in the stacked structure of the copper layer and the silver nanowire layer, the adhesive force between the copper layer and the silver nanowire layer is increased, so as to prevent a peeling phenomenon of the copper layer occurring in the subsequent yellow-light process. | 2022-07-28 |
20220238750 | Optoelectronic Device with Reduced Optical Loss - A heterostructure with reduced optical losses is disclosed. The heterostructure includes a set of n-type layers; an active region that generates radiation at a peak emitted wavelength; and a set of p-type layers located adjacent to the active region. A reflective structure can be located adjacent to the set of p-type layers. A thickness of the set of p-type layers can be configured to promote constructive interference of the reflected radiation with radiation emitted by the active region in a direction toward the set of n-type layers. | 2022-07-28 |
20220238751 | METHOD OF MANUFACTURING A HYBRID DEVICE - A method of manufacturing a micro-light-emitting diode display includes processing a wafer to form a plurality of functional chips integral with the wafer. A plurality of wafer tiles is defined in the wafer, wherein each wafer tile is composed of a cluster of functional chips. The wafer tiles are singulated by wafer dicing. A plurality of separate wafer tiles is bonded to a semiconductor wafer by hybrid bonding. The functional chips are singulated together with chips of the semiconductor wafer by dicing the bonded-together wafer tiles and semiconductor wafer. | 2022-07-28 |
20220238752 | Method of Laser Treatment of a Semiconductor Wafer Comprising AlGaInP-LEDs to Increase their Light Generating Efficiency - Embodiments provide a method for treating a semiconductor wafer comprising a set of aluminum gallium indium phosphide light emitting diodes (AlGaInP-LEDs) to increase a light generating efficiency of the AlGaInP-LEDs, wherein each AlGaInP-LED includes a core active layer for light generation sandwiched between two outer layers, the core active layer having a central light generating area and a peripheral edge surrounding the central light generating area, wherein the method includes treating the peripheral edge of the core active layer of each AlGaInP-LED with a laser beam thereby increasing a minimum band gap in each peripheral edge to such an extent that, during operation of the AlGaInP-LED, an electron-hole recombination is essentially confined to the central light generating area. | 2022-07-28 |
20220238753 | METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE COMPRISING AXIAL LIGHT-EMITTING DIODES - A method of manufacturing an optoelectronic device including light-emitting diodes comprising forming three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, with a polarity of the group-III element, the method further including, for each semiconductor element, forming an active area covering the semiconductor element and a stack of semiconductor layers covering the active area, the active area being formed by vapor deposition at low pressure and comprising quantum wells separated by barrier layers, each quantum well including a ternary alloy having at least one first group-III element, the group-V element, and a second group-III element, the ratio of the atomic flux of the group-III elements to the atomic flux of the group-V element is in the range from 1 to 1.8. | 2022-07-28 |
20220238754 | BURIED CONTACT LAYER FOR UV EMITTING DEVICE - In some embodiments, a light emitting structure comprises a layered semiconductor stack comprising a first set of doped layers, a second layer, a light emitting layer positioned between the first set of doped layers and the second layer, and an electrical contact to the first set of doped layers. The first set of doped layers can comprise a first sub-layer, a second sub-layer, and a third sub-layer, wherein the third sub-layer is adjacent to the light emitting layer. The electrical contact can be coupled to the second sub-layer. The first, second and third sub-layers can be doped n-type, and an electrical conductivity of the second sub-layer can be higher than an electrical conductivity of the first and third sub-layers. The first, second and third sub-layers, and the light emitting layer can each comprise a superlattice. The second layer can comprise a chirped superlattice. | 2022-07-28 |
20220238755 | MICRON-SIZED LIGHT EMITTING DIODE DESIGNS - A emitting diode (LED) includes an epitaxial structure defining a base and a mesa on the base. The base defines a light emitting surface of the LED and includes current spreading layer. The mesa includes a thick confinement layer, a light generation area on the thick confinement layer to emit light, a thin confinement layer on the light generation area, and a contact layer on the thin confinement layer, the contact layer defining a top of the mesa. A reflective contact is on the contact layer to reflect a portion of the light emitted from the light generation area, the reflected light being collimated at the mesa and directed through the base to the light emitting surface. In some embodiments, the epitaxial structure grown on a non-transparent substrate. The substrate is removed, or used to form an extended reflector to collimate light. | 2022-07-28 |
20220238756 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING ELEMENT UNIT INCLUDING THE LIGHT-EMITTING ELEMENT, AND DISPLAY DEVICE - A light-emitting element includes a light-emitting element core extending in a direction and including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and a device active layer disposed between the first semiconductor layer and the second semiconductor layer, a device insulating film surrounding a lateral surface of the light-emitting element core, and a reflective film disposed on an outer lateral surface of the device insulating film and surrounding at least a lateral surface of the device active layer. | 2022-07-28 |