30th week of 2011 patent applcation highlights part 57 |
Patent application number | Title | Published |
20110185154 | SYNCHRONIZATION OF MULTIPLE PROCESSOR CORES - The invention relates to a spinlock-based multi-core synchronization technique in a real-time environment, wherein multiple processor cores perform spinning attempts to request a lock and the lock is allocated to at most one of the multiple cores for a mutually exclusive operation thereof. A method embodiment of the technique comprises the steps of allocating the lock to the first core requesting it; establishing for each core an indication of a waiting time for receiving the lock; selecting at least one of the spinning cores based on the waiting time indications; and, upon return of the lock, conditionally allocating the lock to the selected core, if the selected core performs a spinning attempt within a predefined time window starting with the return of the lock. | 2011-07-28 |
20110185155 | MICROPROCESSOR THAT PERFORMS FAST REPEAT STRING LOADS - A microprocessor invokes microcode in response to encountering a repeat load string instruction. The microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into a cache memory of the microprocessor a series of cache lines implicated by a string of data bytes specified by the instruction. A memory subsystem of the microprocessor guarantees within architectural limits that the cache line specified by each GPREFETCH instruction will be fetched into the cache. The memory subsystem completes each GPREFETCH instruction once it determines that no conditions exist that would prevent fetching the cache line specified by the GPREFETCH instruction and once it allocates a fill queue buffer to receive the cache line. A retire unit frees a reorder buffer entry allocated to each GPREFETCH instruction in response to completion of the GPREFETCH instruction regardless of whether the cache line specified by the GPREFETCH instruction has been fetched into the cache. | 2011-07-28 |
20110185156 | EXECUTING WATCHPOINT EVENTS FOR DEBUGGING IN A "BREAK BEFORE MAKE" MANNER - A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable execution to continue from the instruction in which the watchpoint event occurred. The watchpoint event is executed in a “break before make” manner. | 2011-07-28 |
20110185157 | MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT - A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle. | 2011-07-28 |
20110185158 | HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES - Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction. | 2011-07-28 |
20110185159 | PROCESSOR INCLUDING AGE TRACKING OF ISSUE QUEUE INSTRUCTIONS - An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power. | 2011-07-28 |
20110185160 | MULTI-CORE PROCESSOR WITH EXTERNAL INSTRUCTION EXECUTION RATE HEARTBEAT - A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle. | 2011-07-28 |
20110185161 | ELECTRONIC DEVICE AND METHOD FOR DETECTING OPERATIVE STATES OF COMPONENTS IN THE ELECTRONIC DEVICE - An electronic device and method for detecting operative states of components in the electronic device includes determining a selected component of the electronic device, and setting a threshold time of the selected component. In response to the electronic device detecting a first interrupt instruction from the selected component, a timer of the electronic device is enabled to time the threshold time. Upon the condition that the threshold time elapses, the selected component is determined to be in an abnormal state. Then the selected component is restarted and initialized. | 2011-07-28 |
20110185162 | METHOD AND SYSTEM TO TRANSMIT CODE TO A SYSTEM ON A CHIP (SOC) - A method and system to transmit code to a System on Chip (SOC) from a host processor using a host-side driver is provided herein. The SOC and host processor are coupled by a bus. The host driver receives an overlay from an application layer and stores the overlay. The host driver receives an IOCTL to be transmitted to the SOC. The host driver determines whether an input/output control (IOCTL) value of the IOCTL to be transmitted to the SOC corresponds to an IOCTL value in one of the stored overlays. The host driver transmits an overlay to the SOC if the IOCTL value of the IOCTL to be transmitted is equal to at least one IOCTL value in the overlay. The host driver then transmits the IOCTL to the SOC. | 2011-07-28 |
20110185163 | MULTI-ROOT PCI EXPRESS SWITCH, BOOT METHOD THEREOF, AND MULTI-ROOT PCI MANAGER PROGRAM - Provided is an MRA (multi-root aware) PCI express switch accommodating a plurality of root complexes. The MRA PCI express switch includes: a setting register storing necessary information to set a PCI tree based on a switch connection topology and a physical connection state; and a virtual switch bridge controller storing necessary information to establish a virtual PCI tree, irrespective of a status of the setting register. The root complexes can be booted based on the information in the virtual switch bridge controller. | 2011-07-28 |
20110185164 | Information processing apparatus and boot completion notification program - In an information processing apparatus, a stopwatch unit detects boot-up of an information processing apparatus, and measures as a boot time a time elapsed from the detection of the boot-up. A determination unit determines whether the boot time has reached notification timing. An output unit outputs a boot completion notification when the determination unit determines that the boot time has reached the notification timing indicated by boot completion notification timing information as a result of comparison therebetween. | 2011-07-28 |
20110185165 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, AND INTEGRATED CIRCUIT - It is possible to update and re-seal sealed data having a usability condition of matching with predetermined terminal environment information during a secure boot without rebooting a terminal when a program using the sealed data is updated. An information processing terminal ( | 2011-07-28 |
20110185166 | Slider Control for Security Grouping and Enforcement - A group of security functions may be configured and managed by organizing the security functions and their features into a ranked list and made available through an administrative console. The ranked list may represent various levels of security from which a user may select. Once selected, the security functions may be configured according to the selected level. The console may determine a current security level by analyzing the configuration or status of each of the security functions and presenting a single status level from the ranked list determined by the least secure setting of the various security functions. | 2011-07-28 |
20110185167 | CHANGE IMPACT RESEARCH SUPPORT DEVICE AND CHANGE IMPACT RESEARCH SUPPORT METHOD - There is provided a change impact research support device. Whenever CI included in configuration management information is modified, CIs modified along with a combination of CIs modified in the present configuration management change are extracted. Then, the more the number of modifications performed along with the combination of the CIs is, the higher impact is set for the extracted CIs, and the CIs are indicated to a user as modification-candidate CIs in descending order of impacts. | 2011-07-28 |
20110185168 | Method and Apparatus for File Sharing Between a Group of User Devices with Separately Sent Crucial Portions and Non-Crucial Portions - A communication system and method for operating the same includes a group of user devices and a content delivery network in communication with the group of user devices. The content delivery network selects a plurality user devices from the group of user devices, divides the content into a crucial portion and a non-crucial portions, and encrypts the crucial portions differently for each of the user devices in the group using conditional access encryption. The content delivery network communicates the non-crucial portions to the plurality of user devices, communicates the encrypted crucial portion to the plurality of user devices separately from the non-crucial. The plurality of user devices assembles the crucial portion and the non-crucial portions to form the content. | 2011-07-28 |
20110185169 | Agile Network Protocol For Secure Communications With Assured System Availability. - A plurality of computer nodes communicate using seemingly random Internet Protocol source and destination addresses. Data packets matching criteria defined by a moving window of valid addresses are accepted for further processing, while those that do not meet the criteria are quickly rejected. Improvements to the basic design include (1) a load balancer that distributes packets across different transmission paths according to transmission path quality; (2) a DNS proxy server that transparently creates a virtual private network in response to a domain name inquiry; (3) a large-to-small link bandwidth management feature that prevents denial-of-service attacks at system chokepoints; (4) a traffic limiter that regulates incoming packets by limiting the rate at which a transmitter can be synchronized with a receiver; and (5) a signaling synchronizer that allows a large number of nodes to communicate with a central node by partitioning the communication function between two separate entities. | 2011-07-28 |
20110185170 | COMMUNICATION WITH NON-REPUDIATION AND BLIND SIGNATURES - Apparatus, systems, and methods may operate to receive, at a trusted third party (TTP), a signed disguised message as a disguised receiver signature from a receiver that has signed a disguised message using a blind signature process to transform the disguised message into the signed disguised message. Additional activities may include sending, from the TTP, an undisguised version of the disguised message to the receiver, and the receiver signature to a sender of the undisguised version, after determining that the receiver signature is valid. Additional apparatus, systems, and methods are disclosed. | 2011-07-28 |
20110185171 | CERTIFICATE AUTHENTICATING METHOD, CERTIFICATE ISSUING DEVICE, AND AUTHENTICATION DEVICE - A terminal device | 2011-07-28 |
20110185172 | GENERATING PKI EMAIL ACCOUNTS ON A WEB-BASED EMAIL SYSTEM - The present invention provides systems and methods for allowing an Email User to create a Public Key Infrastructure (PKI) Email Account and thereafter to digitally sign, send, verify and receive PKI encrypted emails over a computer network, such as the Internet. The systems and methods preferably include a Web-based Email System and a Certificate Authority that coordinate their actions to make the process of creating, maintaining and using the PKI Account as easy as possible for the Email User. In a preferred embodiment, a Keystore System may also be used to enhance the management and use of digital keypairs. | 2011-07-28 |
20110185173 | Method for Implementing Encryption and Device Thereof - The present invention provides an encryption method in which the encryption device stores data to be encrypted received via the input/output interface in its own memory, converts the data to be encrypted in the memory into a format required by the output device and transmits the converted data to the output device via the management interface, and the output device outputs the received information. The present invention also provides an encryption device for implementing the above method. The encryption device determines whether confirmation information has been received from a management interface, encrypts the data to be encrypted in the memory if the answer is positive, while performs no encryption or prompts to input correct confirmation information if the answer is negative. With the present invention, the user is allowed to view the contents to be actually encrypted, thereby avoiding such a case as signature counterfeiting or tampering. | 2011-07-28 |
20110185174 | System and Method for Providing a One-Time Key for Identification - A server includes a key generator and an authenticator. The key generator is configured to receive a request for a first key from a worker device, to create the first key that is associated with a worker, and to transmit the first key to the worker device. The authenticator is in communication with the key generator, the authenticator is configured to receive a second key and identification details from a customer device, to transmit the identification details to the worker device, to receive acknowledgment of the identification details from the worker device, and to authenticate the second key and the identification details with the customer device. | 2011-07-28 |
20110185175 | Authentication Method and System for Online Gaming - Embodiments of an authentication technique for online gaming are provided. In one aspect, an authentication method for online gaming includes storing a user identity of a user in a portable data storage device; providing access to the user identity for an authentication server to authenticate the user such that the authentication server allows the user to participate in online gaming when the user is authenticated; and when the online gaming continues, providing access to the user identity for the authentication server to validate the authenticity of the user at a first threshold time after the user identity is accessed previously. | 2011-07-28 |
20110185176 | BIOMETRIC AUTHENTICATION METHOD AND SYSTEM - At a registration time, a feature data array for registration is generated from biometric information acquired by a client, and a position correction template and a comparison template obtained by converting the feature data array for registration are registered in a server. | 2011-07-28 |
20110185177 | Method for generating an asymmetric cryptographic key pair and its application - The invention pertains to a method, computer readable medium, and data processing system for generation of an asymmetric cryptographic key pair including reception of an arbitrarily selectable login name, calculation of a first data object key, whereby a random value and the login name are included in the calculation, and calculation of a second data object key from the first data object key, whereby the first and second data object keys form the asymmetric cryptographic key pair. | 2011-07-28 |
20110185178 | COMMUNICATION METHOD OF AN ELECTRONIC HEALTH INSURANCE CARD WITH A READING DEVICE - The invention relates to a communication method of an electronic health insurance card ( | 2011-07-28 |
20110185179 | System And Method For Digital Rights Management With A Lightweight Digital Watermarking Component - Various embodiments of a system and method for digital rights management with a lightweight digital watermarking component are described. Embodiments may include methods as well as elements for performing such methods. Such a method may include receiving content onto a computer system; the computer system may include a runtime component configured to consume the content. The method may include receiving a digital watermarking component on the computer system. The digital watermarking component may specify information for generating a digital watermark on the content. The method may include applying a digital watermark to the content with the runtime component in order to generate watermarked content. The digital watermark may be applied by the runtime component in accordance with the digital watermarking component. In various embodiments, the received runtime component may be configured to prevent the received content from being consumed without the digital watermark applied to the received content. | 2011-07-28 |
20110185180 | METHOD AND DEVICE FOR CREATING DIGITAL SIGNATURE - A method is disclosed for creating a digital signature associated with a user having a code-generating device including a data interface, a display device, a user input device and processing circuitry, the digital signature being indicative of at least one signature object including a signature element having been pre-selected for display to the user. In at least one embodiment, the method includes: receiving, through the data interface, signature data from a user communication device, the signature data including reference data indicating a location of the signature object and a corresponding identifier code, uniquely identifying the signature object; acquiring, through the data interface, the signature object including the signature element having been pre-selected for display; determining a candidate identifier code for the signature object including the signature element having been pre-selected for display; displaying, if the candidate identifier code matches the identifier code included in the signature data, information indicative of the signature element having been pre-selected for display using the display device; determining, if user input indicative of approval of the displayed information is received through the user input device, a digital signature based on the signature data using the processing circuitry; and providing the digital signature to the user communication device. | 2011-07-28 |
20110185181 | NETWORK AUTHENTICATION METHOD AND DEVICE FOR IMPLEMENTING THE SAME - A network authentication method is to be implemented using a network authentication device and a user end for authenticating the user end. The network authentication method includes the steps of: configuring the network authentication device to store hardware information associated with unique identification codes of hardware components of the user end; when it is intended to verify identity of the user end, configuring the user end to execute a terminal program stored therein for scanning the hardware components thereof to obtain the identification codes of the hardware components, for establishing a hardware list according to the identification codes thus obtained, and for sending to the network authentication device verification data that is associated with the hardware list; and configuring the network authentication device to verify identity of the user end based on relationship between the verification data received from the user end and the hardware information stored therein. | 2011-07-28 |
20110185182 | IMPROVEMENTS RELATED TO THE AUTHENTICATION OF MESSAGES - A method of authenticating a message from a sending party to a receiving party. The sending party generates a digest of the message using a key, and sends the digest to the receiving party. The receiving party also generating the digest of the message using the key, and compares the digests to confirm the message was sent by the sending party. The key may be sent by the sending party to the receiving party by an authenticatable method; alternatively, the parties may use a secret previously agreed key. | 2011-07-28 |
20110185183 | PERIPHERAL DEVICE, NETWORK SYSTEM, COMMUNICATION PROCESSING METHOD - A peripheral device includes an interface for connection to a wired or wireless LAN, a local interface for wireless connection, and a control unit configured to check a legitimacy of a user based on a user-specific certificate stored in a communication-function-equipped device upon being accessed through the local interface by the communication-function-equipped device using near-field wireless communication, and to allow a predetermined process to be performed upon successful authentication of the legitimacy. | 2011-07-28 |
20110185184 | METHOD AND DEVICE FOR ELECTRONICALLY CAPTURING A HANDWRITTEN SIGNATURE AND SAFEGUARDING BIOMETRIC DATA - A method and apparatus for encrypting an electronic document involves a computer having a first monitor and a signature capture apparatus configured to capture a handwritten signature on a second monitor. A hash sum of the electronic document generated in the computer is transmitted to the signature capture apparatus. The electronic document and the first hash sum thereof are displayed on the first monitor. The first hash sum is also displayed on the second monitor. After electronically capturing the handwritten signature, the signature data and the first hash sum are encrypted in the signature capture apparatus and then transmitted to the computer. The encrypted signature data, the first hash sum and the signed document are stored on a computer-readable medium. | 2011-07-28 |
20110185185 | METHOD AND APPARATUS FOR PARENTAL CONTROL OF WIRELESS BROADCAST CONTENT - A method comprises detecting zapping to or from one or more services; determining whether the zapping includes termination of a password-protected service; and sending a trigger message ( | 2011-07-28 |
20110185186 | SYSTEM AND METHOD FOR PROTECTING DATA ON A MOBILE DEVICE - Methods and systems are disclosed for protecting data on a mobile device. A data protection module on the mobile device receives a transmission including a secret key. The secret key is used in encrypting data on the device and is then deleted. Subsequent to an event detectable to the mobile device, the data protection module receives another transmission including said secret key. The secret key is then used to decrypt the encrypted data. | 2011-07-28 |
20110185187 | ELECTRONIC DEVICE AND METHOD - According to one aspect of embodiments of the present invention there is provided apparatus comprising a main assembly having a processing element configured to: obtain a first and second sub-assembly identifier stored on a second-assembly in communication with the main assembly; and enable operation of the main assembly and second assembly based on a determination that the first and second sub-assembly identifiers are cryptographically related. | 2011-07-28 |
20110185188 | COMPUTER IMPLEMENTED METHOD FOR ANALYZING DATA OF A USER WITH THE DATA BEING STORED PSEUDONYMOUSLY IN A DATABASE - The invention relates to a computer implemented method for analyzing data of a first user, wherein an asymmetric cryptographic key pair is associated with the first user, said asymmetric cryptographic key pair comprising a public key and a private key, the data being stored pseudonymously in a database with the data being assigned to an identifier, wherein the identifier comprises the public key, the method comprising: | 2011-07-28 |
20110185189 | SDK Use-Restriction Imposing Device, Use-Restriction-Imposed SDK Developing System, and SDK Use-Restriction Imposing Method - An SDK use-restriction imposing device includes a user interface unit, a source file of a use-restriction plug-in, a use-restriction plug-in edit unit, a build unit, and a use-restriction plug-in generation unit. The use-restriction plug-in edit unit sets use restrictions to the source file on the basis of use-restriction information received via the user interface unit. The build unit compiles the source file so as to generate an executable file of the use-restriction plug-in in response to a build instruction received via the user interface unit. The use-restriction plug-in generation unit generates a use-restriction-imposed SDK including an original SDK and the executable file of the use-restriction plug-in in response to an output instruction received via the user interface unit. | 2011-07-28 |
20110185190 | SYSTEM AND METHOD FOR PROTECTING CONTENT ON A STORAGE DEVICE - A system apparatus and method for protecting information on a storage device. Embodiments of the invention may create a virtual volume on a storage device. Embodiments of the invention may further transfer information to the virtual volume, remove information stored outside the virtual volume and extend the size of the virtual volume. Other embodiments are described and claimed. | 2011-07-28 |
20110185191 | ELECTRONIC BOOK ELECTRONIC LINKS - The invention, an electronic book selection and delivery system, is a new way to distribute books and other textual information to bookstores, libraries and consumers. The primary components of the system are a subsystem for placing text in a video signal format and a subsystem for receiving and selecting text that is placed in the video signal format. The system configuration for consumer use contains additional components and optional features that enhance the system, namely: ( | 2011-07-28 |
20110185192 | STORAGE SYSTEM, CONTROL METHOD THEREFOR, AND PROGRAM - It is made possible to correctly decrypt data in a storage area in a computer system (storage system) having various encryption execution sections (such as a storage device or encryption appliance having an encryption function). In the case where storage areas may be encrypted by the various encryption execution sections, there is a possibility that, when a storage area is copied or the configuration of the computer system is changed, the storage area cannot be correctly decrypted unless it is managed where the storage area has been encrypted or whether the storage area is not encrypted. To prevent this, a management computer manages the key and the encryption execution section for each storage area in the system. Furthermore, when copying a storage area or the like is performed, the management computer determines which storage area's state and key should be changed together with performing the copy operation is performed, and instructs the encryption execution section to change the state and key for the storage area if it is necessary to change it. | 2011-07-28 |
20110185193 | DE-SEQUENCING ENCODED DATA SLICES - A method begins by a processing module obtaining at least an ordering threshold number of encoded data slices to produce obtained encoded data slices. The method continues with the processing module ordering the obtained encoded data slices based on a pseudo-random de-sequencing order to produce a plurality of sets of encoded data slices. The method continues with the processing module dispersed storage error decoding the plurality of sets of encoded data slices to produce a plurality of encrypted data segments. The method continues with the processing module decrypting the plurality of encrypted data segments to produce a plurality of data segments. The method continues with the processing module aggregating the plurality of data segments to produce a data stream. | 2011-07-28 |
20110185194 | STANDBY POWER CONTROL DEVICE - This invention relates to a standby power control device, which is able to apply in controlling the ON/OFF state of the power of a computer and a plurality of peripheral devices, which comprises: a power input unit, a power transformation unit, a switching unit, a start control unit, a power control unit, a power output unit, and a micro-process unit, wherein the micro-process unit is connected to the computer to detect a boot signal and a shut down signal. When the computer is shut down, the micro-process unit receives the shut down signal and to turn off the start control unit to facilitate the power control unit to disable the connection of the power input unit and the power output unit, so that the standby power of the computer and the peripheral devices is turned off for achieving the purpose of saving the electrical power. | 2011-07-28 |
20110185195 | ENERGY EFFICIENT MANAGEMENT OF DATALINKS - A system including a first physical network interface card (NIC) include a number of rings, where at least one of the rings is an active ring. The system further includes a host, operatively connected to the first NIC, and including Media Access Control (MAC) layer. The MAC layer is configured to obtain a power management policy, obtain a load associated with the active ring, determine, using the power management policy and the load, that the state associated with at least one of the rings must be changed, and change, in response to the determining, the state of at least one of the of rings. | 2011-07-28 |
20110185196 | Power Management Apparatus, Electronic Appliance, and Method of Managing Power - There is provided a power management apparatus including: a managed appliance registering unit carrying out authentication on an electronic appliance connected to a power network and registering an electronic appliance for which the authentication has succeeded as a managed appliance, a control unit controlling operation of the managed appliance and supplying of power to the managed appliance, a managed appliance information acquiring unit acquiring, from the managed appliance, as managed appliance information, at least any of appliance information including identification information that is unique to the electronic appliance, information indicating an operation state of the electronic appliance, information indicating an usage state of the electronic appliance and power information of the electronic appliance, and an appliance state judging unit judging a state of the managed appliance based on the managed appliance information acquired by the managed appliance information acquiring unit. | 2011-07-28 |
20110185197 | OUTLET EXPANSION APPARATUS, AND DELEGATE AUTHENTICATION METHOD - There is provided an outlet expansion apparatus including a first connection outlet to which an electronic appliance is to be connected, a second connection outlet that is for connecting to a power supply outlet that is to be a supply source of power, and a delegate authentication unit that carries out, in a case the electronic appliance not having a function of carrying out authentication with a power management apparatus managing an amount of power to be supplied to the electronic appliance is connected to the first connection outlet and the power supply outlet is connected to the second connection outlet, authentication to be carried out on the power management apparatus by the electronic appliance connected to the first connection outlet on behalf of the electronic appliance. | 2011-07-28 |
20110185198 | ELECTRONIC APPLIANCE, POWER MANAGEMENT APPARATUS, AND METHOD OF IDENTIFYING APPLIANCE - There is provided an electronic appliance including a plurality of electrical parts having electrical characteristics that are different thereamong and for each electronic appliance, a characteristics measuring unit that measures the characteristics of at least one electrical part, a switch that switches between the electrical parts whose characteristics are to be measured by the characteristics measuring unit, and a control unit that controls the switch and causes the characteristics measuring unit to measure the characteristics of a predetermined electrical part, and that transmits, to a power management apparatus managing at least power supply to its own electronic appliance, information relating to the characteristics measured by the characteristics measuring unit and an appliance ID of its own electronic appliance. | 2011-07-28 |
20110185199 | EMBEDDED SYSTEM AND POWER SAVING METHOD THEREOF - An embedded system comprises a main chip generating a sleep signal, a network interface controller (MC) generating a wake-up signal, a microprogrammed control unit (MCU), a switch, and a power source. The MCU sends a closing signal upon receiving the wake-up signal and an opening signal upon receiving the sleep signal. The switch comprises a public terminal, a free terminal, and a control terminal. The free terminal connects to the main chip, the control terminal connects to the MCU, the public terminal connects to the free terminal upon receiving the closing signal, and the public terminal disconnects from the free terminal upon receiving the opening signal. The power source connects to the MC and the MCU to provide power, and further connects to the public terminal to provide power if the public terminal and the free terminal are connected, and stop power if disconnected. | 2011-07-28 |
20110185200 | METHOD AND APPARATUS FOR WAKING DEVICE FROM POWER SAVE MODE - A method for waking a device from a power save mode to an active mode includes: transmitting, by a first device, a magic packet through a predetermined channel to a second device, which operates in the power save mode by repeating a doze state and an awake state according to a predetermined period of time, for notifying the second device to switch to the active mode; and retransmitting the magic packet to the second device through the predetermined channel if a response to the magic packet has not been received from the second device and a predetermined time has not elapsed after transmitting the magic packet through the predetermined channel. | 2011-07-28 |
20110185201 | STORAGE SYSTEM AND ITS POWER CONTROL METHOD - In the process of controlling a plurality of storage devices | 2011-07-28 |
20110185202 | Mobile Computing Device and Method for Maintaining Application Continuity - A method of maintaining application continuity ( | 2011-07-28 |
20110185203 | METHOD AND APPARATUS FOR POWER CONTROL - Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application. | 2011-07-28 |
20110185204 | CONTROL OF ACCESSORY COMPONENTS BY PORTABLE COMPUTING DEVICE - A portable computing device (PCD) can control the operating state of a component within an accessory. For example, an accessory can have some components (e.g., a video processor) that are used for some operations but not for others. A PCD can determine whether a particular component will be used and can instruct the accessory to set the component to a desired state, e.g., powered up when in use and powered down when not in use. In some embodiments, the PCD can use status information provided by the accessory in determining a desired state for the accessory component. For example, in the case of a video converter accessory, if no display device or other video receiver is connected to the accessory, a video processor within the accessory can be powered down. | 2011-07-28 |
20110185205 | POWER-SAVING DISPLAY INFORMATION CONVERTING SYSTEM AND METHOD - Display information to be displayed by a display device having a power consumption model is converted according to a power-saving conversion model and the power consumption model, such that the power consumption of the display device for displaying the converted display information is lower than that for displaying the original display information. | 2011-07-28 |
20110185206 | MULTIPLE VOLTAGE GENERATOR AND VOLTAGE REGULATION METHODOLOGY FOR POWER DENSE INTEGRATED POWER SYSTEMS - An integrated power system suitable for simultaneously powering marine propulsion and service loads. The system includes: (a) at least one generator configured with at least first and second armature windings configured to output respective first and second alternating current power signals of different voltages, the at least two armature windings positioned within the same stator slots so that they magnetically couple; (b) at least first and second rectifier circuits coupled to said generator to convert said first and second alternating current power signals into first and second direct current power signals; (c) a first load to which said first direct current power signal is coupled and a second load to which said second direct current power signal is coupled. | 2011-07-28 |
20110185207 | PCMCIA MEMORY CARD WITH ETHERNET/WIRELESS CONNECTIVITY AND BATTERY BACKUP FOR AVIONICS APPLICATIONS - A method to facilitate data transfer to a line replaceable unit that lacks a transmission control protocol/Internet protocol (TCP/IP) interface is provided. The method comprises interfacing a memory-processing card to the line replaceable unit. The memory-processing card includes a memory, a central processing unit module, an interface to the line replaceable unit, an interface to an access point communicatively coupled to the central processing unit module, and a bus arbitrator communicatively coupled to the memory, the central processing unit module, and the interfaces. The method also includes determining a state of the line replaceable unit at the bus arbitrator responsive to the interfacing, providing access at the bus arbitrator from the central processing unit module to the memory when the determined state of the line replaceable unit is OFF, and providing access at the bus arbitrator from the line replaceable unit to the memory when the determined state of the line replaceable unit is ON. | 2011-07-28 |
20110185208 | MEMORY POWER REDUCTION IN A SLEEP STATE - A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state. | 2011-07-28 |
20110185209 | COMPUTER THAT REDUCES POWER CONSUMPTION WHILE MAINTAINING A SPECIFIC FUNCTION - A laptop PC is enabled to operate with small power consumption while maintaining a specific function. A laptop PC is provided with a HDD and can operate in a normal mode and a doze mode as a new operating mode. In the doze mode, the computer can operate with power consumption less than in the normal mode while executing a process to implement a specific function. In the doze mode a shift event is created, and a process existing at that time is force-suspended or an I/O processing completion notification is suspended to a process that makes an I/O request to the HDD. As a result, the laptop PC is enabled to operate with small power consumption by stopping the HDD while maintaining a specific function. | 2011-07-28 |
20110185210 | Method and Arrangement for Saving Energy In Microprocessors - The invention relates to a method for operating an electronic system, wherein the energy consumption of at least parts of the system is regulated such that on the basis of at least a time-related curve of the current (IFE | 2011-07-28 |
20110185211 | Systems and Methods for Determining the State of Health of a Capacitor Module - Systems and methods for determining the state of health for a capacitor module are provided. In some embodiments, a method for monitoring the health of a capacitor module comprising an array of capacitors is provided. The method may include steps for disabling a charger coupled to an array of capacitors of the capacitor module, determining if the capacitor module is healthy based at least on operating values of the capacitor module, and enabling a write back mode for the memory module if the capacitor module is determined to be healthy. | 2011-07-28 |
20110185212 | DATA PROCESSING SYSTEM HAVING BROWN-OUT DETECTION CIRCUIT - A brown-out detection circuit comprises a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor is of a first conductivity type and has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor is of a second conductivity type and has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal. | 2011-07-28 |
20110185213 | STORAGE MANAGEMENT APPARATUS, STORAGE SYSTEM, AND STORAGE MANAGEMENT METHOD - A storage management apparatus includes a memory for storing logical volume information for indicating logical volumes and priority information for determining an order of the logical volumes to be activated, a first interface for connecting storages to the storage management apparatus, at least one of the storages corresponding to one of the logical volumes, a second interface connected to a power supply unit for supplying power to the storages, and a processor for executing determining whether the power supply unit is capable of supplying power for simultaneously starting the storages corresponding to the logical volumes corresponding to an access request for accessing the logical volumes, selecting one logical volume based on the priority information when the power supply unit is incapable of supplying power for simultaneously starting the storages, and transmitting a start request for staring the storages corresponding to the selected logical volume by using the first interface. | 2011-07-28 |
20110185214 | TIME FORMAT CONVERSION METHOD, DEVICE AND SYSTEM - A method and device for converting between different time domains at a local unit utilizing an processor is disclosed. Time counters to count time in at least two different formats are located locally at each unit. Once a time conversion is initiated, a time stamp is received by the processor and the time counter in the new time domain commences calculating an adjustment count. Once the converted time is received from the processor, the received time plus the adjustment count are summed to provide a time base for the new time domain. The time counters continue counting in their respective time domains after conversion. | 2011-07-28 |
20110185215 | Single-Wire Serial Interface - A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC. | 2011-07-28 |
20110185216 | Time Synchronization Method and System for Multicore System - A time synchronization method and system for a multi-core system are provided. The time synchronization method comprises: establishing at least one clock synchronization domain, and respectively allocating each core to each clock synchronization domain; selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization source in the clock synchronization domain, and selecting the clock synchronization domain having the master clock synchronization source with a lowest load as a master clock synchronization domain, while other clock synchronization domains as slave clock synchronization domains; the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value; when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity and releasing to each slave clock synchronization domain, making adjustment based on its time adjustment quantity. | 2011-07-28 |
20110185217 | Method and Apparatus for the Realization of a Failsafe Time Function - A method for enabling an oscillating crystal available in a system to be used to generate a software-realized time function, and an apparatus for implementing the method, without requiring additional hardware components, wherein a periodic interrupt signal is generated by the system-internal real-time clock, a table entry with a reference to a routine in an intra-system table is accessed upon receipt of the periodic interrupt signal and a counter is formed by the routine. | 2011-07-28 |
20110185218 | Adjustment of Write Timing Based on a Training Signal - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 2011-07-28 |
20110185219 | MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS - A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode. | 2011-07-28 |
20110185220 | REMOTE DIAGNOSTIC SYSTEM AND METHOD BASED ON DEVICE DATA CLASSIFICATION - A remote diagnostic system and method based on device data classification. Device diagnostic data with respect to a device can be acquired and a conditional probability look up table can be constructed for each fault code associated with the device diagnostic data by a classification module. A score function can then be created by summing the conditional probabilities and an occurrence of the fault code can be mapped to a service call category with a numerically highest score function. The fault occurrence data in association with a number of time stamps and device identifiers can be stored in a data warehouse. The occurrence of fault code can be matched with respect to a solution set which can be automatically dispatched to a customer via a communications link. | 2011-07-28 |
20110185221 | FAULT TOLERANT ROUTING IN A NON-HOT-STANDBY CONFIGURATION OF A NETWORK ROUTING SYSTEM - Methods and systems for facilitating fault tolerance in a non-hot-standby configuration of a network routing system are provided. According to one embodiment, a failover method is provided. One or more processing engines of a network routing system are configured to function as active processing engines, each of which having one or more software contexts. A control blade is configured to monitor the active processing engines. One or more of the processing engines are identified to function as non-hot-standby processing engines, each of which having no pre-created software contexts corresponding to the software contexts of the active processing engines. The control blade monitors the active processing engines. Responsive to detecting a fault associated with an active processing engine the active processing engine is dynamically replaced with a non-hot-standby processing engine by creating one or more replacement software contexts within the non-hot-standby processing engine corresponding to those of the active processing engine. | 2011-07-28 |
20110185222 | STORAGE DEVICE, CONTROL DEVICE, AND CONTROL METHOD FOR STORAGE DEVICE - A storage device includes first-storage-module having a storage region for storing data transmitted from a higher-order-device, a plurality of second-storage-module temporarily storing data, reception-processing-module receiving data transmitted from the higher-order-device, first-storage-processing-module storing data received from the higher-order-device in the first-storage-module and storing data received from the higher-order-device in the second-storage-module following the order of reception, data-group-output-module outputting a data group including data stored in each of second-storage-module, data-group-storage-region-securing-module detecting an abnormality in output processing by the data-group-output-module and securing a data-group-storage-region for storing the data group in the first-storage-module or third-storage-module, evacuation-processing-module reading out the data group from the second-storage-module and evacuating to the data-group-storage-region depending on the usage state of the second-storage-module, and second-storage-processing-module storing the data group evacuated to the data-group-storage-region in each storage region of the second-storage-module which have become available due to output processing by the data-group-output-module having been completed. | 2011-07-28 |
20110185223 | Target Operating System and File System Agnostic Bare-Metal Restore - A system, method, and computer program product for performing a bare-metal restore, the system including a target storage device, and a target computer configured to boot independent of the target storage device, expose the target storage device to a restoring computer after the target computer has booted, and act as a conduit for the restoring computer to perform a bare-metal restore of backup data onto the target storage device, and the method including booting a target computer independent of a target storage device, exposing the target storage device to a restoring computer after the target computer has booted, and causing the target computer to act as a conduit for the restoring computer to perform a bare-metal restore of backup data onto the target storage device. | 2011-07-28 |
20110185224 | FLASH STORAGE DEVICE AND DATA PROTECTION METHOD THEREOF - A flash storage device comprises: a memory module, for storing data; a control unit, electrically connected to the memory module, for accessing the data in the memory module; and a detecting unit, electrically connected to the control unit, for passing a temperature detecting result to the control unit, and the control unit determining whether a data protection operation is activated according to the temperature detecting result. | 2011-07-28 |
20110185225 | MEMORY SYSTEM WITH NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued. | 2011-07-28 |
20110185226 | STORAGE SYSTEM AND CONTROL METHODS FOR THE SAME - A RAID group is configured and operated by using multiple storage drives | 2011-07-28 |
20110185227 | METHOD AND SYSTEM FOR VIRTUAL ON-DEMAND RECOVERY FOR REAL-TIME, CONTINUOUS DATA PROTECTION - A data management system or “DMS” provides an automated, continuous, real-time, substantially no downtime data protection service to one or more data sources associated with a set of application host servers. To facilitate the data protection service, a host driver embedded in an application server captures real-time data transactions, preferably in the form of an event journal that is provided to other DMS components. The driver functions to translate traditional file/database/block I/O and the like into a continuous, application-aware, output data stream. The host driver includes an event processor. When an authorized user determines that a primary copy of the data in the host server has become incorrect or corrupted, the event processor can perform a recovery operation to an entire data source or a subset of the data source using former point-in-time data in the DMS. The recovery operation may have two phases. First, the structure of the host data in primary storage is recovered to the intended recovering point-in-time. Thereafter, the actual data itself is recovered. The event processor enables such data recovery in an on-demand manner, in that it allows recovery to happen simultaneously while an application accesses and updates the recovering data. | 2011-07-28 |
20110185228 | REMEDYING METHOD FOR TROUBLES IN VIRTUAL SERVER SYSTEM AND SYSTEM THEREOF - According to the invention, a managing server, using a snapshot-appended information table which stores management information for identifying snapshots of a virtual server, a setting change table which stores setting change information on the virtual server, and a policy table which stores policies to be met by the virtual server, acquires the setting change information from the setting change table, selects the setting change information items from the acquired setting change information matching policies stored in the policy table, acquires management information on the snapshots of the virtual server from the snapshot-appended information table, identifies a snapshot of the virtual server with reference to the acquired management information, changes the identified snapshot of the virtual server based on the selected setting change information items, and rolls back the virtual server according to the changed snapshot. | 2011-07-28 |
20110185229 | FAULT DIAGNOSIS EMPLOYING PROBABILISTIC MODELS AND STATISTICAL LEARNING - A computer implemented fault diagnosis method employing both probabilistic models and statistical learning that diagnoses faults using probabilities and time windows learned during the actual operation of a system being monitored. In a preferred embodiment, the method maintains for each possible root cause fault an a-priori probability that the fault will appear in a time window of specified length as well as maintaining—for each possible resulting symptom(s)—probabilities that the symptom(s) will appear in a time window containing the fault and probabilities that the alarm will not appear in a time window containing the fault. Consequently, the method according to the present invention may advantageously determine—at any time—the probability that a fault has occurred, and report faults which are sufficiently likely to have occurred. These probabilities are updated based upon past time windows in which we have determined fault(s) and their cause(s). Advantageously, each root cause fault may be assigned its own time window length. By maintaining these probability parameters for several different window lengths, a window length that is particularly well-suited to a particular set of conditions may be chosen. | 2011-07-28 |
20110185230 | LEARNING PROGRAM BEHAVIOR FOR ANOMALY DETECTION - A computer-enabled method of learning the behavior of a program. A processor can execute a target program during a learning interval while varying a plurality of stimuli provided to the target program so as to produce a multiplicity of different sequences of events which differ in combinations of types of events in respective sequences, orders in which the types of events occur in respective sequences, or in the combinations and in the orders in which the types of events occur. The multiplicity of event sequences can be recorded, and a second program can be executed by a processor to: determine a plurality of clusters based on similarities between the event sequences in their entirety; and determine a plurality of signatures corresponding to the plurality of clusters. Each signature can be the longest common subsequence of all sequences in the respective cluster and thus representative of the cluster. In such method, each of the plurality of signatures can be a benchmark representative of acceptable behavior of the target program. | 2011-07-28 |
20110185231 | SOFTWARE APPLICATION TESTING - An online marketplace for distributing software applications is established. From the online marketplace, devices are enabled to select respective ones of the software applications and initiate testing of the selected software applications in connection with testing tools operating in respective secure testing environments that shield the devices from potential adverse effects arising from testing the selected software applications. The testing tools generate testing data relating to one or more criteria for certifying the selected software applications. For each of one or more of the selected software applications, a determination is made whether or not to classify the software application as a certified software application based on an evaluation of the testing data generated during the testing of the software applications initiated by a plurality of the devices. | 2011-07-28 |
20110185232 | DYNAMIC CONFIGURATION OF VIRTUAL MACHINES - A computer implemented method for configuring virtual internal networks for testing is provided, such that affects of testing are internally isolated. The method includes deploying a virtual firewall and deploying a public switch enabling access to an external local area network through a first interface of the virtual firewall. A private switch enabling access to a plurality of virtual machines through a second interface of the virtual firewall is provided. The plurality of virtual machines defines a private network behind the firewall. A network address is assigned to the virtual firewall and a private address is assigned to each of the virtual machines. The plurality of virtual machines is then tested through a test launcher in communication with the public switch. | 2011-07-28 |
20110185233 | AUTOMATED SYSTEM PROBLEM DIAGNOSING - Embodiments of the invention relate to automated system problem diagnosing. An index is created with problem description information of previously diagnosed problems, a diagnosis for each problem, and a solution to each diagnosis. System states, traces and logs are extracted from a source system with a new problem. The problem diagnosis system generates problem description information of the new problem from the system states, traces and logs. Problem description information of the new problem is compared with problem description information in the problem description index. A search score is computed for each document in the problem description index. The search score is a measure of similarity between each document in the index and the description of the new problem. A matching score is assigned to each previously diagnosed problems based on the search score. The matching score is a measure of similarity between the new problem and each previously diagnosed problem. The system determines a diagnosis and solution of the new problem based on a diagnosis and solution of one of the previously diagnosed problems. | 2011-07-28 |
20110185234 | SYSTEM EVENT LOGS - An automated method of processing computer system event logs comprises receiving event messages associated with one or more system event logs, each event message including event text, determining a set of message clusters, each comprising a template text, representative of the event messages across the one or more event logs, and assigning each event message to a message cluster of the set, according to a measure of similarity between the respective event text of the event message and the template text of the message cluster. | 2011-07-28 |
20110185235 | APPARATUS AND METHOD FOR ABNORMALITY DETECTION - An abnormality detection apparatus includes: a performance information obtaining unit to obtain load information of a computer; a response time obtaining unit to obtain a response time of the computer; a first abnormality determination unit to determine whether the computer is in abnormal operation state based on the load information; a second abnormality determination unit to determine whether the computer is in abnormal operation state based on the response time, when the first abnormality determination unit determines that the computer is in abnormal operation state; and an abnormality notification unit to perform notification of an abnormality, when the second abnormality determination unit determines that the computer is in abnormal operation state. | 2011-07-28 |
20110185236 | COMMON TROUBLE CASE DATA GENERATING METHOD AND NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING COMMON TROUBLE CASE DATA GENERATING PROGRAM - A method of generating common trouble case data for managing a plurality of systems. The method includes (a) obtaining first identifiers of actual system components and a second identifier of a template from a system data storage unit, (b) obtaining third identifiers of definitional system components from a template data storage unit on the basis of the second identifier, (c) selecting, by a computer, a first identifier subset among the first identifiers on the basis of the third identifiers, and (d) selecting, by the computer, a first trouble case data subset among a plurality of first trouble case data pieces on the basis of the first identifier subset to generate the common trouble case data. In the above (c), the first identifiers of the first identifier subset are identical to the third identifiers. In the above (d), the first trouble case data subset includes the first identifier subset. | 2011-07-28 |
20110185237 | System and Method for Delivering Messages - A system and method for delivering messages are provided. A method for communications device operations includes detecting a failure in a delivery of a message to a first recipient device, determining a second recipient device for the message, and initiating a redelivery of the message to the second recipient device. The first recipient device is formerly registered in a first domain of a communications network or is unavailable in the first domain. | 2011-07-28 |
20110185238 | MICROCOMPUTER, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLIED EQUIPMENT - In plural analog circuits that can operate in parallel and are coupled to a common analog power supply terminal, one analog circuit is controlled in the analog operation start according to timing control data that specifies an interval for suppressing the analog operation start of the one analog circuit in the analog operation cycle of the other analog circuit that has already started the analog operation. The control is conducted so that when the operation of one analog circuit starts, timing when the operation of the one analog circuit is influenced by the analog operation start of the other analog circuits in the operation cycle of the one analog circuit is retained as timing control data in advance, and the analog operation start of the other analog circuits is delayed or temporarily suppressed in synchronization with the operation start of the one analog circuit according to the timing control data. | 2011-07-28 |
20110185239 | SEMICONDUCTOR TESTING APPARATUS AND METHOD - The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened. | 2011-07-28 |
20110185240 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 2011-07-28 |
20110185241 | Method and System for Packet Switch Based Logic Replication - A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels. The destination logic may emulate the source logic synchronized with the plurality of clock domains delayed by the delay period. | 2011-07-28 |
20110185242 | INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES - The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( | 2011-07-28 |
20110185243 | CONTROLLING TWO JTAG TAP CONTROLLERS WITH ONE SET OF JTAG PINS - Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan circuit with a second plurality of control inputs, and a plurality of boundary scan control signals connected to the first plurality of control inputs on the first boundary scan circuit and to the second plurality of control inputs on the second boundary scan circuit. At least two of the plurality of boundary scan control signals are connected between the first boundary scan circuit and the second boundary scan circuit in a crossover fashion. | 2011-07-28 |
20110185244 | Scan test circuit and scan test control method - A semiconductor integrated circuit, includes a control flip-flop for inputting a scan control signal and a scan path chain formed of a plurality of scan storage elements serially connected to each other. The scan path chain performs a shift operation as a first mode when an output of the control flip-flop is a first status value, and performs a normal operation as a second mode when an output of the control flip-flop is a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the plurality of scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the plurality of scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the plurality of scan storage elements at a timing of the scan control signal switching. | 2011-07-28 |
20110185245 | METHOD FOR DETECTING AND CORRECTING ERRORS FOR A MEMORY WHOSE STRUCTURE SHOWS DISSYMMETRICAL BEHAVIOR, CORRESPONDING MEMORY AND ITS USE - To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ⅓. | 2011-07-28 |
20110185246 | METHOD AND APPARATUS FOR CORRECTING DATA POINTS ACQUIRED DURING WELL DRILLING - Described herein are a method, apparatus and computer readable medium for correcting data points acquired during well drilling. The data points are typically stored in a text file that is accessible by a processor. The processor applies one or more tags to the data points, with each of the tags corresponding to a characteristic of the data points. The processor then identifies one or more data faults in the data points using the one or more tags. Each data fault is indicative of inaccurate data in the data points; i.e., data that does not accurately represent the well as drilled. Following identification of the one or more data faults, the processor corrects one or more of the data faults. The resulting corrected, or cleaned, data is more indicative of the well as actually drilled than the uncorrected data. The processor can be connected to a computer readable medium that stores the statements and instructions that the processor executes. | 2011-07-28 |
20110185247 | MASSIVE STRUCTURED DATA TRANSFER OPTIMIZATIONS FOR HIGH-LATENCY, LOW-RELIABILITY NETWORKS - Optimizations for data transmission may be provided. A portion of a data block may be read into a batch by a read thread on a first server. The batch may be passed to a transmission thread. The transmission thread may then transmit the first batch to a second server while the read thread asynchronously reads a second portion of the data block into another batch. | 2011-07-28 |
20110185248 | MAJORITY VOTE ERROR CORRECTION - In general, techniques are described for performing majority vote error correction techniques. In operation, a communication device comprising a control unit implements the majority vote error correction techniques. The control unit includes a link management module to request a first retransmission of a first communication received over a wireless communication medium in response to detecting a first uncorrectable error in the first communication, requests a second retransmission of the first communication in response to detecting a second uncorrectable error in a second communication received in response to the first retransmission request and receives a third communication in response to the second retransmission. The control unit also includes a majority vote module to, in response to detecting a third uncorrectable error in the third communication, perform a bit-wise majority vote on corresponding bits of the first, second and third communications to generate an error-corrected communication. | 2011-07-28 |
20110185249 | Spatial Multiplexing Communication System With Enhanced Codeword Mapping With Flexible Rate Selection On Each Spatial Layer And With Single HARQ Process - A method of data transmission includes encoding an information block according to a predetermined retransmission protocol to generate, for a single hybrid automatic repeat request (HARQ) instance, a transport block having information bits and error detection bits and channel coding different parts of said transport block using different modulation and coding schemes to generate one or more codewords for transmission to a receiving station. | 2011-07-28 |
20110185250 | APPARATUS, METHOD, AND SYSTEM FOR IP ADDRESS NEGOTIATIONS - A wireless communications device for IP address negotiations is provided and comprises a wireless module, a connection device, and a processing unit. The wireless module provides wireless communications from and to a service network. The connection device is coupled to the terminal device. The processing unit is coupled to the connection device and the wireless module, receiving an IP address request message from the terminal device via the connection device, and requests an IP address and a DNS address from the service network via the wireless module in response to an IP address request message from the terminal device. Also, the processing unit determines whether allocated IP address and DNS address have been received from the service network, and sends a rejection message to the terminal device to trigger the terminal device to resend the IP address request message in response to determining that the allocated IP address and DNS address have not been received from the service network. | 2011-07-28 |
20110185251 | SYSTEM AND METHOD TO CORRECT DATA ERRORS USING A STORED COUNT OF BIT VALUES - In a particular embodiment, at a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits. The adjusted group of data bits may be provided to the ECC engine. | 2011-07-28 |
20110185252 | CODING PATTERN COMPRISING MULTI-PPM DATA SYMBOLS WITH DIFFERENT LAYOUTS - A substrate having a coding pattern disposed thereon or therein. The coding pattern comprises a plurality of macrodots encoding first and second Reed-Solomon data symbols. Each first Reed-Solomon data symbol is represented by d macrodots, each of the d macrodots occupying a respective position from a plurality of predetermined possible positions p within a first symbol layout, the respective positions of the d macrodots representing one of a plurality of possible data values. Each second Reed-Solomon data symbol is represented by d macrodots, each of the d macrodots occupying a respective position from a plurality of predetermined possible positions p within a second symbol layout which is different than the first symbol layout, the respective positions of the d macrodots representing one of a plurality of possible data values. | 2011-07-28 |
20110185253 | DIRECTORY FILE SYSTEM IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a data storage request, wherein the data storage request includes data and a data identifier (ID). The method continues with the processing module dispersed storage error encoding the data to produce a set of encoded data slices and determining a data dispersed storage network (DSN) address. The method continues with the processing module sending the set of encoded data slices to a DSN memory for storage at the data DSN address and updating a directory file with path information corresponding to the data ID and the data DSN address to produce an updated directory file. The method continues with the processing module dispersed storage error encoding the updated directory file to produce a set of encoded updated directory slices and sending the set of encoded updated directory slices to the DSN memory for storage at a directory DSN address. | 2011-07-28 |