30th week of 2017 patent applcation highlights part 51 |
Patent application number | Title | Published |
20170213746 | SEALING STRUCTURE FOR A BONDED WAFER AND METHOD OF FORMING THE SEALING STRUCTURE | 2017-07-27 |
20170213747 | ION TO NEUTRAL CONTROL FOR WAFER PROCESSING WITH DUAL PLASMA SOURCE REACTOR | 2017-07-27 |
20170213748 | METHOD FOR THE RAPID PROCESSING OF POLYMER LAYERS IN SUPPORT OF IMIDIZATION PROCESSES AND FAN OUT WAFER LEVEL PACKAGING INCLUDING EFFIECIENT DRYING OF PRECURSOR LAYERS | 2017-07-27 |
20170213749 | HIGH PRODUCTIVITY SOAK ANNEAL SYSTEM | 2017-07-27 |
20170213750 | SYSTEMS AND METHODS FOR DETECTING THE EXISTENCE OF ONE OR MORE ENVIRONMENTAL CONDITIONS WITHIN A SUBSTRATE PROCESSING SYSTEM | 2017-07-27 |
20170213751 | PLASMA PROCESSING APPARATUS AND HEATER TEMPERATURE CONTROL METHOD | 2017-07-27 |
20170213752 | SUBSTRATE STORAGE CONTAINER | 2017-07-27 |
20170213753 | CONTROLLING THE RF AMPLITUDE OF AN EDGE RING OF A CAPACITIVELY COUPLED PLASMA PROCESS DEVICE | 2017-07-27 |
20170213754 | ELECTROSTATIC CHUCK WITH EXTERNAL FLOW ADJUSTMENTS FOR IMPROVED TEMPERATURE DISTRIBUTION | 2017-07-27 |
20170213755 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2017-07-27 |
20170213756 | WAFER PROCESSING METHOD | 2017-07-27 |
20170213757 | BASE FILM FOR SHEETS FOR SEMICONDUCTOR WAFER PROCESSING, SHEET FOR SEMICONDUCTOR WAFER PROCESSING, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES | 2017-07-27 |
20170213758 | WAFER EDGE RING LIFTING SOLUTION | 2017-07-27 |
20170213759 | WAFER SUPPORTING STRUCTURE, AND DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR | 2017-07-27 |
20170213760 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT | 2017-07-27 |
20170213761 | Semiconductor Devices Including a Diode Structure Over a Conductive Strap and Methods of Forming Such Semiconductor Devices | 2017-07-27 |
20170213762 | PROCESS AND CHEMISTRY OF PLATING OF THROUGH SILICON VIAS | 2017-07-27 |
20170213763 | Cu WIRING MANUFACTURING METHOD AND Cu WIRING MANUFACTURING SYSTEM | 2017-07-27 |
20170213764 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213765 | DIE BONDING/DICING SHEET | 2017-07-27 |
20170213766 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 2017-07-27 |
20170213767 | HYBRID FIN CUT ETCHING PROCESSES FOR PRODUCTS COMPRISING TAPERED AND NON-TAPERED FINFET SEMICONDUCTOR DEVICES | 2017-07-27 |
20170213768 | TECHNIQUE FOR FILLING HIGH ASPECT RATIO, NARROW STRUCTURES WITH MULTIPLE METAL LAYERS AND ASSOCIATED CONFIGURATIONS | 2017-07-27 |
20170213769 | SEMICONDUCTOR STRUCTURE AND MANUFACUTING METHOD OF THE SAME | 2017-07-27 |
20170213770 | FINFET GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME | 2017-07-27 |
20170213771 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 2017-07-27 |
20170213772 | METHOD AND STRUCTURE FOR FORMING DIELECTRIC ISOLATED FINFET WITH IMPROVED SOURCE/DRAIN EPITAXY | 2017-07-27 |
20170213773 | WAFER ARRANGEMENT, A METHOD FOR TESTING A WAFER, AND A METHOD FOR PROCESSING A WAFER | 2017-07-27 |
20170213774 | PACKAGE WAFER PROCESSING METHOD | 2017-07-27 |
20170213775 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213776 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213777 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213778 | SEMICONDUCTOR DEVICE AND ELECTRONIC COMPONENT USING THE SAME | 2017-07-27 |
20170213779 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213780 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF | 2017-07-27 |
20170213781 | INTEGRATED CIRCUIT PACKAGE | 2017-07-27 |
20170213782 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213783 | MULTI-CHIP SEMICONDUCTOR POWER PACKAGE | 2017-07-27 |
20170213784 | LEADFRAME STRIP WITH VERTICALLY OFFSET DIE ATTACH PADS BETWEEN ADJACENT VERTICAL LEADFRAME COLUMNS | 2017-07-27 |
20170213785 | METHOD OF FORMING SOLDER BUMPS ON SOLID STATE MODULE INCLUDING PRINTED CIRUCUIT BOARD | 2017-07-27 |
20170213786 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2017-07-27 |
20170213787 | INTERPOSER WITH BEYOND RETICLE FIELD CONDUCTOR PADS | 2017-07-27 |
20170213788 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2017-07-27 |
20170213789 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213790 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME | 2017-07-27 |
20170213791 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME | 2017-07-27 |
20170213792 | FABRICATION OF IC STRUCTURE WITH METAL PLUG | 2017-07-27 |
20170213793 | NOVEL EMBEDDED PACKAGES | 2017-07-27 |
20170213794 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2017-07-27 |
20170213795 | SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP PROPERTIES | 2017-07-27 |
20170213796 | Electronic chip inspection by backside illumination | 2017-07-27 |
20170213797 | SHIELDED QFN PACKAGE AND METHOD OF MAKING | 2017-07-27 |
20170213798 | FORMING LARGE CHIPS THROUGH STITCHING | 2017-07-27 |
20170213799 | PRINTED WIRING BOARD | 2017-07-27 |
20170213800 | Method of Manufacturing a Semiconductor Package Having a Semiconductor Chip and a Microwave Component | 2017-07-27 |
20170213801 | METHOD FOR MANUFACTURING A PACKAGE-ON-PACKAGE ASSEMBLY | 2017-07-27 |
20170213802 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 2017-07-27 |
20170213803 | Methods for Surface Attachment of Flipped Active Components | 2017-07-27 |
20170213804 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME | 2017-07-27 |
20170213805 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME | 2017-07-27 |
20170213806 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213807 | TUNGSTEN LAYER PASSIVATION PROCESS AND DIRECT BONDING PROCESS | 2017-07-27 |
20170213808 | Dual-Sided Integrated Fan-Out Package | 2017-07-27 |
20170213809 | Sawing Underfill in Packaging Processes | 2017-07-27 |
20170213810 | FABRICATING METHOD FOR WAFER-LEVEL PACKAGING | 2017-07-27 |
20170213811 | HIGH PERFORMANCE POWER MODULE | 2017-07-27 |
20170213812 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213813 | COMPOSITE LIGHT HARVESTING MATERIAL AND DEVICE | 2017-07-27 |
20170213814 | Implant Structure for Area Reduction | 2017-07-27 |
20170213815 | OPTIMIZED CONFIGURATIONS TO INTEGRATE STEERING DIODES IN LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) | 2017-07-27 |
20170213816 | ELECTROSTATIC DISCHARGE PROTECTION WITH INTEGRATED DIODE | 2017-07-27 |
20170213817 | ESD CENTRIC LOW-COST IO LAYOUT DESIGN TOPOLOGY | 2017-07-27 |
20170213818 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT | 2017-07-27 |
20170213819 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | 2017-07-27 |
20170213820 | DECOUPLING CAPACITOR ON STRAIN RELAXATION BUFFER LAYER | 2017-07-27 |
20170213821 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE | 2017-07-27 |
20170213822 | Semiconductor Device Structure and Method | 2017-07-27 |
20170213823 | SEMICONDUCTOR DEVICE AND A FABRICATING METHOD THEREOF | 2017-07-27 |
20170213824 | FIN-DOUBLE-GATED JUNCTION FIELD EFFECT TRANSISTOR | 2017-07-27 |
20170213825 | PITCH SCALABLE ACTIVE AREA PATTERNING STRUCTURE & PROCESS FOR MULTI-CHANNEL FIN FET TECHNOLOGIES | 2017-07-27 |
20170213826 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | 2017-07-27 |
20170213827 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213828 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF | 2017-07-27 |
20170213829 | SEMICONDUCTOR STRUCTURES | 2017-07-27 |
20170213830 | Tuning Tensile Strain on FinFET | 2017-07-27 |
20170213831 | OPERATIONAL AMPLIFIER CIRCUIT | 2017-07-27 |
20170213832 | SEMICONDUCTOR DEVICE | 2017-07-27 |
20170213833 | SEMICONDUCTOR DEVICE AND MEMORY DEVICE | 2017-07-27 |
20170213834 | SEMICONDUCTOR MEMORY DEVICE HAVING ENLARGED CELL CONTACT AREA AND METHOD OF FABRICATING THE SAME | 2017-07-27 |
20170213835 | SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE | 2017-07-27 |
20170213836 | VERTICAL GATE-ALL-AROUND TFET | 2017-07-27 |
20170213837 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING ENLARGED CELL CONTACT AREA | 2017-07-27 |
20170213838 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF | 2017-07-27 |
20170213839 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 2017-07-27 |
20170213840 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME | 2017-07-27 |
20170213841 | INTER-DIGITATED CAPACITOR IN SPLIT-GATE FLASH TECHNOLOGY | 2017-07-27 |
20170213842 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME | 2017-07-27 |
20170213843 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2017-07-27 |
20170213844 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2017-07-27 |
20170213845 | SEMICONDUCTOR MEMORY DEVICE HAVING PILLARS ON A PERIPHERAL REGION AND METHOD OF MANUFACTURING THE SAME | 2017-07-27 |