30th week of 2018 patent applcation highlights part 57 |
Patent application number | Title | Published |
20180212001 | PIXEL STRUCTURE, FABRICATION METHOD THEREOF, DISPLAY PANEL, AND DISPLAY APPARATUS - The present disclosure provides a pixel structure and a fabricating method thereof, as well as a display panel and a display apparatus. The pixel structure includes a plurality of pairs of pixels in a matrix having rows and columns; each pixel is shaped as a right triangle and corresponds to one of four different colors; each pair of pixels is at an intersection between a row and a column and comprises two pixels of different colors; and two pairs of pixels at two neighboring intersections along a direction of the rows or along a direction of the columns comprise four pixels of different colors. Each pair of pixels can have a combined shape of a rectangle, which can form a virtual pixel unit. Adjacent four pixels of four different colors have a combined shape of diamond, which can form a physical pixel unit. | 2018-07-26 |
20180212002 | METHOD FOR MANUFACTURING DISPLAY SUBSTRATE, DISPLAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure discloses a method for manufacturing a display substrate, a display substrate and a display device. The method includes forming an organic thin film layer on a base substrate at a region which corresponds to a non-display region of a to-be-formed display substrate, printing an organic functional layer on the base substrate, and removing the organic functional layer at the non-display region by peeling off the organic thin film layer. | 2018-07-26 |
20180212003 | Organic Electronic Component - An organic electronic component and a method for making an organic electronic component are disclosed. In an embodiment the component includes an anode, an active layer arranged above the anode, an electron injection layer arranged above the active layer and a cathode arranged above the electron injection layer. The electron injection layer further comprises a first organic layer comprising a first organic matrix material, a second organic layer comprising a second organic matrix material and a metallic layer, wherein the first organic matrix material has a higher electron conductivity than the second organic matrix material. | 2018-07-26 |
20180212004 | DISPLAY DEVICE - A display device capable of suppressing rapid degradation of a lifespan. The display device ( | 2018-07-26 |
20180212005 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate in a same layer as the anode electrode; a partition supporter on the auxiliary electrode; a partition on the partition supporter; an organic emitting layer on the anode electrode and on the partition such that portions separated on the partition are separated from other portions; and a cathode electrode connected with the organic emitting layer and the auxiliary electrode. A lower surface of the partition supporter includes a pair of short sides; and a pair of long sides connecting the pair of short sides and including at least one inclined surface. | 2018-07-26 |
20180212006 | Light Emitting Device and Electronic Device - Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are fowled over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element faulted over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof. | 2018-07-26 |
20180212007 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate; an organic emission layer on the anode electrode; a cathode electrode on the organic emission layer and on the auxiliary electrode; an insulating bank on the auxiliary electrode, the bank overlapping a first portion of the auxiliary electrode and exposing a second portion of the auxiliary electrode; a first partition wall on the auxiliary electrode; a second partition wall on the first partition wall and covering the exposed second portion of the auxiliary electrode in plan view. A separation space is between the second partition wall and the bank, the cathode electrode is electrically connected to the auxiliary electrode through the separation space between the second partition wall and the bank, and the second partition wall is supported by the first partition wall and the bank. | 2018-07-26 |
20180212008 | TOP-EMITTING OLED DISPLAY UNIT, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY PANEL - Disclosed are a top-emitting OLED display unit, a method for manufacturing the same, and a display panel. The top-emitting OLED display unit includes a first electrode serving as a common electrode, a light-emitting material layer disposed above the first electrode, and a second electrode disposed above the light-emitting material layer, the second electrode serving as a pixel electrode. A manufacture process of the first electrode and the second electrode can be simplified by means of the OLED display unit, and it is beneficial for reducing consumption of electrode materials. | 2018-07-26 |
20180212009 | DISPLAY DEVICE - A display device in an embodiment according to the present invention includes a display region above a first substrate, the display region includes, a plurality of a pixels, a transistor arranged to each of the plurality of the pixels, a light emitting element arranged to each of plurality of the pixels, an interlayer insulating layer above the transistor, and a planarization film above the inter layer insulating layer, a terminal region above the first substrate in a periphery region of the display region, the terminal region including, a plurality of terminals, each of which includes a first conductive layer above the interlayer insulating layer, the planarization film is arranged in a side part of the first conductive layer, and an inorganic insulating layer covering an upper surface of planarization film and an end part of the first conductive layer. | 2018-07-26 |
20180212010 | ARRAY SUBSTRATE OF OLED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an array substrate of an OLED display device is provided. Active areas of a first thin film transistor T | 2018-07-26 |
20180212011 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - The present disclosure provides an array substrate, its manufacturing method, and a display apparatus. The array substrate includes a monocrystalline silicon layer and an array circuit layer. The array circuit layer is disposed over the monocrystalline silicon layer. The array circuit layer comprises a scan drive circuit, a data drive circuit, and a plurality of pixel circuits. The scan drive circuit and the data drive circuit are configured to respectively control a plurality of scan lines and a plurality of data lines to in turn drive a plurality of pixels. Each of the plurality of pixel circuits is configured to drive one of the plurality of pixels to emit light under control of at least one of the plurality of scan lines and at least one of the plurality of data lines; and the scan drive circuit, the data drive circuit, and the plurality of pixel circuits comprise a plurality of thin film transistors (TFTs), each having an active region disposed in the monocrystalline silicon layer. | 2018-07-26 |
20180212012 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display includes: a substrate; a scan line formed over the substrate and transmitting a scan signal; a data line crossing the scan line and transmitting a data voltage; a driving voltage line crossing the scan line and transmitting a driving voltage; a switching transistor connected to the scan line and the data line; a driving transistor connected to the switching transistor; a driving connection member connected to a driving gate electrode of the driving transistor; a storage capacitor including a first storage electrode and a second storage electrode; a pixel electrode electrically connected to the driving transistor; and a contact hole connecting the first storage electrode and the driving connection member. The second storage electrode may include a cut-out by a curved edge at least partially surrounding the contact hole, and the pixel electrode may be formed not to overlap the cut-out. | 2018-07-26 |
20180212013 | DOUBLE-SIDED OLED DISPLAY DEVICE - A double-sided OLED display device is provided. The double-sided OLED display device has a first display element, a second display element, a first sealing layer, and a second sealing layer. The first display element is disposed on an upper side of the second display element, and the light-emitting direction of the first display element and the second display element are opposite. The first sealing layer is disposed on an upper side of the first display element, and the second sealing layer is disposed on a lower side of the second display element. Thus, the first display element and the second display element are sealed and packaged by the first sealing layer and the second sealing layer. | 2018-07-26 |
20180212014 | DISPLAY DEVICE INCLUDING AN EMISSION LAYER - A display device includes pixels, scan lines, and data lines. A first driving gate electrode is disposed at a first pixel of the display device. A second driving gate electrode is disposed at a second pixel of the display device. A first driving voltage line includes a first extending part that overlaps a first driving gate electrode. A second driving voltage line includes a second extending part that overlaps a second driving gate electrode. A first pixel electrode of the first pixel overlaps the second driving gate electrode. The second extending part includes a first recess portion. A center line of the first recess portion is offset in a direction away from the first pixel electrode with respect to a center line of the second driving gate electrode. | 2018-07-26 |
20180212015 | DISPLAY PANEL AND DISPLAY DEVICE - Disclosed are a display panel and a display device. The display panel includes an active area and two GOA driving circuit areas which are respectively arranged on a right side and a left side of the active area, wherein the display panel is bent along bending positions formed by gaps between the active area and each of the GOA driving circuit areas. Performance of metal lines at the bending positions can be improved and the display panel has an ultra-narrow frame. | 2018-07-26 |
20180212016 | DISPLAY DEVICE INCLUDING AN EMISSION LAYER - A display device includes a scan line extending in a first direction. A plurality of data lines cross the scan line. A driving voltage line crosses the scan line. An active pattern includes a plurality of channel regions and a plurality of conductive regions. A control line is connected to the plurality of data lines and the driving voltage line. The active pattern includes a shielding part overlapping at least one data line of the plurality of data lines. The control line includes a plurality of main line parts each extending in the first direction, and a detour part connecting two adjacent main line parts of the plurality of main line parts to each other. The detour part extends along a periphery of the active pattern and crosses the at least one data line of the plurality of data lines. | 2018-07-26 |
20180212017 | NANOSHEET CAPACITOR - A capacitive device includes a first electrode comprising a nanosheet stack, and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact arranged on a basal end of the second electrode. | 2018-07-26 |
20180212018 | LEAKAGE CURRENT REDUCTION IN STACKED METAL-INSULATOR-METAL CAPACITORS - Capacitors and methods of forming the same include forming an oxygenated dielectric layer on a first conductive layer. A second conductive layer is formed on the oxygenated dielectric layer. The oxygenated dielectric layer is heated to release the oxygen from the oxygenated dielectric layer and to oxidize the first and second conductive layers at interfaces between the dielectric layer and the first and second conductive layers, forming barrier layers at the interfaces. | 2018-07-26 |
20180212019 | CONFORMAL CAPACITOR STRUCTURE FORMED BY A SINGLE PROCESS - A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas. | 2018-07-26 |
20180212020 | LEVEL SHIFTER AND SEMICONDUCTOR DEVICE - A level shifter is provided. The level shifter is located between a high-side circuit area and a low-side circuit area and includes a substrate, a buried island, and an isolation structure. The buried island has a first conductivity type and is located in the substrate. The isolation structure has a second conductivity type, is located in the substrate and surrounds the buried island. In addition, a dimension of the isolation structure near the high-side circuit area is different from a dimension of the isolation structure near the low-side circuit area. A semiconductor device including the level shifter is also provided. | 2018-07-26 |
20180212021 | HIGH-VOLTAGE SUPERJUNCTION FIELD EFFECT TRANSISTOR - In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side. The first device side comprises a column of a second type in contact with the first column, the substrate, and the first surface of the device; a second column of the first type in contact with the substrate and the second column; a third column of the first type in contact with the substrate and the second column; a first region of the first type disposed in contact with the third column; a second region of the first type disposed in contact with the source and with a third region of the first type; and a first trench comprising the second type and a first region of the second type, wherein the first region of the second type is in contact with a gate region. | 2018-07-26 |
20180212022 | INTEGRATED SCHOTTKY DIODE IN HIGH VOLTAGE SEMICONDUCTOR DEVICE - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions. | 2018-07-26 |
20180212023 | HYBRID TRIGATE AND NANOWIRE CMOS DEVICE ARCHITECTURE - Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate. | 2018-07-26 |
20180212024 | STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB) - A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack. | 2018-07-26 |
20180212025 | III-N Based Substrate for Power Electronic Devices and Method for Manufacturing Same - The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices. | 2018-07-26 |
20180212026 | SURFACE MODIFIED DIAMOND MATERIALS AND METHODS OF MANUFACTURING - New compositions of matter and device constructs are disclosed in the form of diamond material layers or films having one or more surfaces treated with chemically active radicals, e.g., photo-radical or thermal-radical generators to reduce and stabilize their surface resistance. The compositions exhibit stable, markedly lower surface resistances, e.g., below about 3 kΩ sq | 2018-07-26 |
20180212027 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device can include: a substrate having a semiconductor material; a plurality of semiconductor layers of a first conductivity type, and being sequentially stacked on the substrate, where a doping concentration of the semiconductor layers successively increases from bottom to top; a trench that extends from the surface of a topmost semiconductor layer into a bottommost semiconductor layer of the semiconductor layers; a plurality of field plates that correspond to the semiconductor layers, each field plate being located in a portion of the trench that corresponds to one of the semiconductor layers; and a trench pad located in a bottom and a sidewall of the trench, and being filled each space between two adjacent field plates, where the thickness of the trench pad between each field plate and corresponding semiconductor layer sequentially decreases from the bottom to the top. | 2018-07-26 |
20180212028 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film. | 2018-07-26 |
20180212029 | SEMICONDUCTOR DEVICES EMPLOYING REDUCED AREA CONFORMAL CONTACTS TO REDUCE PARASITIC CAPACITANCE, AND RELATED METHODS - Semiconductor devices employing reduced area conformal contacts for reducing parasitic capacitance and improving performance, and related methods are disclosed. The area of the source/drain contacts for providing an electrical contract to a source/drain is reduced in size to reduce parasitic capacitance between a gate and the source/drain contacts for improved performance. To mitigate or avoid increase in contact resistance between the source/drain contacts and source/drain, a conformal contact layer of a desired thickness is disposed adjacent to the source/drain to reduce the source/drain contact resistance. Thus, the source/drain contacts may only have to extend down adjacent to an upper region of the source/drain to still achieve a desired, lower contact resistance with the source/drain contacts, which results in a reduced area source/drain contact for reducing parasitic capacitance. | 2018-07-26 |
20180212030 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer. | 2018-07-26 |
20180212031 | Semiconductor Device Having Silicide Layers - A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer. | 2018-07-26 |
20180212032 | CONDUCTIVE LAYER, THIN FILM TRANSISTOR AND MANUFACTURING METHODS THEREFOR, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure relates to a conductive layer, a thin film transistor and manufacturing methods therefor, an array substrate and a display device, in the field of displays. The conductive layer comprises: a metal layer and an organophosphorus-metal complex covering the metal layer. In the embodiments of the present disclosure, the organophosphorus-metal complex is manufactured on the surface of the metal layer to form the conductive layer. The conductive layer is adopted as an electrode material. In one aspect, the organophosphorus-metal complex has conductivity and can prevent the surface of metal from making contact with oxygen, thereby avoiding metal oxidation under the premise of not affecting the performances of the electrode when serving as a material of the electrode in a TFT. In the other aspect, the organophosphorus-metal complex can increase a binding force between the metal and photoresist and avoids stripping of the photoresist. Therefore, etching liquid is prevented from etching the metal in a position without the need of etching. The conductive layer provided by the present disclosure has the performances in the above two aspects. Therefore, the stability and electronic transmission performances of the electrode can be improved by adopting such a conductive layer to manufacture the electrode of the thin film transistor. | 2018-07-26 |
20180212033 | THIN FILM TRANSISTOR - A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a nano-scale semiconductor structure. | 2018-07-26 |
20180212034 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A COBALT SILICIDE FILM - A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film. | 2018-07-26 |
20180212035 | Integrated strained stacked nanosheet FET - Methods of forming a semiconductor device include forming stress liners in contact with both ends of a fin of alternating channel material and sacrificial material layers. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack on the suspended layers of channel material. | 2018-07-26 |
20180212036 | Polysilicon Design for Replacement Gate Technology - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 2018-07-26 |
20180212037 | APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES - A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner. | 2018-07-26 |
20180212038 | SELF-LIMITED INNER SPACER FORMATION FOR GATE-ALL-AROUND FIELD EFFECT TRANSISTORS - A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material. | 2018-07-26 |
20180212039 | SELF-LIMITED INNER SPACER FORMATION FOR GATE-ALL-AROUND FIELD EFFECT TRANSISTORS - Methods of forming a semiconductor device include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material. | 2018-07-26 |
20180212040 | APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES - A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner. | 2018-07-26 |
20180212041 | DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT - Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region. | 2018-07-26 |
20180212042 | LDMOS POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Methods are directed to forming an electronic semiconductor device that includes a body having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side. A body region extends in the second structural region at the first side. A source region extends inside the body region and a lightly-doped drain region faces the first side of the body. A gate electrode is formed over the body region. A trench dielectric region extends through the second structural region in a first trench conductive region immediately adjacent to the trench dielectric region. A second trench conductive region is in electrical contact with the body region and source region. An electrical contact on the body is in electrical contact with the drain region through the first structural region. | 2018-07-26 |
20180212043 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - Disclosed is a method for manufacturing a thin film transistor. The method includes steps of etching a second metal layer and a semiconductor layer to form a boundary region of a thin film transistor; etching the second metal layer again to form a source, a drain and a back channel region of the thin film transistor; removing residual photoresist via an ashing procedure; and etching the semiconductor layer again to form a conductive channel of the thin film transistor. According to the method, the electric leakage problem of thin film transistor due to diffusion of copper and contamination of organic stripping liquid can be eliminated. | 2018-07-26 |
20180212044 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a gate stack over a semiconductor fin such that the gate stack exposes the semiconductor fin. The semiconductor fin exposed by the gate stack is recessed. An epitaxy structure is epitaxially grown on a recessed portion of the semiconductor fin, and the epitaxy structure is etched such that the epitaxy structure has a curved top. | 2018-07-26 |
20180212045 | CONTINUOUS CRYSTALLINE GALLIUM NITRIDE (GaN) PN STRUCTURE WITH NO INTERNAL REGROWTH INTERFACES - A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region. | 2018-07-26 |
20180212046 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and an intermediate region. A position of the first electrode is between a position of the second electrode and a position of the third electrode. The first semiconductor region is separated from the first, second, and third electrodes. The second semiconductor region is provided between the second electrode and the first semiconductor region. The third semiconductor region is provided between the third electrode and the first semiconductor region. The intermediate region includes at least one of a first compound or a second compound. At least a portion of the first electrode is positioned between the second and third semiconductor regions. The intermediate region includes a first partial region, a second partial region, and a third partial region. | 2018-07-26 |
20180212047 | GROUP III-V DEVICE STRUCTURE - A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode. | 2018-07-26 |
20180212048 | TRANSISTOR STRUCTURE WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING IMMUNITY - A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element. | 2018-07-26 |
20180212049 | INTEGRATED CIRCUIT AND CODE GENERATING METHOD - An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table. | 2018-07-26 |
20180212050 | THIN FILM TRANSISTOR, GATE DRIVE ON ARRAY AND DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF - The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a first semiconductor region, a second semiconductor region, and a plurality of semiconductor bridges each of which connecting the first semiconductor region and the second semiconductor region; the plurality of semiconductor bridges spaced apart from each other; the active layer being made of a material including M1O | 2018-07-26 |
20180212051 | CONDUCTIVE LAYER STRUCTURES FOR SUBSTRATES - An example substrate includes a surface, a plurality of thin film layers disposed on the surface, and a conductive layer disposed on the surface. The conductive layer includes a bending structure. The bending structure includes a plurality of openings, where a shape of at least one opening of the plurality of openings has a first curved portion. | 2018-07-26 |
20180212052 | POWER CHIP AND STRUCTURE OF TRANSISTOR - A power chip and a transistor structure thereof are provided. The transistor structure includes a semiconductor substrate, a plurality of gate structures, a plurality of first doped regions and a second doped region. The gate structures are disposed on the semiconductor substrate. The first doped regions are formed respectively in a plurality of first areas surrounded by the gate structures. The second doped region is formed in a second area among the gate structures. Each of the gate structures is arranged in an enclosed ring, and the shape of each of the gate structures is octagon. | 2018-07-26 |
20180212053 | LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICE AND MANUFACTURE THEREOF - A Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device and its manufacturing method are presented. The LDMOS device comprises a first region that has a first conductivity type; a drift region that has a second conductivity type in the first region, wherein the second conductivity type is opposite to the first conductivity type; and a plurality of second regions that have the first conductivity type in the drift region, wherein the second regions are separated from each other and extend to the first region along a depth direction of the drift region. This LDMOS device has an higher Breakdown Voltage and thus better performance than conventional LDMOS devices. | 2018-07-26 |
20180212054 | VERTICAL TRANSISTOR WITH ENHANCED DRIVE CURRENT - A stacked vertical field effect transistor that has enhanced drive current is provided. The stacked vertical field effect transistor includes a lower functional gate structure located adjacent sidewall surfaces of a lower channel portion of a semiconductor channel material pillar. An upper functional gate structure is located above the lower functional gate structure and adjacent sidewall surfaces of an upper channel portion of the semiconductor channel material pillar. A bottom source/drain region is located beneath the lower functional gate structure, a middle source/drain region is located between the lower functional gate structure and the upper functional gate structure, and a top source/drain region is located above the upper functional gate structure. | 2018-07-26 |
20180212055 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape. | 2018-07-26 |
20180212056 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY DEFORMATION OF BURIED INSULATOR INDUCED BY BURIED STRESSOR - Etching trench isolation structures into a semiconductor structure that includes an upper thin semiconductor layer disposed over a buried insulator layer and a buried compressively strained stressor layer under the buried insulator layer, the compressively strained stressor layer being disposed on an underlying semiconductor substrate, causes edge relaxation of the compressively strained stressor layer. The edge relaxation results in the buried insulation layer being deformed, thus inducing tensile strain in an upper surface of the thin semiconductor layer across at least a first portion of a lateral extent of the thin semiconductor layer between walls of one or more trenches formed by the etching. | 2018-07-26 |
20180212057 | DEEP EPI ENABLED BY BACKSIDE REVEAL FOR STRESS ENHANCEMENT & CONTACT - Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region. | 2018-07-26 |
20180212058 | COMPACT OTP/MTP TECHNOLOGY - Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate. | 2018-07-26 |
20180212059 | THIN FILM TRANSISTOR, DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF - The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer. | 2018-07-26 |
20180212060 | ELECTRONIC DEVICE INCLUDING LIGHT DETECTION DEVICE AND OPERATION METHOD THEREOF - An electronic device is disclosed and includes a housing; a display that is exposed through one surface of the housing; a light emitting unit that is disposed on at least a part of a rear surface of the display and includes at least one light source for outputting light of at least one wavelength band; a light receiving unit that includes at least one area for receiving light of the at least one wavelength band; a light blocking element for blocking light, that is output from the at least one light source, from entering a switch for turning on/off at least one pixel of the display; a processor electrically connected with the display, the light emitting unit, and the light receiving unit; and a memory electrically connected with the processor, in which the memory includes instructions that cause, when executed, the processor to output light through the at least one light source in a state where one or more pixels included in a specific area of the display, which includes an area covering the at least one light source, are turned off or displayed in a specific color. | 2018-07-26 |
20180212061 | DUAL GATE OXIDE THIN-FILM TRANSISTOR AND MANUFACTURING METHOD FOR THE SAME - A dual gate oxide thin-film transistor and manufacturing method for the same. The thin-film transistor comprises: a substrate; a bottom gate electrode formed on the substrate; a first gate insulation layer disposed on the bottom gate electrode; a semiconductor layer formed on the first gate insulation layer; a second gate insulation layer formed on the semiconductor layer; and a top gate electrode formed on the second gate insulation layer; wherein, the transistor further comprises a data line, the data line and the bottom gate electrode, or the data line and the top gate electrode are located at a same metal layer. Because the data line and the bottom gate (or the top gate) electrodes are located at a same metal layer, and through one photolithography for patterning to reduce the number of the mask, decrease the production cost. Besides, the stability and the response speed are increased. | 2018-07-26 |
20180212062 | COPLANAR DOUBLE GATE ELECTRODE OXIDE THIN FILM TRANSISTOR AND MANUFACTURE METHOD THEREOF - The present disclosure relates to a coplanar double gate electrode oxide thin film transistor, includes a substrate, a bottom gate electrode, a first gate electrode insulating layer, a oxide semiconductor layer, a source electrode contact area and a drain electrode contact area, a second gate electrode insulating layer and a top gate electrode, wherein, the upper surface of the substrate is recessed toward the inside of the substrate to form a groove, the bottom gate electrode is formed in the groove, so that the upper surface of the bottom gate electrode and the upper surface of the substrate are in the same horizontal plane. The thin film transistor of the present disclosure has the characteristics of the double gate electrode and the coplanar structure, and is capable of improving the stability of the thin film transistor, optimizing the response speed thereof, and lowering the driving voltage. | 2018-07-26 |
20180212063 | LOW TEMPERATURE POLYSILICON ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a low temperature polysilicon array substrate and its manufacturing method. The method includes: forming a light-shielding layer, a buffer layer and U-type polysilicon patterns successively on a glass substrate; doping channels of the U-type polysilicon patterns in the active area and then heavily N+ doping these U-type polysilicon patterns; forming a gate insulation layer and etching first via holes; forming a gate line, a source and lightly-doped regions of the N-type double-gate transistor; and heavily P+ doping U-type polysilicon patterns in the non-active area. | 2018-07-26 |
20180212064 | LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a liquid crystal display panel and a method for manufacturing the same. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer. | 2018-07-26 |
20180212065 | Thin Film Transistor And Method Of Manufacturing Thin Film Transistor - Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask. | 2018-07-26 |
20180212066 | METHOD OF FABRICATING ELECTROSTATICALLY ENHANCED FINS AND STACKED NANOWIRE FIELD EFFECT TRANSISTORS - Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate. | 2018-07-26 |
20180212067 | SEMICONDUCTOR DEVICE - A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets. | 2018-07-26 |
20180212068 | THIN FILM TRANSISTOR - A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a nano-scale semiconductor structure. The second electrode is located on the second end. | 2018-07-26 |
20180212069 | SCHOTTKY DIODE AND METHOD FOR MAKING THE SAME - A Schottky diode includes an insulating substrate and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating substrate. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating substrate. The semiconducting structure is nano-scale semiconductor structure. The second electrode is located on the second end. | 2018-07-26 |
20180212070 | SCHOTTKY DIODE - A Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode includes a first metal layer and a second metal layer. The second electrode includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure is a nano-scale semiconductor structure. | 2018-07-26 |
20180212071 | JUNCTION BARRIER SCHOTTKY DIODE WITH ENHANCED SURGE CURRENT CAPABILITY - A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer having a first main side and a second main side opposite to the first main side. The semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 μm and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer. The at least one pilot region is connected to the transition region by the plurality of stripe-shaped emitter regions. | 2018-07-26 |
20180212072 | MANUFACTURING METHOD FOR SOLAR CELL AND SOLAR CELL - In a manufacturing method for a solar cell, the solar cell includes: a solar cell substrate; and first and second collection electrodes formed on the solar cell substrate. At least one of the first and second collection electrodes includes: grid electrodes formed in a distributed manner over a whole surface of the solar cell substrate; and a bus electrode that is in contact with the grid electrodes and from which current is drawn. The method comprises forming a shape pattern of the bus electrode and the grid electrodes by performing a screen printing a plurality of times in such a manner that the bus electrode is divided in a longitudinal direction and that the divided bus electrodes include an overlapping region only in the longitudinal direction. | 2018-07-26 |
20180212073 | SOLAR CELL MODULE AND METHOD FOR MANUFACTURING THE SAME TECHNICAL FIELD - A solar cell module and a method for manufacturing the same are disclosed. The solar cell module includes a plurality of cell cutting pieces stacked and connected in series, and a connector adapted to connect two adjacent cell cutting pieces in series, the plurality of cell cutting pieces being cut from a solar cell, each cell cutting piece including a front electrode and a back electrode, wherein the connector includes a first surface adapted to connect the front electrode and a second surface adapted to connect the back electrode, the first surface is provided with alternating first connecting areas and first disconnecting areas, the second surface is provided with alternating second connecting areas and second disconnecting areas, and projections of the first disconnecting areas on the first surface overlap with projections of the second connecting areas on the first surface, and wherein the front electrode is adapted to connect the first connecting areas, and the back electrode is adapted to connect the second connecting areas. The solar cell module has improved flexibility, in which grid lines and cells are not easy to be broken. | 2018-07-26 |
20180212074 | POLYMER CONTAINING 1,2,5-BENZOSELENADIAZOLE-N-R1-5,6-DICARBOXYLIC ACID IMIDE AND PREPARATION METHOD AND USE THEREOF - The present invention discloses a polymer containing 1,2,5-benzoselenadiazole-N—R | 2018-07-26 |
20180212075 | Polarized light based solar cell - A solar cell is provided wherein a circular polarizer is positioned proximate an absorptive semiconductor layer which itself is separated from an electrode, such as a loop of conductive metal, by an electrically insulative layer. Upon exposure to non-polarized light, a portion of the incident light is polarized and transmitted to the semiconductor layer. Under the influence of this polarized light, photo excited electrons in the semiconductor layer are induced to move in a circular motion, thereby generating magnetic fields. These magnetic fields drive the flow of current within the electrode. | 2018-07-26 |
20180212076 | ARTICLES, COATING COMPOSITIONS, AND METHODS - There is provided a coating composition comprising nonspherical nanoparticles; spherical nanoparticles; optionally hydrophilic groups and optional an surfactant; and a liquid medium comprising water and no greater than 30 wt % organic solvent, if present, based on the total weight of liquid medium, where at least a portion of the nonspherical nanoparticles or at least a portion of the spherical nanoparticles comprises functional groups attached to their surface through chemical bonds, wherein the functional groups comprise at least one group selected from the group consisting of epoxy group, amine group, hydroxyl, olefin, alkyne, (meth) acrylato, mercapto group, or combinations thereof. There is also provided a method for modifying a substrate surface using the coating composition and articles made therefrom. | 2018-07-26 |
20180212077 | PHOTOACTIVE DEVICES AND MATERIALS - Deposition processes are disclosed herein for depositing thin films comprising a dielectric transition metal compound phase and a conductive or semiconducting transition metal compound phase on a substrate in a reaction space. Deposition processes can include a plurality of super-cycles. Each super-cycle may include a dielectric transition metal compound sub-cycle and a reducing sub-cycle. The dielectric transition metal compound sub-cycle may include contacting the substrate with a dielectric transition metal compound. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant. The thin film may comprise a dielectric transition metal compound phase embedded in a conductive or semiconducting transition metal compound phase. | 2018-07-26 |
20180212078 | ENERGY HARVESTING SYSTEMS FOR PROVIDING AUTONOMOUS ELECTRICAL POWER TO VEHICLES AND ELECTRICALLY-POWERED DEVICES IN VEHICLES - A system is provided that integrates an autonomous energy harvesting capacity in vehicles in an aesthetically neutral manner. A unique set of structural features combine to implement a hidden energy harvesting system on a surface of the vehicle to provide electrical power to the vehicle, and/or to electrically-powered devices in the vehicle. Color-matched, image-matched and/or texture-matched optical layers are formed over energy harvesting components, including photovoltaic energy collecting components. Optical layers are tuned to scatter selectable wavelengths of electromagnetic energy back in an incident direction while allowing remaining wavelengths of electromagnetic energy to pass through the layers to the energy collecting components below. The layers uniquely implement optical light scattering techniques to make the layers appear opaque when observed from a light incident side, while allowing at least 50%, and as much as 80+%, of the energy impinging on the energy or incident side to pass through the layer. | 2018-07-26 |
20180212079 | ENERGY HARVESTING SYSTEMS FOR PROVIDING AUTONOMOUS ELECTRICAL POWER TO BUILDING STRUCTURES AND ELECTRICALLY-POWERED DEVICES IN THE BUILDING STRUCTURES - A system is provided that integrates an autonomous energy harvesting capacity in buildings in an aesthetically neutral manner. A unique set of structural features combine to implement a hidden energy harvesting system on a surface of the building to provide electrical power to the building, and/or to electrically-powered devices in the building. Color-matched, image-matched and/or texture-matched optical layers are formed over energy harvesting components, including photovoltaic energy collecting components. Optical layers are tuned to scatter selectable wavelengths of electromagnetic energy back in an incident direction while allowing remaining wavelengths of electromagnetic energy to pass through the layers to the energy collecting components below. The layers uniquely implement optical light scattering techniques to make the layers appear opaque when observed from a light incident side, while allowing at least 50%, and as much as 80+%, of the energy impinging on the energy or incident side to pass through the layer. | 2018-07-26 |
20180212080 | In-Plane Resonant-Cavity Infrared Photodetectors with Fully-Depleted Absorbers - Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs-GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure. | 2018-07-26 |
20180212081 | SOLAR CELL AND SOLAR CELL PANEL INCLUDING THE SAME - A solar cell includes a semiconductor substrate, a conductive region disposed in or on the semiconductor substrate, and an electrode comprising a plurality of finger lines connected to the conductive region, and formed to extend in a first direction while being parallel, and 6 or more bus bar lines formed to extend in a second direction crossing the first direction. | 2018-07-26 |
20180212082 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - Disclosed in a solar cell including: a semiconductor substrate; a first conductive region for extracting a first carrier on the semiconductor substrate; a second conductive for extracting a second carrier on the semiconductor substrate; a first electrode electrically coupled to the first conductive region; and a second electrode electrically coupled to the second conductive region. The first conductive region includes a first compound layer having a first metal, and the second conductive region includes a second compound layer having a second metal. At least one of the first electrode and the second electrode includes a transparent electrode layer, and a metal electrode layer on the transparent electrode layer. A work function of the transparent electrode layer of the at least one of the first electrode and the second electrode is the same as or greater than a work function of the second conductive region and is the same as or smaller than a work function of the first conductive region. | 2018-07-26 |
20180212083 | HETEROJUNCTION SOLAR CELL AND MANUFACTURING METHOD THEREOF - Discussed is a method of manufacturing a heterojunction solar cell, including: forming a metal compound on a semiconductor substrate; forming a transparent conductive oxide on the metal compound; forming an electrode forming material on the transparent conductive oxide; and sintering the electrode forming material using light sintering to form an electrode part. The transparent conductive oxide may be sintered by light sintering to form a transparent conductive oxide layer formed of the transparent conductive oxide. | 2018-07-26 |
20180212084 | POROUS SILICON NANOWIRE PHOTOVOLTAIC CELL - The porous silicon nanowire photovoltaic cell includes a first electrode, a p-type silicon layer, and a second electrode, which is formed from a transparent electrode with at least one metal contact. An array of porous silicon nanowires is sandwiched between the second electrode and the p-type silicon layer. Each of the porous silicon nanowires is formed from a porous n-type silicon core coated with a layer of p-type silicon. Empty spaces between the porous silicon nanowires of the array may be filled with indium tin oxide, thus forming a photoactive region formed from the array of porous silicon nanowires embedded in indium tin oxide. An up-conversion layer is sandwiched between the first electrode and the p-type silicon layer. Any suitable type of up-conversion material may be used for the up-conversion layer, such as NaYF | 2018-07-26 |
20180212085 | SEMICONDUCTOR DEVICES, A FLUID SENSOR AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×10 | 2018-07-26 |
20180212086 | SOLAR CELL - The present invention aims to provide a solar cell having high photoelectric conversion efficiency and excellent high-temperature, high-humidity durability. The present invention relates to a solar cell including at least: a photoelectric conversion layer; a hole transport layer; and an anode, the hole transport layer being disposed between the photoelectric conversion layer and the anode, the hole transport layer containing a polymer containing a halogen atom and an organic semiconductor component (1), the polymer containing a halogen atom having a structure that contains a halogen atom and an electron-withdrawing group bonded to a hetero atom. The present invention also relates to a solar cell including at least: a photoelectric conversion layer; a hole transport layer; and an anode, the hole transport layer being disposed between the photoelectric conversion layer and the anode, the hole transport layer containing an organic semiconductor component (2), the organic semiconductor component (2) having a structure that contains a halogen atom and an electron-withdrawing group bonded to a hetero atom. | 2018-07-26 |
20180212087 | MOBILE POWER SYSTEM - A mobile power plant comprising a retractable flexible solar array structure comprising a plurality of thin film photovoltaic modules mounted on a flexible substrate; a spool attached to a portion of the flexible solar array structure and around which the flexible solar array structure can be rolled; power cabling integrated into the flexible solar array structure for transmitting power from the plurality of photovoltaic modules to the spool-end of the flexible solar array structure; a transportable container in which the spool is mounted, the transportable container being capable of housing the flexible solar array structure when it is in a rolled configuration. | 2018-07-26 |
20180212088 | SEALING MATERIAL SHEET FOR SOLAR CELL MODULES AND SEALING MATERIAL-INTEGRATED BACKSIDE PROTECTIVE SHEET USING SAME - Provided are: a sealing material sheet for solar cell modules, and a sealing material-integrated rear-surface protecting sheet. A sealing material sheet | 2018-07-26 |
20180212089 | BACK SHEET FOR SOLAR CELL MODULE AND SOLAR CELL MODULE MADE THEREOF - Disclosed herein is a back sheet comprising a substrate comprising a silane crosslinked polyethylene composition, an adhesive layer, and a weather resistant layer. Also, disclosed herein are solar cell modules made thereof and methods for manufacturing the back sheet. | 2018-07-26 |
20180212090 | THIN FILM SOLAR CELL FOR BIPV AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a thin film solar cell for BIPV capable of improving a utility value for the exterior by visually changing a black color of an inorganic thin film solar cell into a color of reflected light therefrom to exhibit an exterior appearance having the color without substantially lowering efficiency required for a solar cell to thereby facilitate commercialization of the inorganic thin film solar cell. Also disclosed is a thin film solar cell for BIPV capable of maintaining a maximum power conversion efficiency (PCE) required for a solar cell when used as a finishing material of a building envelope, and visually changing a black color of an inorganic thin film solar cell into a color of reflected light therefrom to be suitable for the exterior with only a slight reduction of relative harvesting efficiency and a short circuit photocurrent density without a decrease of an open circuit voltage V | 2018-07-26 |
20180212091 | Infrared transmissive concentrated photovoltaics for coupling solar electric energy conversion to solar thermal energy utilization - The use of photovoltaic (PV) cells to convert solar energy to electricity is becoming increasingly prevalent; however, there are still significant limitations associated with the widespread adoption of PV cells for electricity needs. There is a clear need for a high efficiency solar power system that supplies electricity at a competitive cost and that provides for an on-demand supply of electricity as well as energy storage. By combining aspects of concentrated solar power and concentrated photovoltaics, the present invention provides a device that enables the conversion of sunlight to electricity at very high efficiencies and that enables the transmission of thermal energy to heat storage devices for later use. The disclosed device enables transmissive CPV through the use of a multijunction PV cell mounted on a transparent base. The use of a multijunction cell allows for highly efficient absorption of light above the bandgap of the lowest bandgap subcell. The transparent base permits transmission of a high percentage of the remaining light below the bandgap of the lowest bandgap subcell. The present invention also discloses a method of generating electricity through the use of a transmissive CPV device. Sunlight is concentrated onto one or more surfaces of the device. High energy light is absorbed by a multijunction PV cell and converted directly to electricity, while low energy light is transmitted through the device into a thermal storage device, which may then be coupled to a heat engine to generate dispatchable electricity. | 2018-07-26 |
20180212092 | Adhesive Layer For Printed CIGS Solar Cells - An adhesive layer in a copper indium gallium selenide (CIGS) solar cell is provided between the main CIGS layer and molybdenum film to avoid delamination of the CIGS layer and may also act as an electrical modification to increase the charge collection and power conversion efficiency (PCE) of the device. | 2018-07-26 |
20180212093 | PRESSURIZED HEATED ROLLING PRESS FOR MANUFACTURE AND METHOD OF USE - A system for connecting photovoltaic cells is disclosed. The system comprises a flexible component feeder source for feeding the photovoltaic cells to a process that couples them together; a vacuum conveyor for receiving at a first location the coupled photovoltaic cells and including openings through which a vacuum is applied to hold the coupled photovoltaic cells in place; a moving belt above the vacuum conveyor at a second location, where the vacuum conveyor and the moving belt are driven in a predetermined relation to one another for conveying the coupled photovoltaic cells from the first location to the second location; a vacuum source for applying a vacuum through the openings to cause the moving belt to apply a pressure to an upper surface of the coupled photovoltaic cells to compress the coupled photovoltaic cells; and a curing source at the second location for curing the compressed coupled photovoltaic cells. | 2018-07-26 |
20180212094 | INTERDIGITATED BACK CONTACT HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH A FLOATING JUNCTION FRONT SURFACE FIELD - A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having an opposite dopant conductivity from that of the substrate. Methods are also disclosed. | 2018-07-26 |
20180212095 | METHOD OF MANUFACTURING SOLAR CELL - A method of manufacturing a solar cell includes forming a photoelectric converter including an amorphous semiconductor layer, forming an electrode connected to the photoelectric converter, and performing a post-treatment by providing light to the photoelectric converter and the electrode, wherein, in the performing of the post-treatment, a plasma lighting system (PLS) is used as a light source, and a processing temperature is within a range from about 100° C. to about 300° C. | 2018-07-26 |
20180212096 | MICRO LIGHT EMITTING DIODE AND METHOD OF FORMING THE SAME - The present disclosure proposes a micro LED and a method of forming the same. After a body of layers to structure a PN junction is formed sequentially on the outer wall of a buffer layer column, a first electrode is formed on the outer side of the body of layers that structured the PN junction. A second electrode is formed on the inner side of the body of layers that structured the PN junction after the buffer layer column is removed. The first electrode and second electrode are insulating to each other in areas outside of the body of layers structuring the PN junction. The micro LED formed is of a tube structure. The tube-structured micro LED can effectively lower the impedance imposed by the body of layers structuring the PN junction between the first and second electrodes, and thus enhance conductivity and illumination efficiency of the micro LED. | 2018-07-26 |
20180212097 | LIGHT EMITTING DIODE WITH DISPLACED P-TYPE DOPING - Light emitting diodes re described. In an embodiment, an LED includes a graded p-side spacer layer on a p-type confinement layer, and the graded p-side spacer layer graded from an initial band gap adjacent the p-type confinement layer to a lower band gap. For example, the graded band gap may be achieved by a graded Aluminum concentration. | 2018-07-26 |
20180212098 | OPTICAL DEVICE WAFER PROCESSING METHOD - An optical device wafer processing method for dividing an optical device wafer along a plurality of division lines to obtain a plurality of individual device chips includes applying a laser beam to a wafer substrate along each division line to thereby form a laser processed groove along each division line, and next forming a V groove along each laser processed groove on the optical device wafer by using a cutting blade having a V-shaped tip in the condition where each laser processed groove is removed by the cutting blade. A crack is formed so as to extend from the bottom of each laser processed groove due to a load applied from the cutting blade, thereby dividing the optical device wafer into the individual device chips. The depth of each laser processed groove is set smaller than the depth of cut by the cutting blade. | 2018-07-26 |
20180212099 | LIGHT EMITTING DIODE STRUCTURE, LIGHT EMITTING DIODE DEVICE AND THE MANUFACTURING METHOD THEREOF - A method for manufacturing a light emitting diode structure uses a removable prefilled layer to attach the flip-type chip on a temporary substrate. A growth substrate of the flip-type chip is removed by laser lift-off, and then the light emitting diode structure is attached to a transparent support body. Lastly, the temporary substrate and the prefilled layer are removed. | 2018-07-26 |
20180212100 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT - A method of manufacturing a light emitting element includes: providing a wafer that includes a substrate having a first principal face and a second principal face, a dielectric multilayer film disposed on the first principal face, and a semiconductor structure disposed on the second principal face; forming modified regions in the substrate by focusing a laser beam inside the substrate via the dielectric multilayer film, and allowing cracks to form from the modified regions to the dielectric multilayer film; subsequent to forming the modified regions in the substrate, removing regions of the dielectric multilayer film that contain cracks; and cleaving the wafer along regions where cracks were formed in the substrate. | 2018-07-26 |