30th week of 2020 patent applcation highlights part 59 |
Patent application number | Title | Published |
20200235153 | OPTICAL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - An optical package structure includes a substrate, an optical element, a spacer and an encapsulant. The substrate has a top surface. The optical element is disposed adjacent to the top surface of the substrate and has a first height H | 2020-07-23 |
20200235154 | FAN-OUT SENSOR PACKAGE AND OPTICAL FINGERPRINT SENSOR MODULE INCLUDING THE SAME - There are provided a fan-out sensor package and an optical fingerprint sensor module including the same. The fan-out sensor package includes: a connection member having a | 2020-07-23 |
20200235155 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC EQUIPMENT - The present disclosure relates to a semiconductor device, a manufacturing method of the semiconductor device, and electronic equipment that are directed to improving quality and reliability of a semiconductor device including a through electrode, or electronic equipment. The semiconductor device includes a first semiconductor substrate including a through electrode, a first insulating film laminated on a first surface of the first semiconductor substrate, and a second insulating film laminated on the first insulating film, in which an inner wall and a bottom surface of the through electrode are covered with a conductor, the first insulating film and the second insulating film are laminated on the conductor, and the through electrode includes a groove which reaches the first insulating film on the bottom surface from the first surface of the first semiconductor substrate. The present technology may be applied to a packaged solid-state imaging device or the like, for example. | 2020-07-23 |
20200235156 | INTEGRATED CIRCUIT DEVICES HAVING THROUGH-SILICON VIA STRUCTURES - An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels. | 2020-07-23 |
20200235157 | PHOTOELECTRIC CONVERSION APPARATUS, EQUIPMENT INCLUDING PHOTOELECTRIC CONVERSION APPARATUS, AND MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes a semiconductor substrate including a photoelectric conversion portion, a metal containing portion provided on the semiconductor substrate, an interlayer insulation film arranged on the semiconductor substrate to cover the metal containing portion, a first silicon nitride layer arranged on the photoelectric conversion portion to include a portion lying between the interlayer insulation film and the semiconductor substrate, a silicon oxide film including a portion arranged between the first silicon nitride layer and the photoelectric conversion portion, and a portion arranged between the interlayer insulation film and the metal containing portion, a second silicon nitride layer arranged between the silicon oxide film and the metal containing portion. | 2020-07-23 |
20200235158 | GATE MODULATION WITH INDUCTOR - A sensor includes a photodiode disposed in a semiconductor material to receive light and convert the light into charge, and a first floating diffusion coupled to the photodiode to receive the charge. A second floating diffusion is coupled to the photodiode to receive the charge, and a first transfer transistor is coupled to transfer the charge from the photodiode into the first floating diffusion. A second transfer transistor is coupled to transfer the charge from the photodiode into the second floating diffusion, and an inductor is coupled between a first gate terminal of the first transfer transistor and a second gate terminal of the second transfer transistor. The inductor, the first gate terminal, and the second gate terminal form a resonant circuit. | 2020-07-23 |
20200235159 | BAND-PASS FILTER FOR STACKED SENSOR - In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first image sensor disposed within a first substrate and a second image sensor disposed within a second substrate. The second substrate has a first side facing the first substrate. The first side includes angled surfaces defining one or more recesses within the first side. A band-pass filter is arranged between the first substrate and the second substrate and is configured to reflect electromagnetic radiation that is within a first range of wavelengths. | 2020-07-23 |
20200235160 | BACKBOARD, DISPLAY DEVICE, AND METHOD FOR FABRICATING BACKBOARD - The disclosure discloses a backboard, a display device, and a method for fabricating the same, and the backboard includes: a backboard body; and a plurality of LED installation mounts arranged in an array on the backboard body, wherein each of the plurality of LED installation mounts includes at least two lead-out electrodes to be connected with LED pins, and a coil structure around each of the at least two lead-out electrodes, wherein the coil structure is configured to produce a magnetic field upon being powered on. The coils can be formed on the backboard body in the backboard to absorb electrodes of LEDs to thereby position them precisely so as to transfer the LEDs in a mass manner with a high good yield ratio, and the lead-out electrodes can be powered on to thereby detect abnormally operating LEDs. | 2020-07-23 |
20200235161 | METHOD FOR MANUFACTURING MICRO ARRAY LIGHT EMITTING DIODE AND LIGHTING DEVICE - The present invention suggests a method for manufacturing a micro-array light emitting diode comprising: a step for forming a semiconductor lamination structure by stacking an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate; a step for forming a plurality of p-type electrodes so as to be arranged two-dimensionally apart from each other on the p-type semiconductor layer; and a step for forming an isolation part in the p-type semiconductor layer exposed between the plurality of p-type electrodes in a self-aligning manner. | 2020-07-23 |
20200235162 | DOUBLE SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES - Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line. | 2020-07-23 |
20200235163 | SELECTOR DEVICES - Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur. | 2020-07-23 |
20200235164 | NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE - A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle. | 2020-07-23 |
20200235165 | SEMICONDUCTOR DEVICE - A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells. | 2020-07-23 |
20200235166 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging device that can achieve a high S/N ratio at a high sensitivity level without any decrease in resolution, and to an electronic apparatus. In the upper layer, the respective pixels of a photoelectric conversion unit that absorbs light of a first wavelength are tilted at approximately 45 degrees with respect to a square pixel array, and are two-dimensionally arranged in horizontal directions and vertical directions in an oblique array. The respective pixels of a photoelectric conversion unit that is sensitive to light of a second or third wavelength are arranged under the first photoelectric conversion unit. That is, pixels that are √2 times as large in size (twice as large in area) and are rotated 45 degrees are arranged in an oblique array. The present disclosure can be applied to solid-state imaging devices that are used in imaging apparatuses, for example. | 2020-07-23 |
20200235167 | Solid State Tissue Equivalent Detector With Gate Electrodes - An organic semiconductor detector for detecting radiation has an organic conducting active region, an output electrode and a field effect semiconductor device. The field effect semiconductor device has a biasing voltage electrode and a gate electrode. The organic conducting active region is connected on one side to the field effect semiconductor device and is connected on another side to the output electrode. | 2020-07-23 |
20200235168 | PHOTOELECTRIC DIODES AND ORGANIC SENSORS AND ELECTRONIC DEVICES - A photoelectric diode includes a first electrode and a second electrode facing each other; a photoelectric conversion layer between the first electrode and the second electrode, and a compensation layer on the photoelectric conversion layer, the compensation layer being configured to compensate absorption and reflection of light. The photoelectric conversion layer is associated with a first optical spectrum having a light-absorption peak at a first wavelength and a reflection peak at a second wavelength, the first wavelength and the second wavelength both within a wavelength region of about 750 nm to about 1200 nm. The photoelectric diode is associated with a second optical spectrum having a light-absorption peak at a third wavelength, the third wavelength is within the wavelength region of about 750 nm to about 1200 nm, the third wavelength different from the first wavelength. | 2020-07-23 |
20200235169 | DISPLAY DEVICE - The display device includes a substrate, a display region arranged on the substrate and including a plurality of pixels, a first wiring provided on the substrate, an insulating layer overlapping a portion of the first wiring, an oxide conductive layer provided on the first wiring and electrically connected to the first wiring, a sealing layer overlapping the display region and at least an end of the oxide conductive layer and sealing the plurality of pixels, a sensor electrode provided on the sealing layer and overlapping the display region, and a second wiring passing over the at least end of the oxide conductive layer provided with the sealing layer and electrically connecting the sensor electrode and the oxide conductive layer. | 2020-07-23 |
20200235170 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a substrate comprising a first pixel region and a second pixel region adjacent to the first pixel region; a circuit device layer on the substrate; a first light-emitting device module on the circuit device layer, the first light-emitting device module comprising a first light-emitting device overlapping the first pixel region to display a first color; and a second light-emitting device module on the first light-emitting device module, the second light-emitting device module having a first pixel penetration hole overlapping the first pixel region, the second light-emitting device module further comprising a second light-emitting device overlapping the second pixel region to display a second color different from the first color. | 2020-07-23 |
20200235171 | DISPLAY PANEL AND DISPLAY APPARATUS - A display panel includes first color sub-pixels, second color sub-pixels and third color sub-pixels in an array arranged in a first direction and a second direction intersecting the first direction. The first color sub-pixels include a first type of first color sub-pixel of which a first transport layer has a first thickness and a second type of first color sub-pixel of which the first transport layer has a second thickness. The first type of first color sub-pixels are arranged into a plurality of first sub-arrays, each including at least one respective sub-pixel of the first type of first color sub-pixels. The second type of first color sub-pixels are arranged into a plurality of second sub-arrays, each including at least one respective sub-pixel of the second type of first color sub-pixels. The first sub-arrays and the second sub-arrays are alternately arranged in the first direction and the second direction. | 2020-07-23 |
20200235172 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device including a substrate which has a plurality of pixels each including an emission portion and a non-emission portion, a first electrode which is disposed on the emission portion, a pixel definition layer which is disposed on an edge of the first electrode and the non-emission portion, a common organic layer which is disposed on the first electrode and the pixel definition layer, an organic light-emitting layer which is disposed on the common organic layer and overlaps the emission portion, and a second electrode which is disposed on the common organic layer and the organic light-emitting layer. The pixel definition layer includes a plurality of pits between adjacent pixels. The common organic layer and the second electrode are separated by the pits. | 2020-07-23 |
20200235173 | DISPLAY DEVICE - A first subpixel and a second subpixel that are adjacent to each other in a row direction, a third subpixel, and a fourth subpixel and a fifth subpixel that are adjacent to each other in the row direction are provided. Each of the first subpixel and the fourth subpixel that are arrayed in a column direction includes a first-color light-emitting layer. Each of the second subpixel and the fifth subpixel that are arrayed in the column direction includes a second-color light-emitting layer. The third subpixel including a third-color light-emitting layer is adjacent in a diagonal direction to or adjacent in the column direction to at least two of the first subpixel, the second subpixel, the fourth subpixel, and the fifth subpixel. | 2020-07-23 |
20200235174 | DISPLAY DEVICE - A display device includes a first subpixel including a light-emitting layer of a first color, a second subpixel adjacent to the first subpixel in a row direction or a column direction, the second subpixel including a light-emitting layer of a second color, and a third subpixel adjacent to the first subpixel and the second subpixel in a diagonal direction, the third subpixel including a light-emitting layer of a third color, wherein the first subpixel to the third subpixel include light-emitting regions that are geometrically similar to one another, the light-emitting regions of two of the first subpixel to the third subpixel are in the same size, and a light-emitting region of remaining one of the first subpixel to the third subpixel is larger than the light-emitting regions of the two of the first subpixel to the third subpixel. | 2020-07-23 |
20200235175 | DISPLAY PANEL AND ELECTRONIC APPARATUS - A display panel includes a planarization layer, self-luminous elements, a first wiring line, a second wiring line, and a sensing wiring line. The first wiring line is coupled to the first electrode layer through a first opening of the planarization layer. The second wiring line is coupled to the second electrode layer through a second opening of the planarization layer. The sensing wiring line is provided in a region and is electrically separated from the first electrode layer, the second electrode layer, the first wiring line, and the second wiring line. The region is positioned in the same layer as the first electrode layer, in the same layer as the second wiring line, or in a layer disposed between the first electrode layer and the second wiring line, and is positioned between the first electrode layer and the second opening. | 2020-07-23 |
20200235176 | DISPLAY DEVICE - A display device includes: a substrate that includes a first area and a second area; a plurality of pixels included in the first area; and a dummy pattern included in the second area, wherein a size of the dummy pattern is smaller than a pixel area corresponding to a first pixel among the plurality of pixels, a ratio of an area occupied by a pixel pattern of the first pixel with respect to the pixel area is a first value, a ratio of an area occupied by the dummy pattern with respect to a dummy area is a second value that is greater than the first value, and the dummy area and the pixel area have the same size as each other. | 2020-07-23 |
20200235177 | OLED DISPLAY PANEL - The present invention provides an OLED display panel. The display panel includes a plurality of sub-pixels arranged in an array. Each of the sub-pixels comprises a base substrate, a TFT layer, a flat layer, a first electrode, a pixel defining layer, a light emitting layer, a transparent second electrode, and an encapsulation layer. A portion of at least one of the flat layer and the pixel defining layer is formed by a black shielding material. The OLED display panel can be prevented from reflecting ambient light without improving the light extraction efficiency, thereby improving the viewing experience of the OLED display panel by the arrangement of a portion of at least one of the flat layer and the pixel defining layer is formed by a black shielding material. | 2020-07-23 |
20200235178 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An OLED device may include the following elements: a common electrode; a first pixel electrode overlapping the common electrode; a first emission layer positioned between the first pixel electrode and the common electrode; a second pixel electrode; a second emission layer positioned between the second pixel electrode and the common electrode; and a pixel defining layer including a first opening, a second opening, a first flat face, and an uneven surface structure, wherein the first opening partially exposes the first pixel electrode, wherein the second opening partially exposes the second pixel electrode, wherein the first flat face may be opposite the uneven surface and may be positioned between the first pixel electrode to the second electrode, and wherein the uneven surface may be positioned between the first opening and the second opening. | 2020-07-23 |
20200235179 | Organic Light Emitting Display Device, Head Mounted Display Including the Same and Method of Fabricating the Same - An organic light emitting display device includes: an insulating layer; first electrodes on the insulating layer and spaced from each other by a gap; an organic light emitting layer on the first electrodes; and a second electrode on the organic light emitting layer, wherein the insulating layer includes a trench between the first electrodes, wherein the organic light emitting layer includes a first stack on the first electrodes, a charge generating layer on the first stack, and a second stack on the charge generating layer, wherein each of the first and second stacks includes a hole transporting layer, at least one emitting material layer and an electron transporting layer, and wherein the first stack has a discontinuous portion in the trench. | 2020-07-23 |
20200235180 | DISPLAY PANEL - A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove. | 2020-07-23 |
20200235181 | SEMICONDUCTOR DEVICE INCLUDING AN OXIDE THIN FILM TRANSISTOR - A semiconductor device includes a base substrate, a first transistor disposed on the base substrate, the first transistor including a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor, a second transistor disposed on the base substrate, the second transistor including a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor, a plurality of insulating layers disposed on the base substrate, and an upper electrode disposed on the first control electrode with at least one insulating layer of the plurality of insulating layers interposed between the upper electrode and the first control electrode. The upper electrode overlaps the first control electrode and forms a capacitor with the first control electrode. | 2020-07-23 |
20200235182 | DISPLAY DEVICE - A display device according to an embodiment of the present invention includes: a substrate; a first organic light-emitting diode including a first lower electrode provided above the substrate and for each pixel, a first organic layer provided above the first lower electrode, a first light-emitting layer provided within the first organic layer and for each pixel and including a thermally activated material, and an upper electrode provided above the first organic layer; and a first drive TFT provided between the substrate and the first organic light-emitting diode, connected to the first lower electrode, and arranged overlapping the first light-emitting layer as viewed in a plan view. | 2020-07-23 |
20200235183 | DISPLAY DEVICE - A display device having high resolution includes: a first conductive layer, an active pattern, second to fourth conductive layers, and a pixel electrode sequentially formed on a substrate, with first to fourth insulating layers separately interposed therebetween, the first conductive layer including a lower pattern, the active pattern including a source region, a channel region, and a drain region, the second conductive layer including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode, the third conductive layer including a capacitor electrode overlapping the driving gate electrode, the fourth conductive layer including an additional capacitor electrode overlapping the capacitor electrode. The driving gate electrode and the capacitor electrode may form a storage capacitor, the pixel electrode and the additional capacitor electrode may form a first additional capacitor, and the capacitor electrode and the additional capacitor electrode may form a second additional capacitor. | 2020-07-23 |
20200235184 | DISPLAY DEVICE - A display device is provided including a plurality of pixels, wherein the plurality of pixels is arranged in a matrix form, wherein each of the plurality of pixels has an emission region and a transparent region, and wherein the emission region has a light-emitting element, and the transparent region has at least a part of a storage capacitor having transparency and is covered with at least one electrode of the storage capacitor, a first electrode covers the plurality of pixels, a light-emitting layer is arranged below the first electrode, a second electrode is arranged below the light-emitting layer, and the storage capacitor includes the first electrode. | 2020-07-23 |
20200235185 | AMOLED DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure discloses an AMOLED display panel, including a TFT array substrate and sub-pixels arranged in an array on the TFT array substrate, wherein each sub-pixel includes a first light-emitting region and a second light-emitting region which have a same emissive layer structure, one of the first light-emitting region and the second light-emitting region is a top light-emitting structure and the other is a bottom light-emitting structure; the first light-emitting region is for displaying an image, a light-detecting member is disposed on a light-emitting surface of the second light-emitting region, the light-detecting member is configured to detect a light-emitting luminance of the second light-emitting region to determine whether the sub-pixels need to perform brightness compensation and a corresponding brightness compensation value. The present disclosure also discloses a display device including a driving module and an AMOLED display panel as described above. | 2020-07-23 |
20200235186 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an exemplary embodiment of the present invention, a display device includes a base substrate provided with light emitting elements, an encapsulation layer covering the light emitting elements, a first conductive layer disposed on the encapsulation layer and comprising first conductive patterns, a first insulation layer disposed on the encapsulation layer to cover the first conductive patterns, a second conductive layer disposed on the first insulation layer and comprising first sensing patterns, second conductive patterns electrically connecting the first sensing patterns, and second sensing patterns electrically connected by the first conductive patterns, a second insulation layer disposed on the first insulation layer and the second conductive layer without overlapping the light emitting elements to cover the second conductive layer, and a light shielding layer covering the second insulation layer. The light shielding layer and the second insulation layer are in contact with the first insulation layer. | 2020-07-23 |
20200235187 | DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME - A display apparatus has an enlarged display area so that an image can be displayed in a sensor area. The display apparatus includes: a first base layer that includes a display area that includes a plurality of main pixels and a sensor area that includes a plurality of auxiliary pixels and a transmission portion; a conductive layer positioned on the first base layer and that corresponds to the plurality of auxiliary pixels; and a second base layer positioned on the first base layer with the conductive layer positioned between the second base layer and the first base layer. A resolution of an image displayed by the sensor area is lower than a resolution of an image displayed by the display area. | 2020-07-23 |
20200235188 | DISPLAY DEVICE - A display device including a plurality of light emitting elements including first, second, and third light emitting elements; and a color filter including first, second, and third color filters corresponding to respective first, second, and third light emitting elements, wherein first and second light-shielding members are disposed at a light emission direction, first ends of the first and second color filters overlap with the first light-shielding member in a cross sectional view, a first distance between the first end of the first color filter and a first side surface of the first light-shielding member and a second distance between the first end of the second color filter and a second side surface of the second light-shielding member are different in the cross sectional view, a thickness of the first color filter and a thickness of the second color filter are different. | 2020-07-23 |
20200235189 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes: a display substrate including a display area and a pad area disposed around the display area; a signal wiring disposed over the display area and the pad area on the display substrate; at least one wiring pad including: a pad pattern portion disposed on the pad area of the display substrate and electrically connected to the signal wiring; and a separation pattern portion separated from the pad pattern portion by a separation space; and a printed circuit board attached to the pad area of the display substrate, the printed circuit board including a lead wiring connected to the at least one wiring pad. | 2020-07-23 |
20200235190 | DISPLAY APPARATUS - A display apparatus includes a first signal line and a second signal line that each extend on a substrate in a first direction and are spaced apart in a second direction that crosses the first direction; a plurality of first metal patterns spaced apart from each other in the first direction, wherein at least a portion of the first metal patterns overlaps the first signal line and is electrically connected to the first signal line; and a plurality of second metal patterns spaced apart from each other in the first direction, wherein at least a portion of the second metal patterns overlaps the second signal line and is electrically connected to the second signal line, wherein the plurality of first metal patterns and the plurality of second metal patterns are spaced apart in the first direction in a zigzag arrangement. | 2020-07-23 |
20200235191 | DISPLAY DEVICE - A display device includes: a substrate including a display area for displaying an image and a peripheral area positioned adjacent to the display area; a plurality of normal pixels disposed within the display area on the substrate, where each normal pixel includes a first transmissive area and a pixel area disposed adjacent the first transmissive area; and a dummy pixel disposed within the display area on the substrate, adjacent to a curved section of the peripheral area, and disposed between the peripheral area and the plurality of pixels. The dummy pixel includes: a second transmissive area; and a wire area disposed adjacent the second transmissive area. | 2020-07-23 |
20200235192 | DISPLAY APPARATUS - A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group. | 2020-07-23 |
20200235193 | DISPLAY DEVICE - A display device includes a plurality of pixels, first to nth scanning lines, and a first semiconductor film. The plurality of pixels is arranged in first to nth rows and first to mth columns. The first to nth scanning lines are electrically connected to the pixels in the respective first to nth rows. The first semiconductor film overlaps with at least one of first to kth scanning lines. A display region has a cutoff intersecting the first to nth rows, and the first semiconductor film is located in the cutoff. Each of the plurality of pixels includes a light-emitting element (OLED) and a transistor electrically connected to the OLED and having a second semiconductor film. The first semiconductor film and the second semiconductor film exist in the same layer. n and m are each a natural number larger than 1, and k is a natural number smaller than n. | 2020-07-23 |
20200235194 | DISPLAY DEVICE - A display device according to an embodiment of the present invention has a first substrate, a display region provided with a plurality of pixels on the first substrate, each of the plurality of pixels including a light-emitting element, a driving circuit provided along a first direction of the display region on the first substrate, a sealing film covering the display region, and stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer in order from the light-emitting element, a second substrate on the sealing film, a through hole provided in the first substrate, the display region, and the second substrate; and a first region surrounding the through hole. | 2020-07-23 |
20200235195 | DISPLAY DEVICE, MANUFACTURING METHOD OF DISPLAY DEVICE, AND EXPOSURE DEVICE - A display device includes a plurality of picture elements, wherein a first electrode is formed in each of the plurality of picture elements, a cover layer is formed such that an opening of the first electrode is formed, a spacer in a layer identical to the cover layer is provided between two of the first electrodes, the spacer is formed with a height greater than a height of the cover layer, and an outer edge portion of the spacer is spaced from an outer edge portion of the cover layer. | 2020-07-23 |
20200235196 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a display device. The display device includes: a substrate; a gate line disposed on the substrate; a transistor including a part of the gate line; and a light-emitting element connected to the transistor, in which the gate line includes a first layer including aluminum or an aluminum alloy, a second layer including titanium nitride, and a third layer including metallic titanium nitride. An N/Ti molar ratio of the metallic titanium nitride may be in a range from about 0.2 to about 0.75. | 2020-07-23 |
20200235197 | HIGH VOLTAGE DEVICE - We disclose herein a high voltage device comprising: a first electrode; a second electrode disposed underneath and spaced from the first electrode; and a dielectric layer disposed between the first and second electrodes, wherein the first electrode extends further in at least one lateral direction in respect of the second electrode. | 2020-07-23 |
20200235198 | SEMICONDUCTOR DEVICE - An MIM capacitor of a semiconductor device is configured to include a dielectric layer between a lower electrode and an upper electrode, and a floating electrode provided in the dielectric layer, extended in parallel to the upper electrode and the lower electrode, and not electrically connected from any one of the lower electrode and the upper electrode is included. | 2020-07-23 |
20200235199 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor. | 2020-07-23 |
20200235200 | CAPACITOR - According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer. | 2020-07-23 |
20200235201 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; trenches penetrating the second semiconductor layer and the first semiconductor region, and reaching the first semiconductor layer; gate electrodes on gate insulating films in the trenches; a first base region between the trenches; and second base regions at bottoms of the trenches. The first base region includes a lower region equal in thickness to the second base regions and an upper region on the lower region. The first base region has impurity concentration peaks of local maximum values in a thickness direction. A peak nearest an interface between the upper and lower regions is located at a position furthest from any other peak. | 2020-07-23 |
20200235202 | CASTELLATED SUPERJUNCTION TRANSISTORS - A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor. | 2020-07-23 |
20200235203 | SEMICONDUCTOR DEVICE - A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type. | 2020-07-23 |
20200235204 | FORMING FINFET WITH REDUCED VARIABILITY - A semiconductor structure is provided that includes active semiconductor fins that have a uniform fin channel height. The uniform fin channel height is achieved by forming semiconductor fins (active and sacrificial) on an entirety of semiconductor substrate thus there is no loading effect during a subsequently performed dielectric etch step which can lead to fin channel height variation and ultimately variation in device characteristics. A trench isolation structure is located adjacent to the active semiconductor fins. The trench isolation structure includes at least one dielectric plug having a second width and a dielectric pillar having a first width located on each side of the at least one dielectric plug. The second width of the at least one dielectric plug is less than the first width of each dielectric pillar, yet equal to a width of each semiconductor fin. | 2020-07-23 |
20200235205 | TRANSISTOR AND ELECTRONIC APPARATUS - A transistor and electronic apparatus are disclosed. In one example, a transistor includes a semiconductor substrate containing an electrically-conductive impurity. A device separation layer defines a device region. A buried insulation layer is provided in the device region, and a gate electrode crosses the device region. A drain region and a source region are opposed to each other with the gate electrode in between in the device region. A concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in an end region including at least an end portion of the gate electrode on drain region side is different from a concentration or a polarity of the electrically-conductive impurity in the semiconductor substrate in a middle region including a middle portion of the gate electrode. | 2020-07-23 |
20200235206 | REPLACEMENT SACRIFICIAL NANOSHEETS HAVING IMPROVED ETCH SELECTIVITY - Embodiments of the invention are directed to a method of forming a nanosheet transistor. A non-limiting example of the method includes forming a nanosheet stack having alternating layers of channel nanosheets and sacrificial nanosheets, wherein each of the layers of channel nanosheets includes a first type of semiconductor material, and wherein each of the layers of sacrificial nanosheets includes a second type of semiconductor material. The layers of sacrificial nanosheets are removed from the nanosheet stack, and layers of replacement sacrificial nanosheets are formed in the spaces that were occupied by the sacrificial nanosheets. Each of the layers of replacement sacrificial nanosheets includes a first type of non-semiconductor material. | 2020-07-23 |
20200235207 | III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION - Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer. | 2020-07-23 |
20200235208 | P-TYPE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion. | 2020-07-23 |
20200235209 | FINFET CMOS WITH ASYMMETRIC GATE THRESHOLD VOLTAGE - A FinFET having an asymmetric threshold voltage distribution is provided by modifying a portion of the channel region of a semiconductor fin that is nearest to the drain side with an epitaxial semiconductor material layer. In some embodiments, the channel region of the semiconductor fin nearest to the drain side is trimmed prior to forming the epitaxial semiconductor material layer. | 2020-07-23 |
20200235210 | INSULATED-GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches. | 2020-07-23 |
20200235211 | METHOD OF FABRICATING ELECTRICALLY ISOLATED DIAMOND NANOWIRES AND ITS APPLICATION FOR NANOWIRE MOSFET - A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire. | 2020-07-23 |
20200235212 | GRAPHENE ELECTROCHEMICAL TRANSFER METHOD ASSISTED BY MULTIPLE SUPPORTING FILMS - Disclosed is a graphene electrochemical transfer method assisted by multiple supporting films, comprising: (1) growing graphene on a substrate, and then spin-coating a thin layer of photoresist on a surface of the graphene as a first film; (2) spin-coating n layers of thick, tough, and selectively dissolvable polymer films on the surface of the first film as an top film; (3) dissociating the multi-layer composite film and the graphene from the surface of the substrate by an electrochemical process, and dissolving the thick polymer films which is the top film with a first solvent; (4) after cleaning, transferring the thin first film and the graphene to a target substrate, and finally dissolving the thin first film away with a second solvent to complete the transfer process. This transfer process is fast, stable, and capable of transferring a large-size graphene, which may promote the large-scale application of graphene. | 2020-07-23 |
20200235213 | HIGH VOLTAGE THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high voltage thin-film transistor is specified comprising a gate electrode (G | 2020-07-23 |
20200235214 | SEMICONDUCTOR STRUCTURE WITH BARRIER LAYER AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer. | 2020-07-23 |
20200235215 | SEMICONDUCTOR DEVICE - A semiconductor device includes; an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction. | 2020-07-23 |
20200235216 | GALLIUM NITRIDE TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES AND THEIR METHODS OF FABRICATION - Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion. | 2020-07-23 |
20200235217 | SCHOTTKY BARRIER DIODE WITH IMPROVED SCHOTTKY CONTACT FOR HIGH VOLTAGES - The Schottky barrier diode comprises a semiconductor body with a main surface, a doped region and a further doped region of the semiconductor body, which extend to the main surface, the doped region and the further doped region having opposite types of electric conductivity, a subregion and a further subregion of the further doped region, the subregions being contiguous with one another, the further subregion comprising a higher doping concentration than the subregion, a silicide layer on the main surface, the silicide layer forming an interface with the doped region, an electric contact on the doped region, and a further electric contact electrically connecting the further doped region with the silicide layer. | 2020-07-23 |
20200235218 | Enhancement-mode High Electron Mobility Transistor - Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer. | 2020-07-23 |
20200235219 | Conductive Line Construction, Memory Circuitry, And Method Of Forming A Conductive Line Construction - A method of forming a conductive line construction comprises forming a structure comprising polysilicon-comprising material. Elemental titanium is directly against the polysilicon of the polysilicon-comprising material. Silicon nitride is directly against the elemental titanium. Elemental tungsten is directly against the silicon nitride. The structure is annealed to form a conductive line construction comprising the polysilicon-comprising material, titanium silicide directly against the polysilicon-comprising material, elemental tungsten, TiSi | 2020-07-23 |
20200235220 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening. | 2020-07-23 |
20200235221 | FERROELECTRIC GATE DIELECTRICS IN INTEGRATED CIRCUITS - In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device. | 2020-07-23 |
20200235222 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer. | 2020-07-23 |
20200235223 | WAVY CHANNEL FLEXIBLE THIN-FILM-TRANSISTOR ON A FLEXIBLE SUBSTRATE AND METHOD OF PRODUCING SUCH A THIN-FILM-TRANSISTOR - A method for producing a thin-film-transistor involves forming a flexible substrate on a rigid substrate, forming a plurality of fins and trenches in a structural layer arranged on the flexible substrate, forming a wavy gate layer, channel layer, source contact layer, and drain contact layer on each of the plurality of fins and each of a plurality of trenches of the structural layer, and removing the plurality of fins and trenches having the wavy gate, channel, source contact, and drain contact layers from the rigid substrate. | 2020-07-23 |
20200235224 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer. | 2020-07-23 |
20200235225 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer. | 2020-07-23 |
20200235226 | METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR WITH OPTIMIZED PERFORMANCES - The invention relates to a method for fabricating a field-effect transistor ( | 2020-07-23 |
20200235227 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode. | 2020-07-23 |
20200235228 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region; forming a plurality of first initial fin structures on the first region of the semiconductor substrate; forming a dummy gate structure across the first initial fin structures by covering portions of top and sidewall surfaces of the first initial fin structures; forming a dielectric layer covering sidewall surfaces of the dummy gate structure and exposing a top surface of the dummy gate structure; removing the dummy gate structure to form a first opening in the dielectric layer and expose portions of top and sidewall surfaces of the first initial fin structures; and performing at least one trimming process on the first initial fin structures to form fin first structures. A width of each first fin structure is smaller than a width of each first initial fin structure. | 2020-07-23 |
20200235229 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A first region is formed by injecting a first condition type first dopant into a surface layer portion of an IGBT section of a semiconductor substrate. A second region is formed by injecting a second condition type second dopant into a region of the IGBT section shallower than the first region. An amorphous third region is formed by injecting the first conduction type third dopant into a surface layer portion of a diode section at a concentration higher than that of the second dopant. Thereafter, the IGBT section and the diode section are laser-annealed under conditions in which the third region is partially melted and the first dopant is activated. Subsequently, a surface layer portion which is shallower than the second injection region in the entire region of the IGBT section and the diode section is melted and crystallized by annealing the IGBT section and the diode section. | 2020-07-23 |
20200235230 | SUPER-JUNCTION IGBT DEVICE AND METHOD FOR MANUFACTURING SAME - A super-junction IGBT device comprises a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed in a horizontal direction. Device cell structures are formed at tops of super-junction cells and each comprise a trench gate having a gate trench striding across an interface of the corresponding P-type pillar and the corresponding N-type pillar. A body region is formed at a top of the corresponding N-type pillar, and a source region is formed on a surface of the body region. The top of each N-type pillar is provided with one body region and two trench gates located on two sides of the body region, and each body region is isolated from the P-type pillars on the two sides of the body region through the corresponding trench gates. The invention further discloses a method for manufacturing a super-junction IGBT device. Self-isolation of the P-type pillars is realized, the on-state current capacity of the device is improved, and the on-state voltage drop of the device is reduced. | 2020-07-23 |
20200235231 | IGBT DEVICE WITH MOS CONTROLLABLE HOLE PATH - The present invention relates to the technical field of power semiconductor devices, particularly to an insulated gate bipolar transistor with a MOS controllable hole path. According to the present invention, a MOS controllable gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel region are embedded in a P+ floating p-body region of the conventional IGBT structure. The MOS region is equivalent to a switch controlled by a gate voltage. When the device is turned on under a forward voltage, the potential of the p-body region is floated to store holes, reducing the saturation conduction voltage drop of the device. Under the condition of turn-off and short-circuit, the hole extracting path is provided and the Miller capacitance is lowered, thereby lowering the turn-off losses and enhancing the short-circuit withstand capability. | 2020-07-23 |
20200235232 | Method for Producing IGBT with dV/dt Controllability - A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current. | 2020-07-23 |
20200235233 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The present disclosure is directed to a semiconductor device and a manufacturing method therefor. In one implementations, a method includes: providing a semiconductor structure, where the semiconductor structure includes: a substrate, and a first fin and a second fin spaced on the substrate; depositing a first interlayer dielectric layer on the semiconductor structure; performing first partial etching on the first interlayer dielectric layer to expose a top of the first fin; after the top of the first fin is exposed, removing a part of the first fin to form a first groove; epitaxially growing a first electrode in the first groove; performing second partial etching on the first interlayer dielectric layer to expose a top of the second fin; after the top of the second fin is exposed, removing a part of the second fin to form a second groove, where the second groove is separated from the first groove; and epitaxially growing a second electrode in the second groove. The present disclosure addresses the problem of bridging of electrode epitaxial bodies of different devices in the prior art. | 2020-07-23 |
20200235234 | FIELD EFFECT TRANSISTOR - A field-effect transistor includes an n-type semiconductor layer that includes a Ga | 2020-07-23 |
20200235235 | Power Semiconductor Device and Method of Forming a Power Semiconductor Device - A method of forming a power semiconductor device includes: arranging a control electrode at least partially on or inside a semiconductor body; forming elevated source regions in the semiconductor body by: implanting first conductivity type dopants into the semiconductor body; forming a recess mask layer covering at least areas of intended source regions; and removing portions of the semiconductor body uncovered by the recess mask layer to form the elevated source regions and recessed body regions at least partially between the source regions. A dielectric layer is formed on the semiconductor body. A contact hole mask layer is formed on the dielectric layer. Portions of the dielectric layer uncovered by the contact hole mask layer are removed to form a contact hole which is filled at least partially with a conductive material to establish an electrical contact with at least a portion of the elevated source and recessed body regions. | 2020-07-23 |
20200235236 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench. | 2020-07-23 |
20200235237 | LDMOS DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is an LDMOS device comprising a drift region formed by a selected area of a doped layer of a first conductivity type on a semiconductor substrate, a gate structure comprising a gate dielectric layer and a gate conductive layer which are sequentially formed on a surface of the doped layer of the first conductivity type, a doped self-aligned channel region of a second conductivity type, and a doped layer formed by tilted ion implantation with a first side face of the gate structure as a self-alignment condition. A method for manufacturing an LDMOS device is further disclosed. The channel length is not affected by lithography and thus can be minimized to fulfill an ultralow specific-on-resistance, and the distribution uniformity of the channel length can be improved, so that the performance uniformity of the device is improved. | 2020-07-23 |
20200235238 | REMOVAL OF WORK FUNCTION METAL WING TO IMPROVE DEVICE YIELD IN VERTICAL FETS - A vertical transistor that includes a gate structure containing a work function metal liner that is wing-free is provided. The wing-free work function metal liner is provided by recessing a sacrificial material layer portion that is located adjacent to a work function metal liner having a winged surface near the channel and fin ends. The recessed sacrificial material layer portion allows for multi-directional etching of the winged surface of the work function metal liner and thus the wing surface can be removed forming a wing-free work function metal liner. The vertical transistor of the present application has reduced parasitic capacitance and a reduced tendency of electrical shorting between a top source/drain structure and the gate structure. The method of the present application can improve device yield. | 2020-07-23 |
20200235239 | SEMICONDUCTOR DEVICE - A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate. | 2020-07-23 |
20200235240 | Diamond MIS Transistor - The invention relates to a deep depletion MIS transistor ( | 2020-07-23 |
20200235241 | SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH - Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. | 2020-07-23 |
20200235242 | Oxide Sintered Material, Method of Producing Oxide Sintered Material, Sputtering Target, and Method of Producing Semiconductor Device - The present invention relates to an oxide sintered material that can be used suitably as a sputtering target for forming an oxide semiconductor film using a sputtering method, a method of producing the oxide sintered material, a sputtering target including the oxide sintered material, and a method of producing a semiconductor device | 2020-07-23 |
20200235243 | MULTILAYER INSULATOR STACK FOR FERROELECTRIC TRANSISTOR AND CAPACITOR - Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer. | 2020-07-23 |
20200235244 | LOW RESISTANCE FIELD-EFFECT TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator. | 2020-07-23 |
20200235245 | FLEXIBLE ELECTRONIC COMPONENTS AND METHODS FOR THEIR PRODUCTION - A flexible electronic component in this disclosure comprises a flexible fabric substrate and a smoothing layer formed on the flexible fabric substrate. A layer of nanoplatelets derived from a layered material is deposited on the smoothing layer by inkjet printing. The layer of nanoplatelets may form a first layer of a first nanoplatelet material and there may be provided at least a second layer, of a different nanoplatelet material, formed at least in part on the first layer. First and second electrodes are provided in contact respectively with the first and second layers. | 2020-07-23 |
20200235246 | THIN-FILM TRANSISTORS WITH LOW CONTACT RESISTANCE - Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance. | 2020-07-23 |
20200235247 | SPUTTERING TARGET, OXIDE SEMICONDUCTOR THIN FILM, THIN FILM TRANSISTOR, AND ELECTRONIC DEVICE - A sputtering target contains an oxide sinter that contains indium (In) element, tin element (Sn), zinc element (Zn), X element and oxygen, that further contains a spinel structure compound represented by Zn | 2020-07-23 |
20200235248 | WIDE BANDGAP SEMICONDUCTOR SWITCHING DEVICE WITH WIDE AREA SCHOTTKY JUNCTION, AND MANUFACTURING PROCESS THEREOF - A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer. | 2020-07-23 |
20200235249 | FINFET BASED CAPACITORS AND RESISTORS AND RELATED APPARATUSES, SYSTEMS, AND METHODS - This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate. | 2020-07-23 |
20200235250 | POWER COLLECTOR - Embodiments provide a photovoltaic cell, including: a first conduction layer; a second conduction layer; a photonic absorption layer electrically coupled to the first conduction layer, the photonic absorption layer is tuned to absorb incident light at a first wavelength of the incident light to generate a first electric current along the first conduction layer; and a plasma-sonic layer electrically coupled to the photonic absorption layer and the second conduction layer, the plasma-sonic layer includes nanoparticles, the nanoparticles are tuned to a second wavelength of the incident light that induces electrons to oscillate at a surface of the nanoparticles. | 2020-07-23 |
20200235251 | METHOD OF MANUFACTURING AN INTEGRATED COMPONENT WITH IMPROVED SPATIAL OCCUPATION, AND INTEGRATED COMPONENT - A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for detecting electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a mobile mass of a micromirror. The stator and the rotor form an assembly for capacitively driving the mobile mass. | 2020-07-23 |
20200235252 | SEMICONDUCTOR DETECTORS INTEGRATED WITH BRAGG REFLECTORS AND METHODS OF FORMING SAME - The present disclosure generally relates to semiconductor detectors for use in optoelectronic devices and integrated circuit (IC) chips, and methods for forming same. More particularly, the present disclosure relates to integration of semiconductor detectors with Bragg reflectors. The photodetector of the present disclosure includes a substrate, a Bragg reflector disposed on the substrate, and a semiconductor detector disposed on the Bragg reflector. The Bragg reflector includes alternating layers of a semiconductor material and a dielectric material. | 2020-07-23 |