30th week of 2020 patent applcation highlights part 57 |
Patent application number | Title | Published |
20200234953 | METAL-ORGANIC PULSED LASER DEPOSITION FOR STOICHIOMETRIC COMPLEX OXIDE THIN FILMS - Methods and systems for forming complex oxide films are provided. Also provided are complex oxide films and heterostructures made using the methods and electronic devices incorporating the complex oxide films and heterostructures. In the methods pulsed laser deposition is conducted in an atmosphere containing a metal-organic precursor to form highly stoichiometric complex oxides. | 2020-07-23 |
20200234954 | PRODUCTION OF SEMICONDUCTOR NANOWIRES DIRECTLY FROM SOLID PARTICLES - Disclosed is a process for producing semiconductor nanowires having a diameter or thickness from 2 nm to 100 nm, the process comprising: (A) preparing a semiconductor material particulate having a size from 50 nm to 500 μm, selected from Ga, In, Ge, Sn, Pb, P, As, Sb, Bi, Te, a combination thereof, a compound thereof, or a combination thereof with Si; (B) depositing a catalytic metal, in the form of nanoparticles having a size from 1 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the semiconductor material particulate to form a catalyst metal-coated semiconductor material; and (C) exposing the catalyst metal-coated semiconductor material to a high temperature environment, from 100° C. to 2,500° C., for a period of time sufficient to enable a catalytic metal-assisted growth of multiple semiconductor nanowires from the particulate. | 2020-07-23 |
20200234955 | DIRECT-STRUCTURABLE FORMULATIONS BASED ON METAL OXIDE PRECURSORS FOR PRODUCING OXIDIC LAYERS - The invention relates to direct-structurable coating compositions comprising a metal oxide precursor, a photoacid generator, and a solvent. The present invention also relates to the use of such a coating composition to produce directly structured metal oxide layers, a method for producing metal oxide layers using such a coating composition, a metal oxide-containing layer produced according to such a method, and the use of such a metal oxide-containing layer to produce electronic components, in particular to produce transistors, diodes, sensors or solar cells. | 2020-07-23 |
20200234956 | Method of Fabricating Thin, Crystalline Silicon Film and Thin Film Transistors - A method of producing a reduced-defect density crystalline silicon film includes forming a first intrinsic silicon film on a substrate, forming a doped film including silicon or germanium on the first intrinsic silicon film, forming a second intrinsic silicon film on the doped film, and annealing to crystallize the doped film, the second intrinsic silicon film, and the first intrinsic silicon, wherein each film is amorphous at formation, wherein crystallization initiates within the doped film. A method of forming a thin film transistor includes forming an active layer in the crystallized second intrinsic silicon layer by doping the crystallized second intrinsic silicon layer in selected areas to form source and drain regions separated by a channel portion, forming a gate insulator layer on the crystallized second intrinsic silicon layer, and forming a gate electrode pattern over the gate insulator layer. | 2020-07-23 |
20200234957 | DIRECT EXTREME ULTRAVIOLET LITHOGRAPHY ON HARD MASK WITH REVERSE TONE - A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material. | 2020-07-23 |
20200234958 | Simultaneous Hydrophilization of Photoresist and Metal Surface Preparation: Methods, Systems, and Products - Methods and systems for using the downstream active residuals of a reducing-chemistry atmospheric plasma to provide multiple advantages to pre-plating surface preparation with a simple apparatus. As the downstream active species of the atmospheric plasma impinge the substrate surface, three important surface preparation processes can be performed simultaneously:
| 2020-07-23 |
20200234959 | Methods And Materials For Modifying The Threshold Voltage Of Metal Oxide Stacks - Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures. | 2020-07-23 |
20200234960 | Ge-CONTAINING Co-FILM FORMING MATERIAL, Ge-CONTAINING Co FILM AND FILM FORMING METHOD THEREOF - To provide a film forming material and a film forming process for forming, at a lower temperature, a Ge-containing Co film including a desired amount of Ge. A film forming material for forming a Ge-containing Co film according to the invention is represented by either formula (1) or formula (2) below R | 2020-07-23 |
20200234961 | SUBSTRATE PROCESSING METHOD - A substrate processing method includes processing a substrate, which has a first main surface to which a protection tape is attached, from a side of a second main surface thereof, which is opposite from the first main surface; and transferring the substrate in a state that an electrostatic supporter configured to be attracted by an electrostatic attraction force is connected to the substrate after being processed in the processing of the substrate. Since the substrate after being processed is transferred in the state that the electrostatic supporter is connected thereto, weakness of the substrate can be supported by the electrostatic supporter, so that deformation or damage of the substrate during the transfer thereof can be suppressed. | 2020-07-23 |
20200234962 | DRY ETCHING GAS COMPOSITION AND DRY ETCHING METHOD - A dry etching gas composition is used which contains a saturated or unsaturated hydrofluorocarbon compound (excluding 1,2,2,3-pentafluorocyclobutane and 1,1,2,2-tetrafluorocyclobutane) represented by a general formula (1): | 2020-07-23 |
20200234963 | ETCHING METHOD AND ETCHING APPARATUS - An etching method include: etching a silicon-containing film or a metal-containing film formed on a substrate; and heating the substrate by temporarily irradiating the substrate with electromagnetic waves during the etching. | 2020-07-23 |
20200234964 | METHOD OF PLASMA ETCHING AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz. | 2020-07-23 |
20200234965 | METHOD OF PLASMA ETCHING AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - Disclosed are a method of plasma etching and a method of fabricating a semiconductor device including the same. The method of plasma etching includes loading a substrate including an etch target onto a first electrode in a chamber, the chamber including the first electrode and a second electrode arranged to face each other, and etching the target. The etching the target includes applying a plurality of RF powers to one of the first and second electrodes. The plurality of RF powers may include a first RF power having a first frequency in a range from about 40 MHz to about 300 MHz, a second RF power having a second frequency in a range from about 100 kHz to about 10 MHz, and a third RF power having a third frequency in a range from about 10 kHz to about 5 MHz. | 2020-07-23 |
20200234966 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern. | 2020-07-23 |
20200234967 | Method for Multi-Level Etch, Semiconductor Sensing Device, and Method for Manufacturing Semiconductor Sensing Device - Present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached. A semiconductor sensing device manufactured by the multi-level etch is also disclosed. | 2020-07-23 |
20200234968 | SELECTIVE PLASMA ETCHING OF SILICON OXIDE RELATIVE TO SILICON NITRIDE BY GAS PULSING - A method for selective plasma etching of silicon oxide relative to silicon nitride. The method includes a) providing a substrate containing a silicon oxide film and a silicon nitride film, b) exposing the substrate to a plasma-excited treatment gas containing | 2020-07-23 |
20200234969 | Ozone Treatment for Selective Silicon Nitride Etch Over Silicon - Apparatus, systems, and methods for processing a workpiece are provided. In one example implementation, the workpiece can include a silicon nitride layer and a silicon layer. The method can include admitting an ozone gas into a processing chamber. The method can include exposing the workpiece to the ozone gas. The method can include generating one or more species from a process gas using a plasma induced in a plasma chamber. The method can include filtering the one or more species to create a filtered mixture. The method can further include exposing the workpiece to the filtered mixture in the processing chamber such that the filtered mixture at least partially etches the silicon nitride layer more than the silicon layer. Due to ozone gas reacting with surface of silicon layer prior to etching process with fluorine-containing gas, selective silicon nitride etch over silicon can be largely promoted. | 2020-07-23 |
20200234970 | FILM ETCHING METHOD FOR ETCHING FILM - An etching method includes a step of selectively forming deposit on a top surface of a mask disposed on a film of a substrate, a step of etching the film after the step of forming the deposit, a step of forming a layer of chemical species included in plasma of a processing gas, on the substrate, and a step of supplying ions from plasma of an inert gas to the substrate so that the chemical species react with the film. | 2020-07-23 |
20200234971 | SYSTEMS AND METHODS TO FORM AIRGAPS - Exemplary etching methods may include flowing a fluorine-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a hydrogen-containing precursor into the substrate processing region. The methods may include contacting a substrate housed in the substrate processing region with the fluorine-containing precursor and the hydrogen-containing precursor. The substrate may include a trench or recessed feature, and a spacer may be formed along a sidewall of the trench or feature. The spacer may include a plurality of layers including a first layer of a carbon-containing or nitrogen-containing material and a second layer of an oxygen-containing material. The methods may also include removing the oxygen-containing material. | 2020-07-23 |
20200234972 | DOUBLE PATTERNING METHOD - The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask. | 2020-07-23 |
20200234973 | HIGH PRESSURE AND HIGH TEMPERATURE ANNEAL CHAMBER - Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example the method of annealing substrates in a processing chamber includes loading a plurality of substrates into an internal volume of the processing chamber. The method includes flowing a processing fluid through a gas conduit into the internal volume. The method further includes measuring a temperature of the gas conduit at one or more position utilizing one or more temperature sensors. The processing fluid in the gas conduit and the internal volume are maintained at a temperature above a condensation point of the processing fluid. | 2020-07-23 |
20200234974 | Etching Method and Etching Apparatus - There is provided an etching method which includes: forming a blocking film configured to prevent an etching gas for etching a silicon-containing film from passing through each pore of a porous film and prevent the etching gas from being supplied to a film not to be etched, by supplying at least one film-forming gas to a substrate in which the silicon-containing film, the porous film, and the film not to be etched are sequentially formed adjacent to each other in a lateral direction; and etching the silicon-containing film by supplying the etching gas. | 2020-07-23 |
20200234975 | PRE-CUT PLATING LINES ON LEAD FRAMES AND LAMINATE SUBSTRATES FOR SAW SINGULATION - Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame. | 2020-07-23 |
20200234976 | METHOD OF FASTENING A SEMICONDUCTOR CHIP ON A LEAD FRAME, AND ELECTRONIC COMPONENT - A method of attaching a semiconductor chip to a lead frame, including A) providing a semiconductor chip, B) applying a solder metal layer sequence on the semiconductor chip, C) providing a lead frame, D) applying a metallization layer sequence on the lead frame, E) applying the semiconductor chip on the lead frame via the solder metal layer sequence and the metallization layer sequence, and F) heating the arrangement produced under E) to attach the semiconductor chip to the lead frame, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer including gold arranged between the barrier layer and the semiconductor chip. | 2020-07-23 |
20200234977 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region. | 2020-07-23 |
20200234978 | RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME - The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die. | 2020-07-23 |
20200234979 | COATING FILM FORMING METHOD AND COATING FILM FORMING APPARATUS - A coating film forming method includes: rotating a substrate at a first rotation speed in a coating cup with an upper surface open, and supplying and diffusing a coating solution for forming a coating film on the substrate; and after the supplying and diffusing the coating solution, drying the substrate by exhausting air through a gap between an annular member arranged above the substrate with centers thereof being located on a same axis and the front surface of the substrate, while rotating the substrate at a second rotation speed lower than the first rotation speed, wherein at the drying the substrate, a flow velocity of the air exhausted through the gap is higher than a flow velocity of air supplied from above the substrate in the coating cup to the substrate. | 2020-07-23 |
20200234980 | SUBSTRATE DRYING METHOD AND SUBSTRATE DRYING APPARATUS - A processing liquid containing a sublimable material is supplied to a front surface of a substrate to which a liquid adheres to form a liquid film. The liquid film is solidified into a solidified body. Nitrogen gas is supplied to the solidified body formed on the front surface of the substrate so that the flow rate thereof per unit area is constant over the entire surface of the substrate. The solidified body is sublimated uniformly over the entire surface of the substrate, and a gas-solid interface of the solidified body moves in a direction perpendicular to the front surface of the substrate. This precludes protrusions of a pattern from being pulled by the movement of the gas-solid interface of the solidified body, whereby the front surface of the substrate is dried well while the collapse of the pattern formed on the front surface of the substrate is prevented. | 2020-07-23 |
20200234981 | MOVABLE AND REMOVABLE PROCESS KIT - Aspects of the present disclosure generally relate to methods and apparatuses for adjusting an edge ring position, and for removing or replacing one or more components of a process kit of a process chamber. The process kit includes one or more of an edge ring, a support ring, a sliding ring, and other consumable or degradable components. | 2020-07-23 |
20200234982 | LOADLOCK INTEGRATED BEVEL ETCHER SYSTEM - Implementations disclosed herein describe a bevel etch apparatus within a loadlock bevel etch chamber and methods of using the same. The bevel etch apparatus has a mask assembly within the loadlock bevel etch chamber. During an etch process, the mask assembly delivers a gas flow to control bevel etch without the use of a shadow frame. As such, the edge exclusion at the bevel edge can be reduced, thus increasing product yield. | 2020-07-23 |
20200234983 | Method for Processing a Workpiece Using a Multi-Cycle Thermal Treatment Process - A method for processing a workpiece is provided. The method can include placing a workpiece on a susceptor disposed within a processing chamber. The method can include performing a multi-cycle thermal treatment process on the workpiece in the processing chamber. The multi-cycle thermal treatment process can include at least two thermal cycles. Each thermal cycle of the at least two thermal cycles can include performing a first treatment on the workpiece at a first temperature; heating a device side surface of the workpiece to a second temperature in less than one second; performing a second treatment on the workpiece at approximately the second temperature; and cooling the workpiece subsequent to performing the second treatment. | 2020-07-23 |
20200234984 | COMPONENT MOUNTING MACHINE - A component mounting machine includes a control device that controls a wafer supply device and a component transfer device. The control device includes a die information storage section storing the position of the dies stored in the wafer supply device associated with a rank of the dies, a block information acquisition section acquiring the condition of the dies to be mounted on a block provided on a board, a rank designation section designating the rank of the die to be picked up by the component transfer device, and a position designation section designating the position of the die to be picked up by the component transfer device. The position designation section designates the position of the die so that the die having the rank designated by the rank designation section is continuously picked up over the multiple wafers stored in the wafer supply device. | 2020-07-23 |
20200234985 | SUBSTRATE PROCESSING DEVICE AND COMPONENT INSPECTION METHOD FOR SUBSTRATE PROCESSING DEVICE - A substrate processing device according to the present invention is a substrate processing device that performs substrate processing with a processing solution and includes inspection means for inspecting degradation of components constituting the substrate processing device. The inspection means includes: capturing means for acquiring image data of the components; color information acquisition means for acquiring color information of an inspection target component from the image data acquired by the capturing means; and degradation determination means for determining a degradation degree of the inspection target component based on the acquired color information. | 2020-07-23 |
20200234986 | Combination Vacuum And Over-Pressure Process Chamber And Methods Related Thereto - A process chamber system adapted for both vacuum process steps and steps at pressures higher than atmospheric pressure. The chamber door may utilize a double door seal which allows for high vacuum in the gap between the seals such that the sealing force provided by the high vacuum in the seal gap is higher than the opposing forces due to the pressure inside the chamber and the weight of the components. | 2020-07-23 |
20200234987 | POD OPENER - A pod opener includes an elevating mechanism elevating the cassette in a vertical direction, a first hook member engaging with an engagement means of the cassette and supporting the cassette, a second hook member supported by the first hook member, a forward and backward movement mechanism moving the first hook member and the second hook member forward and backward with respect to the cassette, an urging member urging the second hook member upward, and an atmosphere maintaining device maintaining an internal space having the cassette disposed therein in a predetermined atmosphere and the second hook member is displaceable with respect to the first hook member. | 2020-07-23 |
20200234988 | Load Port Assembly with Gas Curtain Device, and Purging Method for Substrate Storage Pod - A load port assembly includes a stage for supporting a substrate storage pod, a port plate with an access port, and a gas curtain device mounted on the port plate for forming a gas curtain having a width sufficient for shielding the access port. The gas curtain device includes an elongated casing and a gate mechanism. A curtain-forming gas is discharged from an elongated port of the elongated casing to form the gas curtain. A gate mechanism is mounted to the elongated casing and is configured to be actutable so as to vary a thickness of the gas curtain. A purging method for the substrate storage pod on the load port assembly is also disclosed. | 2020-07-23 |
20200234989 | SUBSTRATE PROCESSING DEVICE - Provided is an exhaust device with improved exhaust efficiency. The exhaust device includes: a plurality of exhaust ports in communication with an exhaust space and configured to exhaust gas in a first direction; a plurality of exhaust paths respectively connected to the plurality of exhaust ports; and a transfer port in communication with the plurality of exhaust paths and configured to exhaust gas in a second direction. More uniform processing of a substrate may be achieved through a substrate processing device using such an exhaust device. | 2020-07-23 |
20200234990 | TRANSFER DEVICE, SUBSTRATE PROCESSING SYSTEM, TRANSFER METHOD AND SUBSTRATE PROCESSING METHOD - A transfer device, configured to hold a substrate to be thinned and configured to be moved along a transfer path through which the substrate is transferred, includes a grip member configured to hold a frame to which the substrate is mounted with a tape therebetween; a guide member configured to be moved along the transfer path together with the grip member and configured to place thereon the frame held by the grip member; and a moving mechanism configured to move the grip member with respect to the guide member to move the frame held by the grip member along the guide member. | 2020-07-23 |
20200234991 | SUBSTRATE CARRIER - Embodiments of a substrate carrier are provided herein. In some embodiments, a substrate carrier includes a base plate, wherein the base plate is a thin, solid plate with no through holes or embedded components; and a plurality of raised portions extending from the base plate, wherein the plurality of raised portions include first raised portions and second raised portions, the first raised portions disposed radially inward from the second raised portions, wherein the base plate and the plurality of raised portions define pockets configured to retain a plurality of substrates, and wherein an upper surface of the second raised portions have a greater surface area than an upper surface of the first raised portions. | 2020-07-23 |
20200234992 | HOLDING APPARATUS FOR ELECTROSTATICALLY HOLDING A COMPONENT, INCLUDING A BASE BODY JOINED BY DIFFUSION BONDING, AND PROCESS FOR ITS MANUFACTURE - A holding apparatus, which is adapted for electrostatically holding a component, in particular a wafer, comprises an electrically insulating base body, which comprises a first pair of base body plates, which are connected to one another in a planar manner via a joint connection, and an electrode device with at least one electrode layer, which is arranged to generate an electrostatic holding force and extends parallel to the extension of the base body plates along the joining connection, wherein the joining connection comprises a diffusion bond connection, wherein the at least one electrode layer is connected in a planar manner to the respectively adjacent base body plate, and the at least one electrode layer has a contact section, which is arranged for electrically contacting the at least one electrode layer. Methods for manufacturing the holding apparatus are also described. | 2020-07-23 |
20200234993 | LASER-RELEASABLE BONDING MATERIALS FOR 3-D IC APPLICATIONS - Novel polyketanil-based compositions for use as a laser-releasable composition for temporary bonding and laser debonding processes are provided. The inventive compositions can be debonded using various UV lasers, at wavelengths from about 300 nm to about 360 nm, leaving behind little to no debris. The layers formed from these compositions possess good thermal stabilities and are resistant to common solvents used in semiconductor processing. The compositions can also be used as build-up layers for redistribution layer formation. | 2020-07-23 |
20200234994 | PROTECTIVE FILM AGENT FOR LASER DICING - A protective film agent for laser dicing that includes a solution in which at least a water-soluble resin, an organic solvent, and an ultraviolet absorber are mixed and in which the content of sodium (Na) of the solution is equal to or lower than 100 ppb in weight ratio. Preferably, the solution further includes an antioxidant. | 2020-07-23 |
20200234995 | Wafer Processing Tools and Methods Thereof - A wafer processing device may include a wafer exchanger including two or more blades, each of the two or more blades may be configured to receive a wafer, the two or more blades may be rotatable about an axis on a single horizontal plane, and the two or more blades may be movable between at least a load cup and a robot access location; wherein the load cup may include a wafer station that is vertically moveable relative a blade located in the load cup and may be configured to remove a wafer from a blade located in the load cup and place a wafer on a blade located in the load cup. Other devices, load cups and methods are also disclosed herein. | 2020-07-23 |
20200234996 | VENTED SUSCEPTOR - A susceptor can include a generally circular shape and may include an inner and outer susceptor. The outer susceptor can include a support region having one or more support mechanisms as well as a channel region extending from the region boundary to an outer radial boundary radially inward of an outer edge of the susceptor, the channel region can include a plurality of channels extending radially from the region boundary to the outer radial boundary. The inner susceptor can include a second plurality of channels extending from the inner radial boundary to an edge of the inner susceptor. | 2020-07-23 |
20200234997 | SUBSTRATE PROCESSING METHOD - A substrate processing method is implemented in a substrate processing apparatus including a processing chamber, a turntable on which a substrate is placed inside the processing chamber, and first and second gas supplies that supply first and second gases, respectively. The substrate processing method deposits a film, generated by a reaction between the first gas and the second gas, on the substrate in a first state where the substrate rotates and the turntable undergoes a clockwise orbital rotation around a rotating shaft so that the substrate passes through a region supplied with the first gas and thereafter passes through a region supplied with the second gas, and deposits the film on the substrate in a second state where the substrate rotates and the turntable undergoes a counterclockwise orbital rotation. | 2020-07-23 |
20200234998 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A method includes rotating a substrate, supplying a first processing liquid from a first nozzle to the substrate during a first period, and supplying a second processing liquid from a second nozzle to the substrate during a second period. First and second liquid columns are formed by the first and second processing liquids during at least partially overlapped period of the first and second periods, respectively. The shapes and arrangements of the first and second liquid columns satisfy that: at least one of first and second central axis lines of the first and second liquid columns is inclined with respect to a rotational axis line of the substrate, first and second cut surfaces obtained by cutting the first and second liquid columns along a horizontal plane at least partially overlap each other, and any point on the first central axis line is located on the second central axis line. | 2020-07-23 |
20200234999 | GAPS IN TRANSISTOR GATE METAL - Certain aspects of the present disclosure provide a transistor device, such as a fin field-effect transistor (finFET) device, and techniques for fabrication thereof. One example transistor device generally includes one or more semiconductor channel regions and a metal region disposed above the one or more semiconductor channel regions. The metal region has one or more gaps (e.g., air gaps) disposed therein. | 2020-07-23 |
20200235000 | IC STRUCTURE WITH AIR GAPS AND PROTECTIVE LAYER AND METHOD FOR MANUFACTURING THE SAME - Provided is an integrated circuit structure and a method for manufacturing the same. The integrated circuit structure comprises a substrate; a plurality of interconnecting structures on the substrate, each of the interconnecting structures comprises side surfaces and a top surface, the side surfaces directly define air gaps therebetween isolating the interconnecting structures from each other; and a planar protective layer on top of the plurality of interconnecting structures covering all of the air gaps. The protective layer comprises a sheltering film and a supporting film. | 2020-07-23 |
20200235001 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench. | 2020-07-23 |
20200235002 | GAP FILL VOID AND CONNECTION STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively. | 2020-07-23 |
20200235003 | SEMICONDUCTOR DEVICES - A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions. | 2020-07-23 |
20200235004 | METHODS OF FORMING AN APPARATUS, AND RELATED APPARATUSES AND ELECTRONIC SYSTEMS - A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described. | 2020-07-23 |
20200235005 | APPARATUS WITH MULTIDIELECTRIC SPACERS ON CONDUCTIVE REGIONS OF STACK STRUCTURES, AND RELATED METHODS - Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance. | 2020-07-23 |
20200235006 | ENHANCED COBALT AGGLOMERATION RESISTANCE AND GAP-FILL PERFORMANCE BY RUTHENIUM DOPING - In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition. | 2020-07-23 |
20200235007 | CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate. | 2020-07-23 |
20200235008 | OXYGEN-FREE REPLACEMENT LINER FOR IMPROVED TRANSISTOR PERFORMANCE - Embodiments of the invention are directed to a method of forming an interconnect structure. A non-limiting example of the method includes forming a transistor over a substrate, forming a dielectric region over the transistor and the substrate, and forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench includes a gate spacer of the transistor. A volume of the trench is increased by removing the gate spacer from the sidewall of the trench. A first liner and a conductive plug are deposited within a bottom portion of the trench. | 2020-07-23 |
20200235009 | METHOD FOR MANUFACTURING A CHIP PACKAGE - A method of manufacturing chip package is disclosed. The method includes steps of providing a wafer with an upper surface and a lower surface opposite thereto, in which a plurality of conductive pads are disposed on the upper surface; forming a plurality of conductive bumps on the corresponding conductive pads; thinning the wafer from the lower surface towards the upper surface; forming an insulating layer under the lower surface; etching the upper surface of the wafer to form a plurality of trenches exposing the insulating layer; forming a passivation layer covering an inner wall of each of the trenches; and dicing the passivation layer and the insulating layer along each of the trenches to form a plurality of chip packages. | 2020-07-23 |
20200235010 | WAFER PROCESSING METHOD - A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet. | 2020-07-23 |
20200235011 | WAFER PROCESSING METHOD - A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet. | 2020-07-23 |
20200235012 | METHOD FOR PRODUCING A PLURALITY OF COMPONENTS - The invention relates to a method for producing a plurality of components ( | 2020-07-23 |
20200235013 | VERTICALLY STACKED FINFETS & SHARED GATE PATTERNING - Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants. | 2020-07-23 |
20200235014 | INTEGRATED CIRCUITS WITH RECESSED GATE ELECTRODES - Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. | 2020-07-23 |
20200235015 | MASKLESS TOP SOURCE/DRAIN EPITAXIAL GROWTH ON VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR - A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO | 2020-07-23 |
20200235016 | SEMICONDUCTOR STRUCTURE AND METHOD FOR THE FORMING SAME - A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a substrate and a fin protruding from the substrate, an isolation layer is formed on the substrate exposed by the fin, and the isolation layer covers a part of side walls of the fin; forming a dummy gate structure across the fin, including a dummy gate layer, where the dummy gate structure covers a part of the top and a part of the side walls of the fin; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, where the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate layer and forming an opening in the interlayer dielectric layer; removing partial thickness of the isolation layer exposed by the opening and forming a groove in the isolation layer; and forming a gate structure in the groove and the opening, where the gate structure crosses the fin and covers a part of the top and a part of the side walls of the fin. Implementations of the present disclosure are advantageous for reducing the probability that source-drain punching through and OFF current leakage occur in the fin, and improving electrical properties of the semiconductor structure. | 2020-07-23 |
20200235017 | Thermal Profile Monitoring Wafer And Methods Of Monitoring Temperature - Thermal monitors comprising a substrate with at least one camera position on a bottom surface thereof, a wireless communication controller and a battery. The camera has a field of view sufficient to produce an image of at least a portion of a wafer support, the image representative of the temperature within the field of view. Methods of using the thermal monitors are also described. | 2020-07-23 |
20200235018 | TEMPORARY INTERCONNECT FOR USE IN TESTING A SEMICONDUCTOR PACKAGE - Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad. | 2020-07-23 |
20200235019 | PACKAGE - A package has a package body formed by stacked insulating layers and having a front surface including a mounting area, a back surface and a side surface; a plurality of hollow portions arranged so as to be adjacent to each other on the front surface of the package body; a plurality of electrode pads individually placed on respective bottom surfaces of the hollow portions; and a partition wall formed by at least one insulating layer that forms the package body and having protruding banks at its both edge sides. Surfaces of the electrode pads are located at a lower position with respect to the front surface of the package body. The hollow portions are arranged at opposite sides of the partition wall. The electrode pads are electrically connected to respective conductor layers that are formed on the back surface and/or the side surface of the package body. | 2020-07-23 |
20200235020 | Precision Structured Glass Articles, integrated circuit packages, optical devices, microfluidic devices, and Methods for Making the Same - The present disclosure relates to a reconstituted wafer- and/or panel-level package comprising a glass substrate having a plurality of cavities. Each cavity is configured to hold a single IC chip. The reconstituted wafer- and/or panel-level package can be used in a fan-out wafer or panel level packaging process. The glass substrate can include at least two layers having different photosensitivities with one layer being sufficiently photosensitive to be capable of being photomachined to form the cavities. | 2020-07-23 |
20200235021 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - To prevent deterioration of light incident/emission environment in a semiconductor device in which a transmissive material is laminated on an optical element forming surface via an adhesive. | 2020-07-23 |
20200235022 | Method and Apparatus for Reducing Noise on Integrated Circuit using Broken Die Seal - A die seal is broken in at least one place for a conductor strip formed on each conductor layer. Accordingly, no current can flow in a circular pattern around the entire perimeter of the chip. In some embodiments, an angled slot is provided in the original die seal. The angled slots may be vertically aligned. Alternatively, the slots may be vertically staggered or straight. When vertically staggered, the slots on each conductor layer are vertically offset. | 2020-07-23 |
20200235023 | INTEGRATED CIRCUIT PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF - An integrated circuit (IC) packaging structure includes a packaging substrate, one or a plurality of dies, an encapsulation material, at least one trench, and a heat dissipation structure. The one or the plurality of the dies is disposed on the packaging substrate. The encapsulation material is disposed on the packaging substrate and is configured to encapsulate the one or the plurality of the dies on the packaging substrate. The at least one trench is disposed in the encapsulation material. At least a part of the heat dissipation structure is disposed in the at least one trench. The cooling capability of the IC packaging structure may be improved by the heat dissipation structure without increasing the size of the IC packaging structure significantly. | 2020-07-23 |
20200235024 | RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME - The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die. | 2020-07-23 |
20200235025 | ELECTRONIC APPARATUS - An electronic apparatus includes a first board, a second board, a housing, and a first thermal conductive assembly. The housing accommodates the first board and the second board. The first thermal conductive assembly connects a face of the first board, the face of the first board fronting a region between the first board and the second board, to a first face of the housing or a second face of the housing. The first face is opposed to the first board, the second face is opposed to the second board. | 2020-07-23 |
20200235026 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors. | 2020-07-23 |
20200235027 | FLIP CHIP ASSEMBLY OF QUANTUM COMPUTING DEVICES - In an embodiment, a quantum device includes an interposer layer comprising a set of vias. In an embodiment, the quantum device includes a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias. In an embodiment, the quantum device includes a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on a first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In an embodiment, the quantum device includes a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips. | 2020-07-23 |
20200235028 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region. The first element includes a first substrate, the second element includes a second substrate, the first substrate includes a material different from a material of the second substrate, the first substrate contacts the heat dissipation plate, and the second element is bonded to the heat dissipation plate in a flip-chip bonding manner | 2020-07-23 |
20200235029 | SEMICONDUCTOR STRUCTURE WITH BACK GATE AND METHOD OF FABRICATING THE SAME - A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain. | 2020-07-23 |
20200235030 | SWITCHING SEMICONDUCTOR DEVICE AND COOLING APPARATUS THEREOF - The present disclosure relates to a switching semiconductor device and a cooling apparatus thereof. The cooling apparatus of the switching semiconductor device of the present disclosure comprises a first heat dissipation plate configured to facilitate heat dissipation of a surface of the semiconductor device at an installation space, and a second heat dissipation plate disposed inside the installation space along a thickness direction of the first heat dissipation plate. The installation space is formed in a predetermined size at the surface of the semiconductor device, and the second heat dissipation plate is configured to contact the first heat dissipation plate so as to allow heat exchange. Accordingly, a heat dissipation area may be increased without increasing a size of the installation space. | 2020-07-23 |
20200235031 | HEAT SINK, INTEGRATED CIRCUIT CHIP AND CIRCUIT BOARD - A heat sink for an integrated circuit chip. The heat sink includes a base plate and a plurality of fins connected to the base plate. The base plate includes a first segment, a second segment, and a third segment that are sequentially connected; and the first segment and the third segment extend obliquely upward relative to the second segment. | 2020-07-23 |
20200235032 | METHODS OF FORMING POWER ELECTRONIC ASSEMBLIES USING METAL INVERSE OPAL STRUCTURES AND ENCAPSULATED-POLYMER SPHERES - A method of forming a bonding assembly that includes positioning a plurality of polymer spheres against an opal structure and placing a substrate against a second major surface of the opal structure. The opal structure includes the first major surface and the second major surface with a plurality of voids defined therebetween. The plurality of polymer spheres encapsulates a solder material disposed therein and contacts the first major surface of the opal structure. The method includes depositing a material within the voids of the opal structure and removing the opal structure to form an inverse opal structure between the first and second major surfaces. The method further includes removing the plurality of polymer spheres to expose the solder material encapsulated therein and placing a semiconductor device onto the inverse opal structure in contact with the solder material. | 2020-07-23 |
20200235033 | LEAD-FREE SOLDER PASTE AS THERMAL INTERFACE MATERIAL - Some implementations of the disclosure are directed to a thermal interface material. In some implementations, a method comprises: applying a solder paste between a surface of a heat generating device and a surface of a heat transferring device to form an assembly; and reflow soldering the assembly to form a solder composite, wherein the solder composite provides a thermal interface between the heat generating device and the heat transferring device, wherein the solder paste comprises: a solder powder; particles having a higher melting temperature than a soldering temperature of the solder paste, wherein the solder paste has a volume ratio of solder powder to high melting temperature particles between 5:1 and 1:1.5; and flux. | 2020-07-23 |
20200235034 | COATING COMPOSITION(S) - Described herein in some examples is a heat dissipation coating composition for an electronic device, which can comprise: a transparent coating layer deposited on a surface of the electronic device, wherein the coating layer comprises: a heat absorber selected from the group consisting of silica aerogel, carbon nanotubes, carbon nanotube aerogel, graphene, graphene aerogel, and combinations thereof, a transparent resin selected from the group consisting of a polyacrylic resin, a polycarbonate resin, a cyclic olefin resin, an epoxy resin, a urethane resin, a silicone resin, a cyanoacrylate resin, a polyester resin, and combinations thereof, and a solvent; and a heat spreader layer deposited at least partially on top of the transparent coating layer or deposited on the surface of the electronic device adjacent to the transparent coating layer, wherein the heat spreader layer comprises: metallic or non-metallic particles selected from the group consisting of copper, aluminum, graphite, carbon nanotube, graphene on a metal, graphene, and combinations thereof. | 2020-07-23 |
20200235035 | LOCATING UNIT WITH BASE SEAT LOCATING STRUCTURE - A locating unit with a base seat locating structure. The base seat locating structure includes a base seat and a locating unit. The base seat has a pair of locating holes each having a first locating hole section and a second locating hole section and a connection section connected therebetween. The second locating hole section has a locating recess. The locating unit has a main body having a first side and a second side and a through hole passing through the main body between the first and second sides. A first protruding key and a second protruding key protrude from the second side beside the through hole. The first and second protruding keys are displaceably assembled and connected with the locating holes. Free ends of the first and second protruding keys respectively have a first end section and a second end section connected and assembled with the locating recesses. | 2020-07-23 |
20200235036 | FEMALE FASTENER HOLDER FOR FIXING STRUCTURE AND FIXING STRUCTURE FOR HEAT DISSIPATION ASSEMBLY - A fixing structure for heat dissipation assembly includes a base and multiple female fastener holders. The base has at least one through bore axially extending through an upper and a lower surface thereof, as well as coupling holes located outside the through bore and respectively having an engaging element disposed therein. The female fastener holder has a lower side formed with coupling protrusions corresponding to the coupling holes. The coupling protrusion has a guiding groove radially provided thereon and having a lower and an upper end recess for engaging with the engaging element in the corresponding coupling hole. The engaging elements in the coupling holes are guided by the guiding grooves to move from the lower to the upper recesses when the female fastener holder is turned relative to the through bore and the coupling holes on the base, bringing the coupling protrusions to axially insert into the coupling holes. | 2020-07-23 |
20200235037 | FLUORINE-CONTAINING CONDUCTIVE FILMS - An atomic layer deposition (ALD) process for depositing a fluorine-containing thin film on a substrate can include a plurality of super-cycles. Each super-cycle may include a metal fluoride sub-cycle and a reducing sub-cycle. The metal fluoride sub-cycle may include contacting the substrate with a metal fluoride. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant. | 2020-07-23 |
20200235038 | THROUGH-SILICON VIAS FOR HETEROGENEOUS INTEGRATION OF SEMICONDUCTOR DEVICE STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device. | 2020-07-23 |
20200235039 | SENSING DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a sensing device and a method for fabricating the same. The sensing device includes a first sensor including a first substrate, first electrodes, and a first passivation layer and a second sensor disposed on the first sensor and including a second substrate, second electrodes, and a second passivation layer. The second sensor is connected to the first sensor through a chemical bonding. | 2020-07-23 |
20200235040 | RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME - The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die. | 2020-07-23 |
20200235041 | DISPLAY DEVICE AND CHIP-ON-FILM STRUCTURE THEREOF - A display device and a chip-on-film structure thereof are provided. The chip-on-film structure includes a substrate, multiple first output pads, multiple second output pads, multiple first lead wires, and multiple second lead wires. The substrate has a surface including a bonding zone. The first and output pads are located in the bonding zone. The first lead wires and the first output pads are located on the same surface of the substrate. The first lead wires and the second lead wires are located on two opposite surfaces of the substrate. Each of the first lead wires is connected to one of the first output pads. Each of the second lead wires is connected to one of the second output pads. The second lead wires each have a portion corresponding to the bonding zone and having the terminal sections that are respectively opposite to the first and second output pads. | 2020-07-23 |
20200235042 | ELECTRONIC DEVICE WITH LEAD PITCH GAP - An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern. | 2020-07-23 |
20200235043 | SIDERAIL WITH MOLD COMPOUND RELIEF - A method of manufacturing a semiconductor package includes attaching semiconductor dies to an array of leadframes and positioning a clip array in alignment with the array of leadframes within a mold cavity, the clip array including clips that electrically connect to at least some of the semiconductor dies and a siderail along a perimeter of the clip array. The siderail forms a set of reliefs extending from an outer edge of the siderail to an inner edge of the siderail, the inner edge being adjacent to the array of leadframes. The method also includes injecting a mold compound into the mold cavity through a flow path including the set of reliefs of the siderail to form a mold block at least partially covering the semiconductor dies. | 2020-07-23 |
20200235044 | LEADFRAME IN PACKAGES OF INTEGRATED CIRCUITS - Embodiments include apparatuses, methods, and systems that may include a leadframe of a circuit package to conduct heat generated by an integrated circuit (IC) included in the circuit package, while being a part of an interconnect of the circuit package. In various embodiments, a circuit package may include a package substrate, and an IC attached to the package substrate. A leadframe may be disposed on the IC to conduct heat generated by the IC. In addition, the leadframe may be a part of an interconnect of the circuit package, and the leadframe may be electrically coupled to a component of the IC. Other embodiments may be described and/or claimed. | 2020-07-23 |
20200235045 | SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD OF MANUFACTURE - A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane. | 2020-07-23 |
20200235046 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components. | 2020-07-23 |
20200235047 | PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS - Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars. | 2020-07-23 |
20200235048 | LOW-INDUCTANCE CURRENT PATHS FOR ON-PACKAGE POWER DISTRIBUTIONS AND METHODS OF ASSEMBLING SAME - A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor. | 2020-07-23 |
20200235049 | Semiconductor Devices Having Nonlinear Bitline Structures - Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space. | 2020-07-23 |
20200235050 | 3D STACKED MEMORY AND VERTICAL INTERCONNECT STRUCTURES FOR 3D STACKED MEMORY - Provided is a 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate. Vertical memory stacks and a vertical interconnect structure are provided in the cell region. The vertical interconnect structure includes: a via-hole formed along a vertical direction of the cell region; and a conductive pillar shaped by filling the via-hole with a conductive material. The vertical interconnect structure is configured to interconnect a top electrode of the vertical memory stack and a conductive region of the substrate along the vertical direction. The 3D stacked memory device has a vertical interconnect structure configured with a vertical wiring plug of a conductive material in a cell region, so that it is possible to facilitate the manufacturing process and providing a vertical interconnect between top and bottom electrodes of the stacked memory device or a peripheral circuit of the substrate. | 2020-07-23 |
20200235051 | PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE - Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region. | 2020-07-23 |
20200235052 | HEXAGONALLY ARRANGED CONNECTION PATTERNS FOR HIGH-DENSITY DEVICE PACKAGING - Hexagonally arranged connection patterns for device packaging allow high density circuitry dies to be assembled into packages of manufacturable size. The connection patterns may be patterns for solder ball arrays or other types of connection mechanisms under a semiconductor package. Despite the increased density of the connection patterns, the connection patterns meet the demanding crosstalk specifications for high speed operation of the high density circuitry. | 2020-07-23 |