30th week of 2015 patent applcation highlights part 60 |
Patent application number | Title | Published |
20150207458 | FIBER COMPOSITE SOLAR PANEL FOR ELECTRICITY GENERATION AND HEAT COLLECTION - A building integrated photovoltaic and heat (BIPVAH) solar panel system whereby solar panels are layered into a laminate with a top photovoltaic composite layer, a middle heat exchanging fiber composite frame, and a bottom fiber composite layer. These three layers in turn form a composite structure for a strong and lightweight structure for the purposes of electricity and heat generation. The panels are strong and lightweight so as to provide a solution for shading structures such as awning, and a flower like solar tracking system that can close at night and under adverse climate conditions, etc. | 2015-07-23 |
20150207459 | APPARATUS AND METHOD FOR COLLECTING STATE INFORMATION OF SOLAR MODULE - The present invention provides an apparatus and method for collecting state information of a solar module, which map a physical shape of a solar module, a string, and an array to a network layer of a modem, a repeater, and a gateway, and receive information about a solar power generation state from a node of an activated lower layer, thereby increasing an efficiency of data collection. | 2015-07-23 |
20150207460 | PULSE INJECTION CRYSTAL OSCILLATOR - An improved oscillation driver circuit for use in an integrated circuit in combination with an oscillation element. An amplification element is adapted to receive an oscillator output, and to generate an amplified oscillator output. A pulse generator receives the amplified oscillator output and generates positive and negative pulsed outputs substantially in phase with the oscillator output. A driver element is adapted to drive the oscillator input in response to the pulsed outputs. | 2015-07-23 |
20150207461 | DYNAMIC BIASING OF POWER AMPLIFIERS - Systems and methods are provided for dynamically biasing power amplifiers. In particular, dynamic biasing of a power amplifier may be controlled, with the controlling comprising receiving an input signal that is to be amplified; processing the input signal; generating based on said processing of the input signal input signal, a plurality of control signals comprising at least one biasing control signal; and applying the plurality of control signals to one or more control elements that are used in driving and/or control of the power amplifier. The one or more control elements may comprise at least one biasing component that adjusts biasing applied to power amplifier. | 2015-07-23 |
20150207462 | Wide Common Mode Range Sense Amplifier - A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal. | 2015-07-23 |
20150207463 | POWER AMPLIFIER SATURATION DETECTION - In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation. | 2015-07-23 |
20150207464 | TRANSMISSION APPARATUS AND TRANSMISSION METHOD - A transmission apparatus comprises a signal generator that generates input signals of two or more bands of frequencies and outputs the generated input signals; a power amplifier that amplifies the input signals and outputs amplified signals; a branching filter that outputs branched signals for the respective frequencies from the amplified signals; a data transmitter that transmits data based on one of the branched signals of a first frequency; a power regenerator that converts one of the branched signals of a second frequency into regenerated power and output the regenerated power, and a power combiner that combines the regenerated power and power supply power output from a voltage source, as combined power and supplies the combined power to the power amplifier. | 2015-07-23 |
20150207465 | SYSTEM AND METHOD TO REMOVE HEAT FROM A POWER AMPLIFIER - In one aspect a satellite comprises a body, a solid state power amplifier, a heat acquisition and transfer device positioned proximate at least one heat generating element on the solid state power amplifier, and a heat rejection device in thermal communication with the heat acquisition and transfer device to reject heat acquired from the solid state power amplifier. Other aspects may be described. | 2015-07-23 |
20150207466 | Temperature Dependent Amplifier Biasing - An apparatus includes a first bias circuit configured to generate a first current that varies with temperature according to a first slope. The apparatus also includes a second bias circuit configured to generate a second current that varies with temperature according to a second slope. The apparatus further includes a low noise amplifier including a transconductance stage that is responsive to an output of the first bias circuit. The apparatus also includes a load coupled to an output of the low noise amplifier and responsive to an output of the second bias circuit. | 2015-07-23 |
20150207467 | METHOD AND SYSTEM FOR LINEARIZING AN AMPLIFIER USING TRANSISTOR-LEVEL DYNAMIC FEEDBACK - The present disclosure describes a method and system for linearizing an amplifier using transistor-level dynamic feedback. The method and system enables nonlinear amplifiers to exhibit linear performance using one or more of gain control elements and phase shifters in the feedback path. The disclosed method and system may also allow amplifiers to act as a pre-distorter or a frequency/gain programmable amplifier. | 2015-07-23 |
20150207468 | AMPLIFIER CIRCUIT - Provided is an amplifier circuit including an NMOS transistor having a low drain breakdown voltage and an NMOS transistor having a high drain breakdown voltage connected in series thereto, and capable of preventing breakdown of a drain of the NMOS transistor having a low drain breakdown voltage. A clamp circuit configured to limit a drain voltage of the NMOS transistor having a low drain breakdown voltage is connected to the drain thereof. | 2015-07-23 |
20150207469 | PREAMPLIFIER, OPTICAL RECEIVER, OPTICAL TERMINATION DEVICE, AND OPTICAL COMMUNICATION SYSTEM - A current bypass circuit that passes part of a photocurrent output from a photodetector is connected to an input terminal of a current-to-voltage conversion amplifier circuit. A voltage obtained by level conversion of an output voltage by a voltage level conversion circuit is input into the current bypass circuit so that the current bypass circuit is turned on at a photocurrent that is smaller than the photocurrent at which a diode connected in parallel to a feedback resistor of the current-to-voltage conversion amplifier circuit is turned on. Consequently, the current-to-voltage conversion gain is switched in three stages according to the intensity of the photocurrent corresponding to an optical signal level. | 2015-07-23 |
20150207470 | STRUCTURE OF AN ACTIVE CMOS PIXEL - The invention relates to a structure of an active pixel of the CMOS type ( | 2015-07-23 |
20150207471 | AMPLIFIER ARRANGEMENT WITH LIMITING MODULE - An amplifier arrangement for amplifying an audio input signal AES into an audio output signal AAS, having a conditioning apparatus for converting the audio input signal AES into a conditioned intermediate signal ZS. The conditioning apparatus includes an audio input interface for accepting the audio input signal and a digital data processing device. The amplifier arrangement also includes an amplifier apparatus for amplifying the intermediate signal ZS into the audio output signal AAS and the amplifier apparatus has at least one operating voltage BS. The amplifier arrangement also includes a limiting module for limiting the audio output signal AAS by changing a gain parameter VK. | 2015-07-23 |
20150207472 | AMPLIFIER ARRANGEMENT COMPRISING A MASTER AMPLIFIER AND AT LEAST ONE SLAVE AMPLIFIER - An amplifier arrangement for amplifying at least one first and one second audio input signal. In one embodiment, the arrangement includes a master amplifier designed as a class D amplifier. The first audio input signal is applied to the master audio input and a master audio output signal is applied to the master audio output. The arrangement also includes a master feedback loop; thus enabling the master amplifier to be designed as a self-oscillating class D amplifier having a master oscillation frequency, at least one slave amplifier, a slave feedback loop, wherein a slave audio output signal or signal portions thereof are fed back into a slave audio input, and a master-slave coupling loop, wherein the master audio output signal or signal portions thereof is coupled into the slave audio input, so that the slave amplifier has the master oscillation frequency as its oscillation frequency. | 2015-07-23 |
20150207473 | AMPLIFIER ARRANGEMENT COMPRISING A LOW-PASS FILTER DEVICE - An amplifier arrangement with a Class D design is proposed which has a low-pass filter device comprising a first inductor and a second inductor The first inductor is arranged between a first load output and a load and the second inductor is arranged between a second load output and the load. The first and second inductors are coupled to one another so that the total inductance of the two inductors is greater than the sum of the individual inductances of the two inductors and also less than or equal to 1.95 times the sum of the individual inductances of the two inductors. | 2015-07-23 |
20150207474 | CONCURRENT MULTI-BAND RADIO FREQUENCY AMPLIFYING CIRCUIT - A concurrent multi-band RF amplifying circuit may include: an input impedance matching unit performing impedance matching on each of first and second band signals included in an input signal input through one input terminal; an input amplifying unit including first and second band amplifying units each amplifying the first and second band signals input through the input impedance matching unit; a common ground circuit unit connected between a first common node commonly connected to the first and second band amplifying unit and a ground and including an impedance device for matching of an input impedance; and an output amplifying unit amplifying signals from each of the first and second band amplifying units. | 2015-07-23 |
20150207475 | FEEDBACK AND IMPEDANCE CIRCUITS, DEVICES AND METHODS FOR BROADBAND RADIO-FREQUENCY AMPLIFIERS - Feedback and impedance circuits, devices and methods for broadband radio-frequency (RF) amplifiers. An RF amplifier architecture can include an amplifier having a first field-effect transistor (FET) and a second FET arranged in a cascode configuration. The gate of the first FET can be configured to receive an RF signal, the drain of the first FET can be coupled to the source of the second FET, and the drain of the second FET can be configured to output an amplified RF signal. The RF amplifier architecture can further include a first feedback circuit implemented between the drain of the second FET and the gate of the second FET to provide gain control, and a second feedback circuit implemented between the drain of the second FET and the gate of the first FET to provide an increase in a frequency range having a desirable range of gain. | 2015-07-23 |
20150207476 | ANALOG FEEDBACK AMPLIFIER - A comparator | 2015-07-23 |
20150207477 | CHOPPER-STABILIZED AMPLIFIER AND METHOD THEREFOR - In one embodiment a chopper-stabilized amplifier may be formed to include a symmetrical passive RC notch filter having two cut-off frequencies. In an embodiment, the chopper stabilized amplifier may use only two clock signals to control the chopping operations. | 2015-07-23 |
20150207478 | Adjusting Controls of an Audio Mixer - Systems, methods, and computer program products relating to a user interface for mixing audio signals. In one embodiment, a method includes displaying in a user interface multiple source icons and a manipulator, each source icon representing a separate one of multiple audio sources, each audio source having an output level, receiving a first input modifying a position of the manipulator in the user interface, and determining gain control parameters of an audio mixer to adjust the output levels of each of the multiple audio sources according to the positions of the manipulator and the source icons relative to a reference center in response to the first input. Other embodiments include systems and computer program products. | 2015-07-23 |
20150207479 | DYNAMIC RANGE CONTROL WITH LARGE LOOK-AHEAD - A system and method applying Dynamic Range Control/Compression (DRC) to an audio signal. The dynamic range controller presented here differs from conventional DRC techniques by providing a much larger look-ahead time. In particular, the system and method takes advantage of the look-ahead by analyzing macroscopic loudness changes in the order of seconds as opposed to the microscopic changes most conventional DRCs are designed to control. This approach avoids most of the typical DRC distortions associated with conventional DRC techniques and preserves the micro-dynamics of the audio signal. Gain changes are applied at a rate comparable with manual volume adjustments by mixing and mastering engineers to balance a mix. Ideally, the DRC will approach what a professional sound engineer would do to reduce the dynamic range if there were only a volume control to accomplish the task on the final mix. | 2015-07-23 |
20150207480 | DIGITAL EQUALIZER ADAPTATION USING ON-DIE INSTRUMENT - Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased. | 2015-07-23 |
20150207481 | GENRE DEPENDENT AUDIO LEVEL CONTROL - Systems, methods, and computer program products relating to digital audio data are provided. In some implementations a method is provided. The method includes receiving a selection of an audio score, the audio score being a decomposed digital audio data template associated with one or more audio tracks, automatically identifying score information for the selected audio score, generating the selected audio score including retrieving the one or more tracks of digital audio data associated with the audio score, and modifying the settings of at least one of one or more post processors using the identified score information, where the modified settings provide an audio output level within a specified range. Other embodiments of the aspect include systems and computer program products. | 2015-07-23 |
20150207482 | AREA-EFFICIENT DEGENERATIVE INDUCTANCE FOR A LOW NOISE AMPLIFIER (LNA) - A device includes a first and a second low noise amplifier (LNA), a first degenerative inductance coupled between the first LNA and ground by a first ground connection, and a second degenerative inductance coupled between the second LNA and ground by a second ground connection, the first and second degenerative inductances configured to establish negative inductive coupling between the first and second degenerative inductances. | 2015-07-23 |
20150207483 | ANTI-INTERFERENCE METHOD AND DEVICE FOR A WIRELESS COMMUNICATION SYSTEM - An anti-interference method and device for a wireless communication system. The method includes: receiving a RF signal; analyzing the RF signal to obtain the power variation characteristic of the RF signal; and determining a gain control method according to the power variation characteristic of the RF signal. The anti-interference methods and devices according to the embodiments of the present invention can ensure the communication quality of the wireless communication system in a case that there is strong burst interference. | 2015-07-23 |
20150207484 | COMPOSITE RF CURRENT ATTENUATOR FOR A MEDICAL LEAD - A composite RF current attenuator for a medical lead includes a conductor having a distal electrode contactable to biological cells, a bandstop filter in series with the lead conductor for attenuating RF currents flow through the lead conductor at a selected center frequency or across a range of frequencies about the center frequency, and a lowpass filter in series with the bandstop filter and forming a portion of the lead conductor. The bandstop filter has a capacitance in parallel with a first inductance. In a preferred form, the lowpass filter includes a second inductance in series with the bandstop filter, wherein the values of capacitance and inductances for the composite RF current attenuator are selected such that it attenuates MRI-induced RF current flow in an MRI environment. | 2015-07-23 |
20150207485 | RC network - The present invention is related to a variable resistor and a variable capacitor having damping capabilities, more particularly, to a RC network having damping capability and phase shift capability constructed by the variable resistor and the variable capacitor. | 2015-07-23 |
20150207486 | PASSIVE SWITCH-BASED PHASE SHIFTER - Certain aspects of the present disclosure provide apparatus for producing an output signal that may have a phase difference with respect to an input signal. One example phase shifting circuit for producing such an output signal generally includes a transmission line having first and second points, an impedance connected with a node and with a reference voltage level, a first switch connected with the first point of the transmission line and with the node, and a second switch connected with the second point of the transmission line and with the node, wherein a first signal input to the first point of the transmission line has a phase difference with a second signal output from the second point based on one or more properties of the transmission line when the first and second switches are open. | 2015-07-23 |
20150207487 | SPLITTER HAVING MoCA BLOCK FUNCTION - The present invention relates to a splitter having MoCA block function, which includes: a low-pass filtering unit, one end thereof is coupled to an input end of a splitter for inputting a RF signal and performing a low-pass filtering operation to the RF signal; a first-stage splitter, an input end thereof is coupled to an output end of the low-pass filtering unit for attenuating the RF signal to a first value so as to be outputted; and at least a second-stage splitter, an input end thereof is coupled to an output end of the first-stage splitter for attenuating the RF signal to a second value so as to be outputted to at least a user-end connector. | 2015-07-23 |
20150207488 | VoIP PHONE SPLITTING DEVICE HAVING MoCA BLOCK FUNCTION - The present invention relates to a VoIP phone splitting device having MoCA block function, which includes: a low-pass filtering unit used for inputting a RF signal; a first-stage splitter, a first output end thereof is coupled to an output for attenuating the RF signal to a first value so as to be outputted; a second-stage splitter, an input end thereof is coupled to a second output end of the first-stage splitter for attenuating the RF signal to a second value so as to be outputted; and at least a third-stage splitter, an input end thereof is coupled to an output end of the second-stage splitter for attenuating the RF signal to a third value so as to be outputted to at least a user-end connector. | 2015-07-23 |
20150207489 | FILM BULK ACOUSTIC WAVE RESONATOR (FBAR) HAVING STRESS-RELIEF - An acoustic resonator structure comprises: a substrate having a cavity, which has a plurality of sides; a first electrode disposed over the cavity; a piezoelectric layer disposed over a portion of the first electrode and extending over at least one of the sides; and a second electrode disposed over the piezoelectric layer, an overlap of the first electrode, the piezoelectric layer and the second electrode forming an active area of the FBAR. The active area of the FBAR is completely suspended over the cavity. | 2015-07-23 |
20150207490 | PIEZOELECTRIC THIN FILM RESONATOR, FILTER AND DUPLEXER - A piezoelectric thin film resonator includes: a substrate; a piezoelectric film provided on the substrate; a lower electrode and an upper electrode that are opposed to each other to put at least a part of the piezoelectric film therebetween; and an insertion film that is inserted into the piezoelectric film in a resonance region where at least the part of the piezoelectric film is put between the lower electrode and the upper electrode, at least a part of the insertion film corresponding to an outer circumference region in the resonance region being thicker than a part of the insertion film corresponding to a central region in the resonance region. | 2015-07-23 |
20150207491 | DEVICE FOR NEGATIVE GROUP DELAY - A negative group delay circuit comprising a negative group delay component, also comprising a circulator with three ports, further comprising a first resonator, with the negative group delay component arranged between an input port of the negative group delay circuit and a first port in the circulator. The first resonator is arranged between a second port of the circulator and a first reflection amplifier, so that signals reflected from the first reflection amplifier to the second port of the circulator through the first resonator are emitted at the third port of the circulator. The third port is arranged to be used as an output port of the negative group delay circuit. | 2015-07-23 |
20150207492 | RAMP SIGNAL GENERATING CIRCUIT AND SIGNAL GENERATOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS - A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register ( | 2015-07-23 |
20150207493 | METHOD AND APPARATUS FOR SHIFTING DISPLAY DRIVING FREQUENCY TO AVOID NOISE OF ELECTRONIC SENSOR MODULE - A method and apparatus for shifting a display driving frequency to avoid a noise of an electronic sensor module is provided. The method for operating of an electronic device includes detecting a driving frequency of a divider in an operating module of the electronic device, determining whether an offset exists in the detected driving frequency, and controlling an oscillation frequency of an oscillator in the operating module. | 2015-07-23 |
20150207494 | SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE CIRCUIT - Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal. | 2015-07-23 |
20150207495 | Power Converter with Split Voltage Supply - A power converter driver that is supplied with two different voltages. | 2015-07-23 |
20150207496 | LATCH CIRCUIT WITH DUAL-ENDED WRITE - Embodiments of a latch circuit are disclosed that may allow a reduction in storage time of data into the latch circuit. The latch circuit may include an input circuit, a first switch, a second switch, an input circuit, and an inverting amplifier. An input of the inverting amplifier may be coupled to a storage node, and an output of the inverting amplifier may be coupled to a feedback node. The input circuit may be configured to generate buffered and complement data dependent upon received data, and the switched may be configured to allow the generated buffered data to be transferred to the feedback node, and the complement data to be transferred to the storage node. | 2015-07-23 |
20150207497 | LOW-OFFSET BANDGAP CIRCUIT AND OFFSET-CANCELLING CIRCUIT THEREIN - A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current. | 2015-07-23 |
20150207498 | PWM MODULATOR - A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator. | 2015-07-23 |
20150207499 | FREQUENCY SHIFT-KEYING READER CIRCUIT - A frequency shift-keying reader circuit includes a band-pass filter, a low noise amplifier, a first balun, an injection-lock divide-by-2 frequency divider, a sub-harmonic mixer and a low-pass filter. The band-pass filter performs a filtering procedure to a radio frequency signal, wherein the filtered radio-frequency signal is received by the low noise amplifier to provide an injection signal, and the injection signal is received by the first balun to generate a first differential signal and a second differential signal. The injection signal is received by the injection-lock divide-by-2 frequency divider to provide a first oscillation signal and a second oscillation signal, wherein the first differential signal, the second differential signal, the first oscillation signal and the second oscillation signal are received by the sub-harmonic mixer for performing a mixing procedure and thereafter generating an output signal, the low-pass filter performs a filtering procedure to the output signal. | 2015-07-23 |
20150207500 | EMPHASIS SIGNAL GENERATING CIRCUIT AND METHOD FOR GENERATING EMPHASIS SIGNAL - An emphasis signal generating circuit includes: a branch and delay unit configured to branch an input signal, delay a branched signal, and output a first delayed signal; a high-frequency extraction unit configured to extract at least one of high-frequency components of the input signal and the first delayed signal to output a high-frequency signal; and an addition and subtraction unit configured to add and subtract the input signal, the first delayed signal, and the high-frequency signal. | 2015-07-23 |
20150207501 | SYSTEM AND METHOD FOR A DYNAMIC VOLTAGE CONTROLLED OSCILLATOR - A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge. | 2015-07-23 |
20150207502 | Method and Apparatus for Reference-Less Repeater with Digital Control - Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal. | 2015-07-23 |
20150207503 | METHOD FOR COMPENSATING THIN FILM TRANSISTOR THRESHOLD VOLTAGE DRIFT - A method for compensating a threshold voltage drift of a thin film transistor comprises: controlling a drain and a gate of the thin film transistor to have a same voltage; and keeping the voltage at the gate of the thin film transistor unchanged and controlling the voltage at the drain of the thin film transistor to be equal to a voltage at a source of the thin film transistor. | 2015-07-23 |
20150207504 | CONFIGURATION CONTEXT SWITCHER WITH A LATCH - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 2015-07-23 |
20150207505 | SEMICONDUCTOR DEVICE INCLUDING ENHANCED VARIABILITY - A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region. | 2015-07-23 |
20150207506 | LEVEL SHIFTER AND SERIALIZER HAVING THE SAME - A level shifter includes a level shifting unit suitable for changing a swing voltage level of an input signal from a first swing voltage level to a second swing voltage level based on a clock signal, a precharging unit suitable for precharging an output node of the level shifting unit based on the clock signal, and an output unit suitable for latching a signal of the output node having the second swing voltage level to output as an output signal. | 2015-07-23 |
20150207507 | METHOD AND APPARATUS FOR PERFORMING PIPELINED OPERATIONS ON PARALLEL INPUT DATA WITH FEEDBACK - Embodiments of the claimed subject matter provide a method and apparatus for performing pipelined operations on input data with feedback. One embodiment of the apparatus includes a first logic circuit for determining a value of a first function based on input data for a first clock cycle. The first logic circuit includes pipeline stages that perform subsets of calculations of the value of the first function in one clock cycle. The apparatus also includes a second logic circuit for determining a value of a second function for the first clock cycle based on a value of a third function for a second clock cycle prior to the first clock cycle. The apparatus further includes a third logic circuit for determining a value of the third function for the first clock cycle by combining the values of the first and second functions for the first clock cycle. | 2015-07-23 |
20150207508 | LEVEL CONVERSION CIRCUIT - A level conversion circuit has a keeper circuit for retaining an intermediate output node at a high output level to avoid it floating due to leakage through a pullup transistor in a shifting circuit. Thin oxide and thick oxide versions of the level conversion circuit can be provided. The level conversion circuit enables higher performance, reduced power consumption and reduced susceptibility to process variation compared to previous level conversion designs. | 2015-07-23 |
20150207509 | DATA PROCESSING DEVICE AND DRIVING METHOD THEREOF - In a processor or the like including a reconfigurable (RC) circuit, the RC circuit is used to form a test circuit to test a core, a cache memory, or the like, and then part of the RC circuit is used as an auxiliary cache memory. When a memory can store data after stop of power supply, a startup routine program (SRP) of the processor can be stored therein. For example, after the test, an SRP is loaded to a memory in the RC circuit from an external ROM or the like, and when power is resupplied to the processor, a startup operation is performed using the loaded SRP. When the processor is in a normal operation state, this memory is used as an auxiliary cache memory and the SRP is overwritten. The SRP is loaded to the memory again at the end of use of the processor. | 2015-07-23 |
20150207510 | HIGH-SPEED FREQUENCY DIVIDER - A programmable high-speed frequency divider architecture is provided that is programmable to divide an input clock signal frequency by a selectable division N. The frequency divider architecture has a shift register circuit having N/2 shift register stages, connected in series when N is an even integer and trunc[N/2]+1 shift register stages when N is an odd integer. The frequency divider architecture includes a feedback logic circuit that performs a logical NAND of the output clock signal with the logical ORed result of a pre-output signal provided from a shift register stage prior to the output stage and another signal that indicates whether the selectable divisor N is odd or even. | 2015-07-23 |
20150207511 | Digital Counter Comprising Reduced Transition Density - The present document relates to a digital counter providing counting information comprising at least a first and a second counting module, said counting modules being serially coupled forming a counting module chain; each counting module comprising at least a first and a second digital storage cell, each counting module providing module counting information comprising a width of at least two bits; the counting modules being adapted to change only one bit of said module counting information between two successive counting states; wherein the counting modules are coupled such that the start of counting of the second counting module is triggered by the first counting module if said first counting module once has passed through its possible counting states. | 2015-07-23 |
20150207512 | POWER SUPPLY SYSTEM AND METHOD FOR CONTROLLING POWER SUPPLY SYSTEM - A power control device | 2015-07-23 |
20150207513 | CURRENT MIRROR CIRCUIT AND CHARGE PUMP CIRCUIT - A current mirror circuit includes: a reference current circuit including a reference transistor and a constant current source coupled between a high potential source and a low potential source; a first proportional current circuit, including a first transistor that forms a first current mirror circuit with the reference transistor, to generate a first current having a first ratio to a reference current of the reference current circuit; a second proportional current circuit, including a second transistor that forms a second current mirror circuit with the reference transistor, to generate a second current having a second ratio to the reference current; a comparison circuit to output a difference between a drain voltage of the first transistor and a drain voltage of the second transistor; and a current adjustment transistor coupled to a drain of the second transistor and including a gate to which an output of the comparison circuit is applied. | 2015-07-23 |
20150207514 | DIGITAL PHASE-LOCKED LOOP (DPLL), METHOD OF CONTROLLING DPLL, AND ULTRA LOW POWER (ULP) TRANSCEIVER USING DPLL - A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information. | 2015-07-23 |
20150207515 | Low-Power Oscillator - An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency. | 2015-07-23 |
20150207516 | QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, AND MOVING OBJECT - An atomic oscillator includes: a gas cell which includes two window portions having a light transmissive property and in which metal atoms are sealed; a light emitting portion that emits excitation light to excite the metal atoms in the gas cell; a light detecting portion that detects the excitation light transmitted through the gas cell; a heater that generates heat; and a connection member that thermally connects the heater and each window portion of the gas cell to each other. | 2015-07-23 |
20150207517 | Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators - The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source. | 2015-07-23 |
20150207518 | Method And System For Charge Compensation For Switched-Capacitor Circuits - Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground. | 2015-07-23 |
20150207519 | SIGNAL MODULATION CIRCUIT - Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal. | 2015-07-23 |
20150207520 | CIRCUIT ARRANGEMENT, DEVICE AND METHOD FOR 5B/6B CODING - The present invention proposes a circuit arrangement provided for five bit/six bit (=5 b/6 b) coding and decoding, an associated coding device as well as corresponding methods by means of which a high coded data transfer rate can be attained. | 2015-07-23 |
20150207521 | USB POWER DELIVERY MULTIPLE DROP USING CYCLIC REDUNDANCY CHECK - Methods and apparatus for operating a communication system comprising three or more communication transceivers. In illustrative embodiments, multiple different cyclic redundancy check (CRC) generation schemes are maintained. Each CRC generation scheme corresponds to a unique CRC residual value. A CRC value generated using one of the CRC generation schemes is placed in a data packet to be transmitted. The chosen CRC generation scheme reflects which one or more transceivers are intended recipients of the data packet. When a data packet is received by a transceiver, a CRC residual value is calculated based on the CRC value contained in the received data packet. The calculated CRC residual value is compared against a list of one or more valid CRC residual values for that particular transceiver. If the calculated CRC value matches one of the listed valid CRC residual values, the data packet is accepted, otherwise it is rejected. | 2015-07-23 |
20150207522 | USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCRYPTION - A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data. | 2015-07-23 |
20150207523 | LOW-POWER DUAL QUANTIZATION-DOMAIN DECODING FOR LDPC CODES - A low density parity check decoder is provided that includes a variable-node (VN) processing domain comprising high-bit resolution processing circuitry, a check-node (CN) processing domain comprising low-bit resolution processing circuitry lower than the high-bit resolution processing circuitry, and mapping circuitry configured to transfer a message between the VN processing domain and the CN processing domain. | 2015-07-23 |
20150207524 | SYSTEMS AND METHODS FOR ENCODING AND DECODING OF CHECK-IRREGULAR NON-SYSTEMATIC IRA CODES - Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and/or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers/deinterleavers. | 2015-07-23 |
20150207525 | SIGNAL AMPLIFIERS THAT SUPPORT MOCA COMMUNICATIONS AT BOTH ACTIVE AND PASSIVE OUTPUT PORTS - RF signal amplifiers are provided that include an RF input port, a power divider network having a plurality of active output ports, an active path connecting the RF input port to the power divider network, the active path including an upstream diplexer, a downstream diplexer and a power amplifier between the upstream diplexer and the downstream diplexer, a passive output port, a MoCA diplexer that is coupled to the passive output port, a passive path connecting the RF input port to the MoCA diplexer and a MoCA rejection filter between the power divider network and the active path. | 2015-07-23 |
20150207526 | Electrostatic Discharge Device Gate Biasing for a Transmitter - A transmitter, comprises: a first branch for providing a positive output having a first set of serially-connected transistors; a second branch for providing a negative output having a second set of serially-connected transistors; and a biasing circuit, wherein the biasing circuit generates a first biasing voltage and a second biasing voltage as a function of the positive output, the negative output, and a predefined threshold voltage, and wherein the first biasing voltage, the second biasing voltage, and a differential input signal drive the first set of serially-connected transistors and the second set of serially-connected transistors. | 2015-07-23 |
20150207527 | COMMUNICATION METHODS AND SYSTEMS FOR NONLINEAR MULTI-USER ENVIRONMENTS - An electronic receiver comprises a nonlinear distortion modeling circuit and a nonlinear distortion compensation circuit. The nonlinear distortion modeling circuit is operable to determine a plurality of sets of nonlinear distortion model parameter values, where each of the sets of nonlinear distortion model parameter values representing nonlinear distortion experienced by signals received by the electronic receiver from a respective one a plurality of communication partners. The nonlinear distortion compensation circuit is operable to use the sets of nonlinear distortion model parameter values for processing of signals from the plurality of communication partners. Each of the sets of nonlinear distortion model parameter values may comprises a plurality of values corresponding to a plurality of signal powers. The sets of nonlinear distortion model parameters may be stored in a lookup table indexed by a signal strength parameter. | 2015-07-23 |
20150207528 | BAND-LIMITED DIFFERENTIATOR FOR GRID APPLIANCE CONTROLLERS - A method and device for measuring electrical grid data in the presence of noise is disclosed. Noisy frequency data is received from the grid. The noisy data is filtered above a predetermined frequency. The filtered data is differentiated using band-limited differentiator. The data may be filtered and differentiated simultaneously by the band-limited differentiator. | 2015-07-23 |
20150207529 | Radiofrequency Signal Setting Reaching a Condition of Jamming or Clipping - A method of setting a Radiofrequency, RF, signal level in a RF receiver comprising:—estimating an error of the signal level due to signal level reaching a condition of jamming or clipping by correlating the signal level with a point of a characterisation curve of jamming condition or with a point of a characterisation curve of clipping condition ( | 2015-07-23 |
20150207530 | SUPER-REGENERATIVE RECEIVER (SRR) AND SUPER-REGENERATIVE RECEPTION METHOD WITH INCREASED CHANNEL SELECTIVITY - A super-regenerative receiver (SRR) includes a super-regenerative oscillator (SRO), and an active channel filter disposed at a front end of the SRO, and configured to filter out an interferer in a signal received by the SRR. | 2015-07-23 |
20150207531 | FILTERING BLOCKER COMPONENTS OF A SIGNAL - An apparatus includes a main amplifier configured to receive an input signal. The main amplifier is also configured to generate an output signal. The apparatus also includes an auxiliary path configured to phase-shift the input signal to generate a cancellation signal to reduce or cancel a blocker component of the output signal. | 2015-07-23 |
20150207532 | System and Method for a Mixer - In accordance with an embodiment, a circuit includes a mixer having a signal input port, a local oscillator input port and an output port, a lowpass filter circuit having an input coupled to the output port of the mixer and a terminal configured to be connected to a shunt capacitor, and a difference circuit having a first input coupled to the output port of the mixer, and a second input coupled to an output of the lowpass filter. The output of the difference circuit substantially rejects a DC signal component at the output port of the mixer. | 2015-07-23 |
20150207533 | WEATHERPROOF BULKHEAD MOUNT - Disclosed is a weatherproof bulkhead mount that includes a weatherproof bulkhead housing having a portion sized to pass through a surface of a waterproof, sealed enclosure to an inside space of the enclosure and a portion sized to remain on the surface. The mount has a connector in the housing that provides electrical connection for an active component and is accessible from the outdoor environment, a circuit board in electrical connection with the connector for providing electrical communication between the connector and the inside space, and a removable cap to provide access to the connector when removed and to provide a weatherproof seal for the connector when not removed. Preferably, the “active” component socket is a SIM socket. Preferably, the cap has a push/pull grip, an elastic tether and a tether retaining ring. The tether retaining ring can also function as a weatherproof bulkhead gasket against the weatherproof bulkhead. | 2015-07-23 |
20150207534 | COMMUNICATION CHANNEL USING LOGARITHMIC DETECTOR AMPLIFIER (LDA) DEMODULATOR - A method is provided for communicating signals at a low power level in an electromagnetic interference (EMI) environment. A first device transmits a modulated signal having a first carrier frequency, including the encoded information via a hardwire transmission medium. In one aspect, the power level of the modulated signal can be adjusted to minimize power consumption or reduce the generation of EMI. The modulated signal may be in one of the following formats: frequency modulation (FM) or phase modulation (PM) to name a few examples. A second device including a logarithmic detector amplifier (LDA) demodulator circuit receives the signal, which may be mixed with EMI. The LDA demodulator circuit amplifies the modulated signal, without amplifying the EMI, to supply a demodulated baseband signal, which may be an n-ary digital signal, or an audio signal. A low-power, noise insensitive communication channel is also provided. | 2015-07-23 |
20150207535 | MAGNETIC BUTTON PHONE CASE - The various embodiments of the present invention disclose a mobile phone holder with magnetic adherence enhancement comprises a ruggedized case, a primary magnetic strip and a mating magnetic strip. The ruggedized case comprises an adjustable chamber on an internal surface. The primary magnetic strip is adhered to a back surface of the mobile phone holder using an adhesive. The mating magnetic strip comprises a rear surface applied with an adhesive. The mating magnetic strip is fixed to a non-metallic surface. The primary magnetic strip is magnetically locked to the mating magnetic strip. | 2015-07-23 |
20150207536 | SWITCHABLE ANTENNA ARRAY - An apparatus includes an impedance circuit and a plurality of inductors coupled to the impedance circuit. Each of the plurality of inductors is coupled in parallel to a corresponding switch of a plurality of switches. | 2015-07-23 |
20150207537 | Same-Aperture Any-Frequency Simultaneous Transit And Receive Communication System - A same-aperture any-frequency simultaneously transmit and receive (STAR) system includes a signal connector having a first port electrically coupled to an antenna, a second port electrically coupled to a transmit signal path, and a third port electrically coupled to receive signal path. The signal connector passes a transmit signal in the transmit signal path to the antenna and a receive signal in the receive signal path. A signal isolator is positioned in the transmit signal path to remove a residual portion of the receive signal from transmit signal path. An output of the signal isolator provides a portion of the transmit signal with the residual portion of the receive signal removed. A signal differencing device having a first input electrically coupled to the output of the signal isolator and a second input electrically coupled to the third port of the signal connector subtracts a portion of the transmit signal in the receive signal path thereby providing a more accurate receive signal. | 2015-07-23 |
20150207538 | AUTOMATIC CONFIGURATION OF A DEVICE FOR COMMUNICATION - A method for configuring a device to receive an electrical input signal includes: generating the electrical input signal in compliance with a predetermined communication technology; performing a measurement of the electrical input signal; selecting, based on a result of the measurement, the predetermined communication technology for receiving the electrical input signal at the device from a plurality of available communication technologies supported by the device; and actuating the device to receive the electrical input signal according to the predetermined communication technology. | 2015-07-23 |
20150207539 | System and Method for Multi-Dimensional Modulation Schemes with High Noise Immunity and Low Emission Idle Signaling for Automotive Area Networks - System, method and apparatus for multi-dimensional modulation schemes with high noise immunity and low emission idle (LEI) signaling for automotive area networks. An extra zero constellation point can be used during an idle mode and extra constellation points can be assigned to control signals. | 2015-07-23 |
20150207540 | SYSTEMS AND METHODS FOR IMPLEMENTING APPLICATION PROFILES AND DEVICE CLASSES IN POWER LINE COMMUNICATION (PLC) ENVIRONMENTS - Systems and methods for application profiles and device classes in power line communications (PLCs) are described. In some embodiments, a PLC device has the device class defined by a PHY layer and may include a processor and a memory coupled to the processor. The memory may be configured to store program instructions, which may be executable by the processor to cause the PLC device to communicate with a higher-level PLC apparatus over a power line using a frequency band. The frequency band may be selected based upon an application profile and/or a device class associated with the PLC device. In some implementations, the higher-level PLC apparatus may include a PLC gateway or a data concentrator, and the PLC device may include a PLC modem or the like. Examples of application profiles include access communications, in-premises connectivity, AC charging, and/or DC charging. Device classes may represent a minimum communication data rate and/or an operating frequency band restriction of the PLC device. | 2015-07-23 |
20150207541 | DIRECTIONAL COUPLING COMMUNICATION APPARATUS - The invention relates to a directional coupling communication apparatus where the coupling impedance can be easily matched to reduce reflections, and thus, the speed of communication channels is increased as compared to that with inductive coupling, and at the same time, the reliability of communication is improved by increasing the signal intensity. Modules having a coupler where an input/output connection line is connected to a first end, and either a ground line or an input/output connection line to which an inverse signal of a signal to be inputted into the input/output connection line connected to the above-described first end is inputted is connected are layered on top of each other so that the couplers are couplers to each other using capacitive coupling and inductive coupling. | 2015-07-23 |
20150207542 | SYSTEMS AND METHODS FOR WIRELESS POWER AND COMMUNICATION - The present invention relates to systems and methods for a charger which interacts with devices equipped with receivers. The charger may likewise have access to a server via a network connection. The charger receives a beacon signal from the receiver, and transmits power, and a control signal, to the device. Applications enable proper communication between the charger and the receiver. The receiver interprets and effectuates the commands. The receiver also includes sensors which generate data regarding the device status and usage. This data is provided to the server, via the charger. The server maintains a database of all user data collected from the devices, as well as user configurations. The user and third parties may access this data. | 2015-07-23 |
20150207543 | WIRELESS POWER TRANSFER APPARATUS AND METHOD THEREOF - In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of a receiving antenna configured to wirelessly receive power transmitted by a transmitting device and arranged to associate or dissociate with the transmitting device. | 2015-07-23 |
20150207544 | NEAR FIELD COMMUNICATION DEVICE - A near field communication device is disclosed herein. An example of such a device includes a user interface and an application that displays information on the user interface. The device also includes a non-transitory storage medium including a list of data elements that may appear within the information displayed in the user interface and a near field communication filter module to automatically extract any of the data elements from the information displayed on the user interface via the application. The example additionally includes a near field communication write module to automatically record any of the extracted data elements transferred by the near field communication filter module to a near field communication data tag. Examples of a method for use in a near field communication device and a non-transitory storage medium are also disclosed herein. | 2015-07-23 |
20150207545 | DIGITAL TRANSPORT OF DATA OVER DISTRIBUTED ANTENNA NETWORK - A system for transporting data in a Distributed Antenna System (DAS) includes at least one Digital Access Unit (DAU) and a plurality of Digital Remote Units (DRUs) coupled to the at least one DAU. The plurality of DRUs are operable to transport signals between the plurality of DRUs and the at least one DAU. The at least one DAU includes: a data transport coder comprising: a framer, an encoder, a scrambler, and a serializer and a data transport decoder comprising: a deserializer, a decoder, a descrambler, a frame synchronizer, and a deframer. | 2015-07-23 |
20150207546 | Beamforming Signaling in a Wireless Network - A wireless receives at least one channel state input information element (IE) from a first base station. The wireless device computes a precoding matrix indicator (PMI) employing, at least in part, the at least one channel state input IE and measurement of signals received from a second base station. The wireless device transmits the PMI to the first base station. | 2015-07-23 |
20150207547 | METHOD AND APPARATUS FOR TRANSMITTING CODEBOOK-BASED SIGNAL IN WIRELESS COMMUNICATION SYSTEM - The present invention relates to a wireless communication system, and more specifically, disclosed are a method and an apparatus for transmitting a codebook-based signal. A method for transmitting channel state information from a terminal in the wireless communication system, according to one embodiment of the present invention, comprises the steps of: measuring a downlink channel from a downlink signal that is received from a base station; determining a first precoding matrix indicator (PMI) and a second PMI of the downlink channel based on the measurement of the downlink channel; and transmitting the first PMI and the second PMI to the base station, wherein the first PMI indicates a first precoding vector that includes a first elevation angle component of a multi-antenna of the base station, the second PMI indicates a second precoding vector that includes a second elevation angle component and an azimuth angle component of the multi-antenna of the base station, and wherein resolution of the azimuth angle component can be determined based on the first elevation angle component or the second elevation angle component. | 2015-07-23 |
20150207548 | METHOD AND APPARATUS FOR MANAGING GROUP COMMUNICATIONS - A method and apparatus for managing group communications are disclosed. A wireless transmit/receive unit (WTRU) may receive the same data using multiple-input multiple output (MIMO) transmission from each of a plurality of synchronized network nodes. The synchronized network nodes may transmit the same data in a synchronized manner. The WTRU may transmit feedback information, including negative acknowledgements (NACKs) and channel quality indicators, to a single one of the plurality of synchronized network nodes. In addition, the feedback information may not be transmitted to the other synchronized network nodes. In response to the transmitted channel quality indicators, the WTRU may receive the same data again from the synchronized network nodes. The synchronized network nodes may transmit the same data again in a synchronized manner. Further, the same data may be received by a plurality of WTRUs. Also, the WTRU may be in a group of a plurality of groups of WTRUs. | 2015-07-23 |
20150207549 | BASE STATION APPARATUS, USER TERMINAL, COMMUNICATION SYSTEM AND COMMUNICATION CONTROL METHOD - A base station apparatus, a user terminal, a communication system and a communication control method that can support the diversification of communication is disclosed. In a base station apparatus, downlink measurement object signals are pre-coded in a precoding multiplication section using precoding weights for downlink measurement object signals, and transmitted to a user terminal, and, in the user terminal, the downlink measurement object signals are demodulated using the precoding weights, and measurement processes are performed based on the demodulated downlink measurement object signals. | 2015-07-23 |
20150207550 | METHOD AND APPARATUS FOR TRANSMITTING SIGNAL IN WIRELESS COMMUNICATION SYSTEM - A method and apparatus for transmitting a signal in a wireless communication system are provided. The method includes: generating R spatial stream each of which is generated on the basis of an information stream and reference signal; generating N transmit streams on the basis of the R spatial streams and a precoding matrix (where R2015-07-23 | |
20150207551 | SPATIAL MODULATION METHOD USING POLARIZATION AND APPARATUS USING THE SAME - A spatial modulation method using a polarization and an apparatus using the same are provided. A spatial modulation method by a transmitting apparatus in a wireless communication system may comprise selecting an antenna to send data among transmit antennas arranged to have different polarization angles using a predetermined bit of input data based on indexes of the transmit antenna and mapping remaining bits of the input data to a preset constellation and transmitting the remaining bits of the mapped input data through the selected antenna. | 2015-07-23 |
20150207552 | Precoding Codebook Bitmaps in Telecommunications - A base station node ( | 2015-07-23 |
20150207553 | RADIO AND ANTENNA SELECTION METHOD FOR RADIO - A radio that calculates an SINR on a basis of received preamble information received by an antenna and corresponding preamble information stored in advance corresponding to the received preamble information, the radio including: an integration unit that calculates a phase signal for each symbol with respect to the received preamble information; a power value calculation unit that calculates a power value on a basis of the phase signal; a correlation calculation unit that calculates a desired signal power from a correlation value between the phase signal and the corresponding preamble information; and an SINR calculation unit that calculates an SINR value from the power value and the desired signal power. | 2015-07-23 |
20150207554 | MULTIPLE ANTENNA PROCESSING ON TRANSMIT FOR WIRELESS LOCAL AREA NETWORKS - A method and an apparatus in a first wireless station of a network transmitting to a second wireless station. The network uses multi-tone OFDM signals. The first station includes multiple antennas and a receive and a transmit signal path per antenna. Each receive signal path includes a discrete Fourier transformer determining the tones in a received signal, and each transmit signal path includes an inverse discrete Fourier transformer converting tones to a signal. The method includes determining channel estimates for each tone and each receive path while receiving from the second station, determining transmit weights to transmit to the second station, tone-by-tone weighting a signal for transmission to the second station to produce weighted tone sets for each transmit signal path, and transmitting the weighted tone sets. The first station is configured so that the weighting produces additive beamforming without the second station needing multiple antennas. | 2015-07-23 |
20150207555 | METHOD AND DEVICE FOR FEEDING BACK CHANNEL INFORMATION IN WIRELESS COMMUNICATION SYSTEM SUPPORTING MULTI-INPUT MULTI-OUTPUT SCHEME - The present invention relates to a wireless communication system and, more particularly, to a method and device for compressing and feeding back channel information in a wireless communication system supporting a multi-input multi-output (MIMO) scheme. A method for feeding back channel information by a terminal in a wireless communication system supporting a MINO scheme, according to one embodiment of the present invention, can comprise the steps of: calculating a channel matrix on the basis of a reference signal received from a base station; calculating a first valid channel vector by using a reception weight vector and the channel matrix; and calculating a second valid channel vector by setting a coefficient corresponding to each basis vector included in a basis matrix as 0 if the coefficient is equal to or less than a threshold when the first valid channel vector is factored by the basis matrix. | 2015-07-23 |
20150207556 | Implementing Codebook Subset Restrictions in Wireless Communication Systems - In MU-MIMO scenarios, a transmitting node ( | 2015-07-23 |
20150207557 | SIGNAL REPRODUCTION APPARATUS AND SIGNAL REPRODUCTION METHOD - A signal reproduction apparatus reproduces, from an input signal containing a weak signal which is a piece of transmission information and noise superimposed thereon, the weak signal through use of a stochastic resonance phenomenon. The apparatus includes N nonlinear elements NL | 2015-07-23 |