30th week of 2015 patent applcation highlights part 55 |
Patent application number | Title | Published |
20150206958 | TUNNEL FIELD-EFFECT TRANSISTOR - A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided. | 2015-07-23 |
20150206959 | FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION - Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance C | 2015-07-23 |
20150206960 | SEMICONDUCTOR DEVICE - A semiconductor device | 2015-07-23 |
20150206961 | FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES - At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET. | 2015-07-23 |
20150206962 | SEMICONDUCTOR DEVICE, TRANSISTOR HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. | 2015-07-23 |
20150206963 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure includes a semiconductor layer having a first surface, and an interlayer dielectric (ILD) defining a metal gate over the first surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a barrier layer, and a work function metal layer. A thickness of a first portion of the barrier layer at the sidewall of the metal gate is substantially thinner than a thickness of the barrier layer at the bottom of the metal gate. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate trench in an ILD, forming a barrier layer in a bottom and a sidewall of the metal gate trench, removing a first portion of the barrier layer at the sidewall of the metal gate trench, and forming a work function metal layer conforming to the barrier layer. | 2015-07-23 |
20150206964 | SEMICONDUCTOR DEVICE STRUCTURE WITH METAL RING ON SILICON-ON-INSULATOR (SOI) SUBSTRATE - In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring. | 2015-07-23 |
20150206965 | HIGH PERFORMANCE FINFET - A FinFET is described having first, second, and third pluralities of fins with gate structures and source and drain regions formed on the fins so that PMOS transistors are formed on the first plurality of fins, NMOS transistors are formed on the second plurality and PMOS transistors are formed on the third plurality. In one embodiment, the first and second pluralities of fins are made of strained silicon; and the third plurality of fins is made of a material such as germanium or silicon germanium that has a higher hole mobility than strained silicon. In a second embodiment, the first plurality of fins is made of silicon, the second plurality of strained silicon, germanium or a III-V compound; and the third plurality is made of germanium or silicon germanium. | 2015-07-23 |
20150206966 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region. | 2015-07-23 |
20150206967 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon carbide semiconductor substrate, a silicon carbide layer, a switching element section, and an overvoltage detection element section whose area is smaller than that of the switching element section. The switching element section includes a first electrode pad, a first terminal section surrounding the first electrode pad and provided in the silicon carbide layer, and a first insulating film covering the first terminal section. The overvoltage detection element section includes a second electrode pad, a second terminal section surrounding the second electrode pad and provided in the silicon carbide layer, and a second insulating film covering the second terminal section and being in contact with the silicon carbide layer. A breakdown field strength of at least part of a portion of the second insulating film being in contact with the silicon carbide layer is lower than that of the first insulating film. | 2015-07-23 |
20150206968 | POWER LDMOS SEMICONDUCTOR DEVICE WITH REDUCED ON-RESISTANCE AND MANUFACTURING METHOD THEREOF - An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region. | 2015-07-23 |
20150206969 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device. | 2015-07-23 |
20150206970 | Body-Tied, Strained-Channel Multi-Gate Device and Methods of Manufacturing Same - A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials. | 2015-07-23 |
20150206971 | Hybrid Fin Field-Effect Transistor Structures and Related Methods - Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. | 2015-07-23 |
20150206972 | METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER - A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region. | 2015-07-23 |
20150206973 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - [Problem] To suppress damage to a semiconductor beam or a semiconductor substrate resulting from dry etching of gate electrode material during manufacture. | 2015-07-23 |
20150206974 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region. | 2015-07-23 |
20150206975 | FIN-Type Semiconductor Device and Manufacturing Method - One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, the source contact extending along a vertical direction along the source region, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region | 2015-07-23 |
20150206976 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor includes a gate electrode disposed on a substrate, a gate insulating layer disposed on the gate electrode and the substrate, an oxide semiconductor pattern disposed on the gate insulating layer, wherein a part of the oxide semiconductor overlaps the gate electrode, a source electrode disposed on a part of the oxide semiconductor pattern, and a drain electrode disposed on a part of the oxide semiconductor pattern spaced apart from the source electrode, wherein a thickness of the gate insulating layer in a channel region, the channel region overlapping the gate electrode, is thinner than a thickness of the gate insulating layer in a remaining region, the remaining region other than the channel region. | 2015-07-23 |
20150206977 | METAL OXIDE TRANSISTOR - Provided is a transistor element in which the state thereof is changed into that of a resistor with a small power consumption without migration and melting of the resistor due to a large current, and physical changes, such as breakdown of an insulating film due to high electric field application, and the state change can be used as a memory element. This metal oxide transistor is provided with: a semiconductor thin film formed of a metal oxide semiconductor; a source electrode and a drain electrode, which are in contact with the semiconductor thin film; and a gate electrode, which faces the semiconductor thin film with a gate insulating film therebetween. In the initial state, the metal oxide transistor exhibits first characteristics in which the metal oxide transistor operates as a transistor element having a drain current changed depending on the gate voltage and the drain voltage, and when a drain current at or above a prescribed current density is made to flow for a prescribed time, the characteristics transition to second characteristics in which the drain current depends less on the gate voltage compared with the first characteristics, the drain current depends mainly on the drain voltage, and ohmic resistive characteristics are exhibited irrespective of the gate voltage. | 2015-07-23 |
20150206978 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less. | 2015-07-23 |
20150206979 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This semiconductor device ( | 2015-07-23 |
20150206980 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR SUBSTRATE - An embodiment of the invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a photo-sensitive protective layer which is above the gate electrode and has a first recess and a second recess; etching the active material layer by using the photo-sensitive protective layer as a mask to form an active layer; removing a portion of the photo-sensitive protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion. | 2015-07-23 |
20150206981 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a first region which, in an oxide semiconductor layer, has a higher carrier concentration than a channel region immediately below a gate electrode formed over the oxide semiconductor layer and is formed at least in a partial region other than the channel region, and a second region which, in the oxide semiconductor layer, has a higher carrier concentration than the first region and is formed farther from the channel region than the first region. The first region is formed through a first reduction reaction by stacking a first reduction reaction film over the oxide semiconductor layer and reducing the oxide semiconductor layer by the first reduction reaction film. The second region is formed through a second reduction reaction by stacking a second reduction reaction film over the oxide semiconductor layer and reducing the oxide semiconductor layer by the second reduction reaction film. | 2015-07-23 |
20150206982 | THIN FILM TRANSISTOR FOR A DISPLAY DEVICE, DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE - A thin film transistor for a display device is disclosed. In one aspect, the thin film transistor includes a gate electrode formed over a substrate and including a first conductive pattern and a plurality of second conductive patterns. The thin film transistor also includes a semiconductor layer formed over the gate electrode, wherein the semiconductor layer is formed of a crystallized semiconductor material, a source electrode electrically connected to the semiconductor layer, and a drain electrode electrically connected to the semiconductor layer. The drain electrode is spaced apart from the source electrode in a first direction and the second conductive patterns at least partially overlap the first conductive pattern and are spaced apart from each other in the first direction. | 2015-07-23 |
20150206983 | Semiconductor Diode and Method of Manufacturing a Semiconductor Diode - A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other. | 2015-07-23 |
20150206984 | TRENCH FIELD EFFECT DIODES AND METHODS OF MANUFACTURING THOSE DIODES - Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly and an anode assembly having an anode electrode, a gate electrode layer under the anode electrode, a gate oxide layer under the gate electrode layer, at least one P− body region under the gate oxide layer, and at least one trench that extends through the gate electrode layer, the gate oxide layer, and the at least one P− body region to the cathode assembly. The at least one trench may include a lower portion having (1) a bottom and a plurality of sidewalls defining a bottom volume and having an insulating layer and (2) a conductive material that is disposed within the bottom volume and that is in electrical communication with the anode electrode. The anode electrode may contact extend through the at least one trench to the conductive material. | 2015-07-23 |
20150206985 | SEMICONDUCTOR DIODE ASSEMBLY - TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions. | 2015-07-23 |
20150206986 | LEAD-BISMUTH-TELLURIUM-SILICATE INORGANIC REACTION SYSTEM HAVING IMPROVED ADHESION PROPERTIES - An inorganic reaction system comprising a lead-bismuth-tellurium-silicate composition of Formula (I): Pb | 2015-07-23 |
20150206987 | SOLAR CELL MODULE, SOLAR CELL MODULE ASSEMBLY, AND SOLAR PHOTOVOLTAIC POWER GENERATION SYSTEM - A solar cell module, a solar cell module assembly, and a solar photovoltaic power generation system capable of reducing power loss are provided. A light-concentrating panel configured to collect light which is incident from the outside and a plurality of solar cell elements installed on the light-concentrating panel and configured to receive light which is collected by the light-concentrating panel are provided. Each of the plurality of solar cell elements is provided with a positive terminal and a negative terminal. The plurality of solar cell elements include a first solar cell element and a second solar cell element which are connected to each other in series via connection wiring and a third solar cell element which is not connected to the first solar cell element and the second solar cell element in series. The first solar cell element and the second solar cell element configure a first current path, and the third solar cell element configures a second current path. | 2015-07-23 |
20150206988 | DOPANT INK COMPOSITION AND METHOD OF FABRICATING A SOLAR CELL THERE FROM - Dopant ink compositions and methods of fabricating solar cells there from are described. A dopant ink composition may include a cross-linkable matrix precursor, a bound dopant species, and a solvent. A method of fabricating a solar cell may include delivering a dopant ink composition to a region above a substrate. The dopant ink composition includes a cross-linkable matrix precursor, a bound dopant species, and a solvent. The method also includes baking the dopant ink composition to remove a substantial portion of the solvent of the dopant ink composition, curing the baked dopant ink composition to cross-link a substantial portion of the cross-linkable matrix precursor of the dopant ink composition, and driving dopants from the cured dopant ink composition toward the substrate. | 2015-07-23 |
20150206989 | SEMICONDUCTOR COMPONENT WITH A PASSIVATION LAYER MADE OF HYDRATED ALUMINIUM NITRIDE AND ALSO METHOD FOR SURFACE PASSIVATION OF SEMICONDUCTOR COMPONENTS - The invention relates to a semiconductor component with base emitter and electrical contacts and also at least one passivation layer which consists of hydrated aluminium nitride or essentially comprises this. The invention relates likewise to a corresponding method for surface passivation of semiconductor components. | 2015-07-23 |
20150206990 | SOLAR CELL PRODUCTION METHOD, AND SOLAR CELL PRODUCED BY SAME PRODUCTION METHOD - This solar cell production method involves productively forming an antireflection film comprising silicon nitride, said antireflection film having an excellent passivation effect. In an embodiment, a remote plasma CVD is used to form a first silicon nitride film on a semiconductor substrate ( | 2015-07-23 |
20150206991 | PHOTOVOLTAIC DEVICES WITH THREE DIMENSIONAL SURFACE FEATURES AND METHODS OF MAKING THE SAME - This disclosure provides photovoltaic cells and substrates with three dimensional optical architectures and methods of manufacturing the same. In particular, the disclosure relates to a continuously formed photovoltaic substrate, and to systems, devices, methods and uses for such a product, including the collection of solar energy. | 2015-07-23 |
20150206992 | LEAD-TELLURIUM INORGANIC REACTION SYSTEMS - An inorganic reaction system comprising a lead-tellurium-zinc composition of Formula (I): Pb | 2015-07-23 |
20150206993 | LEAD-BISMUTH-TELLURIUM INORGANIC REACTION SYSTEM FOR ELECTROCONDUCTIVE PASTE COMPOSITION - An inorganic reaction system comprising a lead-bismuth-tellurium composition of Formula (I): Pb | 2015-07-23 |
20150206994 | SOLAR CELL FRONT CONTACT WITH THICKNESS GRADIENT - A solar cell has a back contact layer over a substrate. The substrate has a scribe line extending through it. An absorber layer is over the back contact layer. A front contact layer is over the absorber layer. The front contact layer has a first end and a second end opposite the first end. The scribe line is closer to the second end than to the first end. The front contact layer has a thickness above the first end that is greater than the thickness of the front contact layer at the scribe line. | 2015-07-23 |
20150206995 | SOLAR CELL, SOLAR CELL MODULE AND SOLAR CELL SYSTEM - A first electrode disposed on a first surface of the solar cell. A second electrode disposed on a second surface of the solar cell. A connection member electrically couples the first electrode with an electrode of a solar cell connectable to the solar cell. The first electrode includes multiple fine line-shaped electrodes and a first connection electrode configured to connect electrically with the multiple fine line-shaped electrodes. A width of the first connection electrode is smaller than that of the connection member, and the second electrode comprises an electricity collecting electrode and a second connection electrode configured to connect electrically with the electricity collecting electrode. A width of the second connection electrode is the same as or larger than a region width of the first connection electrode. | 2015-07-23 |
20150206996 | SOLAR CELL SUBSTRATE MADE OF STAINLESS STEEL FOIL AND METHOD FOR MANUFACTURING THE SAME - Provided are a solar cell substrate made of stainless steel foil which contains 7% to 40% by mass Cr and has a coefficient of linear expansion of 12.0×10 | 2015-07-23 |
20150206997 | MULTI-JUNCTION SOLAR CELLS WITH RECESSED THROUGH-SUBSTRATE VIAS - Multi junction solar cells and methods for making multi junction solar cells are disclosed. Back-contact-only multi junction solar cells having recessed through-substrate vias wherein the side facing the sun, is capable of withstanding environments for use in space are disclosed. | 2015-07-23 |
20150206998 | PASSIVATED CONTACTS FOR BACK CONTACT BACK JUNCTION SOLAR CELLS - Passivated contact structures and fabrication methods for back contact back junction solar cells are provided. According to one example embodiment, a back contact back junction photovoltaic solar cell is described that has a semiconductor light absorbing layer having a front side and a backside having base regions and emitter regions. A passivating dielectric insulating layer is on the base and emitter regions. A first electrically conductive contact contacts the passivating dielectric insulating layer together having a work function suitable for selective collection of electrons that closely matches a conduction band of the light absorbing layer. A second electrically conductive contact contacts the passivating dielectric insulating layer together having a work function suitable for selective collection of electrons that closely matches a valence band of the light absorbing layer. | 2015-07-23 |
20150206999 | ELECTROLYTE LAYER HAVING A PATCHWORK-TYPE NANOPOROUS GRAIN BOUNDARY AND A METHOD OF PREPARATION THEREOF - Gadolinium-doped cerium oxide slurries used to form a patchwork type surface structure with nanoporous grain boundary prepared by mixing gadolinium-doped cerium oxide and a polymer binder to form a first mixture; wet-atomizing the first mixture under a pressure of at least 100 MPa to obtain a second mixture; coating the second mixture to a substrate to form a coated substrate; and sintering the coated substrate. The patchwork type structure is a polygonal or honeycomb structure having a size of from 0.1 μm to 3 μm. | 2015-07-23 |
20150207000 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - The inventive concepts provide a solar cell and a method of fabricating the same. The method includes preparing a substrate in a chamber, forming a light absorbing layer on the substrate by setting temperature in the chamber to a first temperature and by supplying a first source into the chamber, forming a buffer layer on the substrate by setting temperature in the chamber to a second temperature lower than the first temperature and by supplying the first source into the chamber, and forming a window layer on the substrate by supplying a second source different from the first source into the chamber. | 2015-07-23 |
20150207001 | COLORED GLASS AND SOLAR CELL ASSEMBLY USING THE SAME - The subject invention is related to a colored glass and a solar cell assembly comprising the same. The subject invention provides a colored glass comprising a glass substrate; and a colored coating formed on the glass substrate, wherein the colored coating comprises an inorganic film-forming material, a pigment and an adhesive. The subject invention also provides a solar cell assembly comprising: a front glass substrate; the aforementioned colored glass; and a photovoltaic cell sealed between the front glass substrate and the colored glass. The colored glass of the subject invention has a good thermal conductivity, improved waterproof performance, mechanical properties and weather resistance such that the colored glass is not only aesthetically pleasing but also useful as a backside protection material of a solar cell assembly for long-term outdoor use. | 2015-07-23 |
20150207002 | MONOLITHIC SOLAR CELL ARRAYS AND FABRICATION METHODS - Solar cell array solutions including monolithic solar cell arrays and fabrication methods. A first patterned cell metallization contacts base and emitter regions of each of a plurality of solar cells having a light receiving frontside and a backside. An electrically insulating continuous backplane layer is attached to the backside of the solar cells and covers the first cell metallization of each of the solar cells. Via holes through the continuous backplane layer provide access to the first cell metallization. A second cell metallization is connected to the first cell metallization of each of the solar cells and electrically interconnects the solar cells in the array. | 2015-07-23 |
20150207003 | SOLAR CELL MODULE - A solar cell module is discussed, which includes a plurality of strings each including a plurality of solar cells, which are connected in series to one another through an interconnector, a front transparent substrate disposed on front surfaces of the plurality of strings, a first encapsulant disposed between the front transparent substrate and the front surfaces of the plurality of strings, a first reflector disposed in a first space between the plurality of solar cells included in each string, which are separated from one another in a first direction corresponding to a longitudinal direction of each string, and a second reflector disposed in a second space between the plurality of strings, which are separated from one another in a second direction crossing the first direction. The first and second reflectors reflect incident light. | 2015-07-23 |
20150207004 | Trough Shaped Fresnel Reflector Solar Concentrators - The Present invention is a trough shaped solar concentrator with Fresnel strip reflectors disposed in a generally linear V shaped configuration. The present invention shows two unique geometrical supporting structures for the strip Fresnel reflectors. The concentrator is shown in several preferred embodiments as a concentrating solar energy collector with different types of solar energy receiving elements disposed at the focal area of the concentrator. | 2015-07-23 |
20150207005 | PORTABLE SOLAR PANEL SYSTEM AND METHOD - A portable solar panel system and method includes a support structure, one or more solar panels mounted on the support structure, at least three wheels coupled to the support structure and rotatably supporting the support structure on a surface, a controller, a sunlight monitor coupled to the controller and a tracking drive system coupled to the controller and mechanically linked to at least one of the at least three wheels. | 2015-07-23 |
20150207006 | SYSTEM AND METHOD FOR TRAPPING LIGHT IN A SOLAR CELL - This application relates to systems and methods for improving solar cell efficiently by enabling more light to be captured by the absorber layer. The reflector layer in a solar cell may be designed to reflect light back into the absorber layer that has already passed through the absorber layer. The reflector layer may include a surface protrusion that has a surface that has an angle of approximately 45 degrees. Incident light is reflected from that surface towards the absorber layer or towards the reflector layer which, in turn, reflects the light back towards the absorber layer or the silicon stack. The light may be reflected at an angle that enables the light to have total internal reflection within the silicon layer (e.g., absorber layer, μc-Si layer, and a-Si layer). | 2015-07-23 |
20150207007 | Compound Linear V Fresnel-Parabolic Trough Solar Concentrator - The present invention is a trough shaped solar concentrator and collector having its focal area and receiver located inside the trough structure below the trough aperture and having a unique dual section trough reflector with a combination of different underlying reflector geometries. | 2015-07-23 |
20150207008 | MULTILAYER STRUCTURE FOR THERMOPHOTOVOLTAIC DEVICES AND THERMOPHOTOVOLTAIC DEVICES COMPRISING SUCH - A multilayer structure ( | 2015-07-23 |
20150207009 | PHOTOVOLTAIC SYSTEM WITH STACKED SPECTRUM SPLITTING OPTICS AND PHOTOVOLTAIC ARRAY TUNED TO THE RESULTING SPECTRAL SLICES PRODUCED BY THE SPECTRUM SPLITTING OPTICS - The present invention provides photovoltaic devices that comprise multiple bandgap cell arrays in combination with spectrum splitting optics. The spectrum splitting optics include one or more optical spectrum splitting modules that include two or more optical splitting, diffractive elements that are optically in series to successively and diffractively split incident light into segments or slices that are independently directed onto different photovoltaic cell(s) of the array having appropriate bandgap characteristics. | 2015-07-23 |
20150207010 | THREE DIMENSIONAL COMPOSITIONAL PROFILE IN CIS-BASED ABSORBER LAYERS OF THIN FILM SOLAR CELLS - Provided is a structure and method for forming CIS-based absorber layers for thin-film solar cells that include three-dimensional compositional profiles. The disclosure provides a patterned absorber layer with two or more different regions, each of the regions having a different concentration profile of one or more components. In some embodiments, the different regions have different respective GGI profiles. GGI represents an atomic ratio of Ga/(Ga+In) in CIS-based absorber materials and in some embodiments the two or more different regions have GGI gradients from top to bottom of the CIS-based absorber layer. The method includes using two evaporation sources in a co-evaporation system to produce the two or more different regions adjacent one another on a substrate. | 2015-07-23 |
20150207011 | MULTI-JUNCTION PHOTOVOLTAIC CELLS AND METHODS FOR FORMING THE SAME - The present disclosure provides thin film solar cell structures that can achieve dramatically improved power conversion efficiencies in relation to other thin film solar cell structures. The application of tandem solar cells composed of poly-crystalline Group II-VI (e.g., CdTe-based alloy) solar cells under low temperature deposition can achieve practical efficiencies above 25% in a low cost, high through-put, large area production environment. A poly-crystalline Group II-VI (e.g., CdTe-based alloy) solar cell can be deposited in tandem with a crystalline or multi-crystalline silicon p-type substrate with embedded n-type emitter on the deposition side of the substrate. This low temperature poly-crystalline/crystalline approach can allow for the development of a substantially efficient tandem solar cell produced in a relatively low cost, high through-put, large area production environment. | 2015-07-23 |
20150207012 | PRINTING-BASED ASSEMBLY OF MULTI-JUNCTION, MULTI-TERMINAL PHOTOVOLTAIC DEVICES AND RELATED METHODS - Multi-junction photovoltaic devices and methods for making multi-junction photovoltaic devices are disclosed. The multi-junction photovoltaic devices comprise a first photovoltaic p-n junction structure having a first interface surface, a second photovoltaic p-n junction structure having a second interface surface, and an optional interface layer provided between the first interface surface and the second interface surface, where the photovoltaic p-n junction structures and optional layers are provided in a stacked multilayer geometry. In an embodiment, the optional interface layer comprises a chalcogenide dielectric layer. | 2015-07-23 |
20150207013 | INVERTED METAMORPHIC MULTIJUNCTION SOLAR CELLS HAVING A PERMANENT SUPPORTING SUBSTRATE - The present disclosure provides a method of manufacturing a solar cell that includes providing a semiconductor growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a metal contact layer over said sequence of layers; affixing the adhesive polyimide surface of a permanent supporting substrate directly over said metal contact layer and permanently bonding it thereto by a thermocompressive technique; and removing the semiconductor growth substrate. | 2015-07-23 |
20150207014 | SENSOR, DISPLAY DEVICE, MOBILE TELEPHONE, AND DIGITAL CAMERA - In order to provide a single-unit sensor which serves as both an illuminance sensor and a proximity sensor, the sensor ( | 2015-07-23 |
20150207015 | Apparatus and method for optically initiating collapse of a reverse biased P-type-N-type junction - An optical method of collapsing the electric field of an innovatively fabricated, reverse-biased PN junction causes a semiconductor switch to transition from a current blocking mode to a current conduction mode in a planar electron avalanche. This switch structure and the method of optically initiating the switch closure is applicable to conventional semiconductor switch configurations that employ a reverse-biased PN junction, including, but not limited to, thyristors, bipolar transistors, and insulated gate bipolar transistors. | 2015-07-23 |
20150207016 | METHODS FOR MAKING WAFER LEVEL OPTOELECTRONIC DEVICE PACKAGES - Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint. | 2015-07-23 |
20150207017 | INTEGRATED MICRO-INVERTER AND THIN FILM SOLAR MODULE AND MANUFACTURING PROCESS - Embodiments of the present invention include a method for manufacturing, and a structure for a thin film solar module. The method of manufacturing includes fabricating a thin film solar cell and fabricating an electronic conversion unit (ECU) on a single substrate. The thin film solar cell has at least one solar cell diode on a substrate. The ECU has at least one transistor on the substrate. The ECU may further comprise a capacitor and an inductor. The ECU is integrated on the substrate monolithically and electrically connected with the thin film solar cell. The ECU and the thin film solar cell interconnect to form a circuit on the substrate. The ECU is electrically connected to a microcontroller on the solar cell module. | 2015-07-23 |
20150207018 | Apparatus and Method for Manufacturing of Thin Film Type Solar Cell - Disclosed is an apparatus and method for manufacturing a thin film type solar cell, which enables the enhancement of productivity, the apparatus for manufacturing a thin film type solar cell including a first electrode forming unit; a first separation part; an optoelectric conversion layer forming unit; a contact line forming unit; a printing unit; and an etching process unit, wherein the etching process unit removes the optoelectric conversion layer in a second separation part to expose the first electrode in the second separation part through a wet etching process. | 2015-07-23 |
20150207019 | Method for Fabricating Crystalline Silicon Solar Cell Having Passivation Layer and Local Rear Contacts - The present invention is a method for fabricating a crystalline silicon solar cell having a passivation layer and a plurality of local rear contacts, which comprises steps of forming a passivation layer on the rear surface of the silicon substrate; coating distributed metal electrodes on the rear surface and forming a plurality of local rear contacts through firing and forming a metallic reflector at the rear surface so that the metallic reflector electrically contacts with the plurality of local rear contacts. | 2015-07-23 |
20150207020 | BACK SURFACE FIELD FORMATION IN SILICON MICROSPHERES IN A PHOTOVOLTAIC PANEL - A PV panel is manufactured using a monolayer of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The spheres are embedded in an uncured aluminum-containing layer on an aluminum foil substrate in a roll-to-roll process, and the aluminum-containing layer is heated to anneal the aluminum-containing layer as well as p-dope the bottom surface of the spheres. The diffusion of the p-type dopants also creates a back surface field in the spheres to improve efficiency. A dielectric layer is formed, and a phosphorus-containing layer is deposited over the spheres to dope the top surface n-type, forming a pn junction. The phosphorus layer is then removed. A conductor is deposited to contact the top surface. Conformal, index-graded lenses are then formed over each of the spheres to form a thin and flexible PV panel. | 2015-07-23 |
20150207021 | Method for Coating a Solar Panel - The present invention relates to a method for coating a solar panel to reduce the amount of light being received by the solar panel's photovoltaic cells and reduce their electrical output. The method comprises the step of coating the light-receiving area of said solar panel with a sufficient thickness of a coating composition which is adapted to reduce the amount of light reaching the photovoltaic cells such that the resulting electrical output of said solar panel is reduced to below a level which causes physiological injury. The invention also relates to a composition for coating the light-receiving area of a solar panel comprising: a binder and an opacifier, wherein the opacifier is included in a sufficient quantity such that a predetermined film thickness of said composition reduces light transmission therethrough such that the resulting electrical output of said solar panel is reduced to below the predetermined level. | 2015-07-23 |
20150207022 | System for the production of single crystal semiconductors and solar panels using the single crystal semiconductors - A process and the required technical arrangement has been developed to produce single crystal solar panels or otherwise used semiconductors, which starts with the raw material to produce single crystal copper ribbons, extruded directly from the melt, with unharmed and optical surfaces onto which in the next unit a silicon or germanium film will be deposited. In the next unit the copper ribbon will be removed from the silicon film, whilst a hard plastic support or ceramic support is mounted, leaving copper contours on the silicon film to be used as electrical conductors or contacts. In the next unit a thin film is deposited of II-VI compounds that enhance the infrared sensitivity of the base film of silicon or germanium up to 56% of the incoming light. This technology guarantees the lowest possible cost in production of the highest possible efficiency of materials for infrared applications and electronic applications. | 2015-07-23 |
20150207023 | A METHOD FOR FABRICATING PIXELATED SILICON DEVICE CELLS - A method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps. | 2015-07-23 |
20150207024 | REDUCING OR ELIMINATING NANOPIPE DEFECTS IN III-NITRIDE STRUCTURES - Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer. | 2015-07-23 |
20150207025 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - A method of manufacturing a semiconductor light emitting device includes forming, on a substrate, a first region of a light emitting structure and the light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A protective layer is formed on the first region in a first chamber. The substrate with the first region and the protective layer formed thereon is transferred to a second chamber. A second region is formed on the first region. The first and second regions are disposed in a direction perpendicular to the substrate. The protective layer is grown above a defective region included in the first region and removed before or while the second region is formed. | 2015-07-23 |
20150207026 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of manufacturing a semiconductor light emitting device includes forming a light emitting structure layer including an active layer on a first substrate. A second substrate is bonded to the light emitting structure layer at a first temperature higher than room temperature. The first substrate is removed from the light emitting structure layer at a second temperature higher than room temperature. The second substrate and the light emitting structure are cooled to reach room temperature. A coefficient of thermal expansion of the second substrate is different from a coefficient of thermal expansion of the active layer. | 2015-07-23 |
20150207027 | SEMICONDUCTOR COMPONENT AND PROCESS FOR FABRICATING A SEMICONDUCTOR COMPONENT - A semi-conducting component including a semi-conducting layer of a first conductivity type including a plurality of semi-conducting zones of a second conductivity type opposite that of the semi-conducting layer, and an insulating layer. The component further includes a first bias mechanism configured to bias the semi-conducting layer and a second bias mechanism configured to bias a semi-conducting zone. The first bias mechanism includes a conducting layer in contact with the insulating layer and which includes passageways for each second bias mechanism with the spacing between the conducting layer and the second bias mechanism which is located facing the corresponding semi-conducting zone. | 2015-07-23 |
20150207028 | III-NITRIDE NANOWIRE LED WITH STRAIN MODIFIED SURFACE ACTIVE REGION AND METHOD OF MAKING THEREOF - A light emitting diode (LED) device includes a semiconductor nanowire core, and an In(Al)GaN active region quantum well shell located radially around the semiconductor nanowire core. The active quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the same shell. The active region quantum well shell has a non-uniform surface profile having at least 3 peaks. Each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley, and each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley. | 2015-07-23 |
20150207029 | Superlattice Structure - A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation. | 2015-07-23 |
20150207030 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure comprising a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer is provided. The substrate has a first surface and a second surface opposite to the first surface. The patterned structure is formed on the first surface of the substrate. The patterned structure comprises a plurality of pyramid structures with different sizes. The first semiconductor layer is disposed on the first surface. The active layer is disposed on the first semiconductor layer. The second semiconductor layer is disposed on the active layer. | 2015-07-23 |
20150207031 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure is provided. The semiconductor light emitting structure comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer. The first semiconductor layer is formed on the substrate. The active layer is formed on a portion of the first semiconductor layer, and the other portion of the first semiconductor layer is exposed and used as a first electrode predetermined area. The second semiconductor layer is formed on the active layer. The second semiconductor layer has a second electrode predetermined area and a micro-structure predetermined area disposed thereon. The micro-structure predetermined area comprises a plurality of concaves and a plurality of protrusions, and each protrusion is correspondingly located within one of the concaves. | 2015-07-23 |
20150207032 | METHODS AND DEVICES FOR LIGHT EXTRACTION FROM A GROUP III-NITRIDE VOLUMETRIC LED USING SURFACE AND SIDEWALL ROUGHENING - Embodiments of the present disclosures are directed to improved approaches for achieving high-performance light extraction from a Group III-nitride volumetric LED chips. More particularly, disclosed herein are techniques for achieving high-performance light extraction from a Group III-nitride volumetric LED chip using surface and sidewall roughening. | 2015-07-23 |
20150207033 | Nanopyramid Sized Opto-Electronic Structure and Method for Manufacturing of Same - Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanopyramids are grown utilizing a CVD based selective area growth technique. The nanopyramids are grown directly or as core-shell structures. | 2015-07-23 |
20150207034 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device may include a base semiconductor layer formed on a substrate and having defect regions therein; cavities disposed in regions corresponding to the defect regions on the base semiconductor layer; a capping layer disposed to cover at least one region of the base semiconductor layer and the cavities; and a light emitting structure disposed on the capping layer and including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. Lattice defects formed in the light emitting structure may be reduced to enhance luminous efficiency. | 2015-07-23 |
20150207035 | Light-Emitting Element Having a Tunneling Structure - A light-emitting element includes a first light-emitting stacked structure including a first active layer; and a tunneling structure on the light-emitting stacked structure including a first doped semiconductor layer; a first undoped semiconductor layer on the first doped semiconductor layer; a second undoped semiconductor layer on the first undoped semiconductor layer; a third undoped semiconductor layer between the first undoped semiconductor layer and the second undoped semiconductor layer, wherein the third undoped semiconductor layer includes a material different from that of the first undoped semiconductor layer; and a second doped semiconductor layer on the second undoped semiconductor layer, having a different conductivity from that of the first doped semiconductor layer; wherein the tunneling structure has a polarization field enhanced by the third undoped semiconductor layer. | 2015-07-23 |
20150207036 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic devices involving contact structures, and related components, systems and methods associated therewith are described. The contact structures are particularly suitable for use in a variety of light-emitting devices, including LEDs. | 2015-07-23 |
20150207037 | NANOWIRE SIZED OPTO-ELECTRONIC STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure. | 2015-07-23 |
20150207038 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a first conductive type semiconductor layer having a main surface, a plurality of vertical type light-emitting structures protruding upward from the first conductive type semiconductor layer; a transparent electrode layer covering the plurality of vertical type light-emitting structures; and an insulation-filling layer disposed on the transparent electrode layer. The insulation-filling layer extends parallel to the first conductive type semiconductor layer so as to cover the plurality of vertical type light-emitting structures. A selected one of the first conductive type semiconductor layer and the insulation-filling layer, which is disposed on a light transmission path through which light generated from the plurality of vertical type light-emitting structures is radiated externally, has an uneven outer surface. The uneven outer surface is opposite to an inner surface of the selected one, and the inner surface faces the plurality of vertical type light-emitting structures. | 2015-07-23 |
20150207039 | LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME - A light-emitting diode chip configured to emit light of a first wavelength range and light of a second wavelength range, including a substrate, a light-emitting structure disposed on a first surface of the substrate, the light-emitting structure including an active layer disposed between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, and configured to emit light of the first wavelength range, and first and second distributed Bragg reflectors (DBRs) disposed on a second surface of the substrate. The first DBR is disposed closer to the substrate than the second DBR, the first wavelength range comprises a blue wavelength range, the first DBR comprises a higher reflectivity for light of the second wavelength range than for light of the first wavelength range, and the second DBR comprises a higher reflectivity for light of the first wavelength range than for light of the second wavelength range. | 2015-07-23 |
20150207040 | LIGHT EMITTING DEVICES FOR LIGHT EMITTING DIODES (LEDS) - Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a submount and a light emission area disposed over the submount. The light emission area can include one or more light emitting diodes (LEDs), a fillet at least partially disposed about the one or more the LEDs, and filling material. The filling material can be disposed over a portion of the one or more LEDs and a portion of the fillet. | 2015-07-23 |
20150207041 | PHOSPHOR SEPARATED FROM LED BY TRANSPARENT SPACER - To reduce absorption by an LED die ( | 2015-07-23 |
20150207042 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device includes preparing wafer with a plurality of light emitting elements arrayed on a growth substrate, on a first side of a semiconductor stacked layer body, forming a resin layer which includes metal wires respectively connected to a p-side electrode and an n-side electrode, forming a groove by removing at least portion of the resin layer from an upper surface side in a boundary region between the light emitting elements and exposing end surfaces of metal wires which are internal conductive members on an inner side surface defining a groove, forming electrodes for external connection respectively connecting to exposed end surfaces of metal wires, and singulating the wafer into a plurality of singulated light emitting elements. | 2015-07-23 |
20150207043 | METHOD OF PRODUCING A MULTICOLOR LED DISPLAY - A method produces a multicolor LED display, the display including an LED luminous unit having a multiplicity of pixels. First subpixels, second subpixel and third subpixels contain an LED chip that emits radiation of a first color, wherein a first conversion layer that converts the radiation into a second color is arranged at least above the second subpixels and a second conversion layer that converts the radiation into a third color is arranged above the third subpixels. At least one process step is carried out in which the first or second conversion layer is applied or removed in at least one defined region above the pixels, wherein a portion of the LED chips is electrically operated, and wherein the region is defined by the radiation generated by the operated LED chips, generated heat or a generated electric field. | 2015-07-23 |
20150207044 | METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - A method for producing a plurality of optoelectronic components ( | 2015-07-23 |
20150207045 | Light-Emitting Device and Method of Manufacturing the Same - A light-emitting device includes a plurality of light-emitting elements face-down mounted on a substrate, a phosphor-containing film on the plurality of light-emitting elements directly or via a transparent adhesive layer, a transparent plate provided on the phosphor-containing film so as to directly contact the film, and a white reflector to cover a side surface of the plurality of light-emitting elements and, of side surfaces of the phosphor-containing film, at least a side surface not located above a gap between the plurality of light-emitting elements. At least a portion of a region directly above the gap is not covered with the phosphor-containing film. | 2015-07-23 |
20150207046 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - Provided is a light emitting device having a phosphor layer on a surface of a semiconductor light emitting element and reducing unevenness in light distribution color, and a method of manufacturing the same. A light emitting device | 2015-07-23 |
20150207047 | GRADIENT POLYMER STRUCTURES AND METHODS - An optical article includes a silicone-containing composition. The silicone composition includes a first region having a first refractive index and a second region having a second refractive index. The first refractive index is different than the second refractive index. | 2015-07-23 |
20150207048 | LIGHT EMITTING DEVICE - A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a dam resin made of a resin having a low optical transmittance; a fluorescent-material-containing resin layer; and an anode-side electrode and a cathode-side electrode, (a) which are provided on a primary surface of the ceramic substrate so as to face each other along a first direction on the primary surface and (b) which are disposed below at least one of the dam resin and the fluorescent-material-containing resin layer. With the configuration in which a plurality of LEDs, which are connected in a series-parallel connection, are provided on a substrate, it is possible to provide a light emitting device which can achieve restraining of luminance unevenness and an improvement in luminous efficiency. | 2015-07-23 |
20150207049 | LED DEVICE AND LED LAMP USING THE SAME - A LED device is provided. The LED comprises a frame, a housing, a LED chip and a protection component. The frame comprises a first lead frame and a second lead frame disposed along a first direction and isolated from each other. The housing partially covers the first and second lead frames, and has a receiving portion exposing parts of the surfaces of the first and second lead frames. The LED chip is disposed in the receiving portion on the exposed surface of the first lead frame, and electrically connected to the first and second lead frames. The protection component is disposed on a surface of the second lead frame that is covered by the housing and electrically connected to the first lead frame. None of the sides of a vertical projection of the protection component on the second lead frame is parallel or perpendicular to the first direction. | 2015-07-23 |
20150207050 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - For a semiconductor package mounted on a mounting member with wiring which connects an electrode on the upper surface of an LED device (semiconductor device) and an electrode at the mounting member side formed by a droplet discharge method or printing method, a stress relaxation film to reduce stresses applied to the wiring due to the difference in expansion/contraction between a land at the level difference sections and the wiring is formed at least at the level difference sections in the land which forms wiring, and the wiring is formed by a droplet discharge method or printing method on the stress relaxation film. The stress relaxation film may be formed of an insulating material for which the difference of the linear expansion coefficient from wiring is as small as possible and for which the Young's modulus is as large as possible. | 2015-07-23 |
20150207051 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a stacked semiconductor structure including a first conductivity-type semiconductor layer having a top surface divided into a first region and a second region, and an active layer and a second conductivity-type semiconductor layer disposed sequentially on the second region of the first conductivity-type semiconductor layer. First and second contact electrodes are disposed in the first region of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, respectively. A current spreading layer is disposed on the second contact electrode and comprises a first conductive layer having a first resistivity and a second conductive layer having a second resistivity smaller than the first resistivity alternately stacked. | 2015-07-23 |
20150207052 | Thermoelectric Micro-Platform for Cooling and Temperature Sensing - A thermoelectric micro-platform includes a suspended micro-platform, the suspended micro-platform being configured as a support layer with a device layer disposed thereon. Two arrays of series-connected thermoelectric devices are disposed partially on the micro-platform. One array is operated as Peltier coolers and the other array is operated as Seebeck sensors. | 2015-07-23 |
20150207053 | APPARATUS AND METHOD FOR HARVESTING ENERGY IN AN ELECTRONIC DEVICE - An apparatus, a method, and a computer program product are provided. The apparatus may be an electronic component. The electronic component includes at least one energy harvester coupled between at least one pair of hot and cold regions of the electronic component and configured to convert thermal energy to electrical energy in order to provide power to at least the electronic component, the at least one energy harvester including a radiative thermal channel or a conductive thermal channel. A first end of the conductive thermal channel is coupled to a first semiconductor material and a second end of the conductive thermal channel is coupled to a second semiconductor material, the first semiconductor material being coupled to the hot region and isolated from the cold region and the second semiconductor material being coupled to the cold region and isolated from the hot region. | 2015-07-23 |
20150207054 | THERMOELECTRIC GENERATOR UNIT AND METHOD OF TESTING THE THERMOELECTRIC GENERATOR UNIT - A thermoelectric generator unit according to this disclosure includes a plurality of tubular thermoelectric generators, each of which generates electromotive force based on a difference in temperature between the inner and outer peripheral surfaces. The unit further includes a plurality of electrically conductive members providing electrical connection for the generators and a container housing the generators inside. The container includes a shell surrounding the generators and a pair of plates, at least one of which has a plurality of openings and channels. Each channel houses an electrically conductive member. The generators are electrically connected together in series via the electrically conductive member. At least one of the channels has an interconnection which connects at least two of the openings together and a testing hole portion. The testing hole portion runs from the interconnection through an outer edge of the at least one plate. | 2015-07-23 |
20150207055 | THERMOELECTRIC CONVERSION ELEMENT INCLUDING, IN THERMOELECTRIC MATERIAL, SPACES OR BRIDGING SPACES SUCH THAT HEAT TRANSFER AMOUNTS ARE REDUCED AND WORKING SUBSTANCE FLOW IS EQUAL TO OR GREATER THAN THOSE OF ORIGINAL THERMOELECTRIC MATERIAL - The purpose of the present invention is to improve, by providing, in the terminals of thermoelectric materials and electrodes or the inside of the material, one or more spaces or either thin or fine line structures in spaces such that heat transfer or working substance (WS) flow is prevented from propagating, figure-of-merit of thermoelectric materials without the same. Thermal conductivity due to causes other than WS that can move within a thermoelectric conversion element can be reduced by providing the spaces, alternatively, microstructures in thermoelectric materials. If the terminal of thermoelectric material or surfaces facing the terminal of the thermoelectric material is modified and/or the steeple tips or steeples formed on the terminal, the potential barrier height for WS can be reduced or the tunnel potential barrier width can be reduced when WS leaps into the space from the surface of the steeple tips or the steeples. | 2015-07-23 |
20150207056 | ALUMINUM-MAGNESIUM-SILICON COMPOSITE MATERIAL AND PROCESS FOR PRODUCING SAME, AND THERMOELECTRIC CONVERSION MATERIAL, THERMOELECTRIC CONVERSION ELEMENT AND THERMOELECTRIC CONVERSION MODULE EACH COMPRISING OR INCLUDING THE COMPOSITE MATERIAL - Disclosed is an aluminum-magnesium-silicon composite material that contains an alloy comprising Al, Mg, and Si and can be used favorably as a material for a thermoelectric conversion module, and that has excellent thermoelectric conversion properties. The aluminum-magnesium-silicon composite material contains an alloy comprising Al, Mg and Si, and has an electrical conductivity (σ) of 1000-3000 S/cm at 300 K. This aluminum-magnesium-silicon composite material is favorable in the production of a thermoelectric exchange element as a result of having excellent thermoelectric conversion properties. | 2015-07-23 |
20150207057 | THIN FILM PIEZOELECTRIC ELEMENT, THIN FILM PIEZOELECTRIC ACTUATOR, AND THIN FILM PIEZOELECTRIC SENSOR; AND HARD DISK DRIVE, AND INKJET PRINTER - An object is to increase the amount of displacement of a thin-film piezoelectric element including a piezoelectric thin film having an uneven-shaped contact surface with the planar shape and the layer structure of the thin-film piezoelectric element kept unchanged. The thin-film piezoelectric element includes a pair of electrode layers and a piezoelectric thin film sandwiched between the pair of electrode layers, in which a surface roughness P-V of an interface between the piezoelectric thin film and at least one of the pair of electrode layers is 220 nm or more and 500 nm or less. | 2015-07-23 |