30th week of 2009 patent applcation highlights part 22 |
Patent application number | Title | Published |
20090185390 | EMERGENCY WHEEL LIGHT AND METHOD OF USE THEREOF - An emergency wheel light located in a protected environment behind an access door when not in use is extractable from under the wheel well or frame/bed of a vehicle to illuminate a wheel for servicing in darkness. The lamp portion, preferably of LED bulbs, is held in a retainer attached to the weatherproof access door or within the vehicle frame/wheel well. A plurality of the lamps is independently selectable for activation, such that any combination of the lamps can be on. To use, the lamp is pulled from its retaining mount and extended on its retractable cord reel into a position where it can be utilized to shine on the wheel servicing area by placing the lamp's flat base for placing the lamp on a ground surface. | 2009-07-23 |
20090185391 | Marker light fixture for scale model train - A light fixture for a scale model structure including a waveguide for transmitting light. The wave guide includes a transparent substrate; a first end for receiving light; a second end for emitting light from one or more output apertures; and a light scattering portion with an index of refraction substantially different from the transparent substrate, which scatters or reflects light received at the first end so as to emit light from the output apertures. | 2009-07-23 |
20090185392 | DETACHABLE ILLUMINATION SYSTEM - Illumination devices utilized within detachable illumination systems include a light source including a substantially planar light-emitting surface and an optical rod or optical taper disposed proximate to the substantially planar light-emitting surface to optically couple the optical rod and the substantially planar light-emitting surface. | 2009-07-23 |
20090185393 | LIGHT SOURCE MODULE, METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE HAVING THE LIGHT SOURCE MODULE - A light source module includes a mounting substrate including at least two exposed metal lines, a light-emitting diode (LED) including two electrodes disposed corresponding to the at least two exposed metal lines, and an anisotropic conductive film (ACF) provided on the mounting substrate, the ACF electrically connecting the at least two exposed metal lines to the two electrodes, wherein the ACF comprises an insulation body, and a plurality of conductive particles dispersed in the insulation body and insulated from each other, and an insulation of the conductive particles disposed between the two exposed metal lines and the two electrodes of the LED is prevented in at least a first direction. | 2009-07-23 |
20090185394 | LIGHT UNIT, BACKLIGHT, FRONTLIGHT, AND DISPLAY DEVICE - A light unit, a backlight, a front light, and a display device, have a structure such that an uneven luminance generated in display is suppressed by radiating light in a sufficient amount even to an end portion of a display region, thereby uniformly radiating light in a sufficient amount to the entire display region, without a complicated structure. The light unit includes a light guide plate and a plurality of light sources, the plurality of light sources being arranged in a line to oppose at least one side surface of the light guide plate, wherein one or more light sources at at least one terminal among the plurality of light sources are positioned outside a lateral edge of a display region, and such a light unit is preferably used in a side-light type backlight or front light. | 2009-07-23 |
20090185395 | BACK-LIGHT MODULE - A back-light module includes a light-guiding plate and a light source. The light-guiding plate has a lateral inlet surface. The light source is arranged at one side of the lateral inlet surface. The light source has a plurality of light-emitting diodes which are disposed in a line and at interval. A gap is formed between the adjacent light-emitting diodes. The lateral inlet surface dispose a plurality of convex lenses, each of the convex lenses has a convex surface facing to the corresponding gap between the adjacent light-emitting diodes. | 2009-07-23 |
20090185396 | METHOD AND APPARATUS FOR A CONTROL CIRCUIT WITH MULTIPLE OPERATING MODES - An apparatus of regulating a power converter with multiple operating modes includes a switch coupled to an energy transfer element coupled between an input and an output of the power converter. A control circuit is also included, which is coupled to the switch to control the switch. The control circuit includes first and second duty cycle control modes to regulate power delivered to the output of the power converter. A transition between the first and second duty cycle control modes is responsive to a magnitude of a current flowing in the switch reaching a current threshold value. | 2009-07-23 |
20090185397 | SECONDARY-SIDE AMPLIFIER WITH SOFT START - An isolated switching regulator has a closed-loop soft-start feature that allows tighter regulation of the output voltage and eliminates or reduces overshoot. It also has an optional reset feature which will resoft-start the regulator during recovery from a fault on the output voltage. | 2009-07-23 |
20090185398 | Integrated magnetics switching converter with zero inductor and output ripple currents and lossless switching - Switching Converter with a novel two-loop Integrated magnetic structure integrates transformer and two output inductors and eliminates large circulating current in the transformer secondary side resulting in ultra high efficiency and zero ripple output current as well as zero ripple currents in both output inductors simultaneously. The novel lossless switching method eliminates the primary side switching losses to result in switching converter with highest efficiency, compact size and additional performance advantages, such as ultra low output ripple voltage, low EMI noise and improved reliability with additional benefits when operated with a front-end Power Factor Converter for computer server applications. | 2009-07-23 |
20090185399 | ACTIVE START JUDGMENT CIRCUIT - An active start judgment circuit is electrically connected to an AC/DC transforming power supply which has at least one standby power unit to transform AC to DC in regular conditions and a main power unit to transform the AC to the DC in an ON condition for operation of an electronic equipment. The start judgment circuit bridges the standby power unit and the main power unit, and generates a reference potential based on a voltage output from the standby power unit, and gets a power signal from the standby power unit to be compared with the reference potential to output a start signal to the main power unit to transform the AC to the DC. Thus the standby power unit can actively drive the main power unit to supply DC power to activate the electronic equipment. | 2009-07-23 |
20090185400 | PARALLEL INVERTER SYSTEM - A parallel inverter system needs neither a dedicated line for synchronizing common portions nor switching operations, and includes a plurality of inverter units operating in parallel. An inverter control circuit of each inverter unit includes a sinusoidal signal generating circuit, a PWM control signal generating circuit, a phase difference circuit, a frequency difference circuit, and a feedback circuit. The feedback circuit inputs to the sinusoidal signal generating circuit an addition result value which is obtained by adding to a commanded value for reference frequency a value obtained from multiplication of a phase difference by a predetermined gain and a value obtained from multiplication of a frequency difference by a predetermined gain. The phase difference among outputs from the inverter units occurring in the parallel operation of the inverter units is reduced by changing the output frequencies of the inverter units. (140 word) | 2009-07-23 |
20090185401 | DC-AC Converter and Controller IC Thereof - A semiconductor switch circuit is connected to a primary winding of a transformer having a secondary winding connected to a load. The semiconductor switch circuit has switches controlled by PWM to provide a controlled constant current. In the inventive inverter, constant current control is performed by PWM operation of the switches of the semiconductor switch circuit. The inverter cuts off electricity to the control circuit when putting the control circuit into a standby state if a run-stop signal gains a logical stop-state. At the same time as the run-stop signal gaining the stop-state, switch drive signals enabling the switches of the semiconductor switch circuit are turned off. Thus, over-current can be prevented from flowing in the load when the control circuit is put into the standby state. | 2009-07-23 |
20090185402 | STANDBY CIRCUIT WITH SUPER LOW POWER CONSUMPTION - The present invention relates to a circuit minimizing standby power in a power adapter with a power-frequency transformer (T | 2009-07-23 |
20090185403 | Controller for Electrically Adjustable Furniture - A controller for electrically adjustable furniture includes a main-voltage area and a low-voltage area that are electrically isolated from one another. A rectifying power supply unit, which is located in the main-voltage area, serves to generate a rectified voltage available at power supply terminals from an alternating main voltage. The rectified voltage present at the power supply terminals can be delivered to a first motor terminal located in the main-voltage area depending on a first control signal. The controller furthermore includes a first control unit that is located in the main-voltage area and which incorporates an operating terminal and a first control output for the supply of a first control signal. An operating unit located in the low-voltage area is connected via an electrically isolating coupling to the operating terminal. | 2009-07-23 |
20090185404 | Regenerative Building Block and Diode Bridge Rectifier and Methods - A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices. | 2009-07-23 |
20090185405 | THREE-PHASE VOLTAGE SOURCE INVERTER SYSTEM - The present invention provides a three-phase voltage source inverter system capable of obtaining a nearly sinusoidal output waveform while minimizing apparatus size increase and cost increases. The three-phase voltage source inverter system of the present invention is provided with: a three-phase inverter unit INV-M; and an auxiliary circuit | 2009-07-23 |
20090185406 | Switched-Capacitor Circuit Having Two Feedback Capacitors - A switched-capacitor circuit performing two-phase operation with a sampling phase and an amplification phase comprising: an inverter having a common source type input transistor and a load transistor; a first capacitor whose first terminal is connected to a gate of the input transistor serving as an input of the inverter; a first switch which connects between the input (the gate of the input transistor) and the output of the inverter, which turns on during the sampling phase and turns off during the amplification phase; a second switch which connects a second terminal of the first capacitor to an input voltage terminal during the sampling phase, and connects the second terminal of the first capacitor to the output terminal of the inverter during the amplification phase; a second capacitor whose first terminal is connected to a gate of the load transistor of the inverter and whose second terminal is connected to the second terminal of the first capacitor; and a third switch which connects the first terminal of the second capacitor to a bias voltage terminal during the sampling phase, and turns off the first terminal of the second capacitor from the bias voltage during the amplification phase. | 2009-07-23 |
20090185407 | Semiconductor Memory Device Having Transistors of Stacked Structure - Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers. | 2009-07-23 |
20090185408 | MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR DESIGN OF MEMORY DEVICE - A memory device may include, but is not limited to, at least one memory module, and a plurality of lumped constant circuit elements. The at least one memory module is electrically coupled to a transmission system that has a characteristic impedance. The plurality of lumped constant circuit elements with an inductance is placed on the transmission system symmetrically with reference to the at least one memory module. The plurality of lumped constant circuit elements in cooperation with the at least one memory module performs as at least one low-pass filter. | 2009-07-23 |
20090185409 | ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the | 2009-07-23 |
20090185410 | METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING UNIDIRECTIONAL POLARITY SELECTION DEVICES - A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and a plurality of unidirectional polarity selection devices. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The unidirectional polarity selection devices are connected in parallel and such that they have opposing polarities. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells. | 2009-07-23 |
20090185411 | INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS - The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material. | 2009-07-23 |
20090185412 | PHASE-CHANGE MATERIAL, MEMORY UNIT AND METHOD FOR ELECTRICALLY STORING/READING DATA - A phase-change material and a memory unit using the phase-change material are provided. The phase-change material is in a single crystalline state and includes a compound of a metal oxide or nitroxide, wherein the metal is at least one selected from a group consisting of indium, gallium and germanium. The memory unit includes a substrate; at least a first contact electrode formed on the substrate; a dielectric layer disposed on the substrate and formed with an opening for a layer of the phase-change material to be formed therein; and at least a second contact electrode disposed on the dielectric layer. As the phase-change material is in a single crystalline state and of a great discrepancy between high and low resistance states, the memory unit using the phase-changed material can achieve a phase-change characteristic rapidly by pulse voltage and avert any incomplete reset while with a low critical power. | 2009-07-23 |
20090185413 | SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH OUTPUT PATH CONTROL UNIT - A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal. | 2009-07-23 |
20090185414 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells. | 2009-07-23 |
20090185415 | CELL OPERATION MONITORING - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation. | 2009-07-23 |
20090185416 | SYSTEM THAT COMPENSATES FOR COUPLING BASED ON SENSING A NEIGHBOR USING COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location). | 2009-07-23 |
20090185417 | Apparatus and method of memory programming - A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells. | 2009-07-23 |
20090185418 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 2009-07-23 |
20090185419 | PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME - A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation. | 2009-07-23 |
20090185420 | PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME - A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation. | 2009-07-23 |
20090185421 | Charge-Trap Flash Memory Device with Reduced Erasure Stress and Related Programming and Erasing Methods Thereof - Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap flash memory device may thus be provided with improved reliability by interrupting erasure stress to unused memory cells. | 2009-07-23 |
20090185422 | Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods - A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit. | 2009-07-23 |
20090185423 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 2009-07-23 |
20090185424 | DECODING CONTROL WITH ADDRESS TRANSITION DETECTION IN PAGE ERASE FUNCTION - Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks. | 2009-07-23 |
20090185425 | Integrated Circuit Having a Memory Cell Arrangement and Method for Reading a Memory Cell State Using a Plurality of Partial Readings - Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels. | 2009-07-23 |
20090185426 | Semiconductor memory device and method of forming the same - The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described. | 2009-07-23 |
20090185427 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD FOR THE SAME - The semiconductor memory device includes: a first well of a first conductivity type, a second well of the first conductivity type and a third well of a second conductivity type formed in a substrate: a diffusion bit line extending in a row direction and a word line extending in a column direction both formed in the second well; a plurality of semiconductor memory elements arranged in a matrix, each connected with the diffusion bit line and the word line; a selection transistor formed in the first well for applying a voltage to the diffusion bit line; and a forward diode formed of a diffusion layer of the first conductivity type formed in the third well and the third well. The diffusion bit line, the forward diode and the source of the selection transistor are electrically connected with one another. | 2009-07-23 |
20090185428 | OPERATING METHOD OF MULTI-LEVEL MEMORY CELL - An operating method of a memory cell is described, wherein the memory cell has a plurality of threshold voltages. The operating method includes programming the cell from an initial state to a programmed state. The initial state is an erased state having a threshold voltage between the lowest threshold voltage and the highest one among the plurality of threshold voltages. | 2009-07-23 |
20090185429 | Non-volatile memory with single floating gate and method for operating the same - A non-volatile memory with single floating gate and the method for operating the same are proposed. The non-volatile memory is formed by embedding a FET structure in a semiconductor substrate. The FET comprises a single floating gate, a dielectric, and two ion-doped regions in the semiconductor at two sides of the dielectric. The memory cell of the proposed nonvolatile memory with single floating gate can perform many times of operations such as write, erase and read by means of a reverse bias. | 2009-07-23 |
20090185430 | Memory sensing and latching circuit - According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal. | 2009-07-23 |
20090185431 | SEMICONDUCTOR DEVICE - The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays. | 2009-07-23 |
20090185432 | SEMICONDUCTOR MEMORY DEVICE - A charge driving circuit and a discharge driving circuit occupy a relatively small area and maintain driving force in a semiconductor memory device having a plurality of banks. The semiconductor memory device includes multiple banks, a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks, and a discharge drivers assigned to the respective banks. The discharge drivers are configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector. | 2009-07-23 |
20090185433 | Semiconductor Device - A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting a second control signal which is enabled when at least one of the banks performs a self-refresh operation or auto-refresh operation, and a second logic unit for performing a logic operation with respect to an output signal from the first logic unit and the second control signal to generate a third control signal having information about activation of the semiconductor device. The third control signal is enabled when at least one of the banks performs the self-refresh operation or auto-refresh operation even though it is in the active state. | 2009-07-23 |
20090185434 | OPERATIONAL MODE CONTROL IN SERIAL-CONNECTED MEMORY BASED ON IDENTIFIER - Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices. | 2009-07-23 |
20090185435 | Method and Circuit for Implementing Enhanced SRAM Write and Read Performance Ring Oscillator - A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator. | 2009-07-23 |
20090185436 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING WRITE CONTROLLING CIRCUIT - A semiconductor integrated circuit includes a write controlling circuit configured to selectively provide a fixed pulse or a variable pulse according to a level of a test mode signal in a write operation mode, thereby adjusting a pulse width of an internal write pulse that is a current pulse driving an internal memory cell in response to the fixed pulse or the variable pulse. | 2009-07-23 |
20090185437 | CLOCK-BASED DATA STORAGE DEVICE, DUAL PULSE GENERATION DEVICE, AND DATA STORAGE DEVICE - Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding to inversion of a clock signal and a second clock signal corresponding to the clock signal by using the delayed clock signal when the clock signal shifts, a pull-up wait for outputting a pull-up output signal to an output port, based on the first clock signal outputted from the dual pulse generating unit and an input data signal which has beeb inputted, a pull-down unit for outputting a pull-down output signal to the output port, based on the second clock signal outputted from the dual pulse generating unit and the input data signal inputted which has been inputted, and a latch unit which is disposed between the pull-up and pull-down units, and the output port so as to store at least one output signal outputted f roars the pull-down unit as well as the pull-down unit. | 2009-07-23 |
20090185438 | SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT FOR REPAIRING DEFECTIVE UNIT CELL, AND METHOD FOR REPAIRING DEFECTIVE UNIT CELL - A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input. | 2009-07-23 |
20090185439 | ARCHITECTURE OF HIGHLY INTEGRATED SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; and a second column control circuit region corresponding to a third memory bank and disposed adjacent to the first column control circuit region. | 2009-07-23 |
20090185440 | ACTIVE CYCYLE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle. | 2009-07-23 |
20090185441 | Integrated Circuit and Method to Operate an Integrated Circuit - Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation. | 2009-07-23 |
20090185442 | MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES - Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode. | 2009-07-23 |
20090185443 | MIXING MACHINE AND ASSOCIATED BOWL SUPPORT ARRANGEMENT - A mixing machine includes a head including a rotatable output member for receiving a mixer tool. A mixer body includes a bowl receiving assembly below the head. The bowl receiving assembly includes a pair of bowl support arms extending outwardly from the mixer body to respective ends located at opposite sides of a bowl receiving location. Each bowl support arm includes a mount protrusion extending upwardly therefrom. The mount protrusions include a notch located at bases of the mount protrusions. The bowl receiving assembly is mounted for movement between a lowered position away from the head and a raised position toward the head. | 2009-07-23 |
20090185444 | Method for wavefield separation in 3D dual sensor towed streamer data with aliased energy in cross-streamer direction - Pressure records and vertical particle velocity records from dual sensor towed streamer data are transformed to the inline wavenumber domain. A series of scaling filters are applied to the transformed vertical particle velocity records at each inline wavenumber, wherein each of the series of scaling filters is calculated for a different cross-streamer wavenumber range and in blocks of inline traces in which all seismic events are approximately linear. The pressure spectrum and the scaled vertical particle velocity spectrum are combined to separate upgoing and downgoing wavefield components. The separated upgoing and downgoing wavefield components are inverse-transformed back to the time-space domain. | 2009-07-23 |
20090185445 | BOREHOLE APPARATUS AND METHODS FOR SIMULTANEOUS MULTIMODE EXCITATION AND RECEPTION TO DETERMINE ELASTIC WAVE VELOCITIES, ELASTIC MODULII, DEGREE OF ANISOTROPY AND ELASTIC SYMMETRY CONFIGURATIONS - An acoustic borehole logging system for generation and detection of multipole modes used to determine elastic properties of earth formations characterized as inhomogeneous anisotropic solids. The system concurrently generates and senses monopole, dipole, quadrupole and any higher order pole in the borehole/formation system in order to characterize the elastic properties and stress state of material penetrated by the borehole. Multipole modes of all orders are induced simultaneously without the need for separate transmitter and receiver systems. Performance of the logging system is not compromised due to eccentering of the axis of the tool in the borehole, tool tilt with respect to the axis of the borehole, or mismatch of response sensitivity of multiple receivers within the tool. The system comprises apparatus for generating and sensing acoustic signals in a borehole in an earth formation, and further comprises a processing method by which the sensor response signals are processed and analyzed to obtain desired formation parameters of interest. | 2009-07-23 |
20090185446 | Identification of Stress in Formations Using Angles of Fast and Slow Dipole Waves in Borehole Acoustic Logging - Cross-dipole measurements are obtained in a borehole. By estimating a direction of polarization of the fast shear mode at low and high frequencies and comparing the estimated distances, a cause of anisotropy is established. Formation stresses and directions may be estimated. | 2009-07-23 |
20090185447 | BOREHOLE APPARATUS AND METHODS FOR SIMULTANEOUS MULTIMODE EXCITATION AND RECEPTION TO DETERMINE ELASTIC WAVE VELOCITIES, ELASTIC MODULII, DEGREE OF ANISOTROPY AND ELASTIC SYMMETRY CONFIGURATIONS - An acoustic borehole logging system for generation and detection of multipole modes used to determine elastic properties of earth formations characterized as inhomogeneous anisotropic solids. The system concurrently generates and senses monopole, dipole, quadrupole and any higher order pole in the borehole/formation system in order to characterize the elastic properties and stress state of material penetrated by the borehole. Multipole modes of all orders are induced simultaneously without the need for separate transmitter and receiver systems. Performance of the logging system is not compromised due to eccentering of the axis of the tool in the borehole, tool tilt with respect to the axis of the borehole, or mismatch of response sensitivity of multiple receivers within the tool. The system comprises apparatus for generating and sensing acoustic signals in a borehole in an earth formation, and further comprises a processing method by which the sensor response signals are processed and analyzed to obtain desired formation parameters of interest. | 2009-07-23 |
20090185448 | METHOD FOR IMAGING THE EARTH'S SUBSURFACE USING PASSIVE SEISMIC SENSING - A method of imaging the Earth's subsurface using passive seismic emission tomography includes detecting seismic signals from within the Earth's subsurface over a time period using an array of seismic sensors, the seismic signals being generated by seismic events within the Earth's subsurface. The method further includes inducing a seismic event within the Earth's subsurface during at least a segment of the time period over which the seismic signals are detected. The method further includes cross-correlating seismic signals detected at each of the seismic sensors to obtain a reflectivity series at a position of each of the seismic sensors. | 2009-07-23 |
20090185449 | Method for 3-C 3-D Wavefield Decomposition - An apparatus and a method for processing of three components, 3-Dimensions seismic (3-C, 3-D) data acquired by down-hole receivers and surface seismic sources. Automatic velocity analysis is used to identify the velocities of dominant events in a VSP panel. Different wave-types (downgoing P, downgoing PS, upcoming PS and upcoming PP) are identified and sequentially removed. | 2009-07-23 |
20090185450 | BOTTLE FOR DENTAL HYGIENE PRODUCT WITH TIMING MECHANISM - A packaging system includes a bottle that holds a dental hygiene product. A closure is configured to be removably coupled to the bottle. The bottle defines an opening when the closure is removed from the bottle. The timing mechanism is coupled to at least one of the bottle and closure. The timing mechanism includes a sensory device and a timer. The timing mechanism measures a time period and provides an output after a preset period of time has elapsed. | 2009-07-23 |
20090185451 | Dive Watch - The invention concerns a mechanical or electromechanical dive watch including hour ( | 2009-07-23 |
20090185452 | PORTABLE ELECTRONIC DEVICE HAVING A HISTORY FUNCTION AND INTENDED TO DISPLAY THE VALUE OF VARIABLES ON THE BASIS OF MEASUREMENTS MADE BY A SENSOR - The present invention relates to a portable electronic device ( | 2009-07-23 |
20090185453 | TIMEPIECE MOVEMENT FOR DRIVING A DISPLAY ELEMENT ALONG A COMPLEX PATH AND TIMEPIECE COMPRISING SUCH A MOVEMENT - A timepiece, includes a frame supporting a drive element, a time base and drive trains pivotably mounted on the frame and arranged so as to drive at least one display train intended to carry an element displaying information, such as the time. The movement also includes a fixed gear, firmly attached to the frame, with which a toothed element of the display train is arranged to mesh, and a drive element having first and second kinematic links, respectively, with one of the drive trains and with the toothed element so as to drive the latter in translation in a first direction along the fixed gear. Preferably, the drive element is embodied in the form of a deformable element, and the movement also includes a retrograde mechanism for driving the toothed element rapidly in the opposite direction by means of the drive element. | 2009-07-23 |
20090185454 | Fillable hourglass and method of using fillable hourglass - A fillable hourglass having a glass component with opening permitting access to the inside of the glass component, a base with a least one opening in communication with the opening of the glass component, and a stopper for selectively opening and closing access to the glass component. The base is preferably formed from two planar members supported in spaced relation by decorative pillars. The stoppers may include decorative enhancements, such as being shaped in the design of a nautical steering wheel. The hourglass may be used as part of wedding sand ceremonies or to hold particular matter related to the wedding ceremony, or as an urn for storing crematory remains of a human or animal. | 2009-07-23 |
20090185455 | Aquatic Event Timer Apparatus and Methods - The inventive technology, in embodiments, includes an aquatic event timer apparatus that comprises at least two independent, touch actuated electrical switches; and a structural connector that adjacently connects them, where the apparatus is configured for establishment within lane markers defining a regulation size swim lane, at the end of the swim lane, and at least partially underwater. Other aspects of the inventive technology address an aquatic event timer apparatus that comprises a first, independent, swim competition type, touch actuated electrical switch that is configured for establishment within swim lane markers, and aside at least a second, independent, swim competition type, touch actuated electrical switch. | 2009-07-23 |
20090185456 | ELECTROMECHANICAL ESCAPEMENT DEVICE AND TIMEPIECE PART UTILIZING SUCH A DEVICE - The electromechanical escapement device is associated with an electronic circuit having a quartz oscillator and calculation means suitable for calculating the difference between the period of the quartz oscillator and the period of a mechanical oscillator and releasing an escape wheel, normally controlled by said mechanical oscillator, when the difference between said periods is greater than a threshold value. | 2009-07-23 |
20090185457 | ONE-MOVEMENT BALANCED HANDS CLOCK - A balanced hands clock. The clock utilizes a single movement, which movement may be located in the minute hand. A gear drive mechanism provides leverage from said movement via a first pivot shaft to drive the hour hand. The clock is mounted in a base for time indicating movement. Covers may be provided to hide the single movement and the gear mechanism so that no visible drive configuration is visible to an observer. | 2009-07-23 |
20090185458 | Watch with Planar Light Diffusion Channel - Structures are disclosed that can improve the visibility of instrument displays. With some implementations, an instrument is provided with an illumination system having a light source and a light diffusion device proximal to the light source. The light diffusion device has at least one surface parallel to a primary plane of the display of the instrument. When the light source is activated, light propagates through the light diffusion device toward the display of the instrument. | 2009-07-23 |
20090185459 | HEAD GIMBAL ASSEMBLY AND INFORMATION RECORDING APPARATUS - When a semiconductor laser is arranged outside a slider and a light is to be guided to the slider through a waveguide, the following problems will be solved: the stability of the flying slider is deteriorated due to a stress from the waveguide; and when an actuator is arranged near the flying slider, the motions of the slider are hindered by the waveguide. A waveguide for guiding a light to a light irradiating unit inside a slider, which floats over a medium and has the light irradiating unit for irradiating a light to the medium; and a waveguide for propagating a light from the light source to the waveguide inside the slider, are included. The two waveguides are not in contact with each other, and a relative portion between the two waveguides is movable. | 2009-07-23 |
20090185460 | Method of correcting head suspension, method of manufacturing head suspension, head suspension, and method of processing thin plate - A method corrects a head suspension by irradiating an objective part of the head suspension with a laser beam. The method is capable of precisely correcting the head suspension even when correcting the head suspension a plurality of times. The method removes residual stress created by the preceding correction from the head suspension, and then, carries out the next correction. Accordingly, the method can precisely correct the objective part of the head suspension with a laser beam even if the objective part has once been irradiated with a laser beam in the preceding correction. | 2009-07-23 |
20090185461 | MEDIUM TRANSPORTING MECHANISM AND MEDIUM PROCESSING APPARATUS HAVING THE SAME - A medium transporting mechanism for transporting one of stacked media each of which has a hole is provided. A holder is provided on a movable transporting arm and holds the one of the media. A guide is provided in the transporting arm, the guide has a tapered surface that is inclined with respect to an axis of the guide. The tapered surface is configured to be brought into contact with an inner surface of the hole of the one of the media when the guide is inserted into the hole of the one of the media. The tapered surface includes a first surface on a tip end portion of the guide and a second surface on a base end portion of the guide. An inclined angle of the first surface with respect to the axis of the guide is greater than an inclined angle of the second surface with respect to the axis of the guide. | 2009-07-23 |
20090185462 | Focus Controller and Focus Control Method - A focus controller and a focus control method are provided. The method allows the optical access apparatus focus from a current data layer onto a target layer. Each of the current layer and the target layer corresponds to a Spherical Aberration Compensation (SAC) value and a focus error related parameter. The method adjusts the SAC value in use to a temporary SAC value, adjusts the focus error related parameter in use to a temporary focus error related parameter, focuses on the target layer, adjusts the focus error related parameter in use to the focus error related parameter corresponding to the target layer, and adjusts the SAC value in use to the focus error related parameter corresponding to the target layer. | 2009-07-23 |
20090185463 | DIFFRACTION GRATING, OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS - A pickup device splits and detects a light beam reflected from a disc with the use of a grating. The grating has first to six areas, wherein the first area and the second area, the third area and the fifth area, and the fourth area and the sixth area are arranged in point symmetry with respect to the center of the grating, respectively. The first area is interposed between the fourth area and the fifth area and the second area is interposed between the third area and the sixth area. Further, the centers of the first area and the second area are arranged to be spaced by a distance d in a direction perpendicular to the displacement direction of the optical pickup device. Even though the center of an optical disc is not located on a straight line in the displacement direction of the optical pickup device, objective lens can obtain a stable servo signal. | 2009-07-23 |
20090185464 | LASER POWER CONTROL METHOD AND OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE - Each of control powers of a first definition group that correspond to a pulse train used to form a recording mark, and a plurality of levels of a second definition group that includes each of the control powers of the first definition group in accordance with the conditions of a recording medium | 2009-07-23 |
20090185465 | DISC WITH TEMPORARY DISC DEFINITION STRUCTURE (TDDS) AND TEMPORARY DEFECT LIST (TDFL), AND METHOD OF AND APPARATUS FOR MANAGING DEFECT IN THE SAME - A disc with a temporary defect management information area and a defect management area includes a defect management area that is present in at least one of a lead-in area, a lead-out area, and an outer area, a temporary defect information area which is formed in the data area and in which temporary defect information is recorded, and a temporary defect management information area which is present in at least one of the lead-in area, and the lead-out area. Accordingly, it is possible to record user data in a recordable disc, especially, a write-once disc, while performing defect management thereon, thereby enabling efficient use of a defect management area having a limited recording capacity. | 2009-07-23 |
20090185466 | RECORDING POWER CALIBRATING METHOD FOR IMPROVING SEEKING STABILITY ON RECORDING POWER CALIBRATION AREA - In an optimal recording power calibration method for improving seeking stability on a recording power calibration area, a specific area serves as a data recording area during an optimal recording power calibration, wherein a length of the specific area is such that a plurality of times of optimal recording power calibrations can be performed. The method includes: an optimal recording power calibration step of recording, with different recording power, a first length of calibration data in the specific area, and calibrating optimal recording power, wherein a data sector recorded in this step is defined as a calibration recording sector; and a data recording step of recording, with data recording power, a second length of information having a logical address beside the calibration recording sector of the specific area, wherein a data sector recorded in the step is defined as an information recording sector. | 2009-07-23 |
20090185467 | METHOD AND DEVICE FOR STORING DATA ON A RECORD MEDIUM AND FOR TRANSFERRING INFORMATION - Data storage system ( | 2009-07-23 |
20090185468 | PHASE ERROR DETECTION APPARATUS - A phase error detection apparatus capable of performing offset correction of a tracking error signal accurately even when there is a defect or a non-recorded position on an optical disc. There are provided a phase difference detection circuit ( | 2009-07-23 |
20090185469 | DEVICE, SYSTEM AND METHOD FOR AUTOMATIC DATA SOLIDIFICATION - A device, system and method is invented to solidify data from temporary storage media to long term storage media without intervention of computer. Those who can not access computer are enabled to use digital recording apparatus, such as digital camera. The operation of the device is restricted in order to increase the ease of use, and to provide the core function. The core function is to read data from temporary storage media, such as various memory cards, and write the data to long term storage media, such as user-writeable CD or DVD. The device features a minimal set of hardware components for accomplishing this function, such as a simplified user interface, an embedded processor, a data reading channel, and a data solidification channel. A data play mode can also be optionally implemented for the user to check the solidified data. | 2009-07-23 |
20090185470 | ADVANTAGEOUS RECORDING MEDIA FOR HOLOGRAPHIC APPLICATIONS - High performance media suitable for recording with a blue laser is disclosed. The blue-sensitized holographic media provides greater dynamic range and higher sensitivity than previously disclosed blue-sensitized holographic media. These media can be used for diverse applications such as data storage where the articles provide denser data storage and more rapid hologram writing times or for optical waveguides where the articles provide greater optical confinement and more rapid manufacturing times. | 2009-07-23 |
20090185471 | Optical Pickup Device and Optical Disc Apparatus - In an optical pickup device, an optical reflection beam from a multi-layer optical disc is divided into a plurality of areas, divided optical fluxes focus upon different positions on a photodetector, a focusing error signal is detected by using a plurality of divided optical fluxes by a knife edge method, and a tracking error signal is detected by using a plurality of divided optical fluxes. The optical flux divided areas and light receiving parts are disposed in such a manner that in an in-focus state of a target layer, stray light from another layer does not enter servo signal light receiving parts of the photodetector. It is therefore possible to obtain stable servo signals including both the focusing error signal and tracking error signal during recording/reproducing a multi-layer optical disc, without being influenced by stray light from another layer. | 2009-07-23 |
20090185472 | Objective Optical System and Optical Information Recording/Reproducing Device Having the Same - There is provided an objective optical system used for information recording/reproducing for three types of optical discs. The objective optical system includes an objective lens, and a diffraction structure formed on an optical surface. The diffraction structure includes a first area for contributing to converging the third light beam. The first area includes first and second steps defined by first and second optical path difference functions, respectively. The first step is configured such that diffraction orders at which diffraction efficiencies for the first, second and third light beams are maximized are 1 | 2009-07-23 |
20090185473 | OBJECTIVE LENS AND OPTICAL PICKUP DEVICE - In order that thickness reduction, weight reduction, and mass productivity improvement should be achieved in an objective lens even in the case where NA is high, an objective lens according to the present invention is a bi-convex single lens having at least one aspheric surface, and satisfies conditions: (1) 3.52009-07-23 | |
20090185474 | METHOD OF STORING DATA USING A MICRO-ELECTROMECHANICAL SYSTEM BASED DATA STORAGE SYSTEM - A method of storing data using data storage system having a positioning system for a micro-electromechanical system (“MEMS”) based data storage is provided. The method includes a moving MEMS-based scanner that interacts with a polymer medium to read, write and erase data. A first positioning system is coupled to the MEMS scanner to allow the storage of data over a defined area. A second positioning system is coupled to the first positioning system and the MEMS scanner to allow the use of a larger polymer medium. A plurality of storage modules is also provided to allow scalability of data storage. | 2009-07-23 |
20090185475 | NON-ORTHOGONAL SUBCARRIER MAPPING METHOD AND SYSTEM - A method and system of accommodating multiple users through non-orthogonal subcarrier mapping of a single carrier frequency division multiple access system in which input data to a transmitter is modulated via an N-point discrete Fourier transform (N-point DFT), non-orthogonal subcarrier mapping, M-point inverse discrete Fourier transform (M-point IDFT), and cyclic prefix (CP) insertion; the modulated data is transmitted to and received by a receiver; and the received data is demodulated for cyclic prefix (CP) removal, M-point discrete Fourier transform (M-point DFT), subcarrier demapping and equalization, and N-point inverse discrete Fourier transform (N-point IDFT). | 2009-07-23 |
20090185476 | DURATION-SHORTENED OFDM SYMBOLS - A communications network comprises a base station ( | 2009-07-23 |
20090185477 | Transmitting Data In A Mobile Communication System - The present invention is related to transmitting data in a mobile communication system. Preferably, the present invention comprises transmitting first data to a receiving side and receiving acknowledgment information for indicating whether the first data was successfully transmitted to the receiving side. If the first data was not successfully transmitted to the receiving side, the method further comprises determining whether an amount of available radio resources is sufficient for retransmitting the first data to the receiving side, retransmitting the first data to the receiving side if the amount of available radio resources is sufficient to retransmit the first data, reconfiguring the first data into at least one second data if the amount of available radio resources is insufficient to retransmit the first data, wherein the at least one second data can be transmitted to the receiving side using the amount of available radio resources, and transmitting the at least one second data to the receiving side. | 2009-07-23 |
20090185478 | METHOD AND NODE FOR IMPLEMENTING MULTICAST FAST REROUTE - A method for implementing multicast fast reroute includes: determining a route for a backup LSP according to the tree topology of a point-to-multipoint primary LSP and establishing the backup LSP according to the determined route for the backup LSP. In the process of establishing the backup LSP, messages for the primary LSP and its corresponding backup LSPs are further merged to decrease the number of network signaling states. A node includes a transceiver unit and a backup LSP path establishing unit. The present invention can save protection bandwidth, optimize network resource utilization, and enhance utilization efficiency of resources. | 2009-07-23 |
20090185479 | Communication Systems - An uplink transmission method for use in a multi-hop communication system, the system comprising a mobile station (MS), a base station (BS) and one or more relay stations (RS), and the system providing two or more different communication paths extending between the mobile station and the base station, the mobile station being operable to transmit information indirectly to the base station along a series of links forming a first such communication path via one or more of the relay stations and also being operable to transmit information to the base station along one link or a series of links forming a second such communication path; the method comprising transmitting particular information from the mobile station along the first and the second communication paths; and combining the same particular information transmitted along the first and second communication paths in the base station. | 2009-07-23 |
20090185480 | Method and System for Re-enabling Disabled Ports in a Network with Two Port MAC Relays - A system and method for enabling a disabled port on a device such as a Two Port Medium Access Control (MAC) Relay (TPMR), which relays MAC frames in a communication network. When a link in the network fails, the TPMR disables the port due to operation of a link failure propagation protocol. When the TPMR detects that the failed link is repaired, the TPMR stops transmitting link failure Packet Data Units (PDUs) and transmits a Link Failure Terminating PDU to other connected TPMRs in the network. Receipt of the Link Failure Terminating PDU indicates the failed link is repaired and all ports disabled as a result of the failure should consequently be enabled. | 2009-07-23 |
20090185481 | METHOD AND NETWORK NODE FOR SELF-REGULATING, AUTONOMOUS AND DECENTRALIZED TRAFFIC DISTRIBUTION IN A MULTIPATH NETWORK - According to one embodiment, traffic load is redirected in reaction to traffic overload or a link failure in a packet-based network that is formed by nodes and links, packets being distributed along multiple paths to other links of an associated array of paths. The redistribution is performed autonomously by the node which is located immediately upstream of the affected link. According to a further development of the method, nodes that are located upstream of the concerned node are notified and are made to perform a redistribution that relieves the concerned node if the array of paths is not made overload-free by the redistribution performed by the node. A mechanism that protects against overload and failures and reacts in a significantly more flexible and less error-prone manner than networks having a central control body due to the nodes being autonomous is provided. | 2009-07-23 |
20090185482 | METHOD AND SYSTEM FOR PROTECTION SWITCHING DECISION - A method for protection switching decision includes: performing performance monitoring and failure detection on a first transmitting entity that transmits services; performing performance monitoring and failure detection on a second transmitting entity that does not transmit services; and making protection switching decision according to the performance monitoring and failure detection results of the first transmitting entity and second transmitting entity. A system for performance monitoring is also disclosed. In embodiments of the present invention, performance monitoring may be performed on the transmitting entity that does not transmit services, thus avoiding invalid switching of services and improving the quality of services. | 2009-07-23 |
20090185483 | Method and Apparatus for Transmitting Data and Error Recovery - A system and method for partitioning and transmitting a frame configuration in a wireless communication system is provided. A preferred embodiment comprises a method for determining a frame configuration in H-FDD systems where multiple time domain groups are supported is disclosed. Another embodiment provides a method for a base station for transmitting an indication of a frame configuration in H-FDD systems where multiple time domain groups are supported. Further, if the mobile stations enter into an error condition because they did not receive the frame configuration, an error recovery process may be utilized to self-recover from the error condition. | 2009-07-23 |
20090185484 | RAPID RESPONSE METHOD FOR THE FAILURE OF LINKS BETWEEN DIFFERENT ROUTING DOMAINS - The invention relates to a rapid response method for the failure of a link between two routing domains in a packet-oriented network. Once the failure of a link has been identified, substitute routes are provided for the interrupted routes by the local selection of alternative routes and by the propagation of messages along the substitute routes. In contrast to conventional inter-domain protocols such as the BGP (Iborder gateway protocol) the transmission of messages and the associated modification to the routing only involves routing domains that lie along the replacement routes. In one embodiment, a network-wide propagation of messages takes place if the failure of the link represents a persistent breakdown. As a consequence, optimal routes are re-determined in the entire network. The invention provides breakdown compensation that is appropriate for temporary breakdowns and prevents instabilities that occur as a result of the use of conventional inter-domain protocols. | 2009-07-23 |
20090185485 | System and method for movement detection and congestion response for transport layer protocol - A system, apparatus, and method for determining network capacity and managing network congestion in response to a change in an end-to-end communication path between sender and receiver hosts. A receiver mobility notification is provided by the receiver host to the sender host. The sender host determines whether the receiver host has moved between networks or sub-networks using the receiver mobility notification. If the sender host determines that the receiver host has moved from one network/subnet to another network/subnet, a congestion state at the sender host is reset to correspond to the new end-to-end communication path established between the sender host and the receiver host in the new subnet. | 2009-07-23 |
20090185486 | Method for controlling traffic balance between peering networks - A method that measures ratio, relative to a peering network, of traffic burden of incoming traffic to traffic burden of outgoing traffic, where traffic burden takes into account traffic volume and distance that the traffic traverses through the network. A determination is made from this ratio as to whether an imbalance exists with the peering network. With the assistance of a simulation of changes in routing policy and their effects, an existing or impending imbalance is remedied by changing the routing policy relative to particular customers, for example from a “hot potato” routing policy to a “best exit” routing policy. | 2009-07-23 |
20090185487 | AUTOMATED ADVANCE LINK ACTIVATION - Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays. | 2009-07-23 |
20090185488 | NETWORK MESSAGE MANAGEMENT DEVICE AND METHODS THEREOF - A method of managing communication of messages via a network includes storing messages received from an application in a queue at a transport layer. The transport layer monitors the amount of information stored at the queue. When the amount of information exceeds a threshold amount, the transport layer provides a warning message to the application. In an embodiment, the transport layer provides the warning message before the queue assigned to store messages from the application is full, so that the application can continue to provide messages to the transport layer after the warning message. The application can take appropriate action in response to the message, such as reducing the amount or frequency of information provided at the transport layer, thereby reducing the likelihood of a communication bottleneck at the transport layer. | 2009-07-23 |
20090185489 | Scheduling the transmission of messages on a broadcast channel of an ad-hoc network dependent on the usage of this channel - In order to provide a communication system ( | 2009-07-23 |