29th week of 2010 patent applcation highlights part 13 |
Patent application number | Title | Published |
20100181558 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND IMAGE DISPLAY DEVICE - A semiconductor device having semiconductor elements disposed with higher density and a method for manufacturing the same are provided. | 2010-07-22 |
20100181559 | ORGANIC EL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - Disclosed is an organic EL display panel which includes: a substrate; a linear first bank which is disposed over the substrate and defines a linear region; a second bank which defines two or more pixel regions arranged in the linear region; a pixel electrode disposed in the pixel region; a linear organic layer which is formed by coating method in the linear region over the pixel electrode and second bank; and a counter electrode over the organic layer, wherein the first bank is larger in height than the second bank, the first and second banks are made of resin, anisole contact angle at the top of the first bank is 30-60°, and anisole contact angle at the top of the second bank is 5-30°. | 2010-07-22 |
20100181560 | ORGANIC ELECTROLUMINESCENT ELEMENT, DISPLAY, AND ELECTRONIC APPARATUS - An organic electroluminescent element includes an electron-transport layer composed of a heterocyclic compound, a negative electrode composed of a metal material, and a transition-metal-complex layer arranged between the electron-transport layer and the negative electrode. | 2010-07-22 |
20100181561 | ORGANIC LIGHT-EMITTING DEVICE - An organic light emitting device with improved light emitting efficiency, the organic light emitting device includes a substrate, a first electrode arranged on the substrate, a second electrode arranged to face the first electrode, an organic light-emitting layer arranged between the first electrode and the second electrode, an electron transport layer arranged between the organic light-emitting layer and the second electrode, wherein the electron transport layer includes a multi-layer structure that includes at least one first layer and at least two second layers, wherein ones of said at least one first layer and ones of said at least two second layers are alternately stacked, wherein ones of the at least two second layers are arranged at both opposite ends of the electron transport layer, each of the at least two second layers having a lower electron mobility than that of each of the at least one first layer. | 2010-07-22 |
20100181562 | Light-Emitting Element, Light-Emitting Device, and Electronic Device - A light-emitting element includes a first electrode, a first light-emitting layer formed over the first electrode, a second light-emitting layer formed on and in contact with the first light-emitting layer to be in contact therewith, and a second electrode formed over the second light-emitting layer. The first light-emitting layer includes a first light-emitting substance and a hole-transporting organic compound, and the second light-emitting layer includes a second light-emitting substance and an electron-transporting organic compound. Substances are selected such that a difference in LUMO levels between the first light-emitting substance, the second light-emitting substance, and the electron-transporting organic compound is 0.2 eV or less, a difference in HOMO levels between the hole-transporting organic compound, the first light-emitting substance, and the second light-emitting substance is 0.2 eV or less, and a difference in LUMO levels between the hole-transporting organic compound and the first light-emitting substance is greater than 0.3 eV. | 2010-07-22 |
20100181563 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A thin film transistor using an oxide semiconductor as an active layer, and its method of manufacture. The thin film transistor includes: a substrate; an active layer formed of an oxide semiconductor; a gate insulating layer formed of a dielectric on the active layer, the dielectric having an etching selectivity of 20 to 100:1 with respect to the oxide semiconductor; a gate electrode formed on the gate insulating layer; an insulating layer formed on the substrate including the gate electrode and having contact holes to expose the active layer; and source and drain electrodes connected to the active layer through the contact holes. Since the source and drain electrodes are not overlapped with the gate electrode, parasitic capacitance between the source and drain electrodes and the gate electrode is minimized. Since the gate insulating layer is formed of dielectric having a high etching selectivity with respect to oxide semiconductor, the active layer is not deteriorated. | 2010-07-22 |
20100181564 | FUNCTIONAL MATERIAL FOR PRINTED ELECTRONIC COMPONENTS - The invention relates to a printable precursor comprising an organometallic zinc complex which contains at least one ligand from the class of the oximates and is free from alkali metals and alkaline-earth metals, for electronic components and to a preparation process. The invention furthermore relates to corresponding printed electronic components, preferably field-effect transistors. | 2010-07-22 |
20100181565 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO | 2010-07-22 |
20100181566 | Electrode Structure, Device Comprising the Same and Method for Forming Electrode Structure - An electrode structure comprises a semiconductor junction comprising an n-type semiconductor layer and a p-type semiconductor layer; a hole exnihilation layer on the p-type semiconductor layer; and a transparent electrode layer on the hole exnihilation layer. The electrode structure further comprises a conductive layer between the hole exnihilation layer and the transparent electrode layer. In the electrode structure, one or more of the hole exnihilation layer, the conductive layer and the transparent electrode layer may be formed by an atomic layer deposition. In the electrode structure, a transparent electrode formed of a degenerated n-type oxide semiconductor does not come in direct contact with a p-type semiconductor, and thus, annihilation or recombination of holes generated in the p-type semiconductor can be reduced, which increases the carrier generation efficiency. Further, the electric conductivity of the transparent electrode is increased by the conductive layer, which improves electrical characteristics of a device. | 2010-07-22 |
20100181567 | Semiconductor device including bonding pads and semiconductor package including the semiconductor device - Provided is a semiconductor device that may prevent a test pad planned not to be wire bonded from being wire bonded. The semiconductor device may include a bonding pad planned to be wire bonded and a test pad planned not to be wire bonded, and a passivation layer including a first opening portion exposing part of the bonding pad and a second opening portion exposing part of the test pad, wherein the diameter of the first opening portion is greater than the diameter of a tip of a bonding wire, and the diameter of the second opening portion is less than the diameter of the tip of the bonding wire. | 2010-07-22 |
20100181568 | INTEGRATED CIRCUITS ON A WAFER AND METHODS FOR MANUFACTURING INTEGRATED CIRCUITS - Integrated circuits ( | 2010-07-22 |
20100181569 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - A display device for preventing misalignment of data lines and pixel electrodes, and a manufacturing method of the display device are provided. The display device includes an insulation substrate, line wiring formed on the insulation substrate, an organic insulating pattern covering the top surface and side surfaces of a portion of the line wiring, a first insulating layer formed on the organic insulating pattern and the insulation substrate, and transparent conductive patterns formed on the first insulating layer, wherein boundaries of the transparent conductive patterns are positioned on inclined surfaces of the first insulating layer in a portion thereof corresponding to the organic insulating pattern. | 2010-07-22 |
20100181570 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An active matrix substrate in which variations in output characteristics of photodiodes are reduced, and a display device using this active matrix substrate, are provided. An active matrix substrate ( | 2010-07-22 |
20100181571 | LAMINATE STRUCTURE, ELECTRONIC DEVICE, AND DISPLAY DEVICE - A laminate structure is disclosed that has a region having high surface free energy and a region having low surface free energy that are well separated, has high adhesiveness between an underlying layer and a conductive layer, and can be formed easily with low cost. The laminate structure includes a wettability-variable layer including a first surface free energy region of a first film thickness and a second surface free energy region of a second film thickness, and a conductive layer formed on the second surface free energy region of the wettability-variable layer. The second film thickness is less than the first film thickness and the surface free energy of the second surface free energy region is made higher than the surface free energy of the first surface free energy region by applying a predetermined amount of energy on the second surface free energy region. | 2010-07-22 |
20100181572 | THIN FILM TRANSISTOR ARRAY PANEL - A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode. | 2010-07-22 |
20100181573 | GATED CO-PLANAR POLY-SILICON THIN FILM DIODE - A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate. | 2010-07-22 |
20100181574 | THIN FILM TRANSISTOR DEVICES WITH DIFFERENT ELECTRICAL CHARACTERISTICS AND METHOD FOR FABRICATING THE SAME - A system for displaying images. The system includes a thin film transistor (TFT) device including a first insulating layer covering a first region and a second region of a substrate. A first polysilicon active layer is disposed in the first region and between the substrate and the first insulating layer. A second polysilicon active layer is disposed on the first insulating layer in the second region. A polysilicon gate layer is disposed above the first polysilicon active layer. A second insulating layer covers the polysilicon gate layer and the second polysilicon active layer. A metal gate layer is disposed above the second polysilicon active layer. A method for fabricating the system for displaying images including the TFT device is also disclosed. | 2010-07-22 |
20100181575 | SEMICONDUCTOR DEVICE PROVIDED WITH THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes at least one thin-film transistor | 2010-07-22 |
20100181576 | Epitaxial Structure Having Low Defect Density - An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer. The polished surfaces are substantially flush with the epitaxial surface so that the first epitaxial layer has a substantially planarized crystal growth surface | 2010-07-22 |
20100181577 | NITRIDE SEMICONDUCTOR SUBSTRATE - There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure. | 2010-07-22 |
20100181578 | PACKAGE STRUCTURE - A package structure is described. A light emitting element and a light sensing element are disposed on a substrate, and are both wrapped by a package layer. Meanwhile, the light emitting element and the light sensing element are separated by a trench of the package layer, such that lights generated by the light emitting element are blocked, thereby reducing the noise interference on the light sensing element and improving the sensing precision of the light sensing element. | 2010-07-22 |
20100181579 | ASSEMBLY STRUCTURE OF A LIGHT-EMITTING DIODE LIGHT SOURCE AND A POWER SUPPLY INTERFACE - The present invention discloses an light emitting diode (LED) light source and an interface for providing power to the LED. The LED light source includes an LED unit and a second coupling unit. The LED unit includes a base, one or more LED, and a first coupling unit. The LED are attached to the base. The joining of the first and second coupling units provides a mechanical support and electricity to the LED. The LED, are connected with independent circuit loops and controlled by controller to change the brightness of the LED. This structure allows the second coupling unit to be applied to any luminaries or replacement of a traditional light source, thus making the LED unit a universal LED light source for mass production and cost reduction. With the use of various types of LED and electric current control, modulation of brightness, color, and color temperature may be achieved. | 2010-07-22 |
20100181580 | LIGHT EMITTING APPARATUS - A light emitting apparatus including a light emitting element of a gallium nitride based semiconductor and a light converter absorbing a part of primary light emitted from the light emitting element to emit secondary light with a longer wavelength than the primary light, the light converter includes, as a red light emitting phosphor, divalent europium activated nitride red light emitting phosphor substantially represented by (MI | 2010-07-22 |
20100181581 | TYPE II BROADBAND OR POLYCHROMATIC LEDS - An LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%, and wherein at least one of the Type II interfaces is within a pn junction. Alternately, an LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%. The Type II interfaces may include interfaces from a layer which is an electron quantum well and not a hole quantum well, interfaces to a layer which is a hole quantum well and not an electron quantum well; and interfaces that satisfy both conditions simultaneously. The Type II interfaces may be within a pn or pin junction or not within a pn or pin junction. In the later case, emission from the Type II interfaces may be photopumped by a nearby light source. The LED may be a white or near-white light LED. In addition, graphic display devices and illumination devices comprising the semiconductor device according to the present invention are provided. | 2010-07-22 |
20100181582 | LIGHT EMITTING DEVICES WITH PHOSPHOR WAVELENGTH CONVERSION AND METHODS OF MANUFACTURE THEREOF - A light emitting device comprises: a package (low temperature co-fired ceramic) having a plurality of recesses (cups) in which each recess houses at least one LED chip and at least one phosphor material applied as coating to the light emitting light surface of the LED chips, wherein the phosphor material coating is conformal in form. In another arrangement a light emitting device comprises: a planar substrate (metal core printed circuit board); a plurality of light emitting diode chips mounted on, and electrically connected to, the substrate; a conformal coating of at least one phosphor material on each light emitting diode chip; and a lens formed over each light emitting diode chip. | 2010-07-22 |
20100181583 | RADIATION-EMITTING SEMICONDUCTOR CHIP - A radiation-emitting semiconductor chip is specified, comprising a semiconductor body ( | 2010-07-22 |
20100181584 | LASER LIFT-OFF WITH IMPROVED LIGHT EXTRACTION - A light emitting device includes a stack of semiconductor layers defining a light emitting pn junction and a dielectric layer disposed over the stack of semiconductor layers. The dielectric layer has a refractive index substantially matching a refractive index of the stack of semiconductor layers. The dielectric layer has a principal surface distal from the stack of semiconductor layers. The distal principal surface includes patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers. | 2010-07-22 |
20100181585 | ILLUMINATION SYSTEM COMPRISING A COMPOUND WITH LOW THERMAL EXPANSION COEFFICIENT - The invention relates to an illumination system with a material having a low or negative thermal expansion coefficient in order to compensate for the thermal expansion of the further materials present in the illumination system. | 2010-07-22 |
20100181586 | LIGHT EMITTING DEVICE - A light emitting device That includes a first photonic crystal structure having a reflective layer and non-metal pattern elements on the reflective layer, a second conductive semiconductor layer on both the reflective layer and the non-metal pattern elements, an active layer on the second conductive semiconductor layer, and a first conductive semiconductor layer on the active layer. | 2010-07-22 |
20100181587 | LED packaging structure and fabricating method thereof - A LED (light emitting diode) packaging structure includes a base, a LED chip, a gel-blocking structure and a phosphor layer. The LED chip disposed on the base and electrically connected to the base. The LED chip having a substrate and a semiconductor layer formed on the substrate. The gel-blocking structure is disposed on the substrate of the LED chip and surrounding the semiconductor layer. The phosphor layer is filled within a space defined by the gel-blocking structure, the substrate and the semiconductor layer. The present invention also discloses a fabricating method of the LED packaging structure. | 2010-07-22 |
20100181588 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed therebetween, and a surface plasmon layer disposed between the active layer and at least one of the n-type and p-type semiconductor layers, including metallic particles and an insulating material, and including a conductive via for electrical connection between the active layer and the at least one of the n-type and p-type semiconductor layers, wherein the metallic particles are enclosed by the insulating material to be insulated from the at least one of the n-type and p-type semiconductor layers. The semiconductor light emitting device can achieve enhanced emission efficiency by using surface plasmon resonance. Using the semiconductor light emitting device, the diffusion of a metal employed for surface plasmon resonance into the active layer can be minimized. | 2010-07-22 |
20100181589 | CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes. | 2010-07-22 |
20100181590 | LIGHT-EMITTING DIODE ILLUMINATING APPARATUS - The invention provides a light-emitting diode illuminating apparatus. The light-emitting diode illuminating apparatus includes a carrier, a substrate, a light-emitting diode die, and a micro-lens assembly. The carrier includes a top surface and a bottom surface. A first recess is formed on the top surface of the carrier. A second recess is formed on the bottom surface of the carrier. The first recess is connected to the second recess. The substrate is embedded into the second recess. The light-emitting diode die is disposed on the substrate. The micro-lens assembly is disposed above the light-emitting diode die. | 2010-07-22 |
20100181591 | LED ILLUMINATION DEVICE USING DIFFRACTION MEMBER - An object of this invention is to provide an LED illumination device that can substitute for a fluorescent light and obtain uniform light with high efficiency. The LED illumination device comprises an LED with a thin-plate-shaped semiconductor element body transmitting the light generated in a PN junction area in a thickness direction and emits it from the surface, a surface electrode that covers the surface of the semiconductor element body, and columnar dielectric antennas that penetrate the surface electrode in the thickness direction and that condense the light transmitted in a body of the semiconductor element and emit it outside, a diffraction member that is arranged on a luminous surface side of the LED and that diffracts and disperses the light emitted by the LED, and a diffusion member that is arranged outside the diffraction member and that diffuses the light dispersed by the diffraction member and emits it outside. | 2010-07-22 |
20100181592 | Semiconductor Device and Method of Manufacturing Same - A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction. | 2010-07-22 |
20100181593 | LED chip package - A LED chip package including a two-phase-flow heat transfer device, at least one LED chip, a metal lead frame and a package material. The two-phase-flow heat transfer device has at least one flat surface. The LED chip is directly or indirectly bonded or adhered to the flat surface of the two-phase-flow heat transfer device. Heat generated by the LED chip can be easily conducted away from the LED chip by the two-phase-flow heat transfer device such as a heat pipe, a vapor chamber and the like so as to prevent heat from accumulating in the LED chip thereby extending the service duration of the LED chip and to prevent the LED chip from deterioration of the light emitting performance caused by the accumulation of heat. | 2010-07-22 |
20100181594 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE HEAT SPREADER AND CAVITY OVER POST - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device extends into a cavity in the adhesive, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly from the base into an opening in the adhesive and is located below the cavity, and the base extends laterally from the post. The cavity extends to the post. The adhesive extends between the cavity and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal. | 2010-07-22 |
20100181595 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - The present invention aims to enhance the light extraction efficiency of the Group III nitride semiconductor light-emitting device. | 2010-07-22 |
20100181596 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage horizontal IGBT, which is an aspect of a semiconductor device relating to the present invention, has a buffer region formed in an SOI substrate and extending from a surface of the SOI substrate to a surface of a buried oxide film. An interface between the buffer region and a drift region is positioned equally in a vicinity of a bottom of the buffer region and in a vicinity of a surface of the buffer region or shifted toward a body region in the vicinity of the bottom of the buffer region compared to that in the vicinity of the surface of the buffer region. With this structure, a concentration of electric field in the vicinity of the bottom of the buffer region is moderated, whereby a collector-emitter breakdown voltage can further be increased. | 2010-07-22 |
20100181597 | Protection device of programmable semiconductor surge suppressor having deep-well structure - A protection device of programmable semiconductor surge suppressor having deep-well structure is provided comprising one, two or four protection units, each of which is composed of a PN-junction diode, a PNPN-type thyristor and a NPN-type triode connected with each other. It is characterized in that in the diode area on the frontal side of the N-type semiconductor base is formed a PN junction with impurity concentration changed gradiently from top to bottom according to the order of P+, P, N and N+; and a group of deep-wells with P-type impurities are positioned at the interface of the PN junction, making the PN junction form a concave-convex type interface. The present invention can be used in the program-controlled switchboard to protect the Subscriber Line Interface Circuit (SLIC) board. The above improvement can further improve the anti-lightning and anti-surge performance and the energy discharge capability of the whole device. The device of the present invention can reach a level of 3000˜3500 V according to the anti-lightning performance test. | 2010-07-22 |
20100181598 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCER DEVICE - Etch block layers having an etching rate smaller than that of a first semiconductor forming a semiconductor substrate are formed on the sidewalls of device isolation grooves by applying oblique ion implantation of Ox, N, or C to the semiconductor substrate including the first semiconductor. Embedded layers including a second semiconductor are selectively formed in recesses by epitaxial-growing the second semiconductor having a lattice constant larger than that of the first semiconductor in the recesses. | 2010-07-22 |
20100181599 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer | 2010-07-22 |
20100181600 | Programmable Transistor Array Design Methodology - A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip. | 2010-07-22 |
20100181601 | SILICON BASED OPTO-ELECTRIC CIRCUITS - A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer. | 2010-07-22 |
20100181602 | Solid-state image sensor, method of manufacturing the same, and image pickup apparatus - Disclosed is a solid-state image sensor including a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. In the solid-state image sensor, the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is longer than the second spacer. | 2010-07-22 |
20100181603 | METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MESFET) SILICON-ON-INSULATOR STRUCTURE HAVING PARTIAL TRENCH SPACERS - In one embodiment, a metal-semiconductor field effect transistor (MESFET) comprises a first silicon layer, an insulator layer formed on the first silicon layer, and a second silicon layer formed on the insulator layer. A gate region, a source region, and a drain region are formed in the second silicon layer. A first partial trench is formed in the second silicon layer between at least a portion of the gate region and at least a portion of the source region, wherein the first partial trench stops short of the insulator layer. A second partial trench formed in the second silicon layer between at least a portion of the gate region and at least a portion of the drain region, wherein the second partial trench stops short of the insulator layer. First and second oxide spacers are formed in the first and second partial trenches. The first and second oxide spacers and the source region, gate region, and the drain region are substantially planar. | 2010-07-22 |
20100181604 | STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY - A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array. | 2010-07-22 |
20100181605 | DATA STORAGE DEVICE HAVING SELF-POWERED SEMICONDUCTOR DEVICE - Provided is a data storage device. The data storage device includes an interface, a buffer controller, a memory controller, a non-volatile memory, and a self-powered semiconductor device adjacent to and electrically connected to the buffer controller. The self-powered semiconductor device includes a semiconductor chip and a rechargeable micro-battery attached to the semiconductor chip. The rechargeable micro-battery includes a first current collector and a second current collector, which face each other, a first polarizing electrode in contact with the first current collector and facing the second current collector, a second polarizing electrode in contact with the second current collector and facing the first polarizing electrode, and an electrolyte layer formed between the first and second polarizing electrodes. | 2010-07-22 |
20100181606 | Semiconductor Device - Provided is a semiconductor device having a high switching speed. A semiconductor device ( | 2010-07-22 |
20100181607 | INCREASING THE SURFACE AREA OF A MEMORY CELL CAPACITOR - Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer. | 2010-07-22 |
20100181608 | FLASH MEMORY DEVICE AND METHOD MANUFACTURING THE SAME - According to the present disclosure, a flash memory device includes a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers. | 2010-07-22 |
20100181609 | Flash Memory Device and Method of Manufacturing the Same - Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures. | 2010-07-22 |
20100181610 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns. | 2010-07-22 |
20100181611 | DIELECTRIC STRUCTURE IN NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film. | 2010-07-22 |
20100181612 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole. | 2010-07-22 |
20100181613 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes first and second active pillar structures protruding at an upper part of a substrate, buried bit lines each extending in a first direction, and first gate patterns and second gate patterns each extending in a second direction. The first and second active pillar structures occupy odd-numbered and even-numbered rows, respectively. The first and the second active pillar structures also occupy even-numbered and odd-numbered columns, respectively. The columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures. Each buried bit line is connected to lower portions of the first active pillar structures which occupy one of the even-numbered columns and to lower portions of the second active pillar structures which occupy an adjacent one of the odd-numbered columns. | 2010-07-22 |
20100181614 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor pillar, an insulator, and an electrode. The semiconductor pillar has a semiconductor portion outwardly extending. The insulator extends along the semiconductor pillar. The insulator has an insulating portion outwardly extending along the semiconductor portion. The electrode extends along the insulator. The insulator is between the semiconductor pillar and the electrode. The electrode has an electrode portion overlapping the insulating portion in plain view. The electrode portion is under the insulating portion. | 2010-07-22 |
20100181615 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device in which an upper main electrode region of a 3D pillar SGT includes a selective epitaxial growth semiconductor film, at least two adjacent 3D pillar SGTs are interconnected in parallel with each other by joining the selective epitaxial growth semiconductor films together, thereby the need for providing an interconnect layer for interconnecting 3D pillar SGTs in parallel with each other is eliminated. | 2010-07-22 |
20100181616 | Semiconductor device and method of manufacturing the same - A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position. | 2010-07-22 |
20100181617 | Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 2010-07-22 |
20100181618 | EXTENDED DRAIN TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - An extended drain transistor ( | 2010-07-22 |
20100181619 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR - A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained. | 2010-07-22 |
20100181620 | STRUCTURE AND METHOD FOR FORMING PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE - A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode. | 2010-07-22 |
20100181621 | SIGNAL AND POWER SUPPLY INTEGRATED ESD PROTECTION DEVICE - An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure. | 2010-07-22 |
20100181622 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film. | 2010-07-22 |
20100181623 | SEMICONDUCTOR DEVICE HAVING DUMMY BIT LINE STRUCTURE - A semiconductor device includes a substrate having a cell area including a memory cell region and a dummy cell region, gate structures formed in the cell region, an insulating interlayer formed on the substrate to cover the gate structures, plugs formed through the insulating interlayer, bit lines contacting the plugs in the memory cell region, and dummy bit line structures contacting the plugs in the dummy cell region. The dummy bit line structure prevents a leakage current generated in a peripheral circuit area from flowing into a cell area. | 2010-07-22 |
20100181624 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a gate electrode line provided to extend from an N-type area through a device isolation area to a P-type area, and source/drain diffused regions formed in N-type and P-type areas. The gate electrode line includes a first silicide region which configures a P-type MOSFET gate electrode and includes therein a silicide of metal M | 2010-07-22 |
20100181625 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor layer formed on a semiconductor substrate; a gate electrode formed on the semiconductor layer via a gate insulating film; an impurity diffusion suppression layer formed between the semiconductor substrate and the semiconductor layer and including a C-containing Si-based crystal containing a first impurity, the C-containing Si-based crystal being configured to suppress diffusion of a second impurity having a p-type conductivity type, and the C-containing Si-based crystal with the first impurity having a function of suppressing generation of fixed charge in the C-containing Si-based crystal; and p-type source/drain regions formed in the semiconductor substrate, the impurity diffusion suppression layer and the semiconductor layer in sides of the gate electrode, the p-type source/drain region having an extension region in the semiconductor layer and containing the second impurity. | 2010-07-22 |
20100181626 | Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates - A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap. | 2010-07-22 |
20100181627 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region. | 2010-07-22 |
20100181628 | SEMICONDUCTOR DEVICE - Prevention of disconnection of a bonding wire resulting from adhesive interface delamination between a resin and a leadframe, and improvement of joint strength of the resin and the leadframe are achieved in a device manufactured by a low-cost and simple processing. A boss is provided on a source lead by a stamping processing, and a support pillar is provided in a concave portion on a rear side of the source lead in order to prevent ultrasonic damping upon joining the bonding wire onto the boss, so that an insufficiency of the joint strength between the bonding wire and the source lead is prevented. Also, a continuous bump is provided on the boss so as to surround a joint portion between the source lead and the bonding wire, so that disconnection of the bonding wire resulting from delamination between the resin and the source lead is prevented. | 2010-07-22 |
20100181629 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method includes forming a source, a drain, and a disposable gate ( | 2010-07-22 |
20100181630 | DIRECT CONTACT BETWEEN HIGH-K/METAL GATE AND WIRING PROCESS FLOW - A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride. | 2010-07-22 |
20100181631 | FABRICATION OF MEMS BASED CANTILEVER SWITCHES BY EMPLOYING A SPLIT LAYER CANTILEVER DEPOSITION SCHEME - Embodiments discussed herein generally disclose novel alternative methods that can be employed to overcome the gradient stress formed in refractory materials to be used for thin film MEMS cantilever switches. The use of a ‘split layer’ cantilever fabrication method, as described herein enables thin film MEMS cantilever switches to be fabricated resulting in low operating voltage devices while maintaining the mechanical rigidity of the landing portion of the final fabricated cantilever switch. | 2010-07-22 |
20100181632 | Magnetic tunnel junction device and memory device including the same - The output voltage of an MRAM is increased by means of an Fe( | 2010-07-22 |
20100181633 | Magnetic Memory Device - A magnetic memory device includes a magnetic tunnel junction (MTJ) structure and an electrode embedded in a dielectric structure. The MTJ structure includes a free layer. The electrode is formed of silicon-germanium and is electrically connected to the MTJ. The electrode heats the free layer to reduce the coercive force of the free layer to reduce a critical current density. | 2010-07-22 |
20100181634 | METHOD AND STRUCTURE FOR REDUCING CROSS-TALK IN IMAGE SENSOR DEVICES - Provided is a method of fabricating an image sensor device. The method includes providing a semiconductor substrate having a front side and a back side, forming a first isolation structure at the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side, and forming a second isolation structure at the back side of the semiconductor substrate. The first and second isolation structures are shifted with respect to each other. | 2010-07-22 |
20100181635 | METHOD AND STRUCTURE FOR REDUCING CROSS-TALK IN IMAGE SENSOR DEVICES - Provided is a method of fabricating an image sensor device. The method includes providing a semiconductor substrate having a front side and a back side, forming a first isolation structure at the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side, and forming a second isolation structure at the back side of the semiconductor substrate. The first and second isolation structures are shifted with respect to each other. | 2010-07-22 |
20100181636 | OPTICAL DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD OF MANUFACTURING OPTICAL DEVICE - An optical device includes the following structures. An optical element includes a light-receiving element at an upper surface of the optical element. A transparent member is disposed on the upper surface to cover the light-receiving element. A case includes a bottom wall, a side wall protruding from an outer edge of the bottom wall, and a through-hole penetrating the bottom wall. A sealant is filled in a space defined by surfaces of the optical element, the transparent member, and the case, and also in the through-hole. Here, the optical element and the transparent member are stored in a region between the bottom wall and the side wall. The sealant is filled to the region to seal the space. The bottom wall is segmented into: a center region in which the optical element is placed; and a peripheral region outside the center region. The through-hole is arranged in the peripheral region. | 2010-07-22 |
20100181637 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark. | 2010-07-22 |
20100181638 | METHOD OF FORMING AN ISOLATION STRUCTURE - Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit. | 2010-07-22 |
20100181639 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices. | 2010-07-22 |
20100181640 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device about which the reliability thereof is certainly kept even when a void is generated in a buried film in its trench. A rectangular element formation region is formed in a silicon layer. A trench having a predetermined width is formed to surround the element formation region. A first TEOS film and a second TEOS film are buried in the trench. A protecting film is formed at an L-shaped intersection region of the trench. | 2010-07-22 |
20100181641 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the first substrate surface into the semiconductor substrate. The trench has a first trench section and a second trench section. The trench surface is exposed in an upper portion of the first and second trench sections and covered with a first insulating layer in a lower portion. A second insulating layer is formed at least on the exposed trench surface in the upper portion. A conductive layer is formed on the second insulating layer at least in the upper portion, wherein the second insulating layer electrically insulates the conductive layer from the semiconductor substrate. The conductive layer is removed in the first trench section without removing the conductive layer in the second trench section. | 2010-07-22 |
20100181642 | WAFER-LEVEL FLIP CHIP PACKAGE WITH RF PASSIVE ELEMENT/ PACKAGE SIGNAL CONNECTION OVERLAY - A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, a transistor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh. | 2010-07-22 |
20100181643 | EFUSE WITH PARTIAL SIGE LAYER AND DESIGN STRUCTURE THEREFOR - A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region. | 2010-07-22 |
20100181644 | IC PACKAGE WITH CAPACITORS DISPOSED ON AN INTERPOSAL LAYER - An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation. | 2010-07-22 |
20100181645 | SEMICONDUCTOR ARRANGEMENT WITH TRENCH CAPACITOR AND METHOD FOR ITS MANUFACTURE - The invention relates to a semiconductor arrangement and method for production thereof, wherein the semiconductor arrangement is provided with an integrated circuit arranged on a substrate. The integrated circuit is structured on the front face of the substrate and at least one capacitor is connected to the integrated circuit, wherein the at least one capacitor is designed as a monolithic deep structure in trenches. The trenches are arranged in at least one first group and at least one second group, the trenches of a group running essentially parallel to each other and the first and second group are at an angle to each other, essentially at right angles to each other. | 2010-07-22 |
20100181646 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode. | 2010-07-22 |
20100181647 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved. | 2010-07-22 |
20100181648 | LOCALIZED SYNTHESIS AND SELF-ASSEMBLY OF NANOSTRUCTURES - Systems and methods for local synthesis of silicon nanowires and carbon nanotubes, as well as electric field assisted self-assembly of silicon nanowires and carbon nanotubes, are described. By employing localized heating in the growth of the nanowires or nanotubes, the structures can be synthesized on a device in a room temperature chamber without the device being subjected to overall heating. The method is localized and selective, and provides for a suspended microstructure to achieve the thermal requirement for vapor deposition synthesis, while the remainder of the chip or substrate remains at room temperature. Furthermore, by employing electric field assisted self-assembly techniques according to the present invention, it is not necessary to grow the nanotubes and nanowires and separately connect them to a device. Instead, the present invention provides for self-assembly of the nanotubes and nanowires on the devices themselves, thus providing for nano- to micro-integration. | 2010-07-22 |
20100181649 | POLYSILICON PILLAR BIPOLAR TRANSISTOR WITH SELF-ALIGNED MEMORY ELEMENT - Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter. | 2010-07-22 |
20100181650 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - With a general wafer level package process, in order to prevent corrosion of an aluminum type pad electrode in a scribe region in a plating process, the pad electrode is covered with a pad protective resin film at the same layer as an organic type protective film in a product region. However, this makes it impossible to perform the probe test on the pad electrode in the scribe region after rewiring formation. The present invention provides a method for manufacturing a semiconductor integrated circuit device of a wafer level package system. The organic type protective films in the chip regions and the scribe region are mutually combined to form an integral film pattern. In a pelletization step, the surface layer portion including the organic type protective film at the central part of the scribe region is first removed by laser grooving, to form a large-width groove. Then, a dicing processing of the central part in this groove results in separation into the chip regions. | 2010-07-22 |
20100181651 | SEALED SEMICONDUCTOR DEVICE - A sealed semiconductor device having reduced delamination of the sealing layer in high temperature, high humidity conditions is disclosed. The semiconductor device includes a substrate and a stack of device layers on the substrate sealed with a sealing layer. The upper surface of a street area of the substrate is oxidized so that the oxidized region extends under the sealing layer. The presence of the oxidized region of the upper surface of the substrate helps reduce the delamination, because the oxidized surface does not react with water to the same extent as a non-oxidized surface. The semiconductor devices remain sealed after dicing through the street area because the oxidized surface does not delaminate. | 2010-07-22 |
20100181652 | SYSTEMS AND METHODS FOR STICTION REDUCTION IN MEMS DEVICES - Systems and methods for reducing stiction between elements of a microelectromechanical systems (MEMS) device during anodic bonding. The MEMS device includes a substrate cover with an optional conductor on its interior surface and the cover is anchored to a first portion of a sensing element. The MEMS device further includes a second portion of the sensing element separated from the substrate cover with a space and an antistiction element disposed between the second portion and cover. The antistiction element can be formed of a material type with high electrostatic resistance, to prevent stiction between MEMS device elements during anodic bonding. | 2010-07-22 |
20100181653 | METHOD FOR RECYCLING A SUBSTRATE, LAMINATED WATER FABRICATING METHOD AND SUITABLE RECYCLED DONOR SUBSTRATE - The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal. The invention also relates to a laminated wafer fabricating method using the recycled substrate and to a recycled substrate in which the surface of a first region lies lower than the surface of the second region. | 2010-07-22 |
20100181654 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, INSULATING FILM FOR SEMICONDUCTOR DEVICE, AND MANUFACTURING APPARATUS OF THE SAME - An object to provide an insulating film for a semiconductor device, which has characteristics of low permittivity, a low leak current, and high mechanical strength, undergoes small time-dependent change of these characteristics, and has excellent water resistance, and to provide a manufacturing apparatus of the same, and a manufacturing method of the semiconductor device using the insulating film. The production process comprises a film forming step of supplying a mixed gas containing a carrier gas and a raw material gas, which is a gasified material having borazine skeletal molecules, into a chamber, causing the mixed gas to be in a plasma state, applying a bias to the substrate placed in the chamber, and carrying out gas-phase polymerization by using the borazine skeletal molecule as a fundamental unit so as to form the insulating film on the substrate; and a reaction promoting step of, after the film forming step, bringing the bias applied to the substrate to a different magnitude from the bias in the film forming step, supplying the mixed gas while gradually reducing only the raw material gas, which is the gasified material having the borazine skeletal molecules, treating the insulating film with a plasma mainly comprising the carrier gas. | 2010-07-22 |
20100181655 | ESTABLISHING A UNIFORMLY THIN DIELECTRIC LAYER ON GRAPHENE IN A SEMICONDUCTOR DEVICE WITHOUT AFFECTING THE PROPERTIES OF GRAPHENE - A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene. | 2010-07-22 |
20100181656 | Methods of eliminating pattern collapse on photoresist patterns - A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces. | 2010-07-22 |
20100181657 | NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE - A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided. | 2010-07-22 |