29th week of 2022 patent applcation highlights part 56 |
Patent application number | Title | Published |
20220231067 | STILTED PAD STRUCTURE - Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate. | 2022-07-21 |
20220231068 | ENABLING SENSOR TOP SIDE WIREBONDING - Provided herein include various examples of an apparatus, a sensor system and examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include forming bumps on a surface of one or more electrical contacts, where the one or more electrical contacts are accessible on an upper surface of a die, where the die is oriented on a substrate, and where the electrical contacts comprise bonding pads. The method may also include coupling one or more additional electrical contacts to the one or more electrical contacts, where the coupling comprises wire-bonding each additional electrical contact of the additional electrical contacts to one of the one or more electrical contacts accessible on the upper surface of the die, via a portion of the bumps on the surface of the one or more electrical contacts, thereby forming wire-bonded connections. | 2022-07-21 |
20220231069 | IMAGE-SENSING DEVICE - Image-sensing devices are provided. An image-sensing device includes a substrate, a first dielectric layer, an image sensor array, a plurality of nanowells and a plurality of electrodes. The first dielectric layer is formed on the substrate, and has a first side and a second side. The image sensor array is formed between the substrate and the second side of the first dielectric layer, and includes a plurality of image-sensing cells. The nanowells are formed in the first dielectric layer, and each of the nanowells has an opening on the first side of the first dielectric layer. Each of the electrodes extends from the second side to the first side of the first dielectric layer and is located between two adjacent nanowells. | 2022-07-21 |
20220231070 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD, AND ELECTRONIC APPLIANCE - There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps. | 2022-07-21 |
20220231071 | LIGHT DETECTION DEVICE - A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each including a light receiving region disposed at a first principal surface side of the semiconductor substrate, the avalanche photodiodes being arranged two-dimensionally at the semiconductor substrate, and a through-electrode electrically connected to a corresponding light receiving region. The through-electrode is provided in a through-hole penetrating through the semiconductor substrate in an area where the plurality of avalanche photodiodes are arranged two-dimensionally. At the first principal surface side of the semiconductor substrate, a groove surrounding the through-hole is formed between the through-hole and the light receiving region adjacent to the through-hole. A first distance between an edge of the groove and an edge of the through-hole surrounded by the groove is longer than a second distance between the edge of the groove and an edge of the light receiving region adjacent to the through-hole surrounded by the groove. | 2022-07-21 |
20220231072 | IMAGING APPARATUS - Provided is an imaging apparatus including an imaging unit having a plurality of pixels, the pixels each having: a conversion element converting incident light into photoelectrons; a floating diffusion layer electrically connected to the conversion element and converting the photoelectrons into a voltage signal; a differential amplifier circuit electrically connected to the floating diffusion layer, including an amplifier transistor to which a potential of the floating diffusion layer is input, and amplifying the potential of the floating diffusion layer; a feedback transistor electrically connected to the amplifier transistor and initializing the differential amplifier circuit; a clamp capacitance connected in series between the floating diffusion layer and the amplifier transistor; and a reset transistor connected in parallel between the floating diffusion layer and the clamp capacitance and initializing the potential of the floating diffusion layer. | 2022-07-21 |
20220231073 | IMAGE SENSOR AND ELECTRONIC APPARATUS INCLUDING THE SAME - This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR. | 2022-07-21 |
20220231074 | IMAGE SENSOR - An image sensor is provided. The image sensor includes a substrate, first photodiodes, second photodiodes, an interlayer, a light-guiding structure, and a micro-lens layer. The first photodiodes and the second photodiodes are alternately disposed in the substrate. The area of each of the first photodiodes is less than the area of each of the second photodiodes from a top view. The interlayer is disposed on the substrate. The light-guiding structure is disposed in the interlayer and over at least one of the first photodiodes or the second photodiodes. The refractive index of the light-guiding structure is greater than the refractive index of the interlayer. The micro-lens layer is disposed on the interlayer. | 2022-07-21 |
20220231075 | Image Sensor With Improved Quantum Efficiency Surface Structure - The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer. | 2022-07-21 |
20220231076 | OPTOELECTRONIC DEVICE COMPRISING TWO WIRE-SHAPED LIGHT-EMITTING DIODES EACH HAVING A LAYER THAT LIMITS THE LEAKAGE CURRENTS - An optoelectronic device includes first and second light-emitting diodes, each LED having: a first semiconductor portion, with a first type of doping, having a wire-like shape along an axis and having side surfaces parallel to this axis; an active portion arranged at least partially on a top end of the first portion; and a second semiconductor portion, with a second type of doping, arranged at least partially on all or part of the active portion. The optoelectronic device further includes an electrically resistive layer having an electrical resistance that is higher than that of the active portion, covering at least all or part of the side surfaces of the first portion and all or part of the surface of the top end of the first portion not covered by the active portion. The resistive layers of the first and second LEDs are separated from one another. | 2022-07-21 |
20220231077 | LED PACKAGE SET AND LED BULB INCLUDING SAME - A light emitting device including a first light source including a plurality of first light emitting structures and a first wavelength converter and configured to emit a first light, a second light source including a second light emitting structure and a second wavelength converter and configured to emit a second light, and a resistor member connected to the first light source and configured to distribute current to the first light emitting structures, in which a color temperature of the first light is configured to be higher than that of the second light, and the first light and second light are configured to have different light intensity. | 2022-07-21 |
20220231078 | REFRACTORY COMPOUND AND BINDER THEREFOR, METHOD FOR THE PRODUCTION AND USE THEREOF - The invention relates to an unshaped refractory compound, in particular, a casting compound, gunning compound and/or free-flowing compound, comprising a bond system which forms upon addition of water, and a dry micro-scale amorphous SiO | 2022-07-21 |
20220231079 | DISPLAY DEVICE AND TILED DISPLAY DEVICE INCLUDING THE SAME - A display device includes a first substrate including a display area comprising pixels, and a non-display area surrounding the display area, a thin film transistor layer disposed on the first substrate and comprising a thin film transistor, a second substrate disposed on the thin film transistor layer and facing the first substrate, a sealing part disposed between the first substrate and the second substrate in the non-display area, and bonding the first and second substrates, a metal line disposed in the non-display area on the thin film transistor layer and overlapping the sealing part, and an antistatic member comprising a support supported by the metal line, a first receiver protruding from a top portion of the support to an exterior of the sealing part, and a second receiver protruding from a bottom portion of the support toward the exterior of the sealing part and facing the first receiver. | 2022-07-21 |
20220231080 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a pixel disposed in a display area. The pixel includes a first electrode; a first insulating layer disposed on the first electrode, and including openings, each of the openings exposing different areas of the first electrode and defining respective cells; light emitting elements disposed in the respective cells, each of the light emitting elements including a first end electrically connected to the first electrode; and a second end protruding upward from the first insulating layer; and a second electrode disposed on the light emitting elements, and electrically connected to the second ends of each of the light emitting elements. | 2022-07-21 |
20220231081 | LIGHT EMITTING DIODE PRECURSOR INCLUDING A PASSIVATION LAYER - A light emitting diode (LED) precursor is provided. The LED precursor comprises a substrate ( | 2022-07-21 |
20220231082 | METHOD OF FABRICATING LED MODULE - An LED module includes light emission windows; LED cells corresponding to the light emission windows, the LED cells each including a lower and upper light emitting structure, the lower light emitting structure having an upper surface with first and second regions and having a first conductivity-type semiconductor layer, the upper light emitting structure being on the first region of the lower light emitting structure and having a second conductivity-type semiconductor layer, the LED cells including an active layer between the first and second conductivity-type semiconductor layers; a protective insulating film on a side surface of the lower light emitting structure and on the second region; a light blocking film on the protective insulating film, between the LED cells; a gap-fill insulating film on the protective insulating film between the LED cells and contacting a side surface of the upper light emitting structure; a first electrode; and a second electrode. | 2022-07-21 |
20220231083 | NON-VOLATILE MEMORY DEVICE HAVING PN DIODE - A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit. | 2022-07-21 |
20220231084 | MAGNETIC DOMAIN WALL MOVING ELEMENT AND MAGNETIC RECORDING ARRAY - A magnetic domain wall moving element includes a magnetic recording layer which extends in a first direction and includes a ferromagnetic material, and a first conductive layer and a second conductive layer which are separately connected to the magnetic recording layer, the first conductive layer includes a ferromagnetic first layer in contact with the magnetic recording layer, the first layer includes a mixing layer at an interface with the magnetic recording layer, a ferromagnetic material and a dissimilar metal are mixed in the mixing layer, and the dissimilar metal is a metal different from each of the ferromagnetic material that mainly constitutes the first layer and the ferromagnetic material that mainly constitutes the magnetic recording layer. | 2022-07-21 |
20220231085 | IMAGING ELEMENT, STACKED IMAGING ELEMENT AND SOLID-STATE IMAGING DEVICE, AND METHOD OF MANUFACTURING IMAGING ELEMENT - An imaging element of the present disclosure includes a photoelectric conversion section including a first electrode | 2022-07-21 |
20220231086 | DETECTION SUBSTRATE AND FLAT-PANEL DETECTOR - A detection substrate and a flat-panel detector, and relates to the technical field of photoelectric detection. The detection substrate can improve radiation resistance and prolong a service life without increasing the thickness of a scintillator layer. The detection substrate includes a plurality of detection pixel units arranged in an array. Each of the detection pixel units includes: a transistor, a photoelectric conversion section, and a scintillator layer, with the photoelectric conversion section disposed between the transistor and the scintillator layer, the photoelectric conversion section includes a radiation sensitive layer and a photosensitive unit, which are laminated in arrangement; the radiation sensitive layer is configured to absorb rays and convert the rays into carriers; and the photosensitive unit is configured to at least absorb visible light and convert the visible light into carriers. The present disclosure is applicable to the production of the detection substrates. | 2022-07-21 |
20220231087 | DISPLAY APPARATUS - A display apparatus includes a first substrate; a bank on the first substrate, the bank including first openings, second openings, third openings, and auxiliary openings, wherein a thickness of a partition wall defining the first openings, the second openings, and the third openings is greater than a thickness of an auxiliary partition wall arranged in the auxiliary opening; a first quantum dot layer in the first openings; and a second quantum dot layer in the second openings. | 2022-07-21 |
20220231088 | METHOD OF INTEGRATING FUNCTIONAL TUNING MATERIALS WITH MICRO DEVICES AND STRUCTURES THEREOF - The disclosure is related to creating different functional micro devices by integrating functional tuning materials and creating an encapsulation capsule to protect these materials. Various embodiments of the present disclosure also related to improve light extraction efficiencies of micro devices by mounting micro devices at a proximity of a corner of a pixel active area and arranging QD films with optical layers in a micro device structure. | 2022-07-21 |
20220231089 | DISPLAY DEVICE AND PHOTOMASK - A display device includes a substrate, a pixel electrode disposed on the substrate, a bank layer which is disposed on the pixel electrode and in which a pixel opening overlapping the pixel electrode is defined, an encapsulation layer disposed on the pixel electrode and the bank layer, a sensing electrode disposed on the encapsulation layer, a first insulating layer which is disposed on the sensing electrode and in which an opening overlapping the pixel opening is defined, and a second insulating layer which is disposed on the first insulating layer and has a higher refractive index than a refractive index of the first insulating layer, where a side inclination angle of the first insulating layer in the opening of the first insulating layer is different depending on a position of the opening of the first insulating layer. | 2022-07-21 |
20220231090 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a display member and a touch member disposed on the display member. The touch member includes a first touch insulating disposed on the display member, a first touch conductive layer disposed on the first touch insulating layer and including a touch bridge electrode, a second touch insulating layer disposed on the first touch conductive layer, including an organic material, and including a first contact hole penetrating the second touch insulating layer in a thickness direction, a second touch conductive layer disposed on the second touch insulating layer and including a first lower sensing line overlapping the second touch bridge electrode, and a third touch conductive layer disposed on the second touch conductive layer and including a first upper sensing line overlapping the first lower sensing line. A width of the first upper sensing line is greater than a width of the first lower sensing line. | 2022-07-21 |
20220231091 | Display Device with Integrated Touch Screen - Disclosed is a display device with integrated touch screen, which prevents external light from being reflected by touch electrodes without a polarizer. The display device includes an organic light emitting device layer disposed on a substrate, a plurality of color filters disposed on the organic light emitting device layer, a plurality of first touch electrodes and a plurality of second touch electrodes disposed on the plurality of color filters to overlap a boundary portion between the plurality of color filters, and a black matrix disposed on the plurality of first touch electrodes and the plurality of second touch electrodes to overlap the plurality of first touch electrodes and the plurality of second touch electrodes. | 2022-07-21 |
20220231092 | DISPLAY DEVICE - A display device includes a substrate including a display area and a pad area, a pixel structure disposed on the display area, a pixel insulating layer disposed on the pad area and having a first opening, and a pad electrode structure including a signal electrode disposed in the first opening, a connection electrode disposed on the signal electrode, and a pad electrode disposed on the connection electrode. An upper surface and a side surface of the signal electrode come into direct-contact with a lower surface of the connection electrode. An upper surface and a side surface of the connection electrode come into direct-contact with a lower surface of the pad electrode. | 2022-07-21 |
20220231093 | DISPLAY PANEL AND DISPLAY APPARATUS - A display panel and a display apparatus. The display panel includes a first display area, a second display area, and a transitional display area located between the first display area and the second display area. A light transmittance of the first display area is greater than that of the second display area. The display panel includes: a plurality of first sub-pixels arranged in the first display area; a plurality of second sub-pixels arranged in the transitional display area; a plurality of first pixel driving circuits arranged in the transitional display area and configured to drive the first sub-pixels and the second sub-pixels; a plurality of blocks arranged in the first display area and corresponding to at least a part of the plurality of first sub-pixels. | 2022-07-21 |
20220231094 | Transparent OLED Device - Display panels and other devices are provided that include emissive devices disposed on two carrier substrates and arranged to achieve a desired emission profile and transparency. Each carrier substrate includes OLED devices of a selected color which may be used to provide one- or two-sided imaging based on emission from devices on each carrier substrate. | 2022-07-21 |
20220231095 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is disclosed. The OLED display includes a first stack having a first emission layer and a first layer. The first emission layer emits red light, green light, or blue light. The OLED display includes a second stack having a second emission layer and a second layer. The second stack emits light of a different angular spectral distribution as that emitted by the first stack. Further, a thickness of the second layer is different from a thickness of the first layer such that light emitted by the first emission layer resonates within the first stack at a first degree and light emitted by the second emission layer resonates within the second stack at a second degree, the first degree being greater than the second degree. | 2022-07-21 |
20220231096 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines. | 2022-07-21 |
20220231097 | DISPLAY SCREEN, METHOD FOR MANUFACTURING SAME AND DISPLAY TERMINAL - Disclosed are a display screen, a method for manufacturing the same, and a display terminal. The display screen includes a display region and a non-display region surrounding the display region; wherein the display region includes a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element and includes at least one metal layer; and the non-display region includes at least one antenna disposed in the same layer as one of the at least one metal layer. | 2022-07-21 |
20220231098 | DISPLAY DEVICE - A display device includes a display panel; and a light path control member disposed on the display panel, wherein the light path control member includes: a housing including a plurality of partition walls and a channel defined between two adjacent partition walls among the plurality of partition walls; a light absorbing solution configured to block transmission of light; and a first fluid transfer portion configured to control flowing of the light absorbing solution into and out of the channel. | 2022-07-21 |
20220231099 | DISPLAY DEVICE AND METHOD OF PROVIDING THE SAME - A display device includes a pixel electrode including silver, a pixel-defining film on the pixel electrode and exposing the pixel electrode, a barrier layer on the pixel electrode and the pixel-defining film and including a low-resistance area and a high-resistance area which has a higher resistance than the low-resistance area, an emission layer on the barrier layer, and a common electrode on the emission layer. The low-resistance area of the barrier layer overlaps with the pixel electrode, and the high-resistance area of the barrier layer overlaps with the pixel-defining film. | 2022-07-21 |
20220231100 | DISPLAY DEVICE - According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface. | 2022-07-21 |
20220231101 | Display substrate, manufacturing method thereof, and display device - Embodiments of the present application provide a display substrate comprising a plurality of first banks distributed in a first direction and a plurality of second banks distributed in a second direction. Two adjacent first banks define a group of sub-pixel units of the display substrate, and two adjacent second banks define one sub-pixel unit. The first bank has a height greater than a height of the second bank. Embodiments of the present application also disclose a manufacturing method of a display substrate and a display device. | 2022-07-21 |
20220231102 | DISPLAY DEVICE - A display device includes a lower substrate, a planarization layer, a first light emission structure, and a second light emission structure. The lower substrate includes a first region and a second region. The planarization layer is disposed on the lower substrate, and has a first thickness in the first region and a second thickness, which is less than the first thickness, in the second region. The first light emission structure is provided in the first region and arranged on the planarization layer, and emits a first color of light. The second light emission structure is provided in the second region and arranged on the planarization layer, and emits the first color of light. | 2022-07-21 |
20220231103 | DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - A display substrate is provided. The display substrate includes a display region and a non-display region surrounding the display region. A portion, in the non-display region, of the display substrate includes: a base, a first material layer disposed on a side of the base, and a second material layer disposed on a side of the first material layer away from the base. The first material layer includes a first portion and a plurality of second portions, a thickness of the first portion is less than a thickness of the second portion, a first portion is disposed between any two adjacent second portions, and the second material layer covers the first material layer. | 2022-07-21 |
20220231104 | STRETCHABLE DISPLAY DEVICE - A stretchable display device capable of correcting resolution depending on a stretching degree is disclosed. The stretchable display device includes a stretchable substrate, first light emitting pixels including first light emitting elements arranged spaced apart from each other on the stretchable substrate, deformation switch parts arranged between the first light emitting pixels on the stretchable substrate and stretched and deformed according to stretch of the stretchable substrate, and second light emitting pixels including second light emitting elements arranged between the first light emitting pixels on the stretchable substrate. The second light emitting pixels are controlled to emit light depending on physical deformation of the deformation switch parts. | 2022-07-21 |
20220231105 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY PANEL, AND DISPLAY DEVICE - An array substrate is configured to carry a plurality of light emitting units with different light emitting colors. The array substrate includes a plurality of pixel driving circuits, a first voltage input line and a second voltage input line. The plurality of pixel driving circuits include at least one first driving circuit and at least one second driving circuit. The first voltage input line is coupled to the at least one first driving circuit, and is configured to transmit a first voltage to the at least one first driving circuit. The second voltage input line is coupled to the at least one second driving circuit, and is configured to transmit a second voltage to the at least one second driving circuit. The first voltage is different from the second voltage. | 2022-07-21 |
20220231106 | DISPLAY PANELS AND DISPLAY DEVICES - A display panel includes a switching transistor and a light-emitting transistor. The switching transistor includes a first gate electrode, a first source electrode, a first active layer, and a first drain electrode. The light-emitting transistor includes a second gate electrode, a second source electrode, a second active layer, a light-emitting layer, and a second drain electrode. The second gate electrode is the first drain electrode of the switching transistor. The switching transistor and the light-emitting transistor may be on a substrate. The switching transistor, the second source electrode, the second active layer, the light-emitting layer, and the second drain electrode are stacked in a direction perpendicular to the surface of the substrate. | 2022-07-21 |
20220231107 | LIGHT EMITTING DISPLAY DEVICE - A light emitting display device including: a first pixel including a first lower storage electrode, a first gate electrode of a first driving transistor, and a first upper storage electrode; and a second pixel provided near the first pixel, and including a second lower storage electrode, a second gate electrode of a second driving transistor, and a second upper storage electrode. In a plan view, the first gate electrode and the second gate electrode have first sides facing each other, the first side of the first gate electrode is positioned inside a border of the first lower storage electrode or the first upper storage electrode in a plan view, and the first side of the second gate electrode is positioned inside a border of the second lower storage electrode or the second upper storage electrode in a plan view. | 2022-07-21 |
20220231108 | DISPLAY PANEL - The present invention relates to a display panel. In an aspect, a source drain electrode layer in a bending region is provided with grooves at positions corresponding to metal traces and the grooves are filled with a conductive material. By using the conductive material to connect to the metal traces, it does not have to consider stress equilibrium for the metal traces in the bending region, thereby reducing a radius of curvature of the bending and a bezel width, increasing a screen-to-body ratio and eventually bringing the customers a better visual experience. In another aspect, a pad plate is provided and the pad plate is provided with conductive bridges arranged at intervals at positions corresponding to the grooves. It can be better connected to the metal traces by the conductive bridges, preventing the conductive material from unable to connect to the metal traces since the metal traces is too low from perspective of thickness. | 2022-07-21 |
20220231109 | DISPLAYING SUBSTRATE AND DISPLAYING DEVICE - A displaying substrate and a displaying device. The displaying substrate comprises a flexible base plate; a first auxiliary electrode arranged on one side of the flexible base plate, the first auxiliary electrode being connected with a first power cord; a pixel unit arranged on a side of the flexible base plate away from a first metal layer, the pixel unit comprising: thin-film transistors arranged on the side of the flexible base plate away from the first metal layer, an insulation layer and a second auxiliary electrode, the second auxiliary electrode being connected with a second power cord, wherein the plurality of thin-film transistors comprise a drive transistor, the drive transistor has a source connected with the first auxiliary electrode and a drain connected with a first electrode of a light emitting device, a second electrode of the light emitting device is connected with the second auxiliary electrode. | 2022-07-21 |
20220231110 | DISPLAY DEVICE - A display device includes a display panel including a display panel pad and a dam structure, a driving film attached to the display panel and including a driving film board, a connection lead disposed on a rear surface of the driving film board and facing the display panel pad, a first signal line electrically connected to the connection lead, and a protection member overlapping at least one of the connection lead and the first signal line, and a conductive adhesive member disposed between the display panel and the driving film and electrically connecting the display panel pad with the connection lead. The display panel pad and the dam structure are disposed on an upper surface of the display panel, the dam structure is disposed more to an outside of the display panel than the display panel pad, and the protection member of the driving film overlaps the dam structure. | 2022-07-21 |
20220231111 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING A POWER SUPPLY WIRE - An organic light emitting diode display includes a lower substrate, a sub-pixel structure, an upper substrate, a sealant, and a first power supply wire. The lower substrate has a display area, a peripheral area, and a pad area. The sub-pixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the sub-pixel structure. The sealant is disposed in the peripheral area between the lower substrate and the upper substrate. The first power supply wire is disposed between the lower substrate and the sealant, and overlaps the lower substrate and the sealant. The first power supply wire includes a first protrusion protruding in a first direction that is a direction from the pad area to the display area in the first peripheral area. | 2022-07-21 |
20220231112 | FLEXIBLE ELECTROLUMINESCENT DISPLAY DEVICE - An electroluminescent display device includes a substrate including an active area, and bezel area outside the active area and including a bending area, a first organic insulation layer (OIL) in the active area, covering a first signal line extending from the active area to the bezel area, a second OIL in the bending area, the second OIL being in a same layer as the first organic insulation film, first and second touch electrodes crossing over each other and sealing the active area on an encapsulation layer above the first OIL with a third OIL therebetween, a first signal line link pattern connected to the first signal line, and on the second OIL in the bending area, and second and third signal lines respectively connected to the first and second touch electrodes, and on the second OIL in parallel with the first signal line link pattern. | 2022-07-21 |
20220231113 | DISPLAY PANEL AND DISPLAY APPARATUS - The display panel includes a first display area, and the display panel includes: a substrate; a first light-emitting element disposed on the substrate and disposed in the first display area; a first driving transistor disposed between the substrate and the first light-emitting element, the first driving transistor being electrically connected with the first light-emitting element and including a first gate; a first conductive line unit electrically connected with the first gate and disposed on a side of the first gate away from the substrate; and a first power supply structure electrically connected with a first electrode of the first light-emitting element and disposed between the first conductive line unit and the first electrode of the first light-emitting element, an orthographic projection of the first power supply structure on the substrate covering an orthographic projection of the first conductive line unit on the substrate. | 2022-07-21 |
20220231114 | DISPLAY DEVICE - An OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring | 2022-07-21 |
20220231115 | PASSIVE COMPONENTS WITH IMPROVED CHARACTERISTICS - Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery. | 2022-07-21 |
20220231116 | INDUCTIVE DEVICE - An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device. | 2022-07-21 |
20220231117 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film. | 2022-07-21 |
20220231118 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an upper structure in which a bottom electrode, a dielectric layer, a top electrode and a plasma protection layer are sequentially stacked on a lower structure, exposing the upper structure to a plasma treatment, and exposing the plasma-treated upper structure and the lower structure to a hydrogen passivation process. | 2022-07-21 |
20220231119 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a substrate, and forming a first isolating layer, a first stabilizing layer, a second isolating layer and a second stabilizing layer, which are sequentially stacked onto one another, on the substrate; forming a through hole penetrating through the first isolating layer, the first stabilizing layer, the second isolating layer and the second stabilizing layer, and forming a lower electrode on a side wall and a bottom portion of the through hole; removing a portion of a thickness of the second stabilizing layer to expose a portion of the lower electrode; forming a mask layer on a side wall of the exposed lower electrode; and etching the second stabilizing layer by using the mask layer as a mask to form a first opening. | 2022-07-21 |
20220231120 | TRANSISTOR CELL INCLUDING AN IMPLANTED EXPANSION REGION - A transistor cell including a semiconductor substrate, which has a front side and a rear side, the front side being situated opposite the rear side. An epitaxial layer is situated on the front side. Channel regions are situated on the epitaxial layer. Source regions are situated on the channel regions. A trench and field shielding regions extending from the front side of the semiconductor substrate into the epitaxial layer, the field shielding regions each being situated laterally spaced apart from the trench and the trench having a shallower depth than the field shielding regions. An implanted expansion region having a particular thickness is situated below the trench. | 2022-07-21 |
20220231121 | ISOLATION REGIONS IN INTEGRATED CIRCUIT STRUCTURES - Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region. | 2022-07-21 |
20220231122 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate having a trench therein, the trench including a corner between a bottom and a sidewall, the corner protruding in a direction away from an opening of the trench; a first isolation layer, covering a surface of the sidewall, a surface of the corner and a surface of the bottom; a second isolation layer, covering a surface of the first isolation layer, a hardness of a material of the second isolation layer being greater than that of the first isolation layer; and a stress adjustment layer, located in the first isolation layer between the corner and the second isolation layer, a hardness of the stress adjustment layer being greater than that of the first isolation layer. | 2022-07-21 |
20220231123 | STACK, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING STACK - A stack includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces. | 2022-07-21 |
20220231124 | Semiconductor Device and Method - A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal. | 2022-07-21 |
20220231125 | Power Semiconductor Device Having a Control Cell for Controlling a Load Current - A power semiconductor device includes a control cell for controlling a load current and electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including a contact region having dopants of the first or second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to control a conduction channel in the channel region; and a contact plug including at least one of a doped semiconductive material or metal, and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which horizontally projects beyond lateral boundaries of the mesa. | 2022-07-21 |
20220231126 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region. | 2022-07-21 |
20220231127 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate. | 2022-07-21 |
20220231128 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first semiconductor type, a first semiconductor layer of the first semiconductor type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first semiconductor type, trenches, a gate insulating film, and gate electrodes. The silicon carbide semiconductor device has a minimum value of a subthreshold slope factor (subthreshold swing) in a subthreshold region in a range from 0.24V/dec. to 0.3V/dec. | 2022-07-21 |
20220231129 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device, includes the steps of preparing a silicon carbide substrate, depositing an insulating film on one principal surface of the silicon carbide substrate, forming a contact hole in the insulating film, and exposing the one principal surface at a bottom surface of the contact hole, forming a Si film on the bottom surface and a side surface of the contact hole, and a top surface of the insulating film, removing the Si film on the bottom surface of the contact hole, and exposing the one principal surface, depositing a Ni film on the bottom surface of the contact hole, and the Si film, and performing a heat treatment after depositing the Ni film, wherein the heat treatment forms a first alloy layer, which becomes an ohmic electrode, at the bottom surface of the contact hole by Si included in the silicon carbide substrate and the Ni film, and forms a second alloy layer at the top surface of the insulating film by the Si film and the Ni film. | 2022-07-21 |
20220231130 | Hetero-Junction Bipolar Transistor and Method for Manufacturing the Same - A first collector layer is composed of n-type InP (n-InP) doped with Si at a low concentration. A second collector layer is composed of non-doped InGaAs. A base layer is composed of p-type GaAsSb (p | 2022-07-21 |
20220231131 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device with low power consumption is provided. In a cascode circuit including a first transistor provided on a low power supply potential side and a second transistor provided on a high power supply potential side, a source or a drain of a third transistor and a capacitor are connected to a gate of the second transistor. A gate of the first transistor is electrically connected to a back gate of the second transistor. An OS transistor is used as the third transistor. | 2022-07-21 |
20220231132 | METHOD FOR MANUFACTURING SELF-ALIGNED EXCHANGE GATES AND ASSOCIATED SEMICONDUCTING DEVICE - A method manufactures exchange gates from a starting structure including a substrate and, disposed on the substrate, a plurality of gate stacks, each gate stack including, a layer of a conductive or semiconductor material and a layer of a hard mask. | 2022-07-21 |
20220231133 | SHIELDING STRUCTURE FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES - A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal. | 2022-07-21 |
20220231134 | SELECTIVE SINGLE DIFFUSION/ELECTRICAL BARRIER - Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity. | 2022-07-21 |
20220231135 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first to third electrodes, first and second conductive members, a semiconductor member, and a first insulating member. The first conductive member is electrically connected with the second electrode or is electrically connectable with the second electrode. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first to fourth partial regions. The third partial region is between the first and second partial regions. The second semiconductor region is between the third partial region and the third semiconductor region. The fourth partial region is between the third partial region and the second semiconductor region. At least a portion of the second semiconductor region is between the second conductive member and the third electrode. The second conductive member is electrically insulated from the second and third electrodes. The first insulating member includes first to third insulating regions. | 2022-07-21 |
20220231136 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE - A method includes: forming a trench in a first major surface of a semiconductor substrate, the trench having a base and a side wall extending from the base to the first major surface; forming a first insulating layer on the trench base and side wall; forming a sacrificial layer on the first insulating layer on the trench side wall; forming a second insulation layer on the sacrificial layer; inserting conductive material into the trench that at least partially covers the second insulation layer; selectively removing portions of the second insulation layer uncovered by the conductive material; selectively removing the sacrificial layer to form a recess that is positioned adjacent the conductive material in the trench and that is bounded by the first insulation layer and the second insulating layer; and forming a third insulating layer in the trench that caps the recess to form an enclosed cavity in the trench. | 2022-07-21 |
20220231137 | METAL CAP FOR CONTACT RESISTANCE REDUCTION - A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer. | 2022-07-21 |
20220231138 | Recessed Contact Structures and Methods - An exemplary method of forming a semiconductor device includes forming, in a substrate, an active region protruding vertically from a major surface of the substrate, the active region including a semiconductor source-drain (S/D) region and a first 3-D channel structure, the S/D region physically contacting the first 3-D channel structure, and forming an opening extending into the S/D region, the opening having a depth greater than half of a height of the first 3-D channel structure; and forming a metallic plug in the opening, the metallic plug making electrical contact with the S/D region. | 2022-07-21 |
20220231139 | Semiconductor Devices and Methods - Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width. | 2022-07-21 |
20220231140 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE INCLUDING A WORD LINE STRUCTURE HAVING A PROTRUDING PORTION - A three-dimensional semiconductor device is provided. The three-dimensional device may include substrate; a common electrode layer on the substrate; a word line stack disposed on the common electrode layer, the word line stack having interlayer insulating layers and word lines structures alternately stacked and; and a vertical channel pillar penetrating the word line stack, the vertical channel pillar being electrically connected to the common electrode layer. Each of the word line structures includes a body portion having a first vertical width and an extension portion having a second vertical width greater than the first vertical width. The extension portion abuts the vertical channel pillar. | 2022-07-21 |
20220231141 | HIGH DIELECTRIC CONSTANT METAL GATE MOS TRANSISTOR - A high dielectric constant metal gate MOS transistor comprises a gate dielectric layer, a metal work function layer, a top capping layer, and a metal conductive material layer. The gate dielectric layer comprises a high dielectric constant layer; the top capping layer comprises a material that prevents metal ions of the metal conductive material layer from diffusing downwards into the metal work function layer. The top capping layer has a non-crystalline structure, which reduces or eliminates oxygen diffusion paths, thereby no oxidation of the surface of the metal work function layer occurs. The work function offset from this oxidation is eliminated, thereby preventing a drift of the threshold voltage of the MOS transistor. | 2022-07-21 |
20220231142 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A silicon carbide semiconductor device includes a silicon carbide substrate having a first principal surface provided with a gate trench, and a second principal surface located on an opposite side from the first principal surface, the gate trench having an inner surface connecting to the first principal surface, a gate insulator provided on the inner surface of the gate trench, and a gate electrode provided on the gate insulator, wherein the gate electrode includes a base portion in contact with the gate insulator, and filling a portion of the gate trench, and a tapered portion provided on the base portion, having a width which continuously decreases in a direction further away from the base portion, in a cross sectional view viewed from a direction perpendicular to a longitudinal direction of the gate trench, and wherein a boundary between the base portion and the tapered portion is located at a position closer to a bottom of the gate trench than an upper end of the gate trench. | 2022-07-21 |
20220231143 | GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion. | 2022-07-21 |
20220231144 | SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND TRANSISTOR - A semiconductor structure, a method for manufacturing the semiconductor structure, and a transistor. A doped structure is provided, where the doped structure includes a dopant. A surface of the doped structure is oxidized to form the oxide film. In such case, the dopant at an interface between the oxide film and the doped structure may be redistributed, and thereby a segregated-dopant layer is formed inside or at a surface of the doped structure under the oxide film. A concentration of the dopant is higher in the segregated-dopant layer than in other regions of the doped structure. After the oxide film is removed, the doped structure with a high surface doping concentration can be obtained without an additional doping process. Therefore, after a conducting structure is formed on the segregated-dopant layer, a low contact resistance between the conducting structure and the doped structure is obtained, and a device performance is improved. | 2022-07-21 |
20220231145 | MEMORY CHIP STRUCTURE HAVING GAA TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND WORK FUNCTIONS FOR IMPROVING PERFORMANCES IN MULTIPLE APPLICATIONS - An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value. | 2022-07-21 |
20220231146 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, TRANSISTOR, AND MEMORY - A manufacturing method of the semiconductor structure includes: providing a semiconductor substrate, and forming a gate region and a source-drain region on the semiconductor substrate; forming an insulating dielectric layer which covers both of the gate region and the source-drain region; patterning the insulating dielectric layer on the source-drain region to form a first contact hole exposing the source-drain region; forming a metal silicide at the bottom of the first contact hole; patterning the insulating dielectric layer on the gate region to form a second contact hole of which an orthographic projection on the semiconductor substrate is located on the gate region; and forming a filling layer in the first contact hole and the second contact hole. | 2022-07-21 |
20220231147 | SEMICONDUCTOR DEVICE AND ASSOCIATED MANUFACTURING METHOD - A semiconductor device includes a substrate; a plurality of gate stacks situated horizontally following one another on the substrate, each gate stack including a layer of a dielectric material in contact with the substrate and a layer of a conductive material on the layer of dielectric material; a source and a drain situated on the substrate on either side of the plurality of gate stacks; a plurality of first spacers made of a first dielectric material, called secondary spacers, having a first width, called width of the secondary spacers, the source and the drain being separated from the closest gate stack by a secondary spacer; at least one main spacer made of a second dielectric material, a main spacer being situated between each gate stack, the width of the main spacer(s) being greater than the width of the secondary spacers. | 2022-07-21 |
20220231148 | METHOD FOR MANUFACTURING A POWER TRANSISTOR, AND POWER TRANSISTOR - A method for manufacturing a power transistor. The method includes: applying a first epitaxial layer including a first doping concentration to a front side of a semiconductor substrate, producing an expansion layer, which is situated inside the first epitaxial layer, producing various implanted areas starting from the front side of the semiconductor substrate, producing a trench structure starting from the front side of the semiconductor substrate, producing first isolation areas in the surroundings of the trench structure, producing transistor heads, and applying metal layers. | 2022-07-21 |
20220231149 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device comprises forming an oxide semiconductor layer, forming a gate insulating layer in contact with the oxide semiconductor layer and covering the oxide semiconductor layer, and forming a gate electrode on the gate insulating layer so as to overlap the oxide semiconductor layer, and injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode, wherein a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E+16 [atoms/cm | 2022-07-21 |
20220231150 | SEMICONDUCTOR DEVICE - A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface. | 2022-07-21 |
20220231151 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES AND METHODS FOR FABRICATING ELECTROSTATIC DISCHARGE PROTECTION DEVICES - An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type. | 2022-07-21 |
20220231152 | Tiled Lateral Thyristor - A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles. | 2022-07-21 |
20220231153 | CMOS Fabrication Methods for Back-Gate Transistor - A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the etch stop layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal. | 2022-07-21 |
20220231154 | ASYMMETRICALLY ANGLED GATE STRUCTURE AND METHOD FOR MAKING SAME - A high electron mobility transistor (HEMT) includes a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate has a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric. Methods for making the HEMT are also disclosed. | 2022-07-21 |
20220231155 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, first and second insulating members. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes a first insulating portion. The first insulating portion is between the third and first electrode portions. The second insulating member includes first and second insulating regions. The first insulating region is between the first electrode and the first electrode portion. The second insulating region is between the first insulating region and the first electrode portion. | 2022-07-21 |
20220231156 | DRAIN CONTACT EXTENSION LAYOUT FOR HARD SWITCHING ROBUSTNESS - A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of III-N semiconductor material. The GaN FET includes both source contacts and drain contacts to a channel layer of III-N semiconductor material. Source contacts to the source region are placed farther from the gate electrode fingertip than drain contacts to the drain region. | 2022-07-21 |
20220231157 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURE - The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process. | 2022-07-21 |
20220231158 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure. | 2022-07-21 |
20220231159 | SEMICONDUCTOR DEVICE INCLUDING ACTIVE REGION AND GATE STRUCTURE - A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions. | 2022-07-21 |
20220231160 | SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer including a super junction layer in which an n-type pillar layer and a p-type pillar layer are alternately disposed and a p-type withstand voltage holding structure formed on an upper layer part of the semiconductor layer to surround an active region. At least one withstand voltage holding structure overlaps with the super junction layer in a plan view. At least one withstand voltage holding structure overlapping with the super junction layer in a plan view has a gap which is an intermittent part of the withstand voltage holding structure. | 2022-07-21 |
20220231161 | TERMINATION FOR TRENCH FIELD PLATE POWER MOSFET - A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region. | 2022-07-21 |
20220231162 | TRENCH-GATE SEMICONDUCTOR DEVICE - A trench-gate semiconductor device and a manufacturing method thereof is provided. The device is provided with each unit cell including a first trench, and a second trench extending from a bottom of the first trench. The device includes a gate oxide layer arranged on a first side wall of the first trench, a second oxide layer arranged on a second side wall and bottom of the second trench, a first polysilicon region arranged inside the first trench, separated from the first side wall by the gate oxide layer, forming a gate of the unit cell. The device includes a second polysilicon region arranged inside the second trench, separated from the second side wall and bottom of the second trench by the second oxide layer, forming a buried source of the unit cell, and a third oxide layer arranged in between the first polysilicon region and the second polysilicon region. | 2022-07-21 |
20220231163 | Semiconductor Transistor Device and Method of Manufacturing the Same - A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material. | 2022-07-21 |
20220231164 | SWITCHING ELEMENT - A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region. | 2022-07-21 |
20220231165 | High-Voltage Semiconductor Devices - High-voltage semiconductor devices are disclosed, each having gate, source and drain electrodes. A deep well layer is formed on a substrate and has a surface, where the substrate and the deep well layer are of first-type and second-type conductivities, respectively. A field isolation layer on the surface isolates a drain active region from a source active region. The source electrode contacts the source active region on the surface to form an ohmic contact. The drain electrode contacts the drain active region on the surface. A first well layer of the first-type conductivity is formed on the surface and between the ohmic contact and the drain active region, and at least a portion of the first well layer is under the field isolation layer. A bottom layer of the first-type conductivity is formed at a bottom of the deep well layer. The gate electrode is on the field isolation layer. | 2022-07-21 |
20220231166 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a deep n-well, a field oxide, a gate structure, a p-type doped region, a source region, and a drain region. The deep n-well is in the semiconductor substrate. The field oxide is partially embedded in the deep n-well and having a tip corner in a position substantially level with a top surface of the semiconductor substrate. The gate structure is on the field oxide and laterally extends past the tip corner of the field oxide. The p-type doped region is in the deep n-well and is interfaced with the tip corner of the field oxide. The source region and a drain region are laterally separated at least in part by the p-type doped region and the field oxide. | 2022-07-21 |