29th week of 2022 patent applcation highlights part 54 |
Patent application number | Title | Published |
20220230867 | MASS FILTER HAVING REDUCED CONTAMINATION - A method of mass filtering ions is disclosed comprising: providing a first, AC-only, mass filter ( | 2022-07-21 |
20220230868 | PLASMA LAMP AS A RADIATION SOURCE IN AN APPARATUS FOR ARTIFICIAL WEATHERING - An apparatus for artificial weathering or lightfastness testing of samples or for simulating solar radiation, the apparatus comprises a weathering chamber, an electrodeless lamp provided in the weathering chamber and comprising a bulb filled with a composition that emits light when in a plasma state, and a radio frequency source being arranged so that it radiate a radio frequency field into the bulb to generate a luminous plasma for emitting a radiation comprising spectral emission characteristics similar to natural solar radiation. | 2022-07-21 |
20220230869 | TAIKO WAFER RING CUT PROCESS METHOD - A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame. | 2022-07-21 |
20220230870 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes forming a film in a concave portion provided on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming an adsorption inhibition layer by supplying an adsorption inhibitor, which inhibits adsorption of a precursor, to the substrate and adsorbing the adsorption inhibitor on adsorption sites of an upper portion in the concave portion; (b) forming a first layer by supplying the precursor to the substrate and adsorbing the precursor on adsorption sites existing in the concave portion in which the adsorption inhibition layer is formed; and (c) modifying the adsorption inhibition layer and the first layer into a second layer by supplying a first reactant, which chemically reacts with both the adsorption inhibition layer and the first layer, to the substrate. | 2022-07-21 |
20220230871 | Low-k Feature Formation Processes and Structures Formed Thereby - Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features. | 2022-07-21 |
20220230872 | WAFER-CLEANING APPARATUS INCLUDING A WINDOW PROTECTOR AND A METHOD OF CLEANING A WAFER - A wafer-cleaning apparatus includes an inner pin that supports a wafer. The wafer-cleaning apparatus further includes a nozzle disposed above the inner pin, a light source disposed under the inner pin, a window disposed between the light source and the wafer, and a window protector disposed between the wafer and the window. The nozzle supplies a chemical liquid to the wafer and the inner pin distributes a portion of the chemical liquid on an upper surface of the wafer by rotating the wafer. The window protector receives a portion of the chemical liquid that flows out of the wafer and the light source supplies the light to the wafer through the window protector and the window. | 2022-07-21 |
20220230873 | CLEANING METHOD AND CLEANING DEVICE FOR WAFER EDGE - A cleaning method includes: providing a wafer, the wafer having a wafer edge; and controlling the wafer in a rotation phase to rotate the wafer, and providing a cleaning solution for the wafer edge in the rotation phase. The rotation phase includes a first rotation phase and/or a second rotation phase. A rotation speed of the wafer increases from a first speed to a second speed during the first rotation phase, and the rotation speed of the wafer decreases from the second speed to the first speed during the second rotation phase. The second speed is greater than the first speed. | 2022-07-21 |
20220230874 | CHALCOGEN PRECURSORS FOR DEPOSITION OF SILICON NITRIDE - Chalcogen silane precursors are described. Methods for depositing a silicon nitride (Si | 2022-07-21 |
20220230875 | METHOD FOR REMOVING IMPURITIES IN THIN FILM AND SUBSTRATE PROCESSING APPARATUS - The present inventive concept relates to a method for removing impurities in thin film and a substrate processing apparatus. The method for removing impurities in a thin film includes the steps of: providing a substrate having a thin film formed thereon in a process chamber; supplying a first gas reacting and coupling with impurities contained in the thin film, into the process chamber; exhausting a coupled product of the impurities and the first gas by depressurizing an interior of the process chamber after stopping the supply of the first gas; curing the thin film by supplying a second gas being different from the first gas into the process chamber; and stopping the supply of the second gas and exhausting the remaining second gas from the interior of the process chamber. | 2022-07-21 |
20220230876 | PREPARATION METHOD FOR CAPACITOR STRUCTURE, CAPACITOR STRUCTURE, AND MEMORY - A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure. | 2022-07-21 |
20220230877 | Selective SIGESN:B Deposition - Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate. | 2022-07-21 |
20220230878 | SEMICONDUCTOR COMPOSITE LAYERS - A semiconductor composite layer can include a source electrode and a drain electrode individually comprising both a carrier mobility contributor and an amorphous phase stabilizer. The semiconductor composite layer can further include a semiconductive portion disposed between the source electrode and the drain electrode wherein the semiconductive portion comprises the carrier mobility contributor and the amorphous phase stabilizer, the semiconductivity controller comprising oxygen and an element having an electrode potential that is lower than that of both the carrier mobility contributor and the amorphous phase stabilizer. | 2022-07-21 |
20220230879 | SOLUTION-BASED DEPOSITION METHOD FOR PREPARING SEMICONDUCTING THIN FILMS VIA DISPERSED PARTICLE SELF-ASSEMBLY AT A LIQUID-LIQUID INTERFACE - A device for coating semiconductor/semiconductor precursor particles on a flexible substrate and a preparation method of a semiconducting thin film, wherein the device includes: a container for a first and second solvent substantially immiscible; injection means for injecting a predetermined dispersion volume of at least one layered semiconductor particle material or its precursor(s), occurring at a liquid-liquid interface formed within the container and between the first and second solvent, and creating a particle film at the liquid-liquid interface; a first support means; substrate extracting means; substrate supply means; compression means, reducing a distance between particles and push the film onto the substrate, wherein the compression means includes several pushing means mounted on a drive device, wherein at least two of the several pushing means are at least partially submerged in the second solvent during drive device rotation, and moved through the second solvent toward the first support means. | 2022-07-21 |
20220230880 | METHOD OF FORMING BISMUTH-CONTAINING GALLIUM OXIDE-BASED SEMICONDUCTOR FILM ON BASE MATERIAL, BISMUTH-CONTAINING GALLIUM OXIDE-BASED SEMICONDUCTOR FILM, AND BISMUTH-CONTAINING GALLIUM OXIDE-BASED SEMICONDUCTOR COMPONENT - There is provided a method of forming a bismuth-containing gallium oxide-based semiconductor film on a base material by a pulse laser deposition method using a target containing gallium oxide and bismuth oxide. In the method, the temperature of the base material is set to 650° C. to 1,000° C., and the laser intensity is set to 1.0 J/cm | 2022-07-21 |
20220230881 | ACTIVE REGION ARRAY FORMATION METHOD - An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer. | 2022-07-21 |
20220230882 | III-N HETEROEPITAXIAL DEVICES ON ROCK SALT SUBSTRATES - Described herein are rock salt substrates and methods of making thereof that are useful as epitaxial substrates for semiconducting materials, including ultra-wide bandgap materials. Advantageously, the described rock salt substrates may be useful as substrates for Group III (Al, Ga, In)—N substrate allowing for pseudomorphic growth of novel, desirable materials. The rock salt may be provided as a bulk material or deposited as a thin film. These substrates may allow for generation of high Al content semiconductor devices with ultra-wide bandgap and other useful properties. | 2022-07-21 |
20220230883 | DEVICES AND METHODS INVOLVING ACTIVATION OF BURIED DOPANTS USING ION IMPLANTATION AND POST-IMPLANTATION ANNEALING - In certain examples, methods and semiconductor structures are directed to use of a doped buried region (e.g., Mg-dopant) including a III-Nitride material and having a diffusion path (“ion diffusion path”) that includes hydrogen introduced by using ion implantation via at least one ion species. An ion implantation thermal treatment causes hydrogen to diffuse through the ion implanted path and causes activation of the buried region. In more specific examples in which such semiconductor structures have an ohmic contact region at which a source of a transistor interfaces with the buried region, the ohmic contact region is without etching-based damage due at least in part to the post-ion implantation thermal treatment. | 2022-07-21 |
20220230884 | SELECTIVE FORMATION OF TITANIUM SILICIDE AND TITANIUM NITRIDE BY HYDROGEN GAS CONTROL - The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow. | 2022-07-21 |
20220230885 | MULTI-FACED MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS - Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of a die included in each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin. | 2022-07-21 |
20220230886 | METHOD FOR FORMING A TRENCH IN A FIRST SEMICONDUCTOR LAYER OF A MULTI-LAYER SYSTEM - A method for forming a trench in a first semiconductor layer of a multi-layer system. The method includes: applying a mask layer onto the first semiconductor layer, a recess being formed in the mask layer so that the first semiconductor layer is exposed within the recess; applying a protective layer which completely covers or modifies the first semiconductor layer exposed within the recess; applying a second semiconductor layer; etching the second semiconductor layer to completely remove it in a subarea surrounding the recess of the mask layer; etching the protective layer so that the first semiconductor layer is exposed within the recess; and forming the trench in the first semiconductor layer, the recess of the mask layer serving as an etching mask, and the trench being formed by a cyclical alternation between etching and passivation steps, the first etching step being longer than the subsequent etching steps. | 2022-07-21 |
20220230887 | METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE - Methods and apparatus for processing a substrate are provided herein. For example, a method includes heating a substrate disposed in an interior volume of a process chamber and having a boron-containing film deposited thereon to a predetermined temperature; and supplying water vapor in a non-plasma state to the interior volume at a predetermined pressure for a predetermined time, while maintaining the substrate at the predetermined temperature to anneal the substrate for the predetermined time and remove the boron-containing film. | 2022-07-21 |
20220230888 | DRY ETCHING METHOD, PRODUCTION METHOD FOR SEMICONDUCTOR ELEMENT, AND CLEANING METHOD - A dry etching method which includes a dry etching step in which an etching gas containing a halogen fluoride, which is a compound of bromine or iodine and fluorine, is brought into contact with a member to be etched ( | 2022-07-21 |
20220230889 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator. | 2022-07-21 |
20220230890 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING GALLIUM OXIDE-BASED SEMICONDUCTOR LAYER - A method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer includes: ion-implanting dopant into a gallium oxide-based semiconductor layer while heating the gallium oxide-based semiconductor layer; and annealing the gallium oxide-based semiconductor layer under an oxygen atmosphere, after the ion-implanting. | 2022-07-21 |
20220230891 | METHOD FOR MANUFACTURING AN ELECTRONIC POWER MODULE - The invention relates to a method for manufacturing a power electronic module ( | 2022-07-21 |
20220230892 | LOW COST PACKAGE WARPAGE SOLUTION - Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer. | 2022-07-21 |
20220230893 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes: supplying a pre-wet liquid to a substrate while rotating the substrate, and forming a liquid film of the pre-wet liquid on a surface of the substrate; supplying a chemical liquid at a first flow rate to the substrate while the substrate is being rotated at a first rotation speed, and processing the substrate with the chemical liquid to form a liquid film of the chemical liquid having a first thickness on the surface of the substrate; and supplying the chemical liquid to the substrate at a second supply flow rate while the substrate is being rotated at a second rotation speed, and performing a second chemical liquid processing on the substrate with the chemical liquid to form a liquid film of the chemical liquid having a second thickness on the surface of the substrate. | 2022-07-21 |
20220230894 | SUBSTRATE PROCESSING APPARATUS HAVING A MIDDLE ELECTRODE - A substrate processing apparatus may include a vacuum chamber, a substrate supporting unit disposed at lower portion of an inside of the vacuum chamber, and an electric field forming unit forming an electric field inside the vacuum chamber. The electric field forming unit may include an upper electrode disposed at an upper portion of the inside of the vacuum chamber, a lower electrode disposed in the substrate supporting unit, and a middle electrode disposed between the upper electrode and the lower electrode. | 2022-07-21 |
20220230895 | BONDING DEVICE AS WELL AS METHOD FOR BONDING SUBSTRATES - A bonding device has two chucks, two gas pressure regulators and a control unit. The chucks each have a holding surface with pressure ports fluidically connected to the respective gas pressure regulator. The control unit is electrically and/or wirelessly connected to the gas pressure regulators and configured to control gas pressure regulators independently from each other. Support elements movably mounted within the pressure ports, are provided to measure the amount of substrate deflection and adjust the respective gas pressures and also to apply additional mechanical pressure to the substrates. The two chucks may be mounted on corresponding support structures so as to be thermally isolated therefrom. The temperature of the two chucks may be equalised by moving the chucks into contact. A chuck tempering device may be used for equalising the temperature of the two chucks. The bonding device is used for bonding two substrates by bonding wave propagation. | 2022-07-21 |
20220230896 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes a vacuum processing container and a rotation arm including a rotary axis disposed at a central portion of the vacuum processing container, wherein, in the rotation arm, a rotation cylinder having a hollow interior constitutes the rotary axis, and a hollow portion of the rotation cylinder constitutes an exhaust path of the vacuum processing container. | 2022-07-21 |
20220230897 | SUBSTRATE PROCESSING APPARATUS - Described herein is a technique capable of reducing an amount of moisture in a low temperature region in a substrate processing apparatus provided with a transfer chamber. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber provided with a heater; a load lock chamber; a transfer chamber provided between the process chamber and the load lock chamber and including a first region provided adjacent to the process chamber and a second region provided more adjacent to the load lock chamber than the first region and whose temperature is lower than a temperature of the first region; a detector capable of detecting an amount of moisture in the transfer chamber; and an inert gas supplier capable of supplying an inert gas toward the second region in the transfer chamber. | 2022-07-21 |
20220230898 | SUBSTRATE PROCESSING APPARATUS - Embodiments of this application discloses a substrate processing apparatus comprising: a vacuum transfer module having a vacuum transfer space and an opening; a wall unit attached to the opening and including a first gate valve and a second gate valve; a substrate processing module attached to the wall unit and having a substrate processing space communicating with the vacuum transfer space via the first gate valve; and a ring stocker attached to the wall unit and having a storage space for storing at least one annular member used in a plasma processing module. Moreover, the apparatus further includes a transfer mechanism disposed in the vacuum transfer space and transfers a substrate between the vacuum transfer space and the substrate processing space through the first gate valve and also transfers at least one annular member between the vacuum transfer space and the storage space via the second gate valve. | 2022-07-21 |
20220230899 | CONTACT AREA SIZE DETERMINATION BETWEEN 3D STRUCTURES IN AN INTEGRATED SEMICONDUCTOR SAMPLE - A method of determining a size of a contact area between a first 3D structure and a second 3D structure in an integrated semiconductor sample, includes the following steps: obtaining at least a first cross section image and a second cross section image parallel to the first cross section image, wherein obtaining the first and second cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample using a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with an imaging device; performing image registration of the obtained cross section images and obtaining a 3D data set; determining a 3D model representing the first 3D structure and the second 3D structure in the 3D data set; and determining a relative overlap of the first 3D structure with the second 3D structure based on the 3D model. | 2022-07-21 |
20220230900 | HANDLE FOR WAFER CARRIER - A handle for a wafer carrier that includes an insertable member configured to be inserted into an aperture of the wafer carrier, and a locking mechanism moveable relative to the insertable member. A tab of the insertable member retains the insertable member in the aperture when in an engaged state. When in a locked state, the locking mechanism maintains the tab in the engaged state and a flexible member of the locking mechanism is positioned to maintain the locking mechanism in the locked state. A wafer carrier includes the detachable handle and the locking mechanism. | 2022-07-21 |
20220230901 | CONTAINERS FOR PROTECTING SEMICONDUCTOR DEVICES AND RELATED METHODS - Containers for supporting one or more semiconductor devices therein may include walls positioned to at least partially surround a semiconductor device. At least one of the walls may include a radiation-shielding material. A support structure may be shaped, positioned, and configured to support the semiconductor device within the walls. | 2022-07-21 |
20220230902 | FALL PREVENTION DEVICES AND METHODS - A gate/barrier assembly includes a first post, a second post, a gate, and a barrier. The first post is arranged to be fixedly supported by a semiconductor processing system. The second post extends in parallel with the first post and is arranged to be pivotably supported by the semiconductor processing system. The gate is pivotably supported by the first post and has a closed position where the gate overlaps the second post and an open position wherein is the gate is spaced apart from the second post. The barrier is fixedly supported by the second post, has guard and guide positions, is spaced apart from the first post in the guide position, and abuts the first post in the guard position. The gate overlaps the barrier when the gate is in the closed position and the barrier is in the guard position. | 2022-07-21 |
20220230903 | TOOL AND METHOD FOR CORRECTING POSITION OF WAFER IN SEMICONDUCTOR MANUFACTURING MACHINE - The present disclosure relates to a tool and method for correcting a position of a wafer in a semiconductor manufacturing machine, including: a cover plate, disposed on one side that is of the chamber away from the wafer bearing apparatus, the cover plate is provided with a mounting hole; a transparent plate, installed in the mounting hole, a projection of the wafer bearing apparatus on the transparent plate is located in the transparent plate; and a first scale and a second scale, disposed on the transparent plate, the first scale extends to edges of the transparent plate along a first direction and a direction away from the first direction, the second scale extends to edges of the transparent plate along a second direction and a direction away from the second direction, and the first scale and the second scale are provided with a plurality of uniformly distributed scale lines. | 2022-07-21 |
20220230904 | SUBSTRATE PROCESSING SYSTEM AND METHOD FOR CONTROLLING SUBSTRATE PROCESSING SYSTEM - A substrate processing system, which includes a transfer device configured to simultaneously transfer a plurality of substrates and suitably corrects positions of the substrate, and a method of controlling the substrate processing system are provided. The substrate processing system includes: a process chamber in which a plurality of substrates is processed; a vacuum transfer chamber connected to the process chamber; a transfer device provided in the vacuum transfer chamber and configured to simultaneously transfer a plurality of substrates; a module connected to the vacuum transfer chamber and having a plurality of stages on which substrates are placed; and a controller. The controller is configured to measure an amount of change of an arm of the transfer device that has transferred processed substrates, and to correct positions of the stages based on the amount of change of the arm of the transfer device. | 2022-07-21 |
20220230905 | WAFER PLACEMENT TABLE AND METHOD OF MANUFACTURING THE SAME - A wafer placement table includes a first ceramic substrate having a wafer placement surface on an upper surface; a second ceramic substrate disposed on a lower surface side of the first ceramic substrate; a metal bonding layer that bonds a lower surface of the first ceramic substrate and an upper surface of the second ceramic substrate; a connection member including an upper base and a lower base, the connection member being embedded in the second ceramic substrate with the upper base in contact with the metal bonding layer; and a power supply terminal electrically connected to the lower base of the connection member, wherein the connection member has a portion in which an area of cross section when the connection member is cut by a plane parallel to the upper base increases from a side of the upper base to a side of the lower base. | 2022-07-21 |
20220230906 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH NAND LOGIC - A 3D semiconductor device including: a first level including a single crystal layer and plurality of first transistors; a first metal layer including interconnects between first transistors, where the interconnects between the first transistors includes forming logic gates; a second metal layer atop at least a portion of the first metal layer, second transistors which are vertically oriented, are also atop a portion of the second metal layer; where at least eight of the first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the second transistors is at least partially directly atop of the NAND logic structure; and a third metal layer atop at least a portion of the second transistors, where the second metal layer is aligned to the first metal layer with a less than 150 nm misalignment. | 2022-07-21 |
20220230907 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes. | 2022-07-21 |
20220230908 | Depositing and Oxidizing Silicon Liner for Forming Isolation Regions - A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin. | 2022-07-21 |
20220230909 | METHOD FOR MAKING DEEP TRENCH ISOLATION OF CIS DEVICE, AND SEMICONDUCTOR DEVICE STRUCTURE - A method for making a deep trench isolation of a CIS device includes: growing a first epitaxial layer on a substrate; forming a hard mask layer on the first epitaxial layer; performing photolithography and etching processes to form deep trenches arranged longitudinally and transversely in the first epitaxial layer; forming a second epitaxial layer in the deep trenches; performing a thermal oxidation process to form a first oxide layer on the surface of the second epitaxial layer; completely filling the deep trenches with polysilicon; performing a back-etching process to expose sidewalls of the first oxide layer in the deep trenches; forming a second oxide layer on the top of the polysilicon; removing the hard mask layer and the first oxide layer above the second oxide layer; rapidly growing a third epitaxial layer; and performing a CMP process to form a deep trench isolation on the substrate. | 2022-07-21 |
20220230910 | Shallow Trench Isolation Forming Method and Structures Resulting Therefrom - A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer. | 2022-07-21 |
20220230911 | Reducing Spacing Between Conductive Features Through Implantation - A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug. | 2022-07-21 |
20220230912 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer. | 2022-07-21 |
20220230913 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH COVERING LINERS - The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer. | 2022-07-21 |
20220230914 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING - A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer. | 2022-07-21 |
20220230915 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a substrate, a conductive trace, a passivation layer and an upper wiring. The conductive trace is disposed over the substrate. The conductive trace includes a body portion disposed on the substrate, and a cap portion disposed on the body portion, and the cap portion is wider than the body portion. The passivation layer covers the conductive trace. The upper wiring is disposed on the passivation layer and electrically connected to the cap portion of the conductive trace through an opening of the passivation layer. | 2022-07-21 |
20220230916 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor structure includes: a substrate is provided; and an intermediate layer is formed on the substrate, an I-shaped member and a wall-shaped member are formed in the intermediate layer, a top surface of the wall-shaped member is not lower than a top surface of the I-shaped member, and a bottom surface of the wall-shaped member is not higher than a bottom surface of the I-shaped member. | 2022-07-21 |
20220230917 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED LATERAL CONTACT ELEMENTS AND METHODS FOR FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack that underlies the retro-stepped dielectric material portion. Some of the pillar-shaped contact-opening assemblies can include a first conductive plug that laterally contacts a cylindrical sidewall of a respective one of the electrically conductive layers and a conductive via structure that contacts a top surface of the first conductive plug. | 2022-07-21 |
20220230918 | METHOD FOR PRODUCING SUBSTRATE HAVING THROUGH-SILICON VIAS, SUBSTRATE HAVING THROUGH-SILICON VIAS, AND COPPER PASTE FOR THROUGH-SILICON VIA FORMATION - An aspect of the invention is a method for producing a substrate having through-silicon vias, the method including a preparation step of preparing a silicon substrate provided with through-holes, in which the through-holes communicate with both principal surfaces; a copper sintered body formation step of forming a copper sintered body having a porous structure such that the copper sintered body fills at least the through-holes; a resin impregnation step of impregnating the copper sintered body with a curable resin composition; and a resin curing step of curing the curable resin composition impregnated into the copper sintered body to form an electric conductor that includes the copper sintered body having pores filled with a resin cured product, and providing through-silicon vias in the through-holes. | 2022-07-21 |
20220230919 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE, DIE, AND DIE PACKAGE - A method of manufacturing a semiconductor package is provided. The method may include singulating a wafer including a plurality of dies fixed to an auxiliary carrier to generate dies having released side surfaces, covering at least the side surfaces of the dies with a passivation layer using a deposition process at a temperature below the melting temperature of the auxiliary carrier, keeping a gap between the passivation layers at the side surfaces of adjacent dies of the plurality of dies. | 2022-07-21 |
20220230920 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; ( | 2022-07-21 |
20220230921 | METHOD AND STRUCTURE FOR METAL GATES - A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes. | 2022-07-21 |
20220230922 | Nanostructure Field-Effect Transistor Device and Method of Forming - A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer. | 2022-07-21 |
20220230923 | INNER FILLER LAYER FOR MULTI-PATTERNED METAL GATE FOR NANOSTRUCTURE TRANSISTOR - An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor. | 2022-07-21 |
20220230924 | MULTI-FIN VERTICAL FIELD EFFECT TRANSISTOR AND SINGLE-FIN VERTICAL FIELD EFFECT TRANSISTOR ON A SINGLE INTEGRATED CIRCUIT CHIP - Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1 | 2022-07-21 |
20220230925 | SOURCE/DRAIN EPI STRUCTURE FOR IMPROVING CONTACT QUALITY - A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI; a contact feature disposed on the metal compound feature and over both the NEPI and the PEPI; and a via structure disposed over the contact feature and over the NEPI, wherein the via structure is partially in the contact feature. | 2022-07-21 |
20220230926 | Semiconductor Device and Method - In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip. | 2022-07-21 |
20220230927 | GLASS AND WAFER INSPECTION SYSTEM AND A METHOD OF USE THEREOF - A method of inspection and an inspection system for the film deposition process for substrates includes glass and wafer. The inspection system includes multiple camera modules positioned in a load lock unit of a process chamber, such as the camera modules that can capture images of the substrate in the load lock. The images are analyzed by a control unit of the inspection system to determine the accuracy of robots in handling the substrate, calibration of the robots based on the analysis, and defects in the substrate caused during the handling and deposition process. | 2022-07-21 |
20220230928 | SCAN TESTABLE THROUGH SILICON VIAs - In one example, an integrated circuit comprises a die. The die has a first surface and a second surface, the second surface opposite to the first surface. The die also includes: a first contact on the first surface and a second contact on the second surface; a through silicon via having a first end and a second end, the first end coupled to the first contact and the second end coupled to the second contact; and a scan cell having a control input, a response input, and a stimulus output, the response input coupled to the first end and the stimulus output coupled to the second end. | 2022-07-21 |
20220230929 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor element, a substrate on which the semiconductor module is mounted, a heat radiating plate on which the substrate is mounted, a resin case, and a first main current electrode and a second main current electrode, in which in the first main current electrode and the second main current electrode, one end of each thereof is joined to a circuit pattern on the substrate, an other end of each thereof is extended through and incorporated in a side wall of the resin case so as to project outward of the resin case, and each thereof has at least a portion of overlap at which a part thereof overlaps in parallel with each other with a gap therebetween, and each thereof has a slope portion provided between an external projection portion and an internal projection portion. | 2022-07-21 |
20220230930 | PACKAGE WITH ENCAPSULATED ELECTRONIC COMPONENT BETWEEN LAMINATE AND THERMALLY CONDUCTIVE CARRIER - A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component. | 2022-07-21 |
20220230931 | CHIP ENCAPSULATION STRUCTURE AND ENCAPSULATION METHOD - A chip encapsulation structure, including: a wafer provided with a groove; a first metal wire arranged on surfaces of the groove and the wafer; a metal solder ball arranged on the first metal wire or on a metal pad of the chip, and is configured to solder the metal pad of the chip to the first metal wire; a first plastic encapsulation film covering upper surfaces of the wafer, the chip and the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire, so as to form a closed cavity among the wafer, the groove and the chip; an inductive structure arranged on an upper surface of the first plastic encapsulation film and/or a lower surface of the wafer, and connected to the chip through the first metal wire; and a pad arranged on the inductive structure. | 2022-07-21 |
20220230932 | IGBT MODULE WITH HEAT DISSIPATION STRUCTURE HAVING SPECIFIC LAYER THICKNESS RATIO - An IGBT module with a heat dissipation structure having a specific layer thickness ratio includes a layer of IGBT chips, an upper bonding layer, a circuit layer, an insulating layer, and a heat dissipation layer. The insulating layer is disposed on the heat dissipation layer, the circuit layer is disposed on the insulating layer, the upper bonding layer is disposed on the circuit layer, and the layer of IGBT chips is disposed on the upper bonding layer. A thickness of the insulating layer is less than 0.2 mm, a thickness of the circuit layer is between 1.5 mm and 3 mm, and a thickness ratio of the circuit layer to the insulating layer is greater than or equal to 7.5:1. | 2022-07-21 |
20220230933 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, first to third semiconductor chips disposed on the substrate, first to third heat transfer components, first and second heat spreaders, and a trench. The first semiconductor chip is between the second and third semiconductor chips. The first to third heat transfer components are disposed on the semiconductor chips, respectively. The first heat spreader is formed on the first to third heat transfer components. The second heat spreader protrudes from the first heat spreader. The trench is formed on the second heat spreader. The second heat spreader includes first and second side units spaced apart with the trench between. A distance between an outer surface of an uppermost part of the first side unit and an outer surface of an uppermost part of the second side unit is smaller than a width of an upper surface of the first semiconductor chip. | 2022-07-21 |
20220230934 | COMPOSITE HAVING DIAMOND CRYSTAL BASE - A composite that includes a base including an oxide layer MOx of an element M on a surface thereof and a diamond crystal base bonded to the surface of the base. The M is one or more selected from among metal elements capable of forming an oxide (excluding alkali metals and alkaline earth metals), Si, Ge, As, Se, Sb, Te, and Bi, and the diamond crystal base is bonded to the surface of the base by M-O-C bonding of at least some C atoms of the (111) surface of the diamond crystal base. | 2022-07-21 |
20220230935 | COPPER/CERAMIC ASSEMBLY, INSULATED CIRCUIT BOARD, METHOD FOR PRODUCING COPPER/CERAMIC ASSEMBLY, AND METHOD FOR PRODUCING INSULATED CIRCUIT BOARD - This A copper/ceramic bonded body includes: a copper member made of copper or a copper alloy; and a ceramic member made of oxygen-containing ceramics, wherein the copper member and the ceramic member are bonded to each other, a magnesium oxide layer is formed on a ceramic member side between the copper member and the ceramic member, and an active metal oxide phase composed of an oxide of one or more active metals selected from Ti, Zr, Nb, and Hf is dispersed inside a copper layer in contact with the magnesium oxide layer. | 2022-07-21 |
20220230936 | Heatsink Arrangement for Integrated Circuit Assembly and Method for Assembling Thereof - Various heatsink arrangements, and methods for implementing and using such are discussed. | 2022-07-21 |
20220230937 | Conformal Cooling Assembly with Substrate Fluid-Proofing for Multi-Die Electronic Assemblies - A conformal cooling assembly for multiple-die electronic assemblies, such as printed circuit boards, integrated circuits, etc., which addresses and solves a multitude of challenges and problems associated with using liquid-cooled cold plates and dielectric immersion cooling to manage the heat produced by a multiplicity of dies. The conformal cooling assembly comprises a conformal cooling module comprising inlet and outlet passageways and a plenum configured to permit a cooling fluid to pass therethrough, thereby facilitating direct fluid contact with heat-generating components affixed to the substrate of the electronic assembly. The conformal cooling assembly also includes a fastener for attaching the conformal cooling module to the substrate; and a fluid-barrier disposed between the substrate and the plenum. The fluid-barrier is adapted to minimize, inhibit or prevent the cooling fluid from penetrating and being absorbed by the substrate. | 2022-07-21 |
20220230938 | POWER MODULE WITH VASCULAR JET IMPINGEMENT COOLING SYSTEM - A vascular jet cooling system for use with a planar power module and a coolant supply includes a manifold housing and one or more jet impingement plates. The manifold housing is constructed of a dielectric polymer molding material, and defines a coolant inlet port configured to fluidly connect to the coolant supply, an internal cavity in fluid communication with the coolant inlet port and containing the power module, and a coolant outlet port in fluid communication with the internal cavity. The jet impingement plate(s) is arranged in the internal cavity. Openings of the plates direct coolant passing through the coolant inlet port onto a respective major surface of the power module. A power module assembly includes a planar power module and the vascular jet cooling system. A method of constructing the power module assembly uses sacrificial materials and overmolding of the jet impingement plates. | 2022-07-21 |
20220230939 | THROUGH-SUBSTRATE VIA FORMATION TO ENLARGE ELECTROCHEMICAL PLATING WINDOW - In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion. | 2022-07-21 |
20220230940 | Barrier Structures Between External Electrical Connectors - A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad. | 2022-07-21 |
20220230941 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method includes: arranging a semiconductor device on a redistribution substrate, the device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, the redistribution substrate having an insulating board having a first major surface and a second major surface having solderable contact pads, so that the first power electrode is arranged on a first conductive pad and the control electrode is arranged on a second conductive pad on the first major surface; arranging a contact clip such that a web portion is arranged on the second power electrode and a peripheral rim portion is arranged on a third conductive pad on the first major surface; and electrically coupling the first power electrode, control electrode and peripheral rim portion to the respective conductive pads and electrically coupling the web portion to the second power electrode. | 2022-07-21 |
20220230942 | PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device is provided, including a first semiconductor die on which a first electrical component is integrated that includes a first terminal at a first surface of the first die and a second terminal at a second surface of the first die, a second semiconductor die similar to the first die, with a first surface of the second die facing the first surface of the first die. A first conductive element on the second surface of the first side electrically connected to the second terminal of the first electrical component, a second conductive element is on the second surface of the second die electrically connected to the second terminal of the second electrical component, and a third conductive element between the first surfaces of the first and the second die. The first terminals of the first and second electrical components are electrically connected through the third conductive element. | 2022-07-21 |
20220230943 | POWER MODULE AND MANUFACTURING METHOD THEREFOR - A manufacturing method for a power module capable of shortening a manufacturing time for a power module is obtained. The manufacturing method for a power module includes: a subassembly arranging step of placing a subassembly including a first electrode, a semiconductor device, and a second electrode on a heat sink via a joining material; and a transfer molding step of, after the subassembly arranging step, under a state in which the first electrode, the semiconductor device, and a second-electrode inner portion are arranged in a region surrounded by the heat sink and a molding die, injecting a thermoplastic resin into the region, wherein, in the transfer molding step, the subassembly is joined to the heat sink via the joining material with use of the resin. | 2022-07-21 |
20220230944 | CONFIGURABLE LEADED PACKAGE - A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer. | 2022-07-21 |
20220230945 | SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit. | 2022-07-21 |
20220230946 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE STRUCTURE - A substrate structure and a semiconductor package structure are provided. The substrate structure includes a first dielectric layer, a pad and a conductive structure. The first dielectric layer has a first surface and a second surface opposite to the first surface. The pad is adjacent to the first surface and at least partially embedded in the first dielectric layer. The first dielectric layer has an opening exposing the pad, and a width of the opening is less than a width of the pad. The conductive structure is disposed on the pad and composed of a first portion outside the opening of the first dielectric layer and a second portion embedded in the opening of the first dielectric layer. The first portion has an aspect ratio exceeding 1.375. | 2022-07-21 |
20220230947 | BACKSIDE POWER DISTRIBUTION NETWORK SEMICONDUCTOR ARCHITECTURE USING DIRECT EPITAXIAL LAYER CONNECTION AND METHOD OF MANUFACTURING THE SAME - Provided is a backside power distribution network (BSPDN) semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device including an active device that includes an epitaxial layer, a second semiconductor device provided on a second surface of the wafer opposite to the first surface, the second semiconductor device including a power rail configured to supply power, and a through-silicon via (TSV) protruding from the power rail and extending to a level of the epitaxial layer of the active device. | 2022-07-21 |
20220230948 | EMBEDDED SEMICONDUCTOR PACKAGES AND METHODS THEREOF - The present disclosure describes semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. In some examples, the semiconductor chips are embedded within the molding compound. In other examples, the semiconductor chips are adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels described herein can be tailored to decrease warpage of the package as the semiconductor chip heats during use. | 2022-07-21 |
20220230949 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE - A circuit board includes a first external circuit layer, a first substrate, a second substrate, a third substrate, and a conductive through hole structure. The first substrate includes conductive pillars electrically connecting the first external circuit layer and the second substrate. The second substrate has an opening and includes a first dielectric layer. The opening penetrates the second substrate, and the first dielectric layer fills the opening. The third substrate includes an insulating layer, a second external circuit layer, and conductive holes. A conductive material layer of the conductive through hole structure covers an inner wall of a through hole and electrically connects the first and the second external circuit layers to define a signal path. The first external circuit layer, the conductive pillars, the second substrate, the conductive holes and the second external circuit layer are electrically connected to define a ground path surrounding the signal path. | 2022-07-21 |
20220230950 | SEMICONDUCTOR DEVICE PACKAGE - The present disclosure provides a semiconductor device package including a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction. | 2022-07-21 |
20220230951 | MAGNETIC INDUCTOR STRUCTURES FOR PACKAGE DEVICES - Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material. | 2022-07-21 |
20220230952 | SEMICONDUCTOR APPARATUS AND METHOD HAVING A LEAD FRAME WITH FLOATING LEADS - In described examples, a packaged semiconductor device includes a frame, a pre-fabricated interposer, and an integrated circuit die. The frame includes multiple conductive frame leads and multiple conductive connection points, as well as a hole in the frame surrounded by the frame leads and the conductive connection points. The pre-molded interposer has an external perimeter including multiple conductive interposer leads, and is for insertion into the hole. At least one of the interposer leads does not extend to the external perimeter of the interposer. The die is electrically coupled to selected ones of the frame leads and of the interposer leads. The interposer is inserted into the hole and coupled to the frame, and the frame, interposer, and die are together encapsulated by encapsulation material. | 2022-07-21 |
20220230953 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE - A semiconductor device includes: a first power supply terminal; a second power supply terminal; an output terminal; a first switching element connected between the first power supply terminal and the output terminal; and a second switching element connected between the second power supply terminal and the output terminal. The first power supply terminal includes: a first facing portion; a second facing portion; and a third facing portion. The first facing portion and the second facing portion are provided such that, upon application of a current, the current flows through the first facing portion and the second facing portion in a direction opposite to a direction in which the current flows through each of portions in the second power supply terminal that face the first facing portion and the second facing portion. | 2022-07-21 |
20220230954 | SEMICONDUCTOR DEVICE - A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region. | 2022-07-21 |
20220230955 | INTEGRATED CIRCUIT STRUCTURE WITH CAPACITOR ELECTRODES IN DIFFERENT ILD LAYERS, AND RELATED METHODS - Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode. | 2022-07-21 |
20220230956 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole. | 2022-07-21 |
20220230957 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device, and a method of manufacturing a semiconductor memory device, includes a stacked structure including a plurality of conductive layers for local lines stacked on a semiconductor substrate defined by a cell region and a slimming region to be spaced apart from each other, wherein the plurality of conductive layers for local lines are stacked in a step structure in the slimming region. The semiconductor memory device also includes a plurality of contact plugs formed to penetrate the stack structure in the slimming region, the plurality of contact plugs corresponding to each of the conductive layers for local lines. Each of the plurality of contact plugs includes a protrusion part protruding horizontally, and the protrusion part is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines. | 2022-07-21 |
20220230958 | STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE - An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate. | 2022-07-21 |
20220230959 | SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING SEMICONDUCTOR STRUCTURE, AND FUSE ARRAY - The present application relates to a semiconductor structure, a method for forming the semiconductor structure, and a fuse array. The semiconductor structure includes at least two first through holes located above a substrate, a first conductive layer located above and electrically connected with the first through holes, at least two second through holes located above the first conductive layer, and a second conductive layer located above the second through holes and electrically connected with the first conductive layer through the second through holes, wherein projections of the first through holes and the second conductive layer on the substrate are non-overlapping. The semiconductor structure requires relatively low fusing energy. | 2022-07-21 |
20220230960 | MICROELECTRONIC DEVICES WITH SYMMETRICALLY DISTRIBUTED FILL MATERIAL IN STADIUM TRENCHES AND RELATED SYSTEMS AND METHODS - Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed. | 2022-07-21 |
20220230961 | STACKED SEMICONDUCTOR DEVICE ARCHITECTURE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor architecture having a metal-oxide-semiconductor field-effect transistor (MOSFET) cell, the semiconductor architecture including a first semiconductor device included in the MOSFET cell, a second semiconductor device included in the MOSFET cell, the second semiconductor device being provided above the first semiconductor device, a first power rail configured to supply power to the first semiconductor device, the first power rail being provided at a vertical level different from the first semiconductor device and the second semiconductor device, and a second power rail configured to supply power to the second semiconductor device, the second power rail being provided at a vertical level between the first semiconductor device and the second semiconductor device. | 2022-07-21 |
20220230962 | TUNGSTEN STRUCTURES AND METHODS OF FORMING THE STRUCTURES - Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material. | 2022-07-21 |
20220230963 | SELF-ALIGNED CAVITY STRUCUTRE - The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer. | 2022-07-21 |
20220230964 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die. | 2022-07-21 |
20220230965 | MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER - A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die. | 2022-07-21 |
20220230966 | MANUFACTURING METHOD OF A SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure. | 2022-07-21 |