29th week of 2014 patent applcation highlights part 54 |
Patent application number | Title | Published |
20140201497 | INSTRUCTION FOR ELEMENT OFFSET CALCULATION IN A MULTI-DIMENSIONAL ARRAY - An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure. | 2014-07-17 |
20140201498 | INSTRUCTION AND LOGIC TO PROVIDE VECTOR SCATTER-OP AND GATHER-OP FUNCTIONALITY - Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results. | 2014-07-17 |
20140201499 | SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A LIST OF INDEX VALUES INTO A MASK VALUE - Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a list of index values into a mask value in response to a single vector packed conversion of a list of index values into a mask value instruction that includes a destination writemask register operand, a source vector register operand, and an opcode are described. | 2014-07-17 |
20140201500 | Controlling Bandwidth Allocations In A System On A Chip (SoC) - In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed. | 2014-07-17 |
20140201501 | DYNAMIC ACCESSING OF EXECUTION ELEMENTS THROUGH MODIFICATION OF ISSUE RULES - Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system including a processor having an instruction issue unit and a plurality of execution units. The processor is configured to detect an error in a first execution unit among the plurality of execution units and adjust instruction dispatch rules of the instruction issue unit based on detecting the error in the first execution unit to restrict access to the first execution unit while leaving un-restricted access to the remaining execution units of the plurality of execution units. | 2014-07-17 |
20140201502 | SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A BUTTERFLY HORIZONTAL AND CROSS ADD OR SUBSTRACT IN RESPONSE TO A SINGLE INSTRUCTION - Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode are described. | 2014-07-17 |
20140201503 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 2014-07-17 |
20140201504 | FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS - A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C | 2014-07-17 |
20140201505 | PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR - A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions. | 2014-07-17 |
20140201506 | METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS - A processing engine includes separate hardware components for control processing and data processing. The instruction execution order in such a processing engine may be efficiently determined in a control processing engine based on inputs received by the control processing engine. For each instruction of a data processing engine: a status of the instruction may be set to “ready” based on a trigger for the instruction and the input received in the control processing engine; and execution of the instruction in the data processing engine may be enabled if the status of the instruction is set to “ready” and at least one processing element of the data processing engine is available. The trigger for each instruction may be a function of one or more predicate register of the control processing engine, FIFO status signals or information regarding tags. | 2014-07-17 |
20140201507 | THREAD SELECTION AT A PROCESSOR BASED ON BRANCH PREDICTION CONFIDENCE - A processor employs one or more branch predictors to issue branch predictions for each thread executing at an instruction pipeline. Based on the branch predictions, the processor determines a branch prediction confidence for each of the executing threads, whereby a lower confidence level indicates a smaller likelihood that the corresponding thread will actually take the predicted branch. Because speculative execution of an untaken branch wastes resources of the instruction pipeline, the processor prioritizes threads associated with a higher confidence level for selection at the stages of the instruction pipeline. | 2014-07-17 |
20140201508 | CONFIDENCE THRESHOLD-BASED OPPOSING BRANCH PATH EXECUTION FOR BRANCH PREDICTION - Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread. | 2014-07-17 |
20140201509 | SWITCH STATEMENT PREDICTION - Methods and branch predictors for predicting a target location of a jump table switch statement in a program. The method includes continuously monitoring instructions at the branch predictor to determine if they write to registers used to store an input variable to a jump table switch statement. Any update to a monitored register is stored in a register table maintained by the branch predictor. Then when it comes time to make a prediction for a jump table switch statement instruction the branch predictor uses the register value stored in the table is used to predict where the jump table switch statement will branch to. | 2014-07-17 |
20140201510 | SYSTEM, APPARATUS AND METHOD FOR GENERATING A LOOP ALIGNMENT COUNT OR A LOOP ALIGNMENT MASK - A loop alignment instruction indicates a base address of an array as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop alignment instruction, decodes the instruction for execution, and stores a result of the execution in the destination. The result indicates the number of data elements at a beginning of the array that are to be handled separately from a remaining portion of the array, such that the base address of the remaining portion of the array aligns with an alignment width. | 2014-07-17 |
20140201511 | METHOD AND APPARATUS FOR OPTIMIZING OUT OF BAND JOB EXECUTION TIME - A method of performing an out of band (OOB) job at a host is disclosed. A boot option query is transmitted from the host to a service processor. It is then determined if a current boot option is an OOB job. At least one of a job type and a device type associated with the OOB job is identified if the current boot option is an OOB job. An Option ROM and a driver relating to the identified job type and the identified device type is then selectively loaded and the OOB job is performed. | 2014-07-17 |
20140201512 | DATA STORAGE FOR REMOTE ENVIRONMENT - A method can include receiving operating system environment settings via a network; storing the received operating system environment settings to a storage device; establishing an operating system environment according to the stored operating system environment settings; receiving information via the network; instructing the established operating system environment according to the received information; and, in response to the instructing, transmitting via the network information generated at least in part by the established operating system environment. Various other apparatuses, systems, methods, etc., are also disclosed. | 2014-07-17 |
20140201513 | POWER MANAGEMENT CIRCUIT, SERVER, AND POWER MANAGEMENT METHOD THEREOF - A server is provided in the present disclosure, and the server includes a power module, a motherboard circuit, and a power management circuit. The power management circuit is coupled to the motherboard circuit and the power module. The motherboard circuit receives a remote control signal through a network module and outputs a power-off command to the power management circuit according to the remote control signal. The power management circuit causes the power module to stop supplying power to the motherboard circuit for a predetermined time according to the power-off command. After the predetermined time, the power management circuit causes the power module to supply power again to the motherboard circuit to execute an initialization procedure. | 2014-07-17 |
20140201514 | COMPUTER DEVICE AND BOOT METHOD THEREOF - A computer device and a boot method thereof are provided. The method is applicable to a computer with a Basic Input Output System (BIOS) and an Operating System (OS). The computer includes a chassis and a memory. In the boot method, after the computer is started, it is judged whether the chassis is opened in an interval from the last boot time to the current boot time. If the chassis is not opened in the interval from the last boot time to the current boot time, the BIOS does not detect hardware elements connected to the computer to obtain setting and parameter values of each hardware element, but reads directly the setting and parameter values of each hardware element that are stored in the memory last time, initializes each hardware element, transmits the setting and parameter values to the OS, and executes the OS to complete the boot process. | 2014-07-17 |
20140201515 | Imaging process - A user-friendly system, method, and program product for installing an image on a computer, the method comprising: booting the computer ( | 2014-07-17 |
20140201516 | AUTOMATED CONTROL PLANE FOR LIMITED USER DESTRUCTION - To avoid user error and breaking operations, administration and management (OAM), the control plane for implementing OAM is automatically generated by network devices without user input. This control plane is hidden from the user, preventing any configuration that may bring down the connectivity for OAM. | 2014-07-17 |
20140201517 | METHOD AND SYSTEM FOR DISTRIBUTED OFF-LINE LOGON USING ONE-TIME PASSWORDS - A method and a system for extending distributed logon services to an off-line computing device includes encrypting, on the off-line computing device, a one-time password (OTP), a nonce, and a unique identifier to generate an authorization request message. Using a mobile device as a proxy to forward the authorization request message to an access control server for authorization. Decrypting the authorization response message to obtain the nonce. Re-encrypting the nonce to generate an authorization response message. Using the mobile device as a proxy to forward the authorization response message to the off-line computing device. Decrypting the authorization response message to obtain the nonce. Comparing the nonce obtained from the authorization response message with the original nonce. The computing device to permit or deny access as result of comparing the nonce obtained from the authorization response message with the original nonce. | 2014-07-17 |
20140201518 | FRAMEWORK FOR PROVISIONING DEVICES WITH EXTERNALLY ACQUIRED COMPONENT-BASED IDENTITY DATA - A method is provided for updating identity data on devices. The method provides for acquiring a device comprising a component associated with a component identifier and having a One Time Programmable Key installed on the component, submitting the component identifier and the One Time Programmable Key to an External Trust Authority, receiving new identity data tied to the component identifier from the External Trust Authority that is encrypted with the One Time Programmable Key, loading the new identity data onto an Update Server, receiving a request at the Update Server from the device that requests new identity data, and providing the new identity data upon receipt of the request, upon which the device decrypts and installs the identity data using the One Time Programmable Key installed on the component within the device. | 2014-07-17 |
20140201519 | METHOD AND SYSTEM FOR THE SUPPLY OF DATA, TRANSACTIONS AND ELECTRONIC VOTING - A method for supply of data, including generating an empowerment certificate signed with a signing entity's electronic signature. The empowerment certificate includes attributes of a described entity, information identifying the signing entity, indication of data relating to the described entity, indication of a source of the data, and identification of a relying entity to which the data can be supplied. The relying entity forwards the empowerment certificate to a source supplying the data indicated in the empowerment certificate. | 2014-07-17 |
20140201520 | ATTRIBUTE-BASED ACCESS-CONTROLLED DATA-STORAGE SYSTEM - The current application is directed to computationally efficient attribute-based access control that can be used to secure access to stored information in a variety of different types of computational systems. Many of the currently disclosed computationally efficient implementations of attribute-based access control employ hybrid encryption methodologies in which both an attribute-based encryption or a similar, newly-disclosed policy-encryption method as well as a hierarchical-key-derivation method are used to encrypt payload keys that are employed, in turn, to encrypt data that is stored into, and retrieved from, various different types of computational data-storage systems. | 2014-07-17 |
20140201521 | Method and Apparatus for Providing an Adaptable Security Level in an Electronic Communication - A method of communicating in a secure communication system, comprises the steps of assembling a message at a sender, then determining a frame type, and including an indication of the frame type in a header of the message. The message is then sent to a recipient and the frame type used to perform a policy check. | 2014-07-17 |
20140201522 | SYSTEM AND METHOD FOR PREVENTING WEB CRAWLER ACCESS - Preventing web crawler access includes receiving a request for a webpage that includes web content that is to be protected from a web crawler, encrypting the web content to be protected to generate encrypted content and responding to the request, including sending the encrypted content and a decryption instruction. The decryption instruction is configured to allow a web browser to decrypt the encrypted content. | 2014-07-17 |
20140201523 | TRANSMISSION APPARATUS, RECEPTION APPARATUS, COMMUNICATION SYSTEM, TRANSMISSION METHOD, AND RECEPTION METHOD - Provided is a transmission apparatus capable of avoiding unnecessary decryption and preventing a denial-of-service attack. The transmission apparatus that establishes a secure communications channel (SA) between the transmission apparatus and a reception apparatus includes a creation section that creates a packet, an encryption section that, based on a ratio of a redundant packet to the packets created by the packet creation section and on an instruction from the reception apparatus, determines an encryption coverage in the created packet and encrypts data in the encryption coverage, and a transmission section that transmits the encrypted packet through SA. | 2014-07-17 |
20140201524 | Systems and Methods for Securing Data in a Cloud Computing Environment Using In-Memory Techniques and Secret Key Encryption - In one embodiment, a computer-implemented method comprises determining, by a controller, whether a first data store is in an initialization mode. The first data store stores client data. A second data store stores credential data of the first user and credential data of a second user. An application server includes a first secret key store. An in-memory database server includes a second secret key store. The method further comprises, if the first data store is in the initialization mode, receiving, by the controller, from the second user a secret key for encrypting the client data stored in the first data store; and storing, in the first key store, the secret key. The method further comprises, in an operational mode, authenticating the first user based on the credential data of the first user; if the first user is authenticated, processing, in the application server, a user request from the first user. | 2014-07-17 |
20140201525 | SYSTEM AND METHOD FOR MULTI-LAYERED SENSITIVE DATA PROTECTION IN A VIRTUAL COMPUTING ENVIRONMENT - Systems and methods for providing sensitive data protection in a virtual computing environment. The systems and methods utilize a sensitive data control monitor on a virtual appliance machine administering guest virtual machines in a virtual computing environment, wherein each of the guest virtual machines may include a local sensitive data control agent. The sensitive data control monitor generates encryption keys for each guest virtual machine which are sent to the local sensitive data control agents and used to encrypt data locally on a protected guest virtual machine. In this manner the data itself on the virtual (or physical) disc associated with the guest virtual machine is encrypted while access attempts are gated by a combination of the local agent and the environment-based monitor, providing for secure yet administrable sensitive data protection. | 2014-07-17 |
20140201526 | SYSTEM, METHOD, AND APPARATUS FOR DATA, DATA STRUCTURE, OR ENCRYPTION KEY COGNITION INCORPORATING AUTONOMOUS SECURITY PROTECTION - A system, method, and apparatus for securing a date file or a cognitive encryption key data file stored in a storage medium or memory device. The date file or encryption key file having stored instructions for an embedded autonomous executable program which is executed each time there is an attempt to access, control, or manipulate the encryption key file includes querying a user of the date file or encryption key file, the user environment of the date file or encryption key file, or both, for information required for analyzing a computational environment in relation to required security parameters for the cognitive date file or encryption key file. The information in relation to the security parameters is received and analyzed. The computational environment of the user is determined and analyzed in relation to the required security parameters. Access to and/or use of the date file or encryption key file is either permitted or denied based on the analysis of the user and computational environment. Autonomous embedded data cognition enables data, cryptographic data, authentication codes, etc. to perform real-time environmental configuration control, self-manage, self-obfuscate, perform analyses, determine its current situation, and evaluate behavior to respond accordingly. Data-to-data reasoning and analyses can be performed. | 2014-07-17 |
20140201527 | SYSTEMS AND METHODS FOR SECURE AND PRIVATE DELIVERY OF CONTENT - The present solution provides a new tool for privately and securely delivering content from a send to a recipient. Additionally, the tool provides a system and method for ensuring the content is not seen by onlookers, retransmitted, or copied. The system described herein accomplishes the protection of content by several different means. For example, the system may never store unencrypted copies of content to a local device, such that content may not be viewed by a system other than the system described herein. Additionally, the system may overlay an obfuscating layer to the content when the content is displayed on a client device. Such an obfuscating layer prevents onlookers from unintentionally viewing the content. It may also prevent a recipient from capturing a screen shot or copying the content. Furthermore, the system may also set a number of expiring timers on the content. For example, a first expiration timer may automatically delete send content from a recipient device a set time after the content has been sent. A self-destruct expiring timer may delete the content a short time after a user begins to view the content. | 2014-07-17 |
20140201528 | TECHNIQUES TO MONITOR CONNECTION PATHS ON NETWORKED DEVICES - Techniques for managing network connections are described. An apparatus may comprise a communications component operative to manage a connection for a client, the connection routed over a network and a traffic analysis component operative to determine one or more characteristics of the routing of the connection. Other embodiments are described and claimed. | 2014-07-17 |
20140201529 | Method for Communication between Gateways in Wireless Sensor Network (WSN), Initiating Party Gateway and Destination Party Gateway - The disclosure provides a method for communication between gateways in Wireless Sensor Network (WSN), comprising: in a WSN configured with a plurality of gateways, an initiating gateway determining a target gateway with which a telecommunication network communication connection is to be established; the initiating gateway and the target gateway performing authentication, after the authentication is successful, establishing the telecommunication network communication connection between the initiating gateway and the target gateway. The disclosure also discloses an initiating gateway and a target gateway in a WSN. Via solutions of the disclosure, the increase of loads of the WSN caused by communication between gateways inside the WSN can be avoided, and the security of communication between gateways is guaranteed. | 2014-07-17 |
20140201530 | Broadband Certified Mail - The present invention provides system and method for providing certified voice and/or multimedia mail messages in a broadband signed communication system which uses packetized digital information. Cryptography is used to authenticate a message that has been compiled from streaming voice or multimedia packets. A certificate of the originator's identity and electronic signature authenticates the message. A broadband communication system user may be provisioned for certified voice and/or multimedia mail by registering with a certified mail service provider and thereby receiving certification. The called system user's CPE electronically signs the bits in received communication packets and returns the message with an electronic signature of the called system user to the calling party, along with the system user's certificate obtained from the service provider/certifying authority during registration. The electronic signature is a cryptographic key of the called party. | 2014-07-17 |
20140201531 | ENHANCED MOBILE SECURITY - Systems and methods for utilizing a remote server for storing credentials associated with a mobile device. For example, a login credential and/or a token credential can be stored at the remote server rather than at the mobile device. Because these credentials are stored at the remote server, the ecosystem including the mobile device and certain applications or services used by the mobile device can be more secure than conventional architectures. | 2014-07-17 |
20140201532 | ENHANCED MOBILE SECURITY - Systems and methods for utilizing a remote server for storing credentials associated with a mobile device. For example, a login credential and/or a token credential can be stored at the remote server rather than at the mobile device. Because these credentials are stored at the remote server, the ecosystem including the mobile device and certain applications or services used by the mobile device can be more secure than conventional architectures. | 2014-07-17 |
20140201533 | QUORUM-BASED VIRTUAL MACHINE SECURITY - Technologies related to quorum-based Virtual Machine (VM) security are generally described. In some examples, VM data, such as a VM payload or other VM data, may be quorum-encrypted, such that that a quorum of decryption keys may be used to decrypt the data. Decryption keys may be distributed among multiple VMs, with different decryption keys provided to different VMs, so that single VMs may not decrypt the VM data without decryption keys held by other VMs. To decrypt its data, a VM may assemble a quorum of decryption keys by requesting decryption keys held by other operational VMs, and the VM may then decrypt its data using the assembled quorum of decryption keys. The VM may be prevented from decrypting its data without a sufficient quorum of other operational VMs. | 2014-07-17 |
20140201534 | NEAR FIELD COMMUNICATION (NFC) DEVICE AND METHOD FOR SELECTIVELY SECURING RECORDS IN A NEAR FIELD COMMUNICATION DATA EXCHANGE FORMAT (NDEF) MESSAGE - A method and apparatus for selectively securing records in a Near Field Communication Data Exchange Format (NDEF) message in a Near Field Communication (NFC) device are provided. The method includes generating a place marker signature record by setting a URI_present field to ‘0’ and setting a signature_type field to a predefined value, wherein a combination of the URI_present field set to ‘0’ and the signature_type field set to the predefined value indicates that a signature Record Type Definition (RTD) is a place marker signature record; and placing the place marker signature record in the NDEF message, wherein a set of records following the place marker signature record are secured. | 2014-07-17 |
20140201535 | INCORPORATING DATA INTO AN ECDSA SIGNATURE COMPONENT - During generation of a signature on a message to create a signed message, a signer determines one of the signature components such that particular information can be extracted from the signature component. The particular information may be related to one or more of the signer and the message to be signed. After receiving a signed message purported to be signed by the signer, a verifier can extract the particular information from the signature component. | 2014-07-17 |
20140201536 | One-Time Passcodes with Asymmetric Keys - Protecting the security of an entity by using passcodes is disclosed. A user's passcode device generates a passcode. In an embodiment, the passcode is generated in response to receipt of user information. The passcode is received by another system, which authenticates the passcode by at least generating a passcode from a passcode generator, and comparing the generated passcode with the received passcode. The passcode is temporary. At a later use a different passcode is generated from a different passcode generator. In these embodiments, there are asymmetric secrets stored on the passcode device and by the administrator. This adds more security so that if the backend servers are breached, the adversary cannot generate valid passcodes. In some embodiments, the passcode depends on the rounded time. | 2014-07-17 |
20140201537 | MOBILE DEVICE-BASED AUTHENTICATION WITH ENHANCED SECURITY MEASURES PROVIDING FEEDBACK ON A REAL TIME BASIS - The tracking of user authentication is disclosed. A first user biometric data set is received from a mobile device on an authentication server, and a second user biometric data set is received from a site resource on the authentication server. The second user biometric is transmitted from the site resource in response to receipt of an authentication command from the mobile device on the site resource. The user is rejected for access to the site resource in the event of an authentication failure. A security procedure is initiated on at least one of the mobile device and a remote physical device separate from the mobile device in response to the rejecting of the user for access to the site resource. | 2014-07-17 |
20140201538 | SYSTEMS AND METHODS FOR SECURING DATA - Systems and methods are provided for securing data. A processing device receives a data set and identifies a first subset of data from a first dimension of a multi-dimensional representation of the data set. The processing device encrypts the first subset of data using a first encryption technique to yield a first encrypted subset of data and replaces the first subset of data in the multi-dimensional representation of the data set with the first subset of encrypted data. The processing device then identifies a second subset of data from a second dimension of the multi-dimensional representation of the data set, with the second subset of data including at least a portion of the first subset of encrypted data, and encrypts the second subset of data using a second encryption technique to yield a second encrypted subset of data. | 2014-07-17 |
20140201539 | AUTHORIZING REMOVABLE MEDIUM ACCESS - For authorizing removable medium access, a reassembly module retrieves a medium portion of an encryption key from a removable medium. The encryption key encrypts encrypted data stored on the removable medium and includes a plurality of portions. The reassembly module further retrieves the user portion of the encryption key assigned to a user requesting the removable medium. The reassembly module reassembles the encryption key using at least the medium portion and the user portion of the plurality of portions. The decryption module decrypts the encrypted data with the reassembled encryption key. | 2014-07-17 |
20140201540 | SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS - Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor. | 2014-07-17 |
20140201541 | SECURE ONLINE DISTRIBUTED DATA STORAGE SERVICES - The data vaporizer provides secure online distributed data storage services that securely store and retrieve data in a public distributed storage substrate such as public cloud. The data vaporizer vaporizes (e.g., fragmented into tiny chunks of configurable sizes) data and distributes the fragments to multiple storage nodes so that the data is not vulnerable to local disk failures, secures data so that even if some of the storage nodes are compromised, the data is undecipherable to the attacker, stores data across multiple cloud storage providers and/or parties using keys (e.g., tokens) provided by multiple parties (including the owners of the data) and maintains data confidentiality and integrity even where one or more data storage provider is compromised. The data vaporizer is configurable for different domain requirements including data privacy and anonymization requirements, encryption mechanisms, regulatory compliance of storage locations, and backup and recovery constraints. | 2014-07-17 |
20140201542 | ADAPTIVE PERFORMANCE OPTIMIZATION OF SYSTEM-ON-CHIP COMPONENTS - Methods, apparatus, and fabrication relating to adaptive performance optimization of a plurality of components in view of power consumption and demand, component activity, and thermal events. A method may comprise allocating a first power budget to a first component of an apparatus, wherein the first power budget is less than a maximum power required by the first component; applying at least a portion of a borrowable power budget, wherein the borrowable power budget equals the maximum power required by the first component minus the first power budget, to a second component of the apparatus; and increasing the first power budget of the first component, in response to a first number or more of thermal events occurring in a first time period. | 2014-07-17 |
20140201543 | Recharging of the Gate Charge of a Transistor - Power switches operate with reduced power consumption. A circuit controls a power switch via its gate having a gate capacitor. The circuit comprises an on-control switch coupling the gate of the power switch with a charge supply to provide a gate charge to the gate capacitor of the power switch, thereby putting the power switch to the on-state; a transformer and an off-control switch coupling the gate of the power switch with ground via a primary winding of the transformer to discharge the gate capacitor of the power switch, thereby causing a discharge current through the primary winding and thereby putting the power switch to the off-state; wherein a secondary winding is coupled to the charge supply, such that a current, which is induced in the secondary winding, recharges the charge supply. | 2014-07-17 |
20140201544 | EXTERNAL STORAGE DEVICE AND DRIVING METHOD THEREOF - An external storage device comprises a plurality of hard disks, a bridging control unit, a connecting port and a voltage converter circuit. The bridging control unit is coupled to the hard disks and ingrates the hard disks into a redundant array of independent disks. The connecting port is coupled to the bridging control unit and the hard disks. The voltage converter circuit is coupled to the bridging control unit and the connecting port. The external storage device receives through a transmission line a power supplied from an electronic device. The power is transmitted through the connecting port directly to the hard disks in order to drive the hard disks. The voltage converter circuit converts the power and supplies the power to the bridging control unit. It is convenient for user to disconnect an extra power supply apparatus and a voltage transformer. | 2014-07-17 |
20140201545 | EXTERNAL STORAGE DEVICE AND METHOD FOR STARTING UP EXTERNAL STORAGE DEVICE - An external storage device includes a storage unit, a D flip-flop, a power supply, an interface unit, and a processing unit. The interface unit receives an out-of-band (OOB) signal from a host computer and transmits the OOB signal to a clock input terminal of the D flip-flop. The processing unit transmits a reset signal to a data input terminal of the D flip-flop. When the processing unit detects that an output value on a output terminal of the D flip-flop changes, the processing unit controls the power supply to provide power to the storage unit. A method for starting up an external storage device is also provided. | 2014-07-17 |
20140201546 | POWER SUPPLY CONTROL METHOD AND SYSTEM - A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU. | 2014-07-17 |
20140201547 | Selective Precharge for Power Savings - Embodiments of a memory device are disclosed that may allow for detecting the opportunity for energy savings and implementing the energy savings for each access to the memory device. The memory device may include a plurality of columns, an address comparator, and a timing and control circuit. Each of the plurality of columns may include a plurality of data storage cells coupled to a common data line, and a pre-charge circuit that may be configured to charge the common data line to a pre-determined voltage. The address comparator may be configured to compare an address value to a previous address value, and generate an output dependent upon the comparison. The timing and control circuit may then selectively disable pre-charge circuits in the plurality of columns dependent upon the generated output of the address comparator. | 2014-07-17 |
20140201548 | Management of the Interaction Between Security and Operating System Power Management Unit - The present invention relates to a method of controlling the operation of a processing device in a first mode or in a second mode. The processing device has a first execution environment and a second execution environment. The method comprises, upon detection of a switch between said first and second modes, setting in the first execution environment a value of a shared variable to an initial value, upon detection of a request of execution of instructions in the second execution environment, updating the value of said shared variable to a value different from the initial value, and reading a current value of the shared variable and causing the processing device to operate in the first mode or in the second mode depending at least on the current value of the shared variable. | 2014-07-17 |
20140201549 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND COMPUTER PROGRAM PRODUCT - An information processing apparatus includes: a power mode information storage unit that stores power mode information indicating whether a power mode of an electronic apparatus is a first power mode in which at least a first communication unit is operable or a second power mode in which the first communication unit is not operable and a second communication unit is operable; an update unit that updates the power mode information; a determination unit that refers to the power mode information and determines the power mode; a first acquisition unit that, if the power mode is the first power mode, obtains state information from the electronic apparatus via the first communication unit; a state information storage unit that stores the state information; and a second acquisition unit that, if the power mode is the second power mode, obtains the state information from the state information storage unit. | 2014-07-17 |
20140201550 | APPARATUS, METHOD, AND SYSTEM FOR ADAPTIVE COMPENSATION OF REVERSE TEMPERATURE DEPENDENCE - Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD). | 2014-07-17 |
20140201551 | METHOD OF CHANGING OVER COMPUTER FROM POWER-ON STATE TO POWER-SAVING STATE AND COMPUTER - A power state controlling method is provided that balances quick resumption with reduction of power consumption. An upper limit value Pih and a lower limit value Pil of a power idle state are set for the magnitude of power consumption of a system. The power consumption of the system in a power-on state is calculated. The system changes over to a suspended state when a predetermined time elapses after the system changes over to the power idle state with the lowering of the power consumption. | 2014-07-17 |
20140201552 | SLEEP WAKE EVENT LOGGING - A machine implemented method includes creating a universally unique identifier, detecting a trigger of a sleep event, and associating the universally unique identifier with the sleep event. The method monitors sub-system events that occur after a sleep event has been triggered and stores data in non-volatile non-disk storage (e.g., non-boot storage) identifying an event stage corresponding to the sub-system event that is occurring. The method determines whether a wake event has completed and logs each of the sub-system events using the universally unique identifier until a wake event has completed. | 2014-07-17 |
20140201553 | MULTI-ELEMENT MEMORY DEVICE WITH POWER CONTROL FOR INDIVIDUAL ELEMENTS - A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes side-band circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers. | 2014-07-17 |
20140201554 | POWER SOURCE MANAGEMENT DEVICE, POWER SOURCE MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A management server includes a storage unit that stores therein destination physical machine information capable of identifying a physical machine serving as a destination candidate of a certain virtual machine that operates on any one of a plurality of physical machines. The management server includes a control unit that performs the following control. To stop power supply to a first physical machine group performed by a first control unit, the control unit detects. The control unit changes the destination physical machine information such that the destination candidate of the certain virtual machine includes at least a physical machine belonging to a second physical machine group when information capable of identifying the physical machine serving as the destination candidate and stored in the storage unit includes no other physical machine than a physical machine belonging to the first physical machine group. | 2014-07-17 |
20140201555 | METHOD AND SYSTEM FOR GOVERNING AN ENTERPRISE LEVEL GREEN STORAGE SYSTEM DRIVE TECHNIQUE - A method and system for manipulating a spin state of each disk in a drive array is disclosed. In one embodiment, a method includes monitoring input/output (I/O) requests to each disk drive in a disk array and identifying any disk drive as an inactive disk drive based on a number of I/O requests directed to said any disk drive for a given time interval. The method further includes moving data from the inactive disk drive to an active disk drive having a free disk space to store the data and updating metadata associated with the data using a log-structured file system for the disk array. Further, the method includes manipulating a spin state of the inactive disk drive by spinning down the inactive disk drive to conserve power. Furthermore, the method includes redirecting subsequent I/O requests for the inactive disk drive to the active disk drive by accessing the metadata of the log-structured file system. | 2014-07-17 |
20140201556 | MANAGING MODEM POWER CONSUMPTION - Methods, systems, and devices are described for managing power consumption in a modem of a mobile device. A receive power associated with a receiver of the modem may be measured during a scheduled power-up of the modem associated with checking for paging messages. A power consumption metric associated with transmitting a pending wireless data transaction at a transmitter of the modem may then be estimated based on the measured receive power associated with the receiver. A determination of whether to transmit the pending wireless data transaction at a first time may then be made based at least in part on the estimated power consumption metric. | 2014-07-17 |
20140201557 | MONITORING THE TEMPERATURE OF A HIGH POWERED COMPUTING COMPONENT - Methods, systems, and products are provided for monitoring the temperature of a high powered computing component. The high powered computing component has a thermal sensor and the high powered computing component in thermal communication with a liquid cooled heatsink. Embodiments include determining, by a thermal monitoring module, a temperature of the thermal sensor; determining, by the thermal monitoring module, a temperature of the heatsink; determining, by the thermal monitoring module, a power delivered to the high powered computing component; and calculating, by the thermal monitoring module, a thermal value in dependence upon the temperature of the thermal sensor, the temperature of the heatsink, and the power delivered to the high powered computing component. | 2014-07-17 |
20140201558 | MONITORING THE TEMPERATURE OF A HIGH POWERED COMPUTING COMPONENT - Methods, systems, and products are provided for monitoring the temperature of a high powered computing component. The high powered computing component has a thermal sensor and the high powered computing component in thermal communication with a liquid cooled heatsink. Embodiments include determining, by a thermal monitoring module, a temperature of the thermal sensor; determining, by the thermal monitoring module, a temperature of the heatsink; determining, by the thermal monitoring module, a power delivered to the high powered computing component; and calculating, by the thermal monitoring module, a thermal value in dependence upon the temperature of the thermal sensor, the temperature of the heatsink, and the power delivered to the high powered computing component. | 2014-07-17 |
20140201559 | CONTROL SYSTEM AND METHOD FOR FANS - A control system comprises a power distribution unit (PDU), a number of fan modules, a processing module, and a storage module. The PDU comprises a number of power-output terminals. The storage module comprises a number of programs to be executed by the processing unit. The storage module obtains power information output by the power-output terminals, and obtains corresponding control information from a mapping unit according to the power information. The storage module further generates a pulse width modulation (PWM) signal corresponding to the control information, and outputs the PWM signal to a corresponding fan module. | 2014-07-17 |
20140201560 | HIERARCHICAL GLOBAL CLOCK TREE - Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed. | 2014-07-17 |
20140201561 | CLOCK SKEW ANALYSIS AND OPTIMIZATION - A method for adjusting clock skew in a network is disclosed. A model is fit to a first clock input signal received at a first receiver of the network and to a second clock input signal received at a second receiver of the network to obtain a fitted model. A first response signal is simulated using the fitted model and the first clock input signal and a second response signal is simulated using the fitted model and the second clock input signal. A time difference is determined between the simulated first response signal and the simulated second response signal. A parameter of at least one of the network clock network, the first receiver and the second receiver is altered to adjust the determined time difference. | 2014-07-17 |
20140201562 | SYSTEMS AND METHODS FOR OPTIMIZING DATA STORAGE AMONG A PLURALITY OF SOLID STATE MEMORY SUBSYSTEMS - A solid state storage device includes an interface system configured to communicate with an external host system over an aggregated multi-channel interface to receive data for storage by the solid state storage device. The solid state storage device also includes a storage processing system configured to communicate with the interface system to receive the data, process the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transfer the parallelized data. The interface system is configured to receive the parallelized data, apportion the parallelized data among the plurality of solid state memory subsystems, and transfer the parallelized data for storage in the plurality of solid state memory subsystems, where each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium. | 2014-07-17 |
20140201563 | Match Server for a Financial Exchange Having Fault Tolerant Operation - Fault tolerant operation is disclosed for a primary match server of a financial exchange using an active copy-cat instance, a.k.a. backup match server, that mirrors operations in the primary match server, but only after those operations have successfully completed in the primary match server. Fault tolerant logic monitors inputs and outputs of the primary match server and gates those inputs to the backup match server once a given input has been processed. The outputs of the backup match server are then compared with the outputs of the primary match server to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup match server to take over for the primary match server in a fault situation wherein the primary and backup match servers are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment. As such, the primary match server need not be specifically designed or programmed to interact with the fault tolerant mechanisms. Instead, the primary match server need only be designed to adhere to specific basic operating guidelines and shut itself down when it cannot do so. By externally controlling the ability of the primary match server to successfully adhere to its operating guidelines, the fault tolerant mechanisms of the disclosed embodiments can recognize error conditions and easily failover from the primary match server to the backup match server. | 2014-07-17 |
20140201564 | HEALING CLOUD SERVICES DURING UPGRADES - Embodiments described herein are directed to migrating affected services away from a faulted cloud node and to handling faults during an upgrade. In one scenario, a computer system determines that virtual machines running on a first cloud node are in a faulted state. The computer system determines which cloud resources on the first cloud node were allocated to the faulted virtual machine, allocates the determined cloud resources of the first cloud node to a second, different cloud node and re-instantiates the faulted virtual machine on the second, different cloud node using the allocated cloud resources. | 2014-07-17 |
20140201565 | SYSTEM AND METHOD FOR USING FAILURE CASTING TO MANAGE FAILURES IN A COMPUTED SYSTEM - A system and method for using failure casting to manage failures in computer system. In accordance with an embodiment, the system uses a failure casting hierarchy to cast failures of one type into failures of another type. In doing this, the system allows incidents, problems, or failures to be cast into a (typically smaller) set of failures, which the system knows how to handle. In accordance with a particular embodiment, failures can be cast into a category that is considered reboot-curable. If a failure is reboot-curable then rebooting the system will likely cure the problem. Examples include hardware failures, and reboot-specific methods that can be applied to disk failures and to failures within clusters of databases. The system can even be used to handle failures that were hitherto unforeseen failures can be cast into known failures based on the failure symptoms, rather than any underlying cause. | 2014-07-17 |
20140201566 | AUTOMATIC COMPUTER STORAGE MEDIUM DIAGNOSTICS - An approach to providing diagnostics of data storage medium units may be performed automatically without interruption to system operations. Upon receipt of one or more error messages occurring on a first data storage medium unit, data content from the first data storage medium unit may be copied to a second data storage medium unit. A system may operate using the second data storage medium unit while the first data storage medium unit is diagnosed for possible disk failure. | 2014-07-17 |
20140201567 | ENCODING DATA UTILIZING A ZERO INFORMATION GAIN FUNCTION - A method begins by a dispersed storage (DS) processing module encoding data using a dispersed storage error coding function to produce a set of encoded data slices. The method continues with the DS processing module encoding a first encoded data slice of the set of encoded data slices using a zero information gain (ZIG) function based on a second encoded data slice of the set of encoded data slices to produce a ZIG encoded data slice. The method continues with the DS processing module outputting the ZIG encoded data slice and a subset of encoded data slices of the set of encoded data slices, wherein the subset of encoded data slices includes less than a decode threshold number of encoded data slices and does not include the first or the second encoded data slice. | 2014-07-17 |
20140201568 | Flash Memory-Hosted Local and Remote Out-of-Service Platform Manageability - A method, apparatus, and system are disclosed. In one embodiment, the method determines whether one or more manageability conditions are present in a computer system, and then invokes an out-of-service manageability remediation environment stored within a portion of a flash device in the computer system when one or more manageability conditions are present. | 2014-07-17 |
20140201569 | DISASTER RECOVERY IN A NETWORKED COMPUTING ENVIRONMENT - In general, embodiments of the present invention provide a DR solution for a networked computing environment such as a cloud computing environment. Specifically, a customer or the like can select a disaster recovery provider from a pool (at least one) of disaster recovery providers using a customer interface to a DR portal. Similarly, using the interface and DR portal, the customer can then submit a request for DR to be performed for a set (at least one) of applications. The customer will then also submit (via the interface and DR portal) DR information. This information can include, among other things, a set of application images, a set of application files, a set of recovery requirements, a designation of one or more specific (e.g., application) components for which DR is desired, dump file(s), database file(s), etc. Using the DR information, the DR provider will then generate and conduct a set of DR tests and provide the results to the customer via the DR portal and interface. In one embodiment, a temporary DR environment can be created (e.g., by the DR provider or the customer) in which the DR tests are conducted. | 2014-07-17 |
20140201570 | Reset Supervisor - Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal. | 2014-07-17 |
20140201571 | INTELLIGENT CONDITION MONITORING AND FAULT DIAGNOSTIC SYSTEM FOR PREVENTATIVE MAINTENANCE - A system for condition monitoring and fault diagnosis includes a data collection function that acquires time histories of selected variables for one or more of the components, a pre-processing function that calculates specified characteristics of the time histories, an analysis function for evaluating the characteristics to produce one or more hypotheses of a condition of the one or more components, and a reasoning function for determining the condition of the one or more components from the one or more hypotheses. | 2014-07-17 |
20140201572 | PROVISIONING VIRTUAL ENVIRONMENTS BASED ON POLICIES FOR TROUBLESHOOTING PURPOSES - A method for selecting a virtual machine (VM) for problem determination utilizes a policy-based process for receiving an authorized program analysis report (APAR) containing problem type, a client information handling system (IHS) environment, a configuration, and a program version. The method determines automatically that the problem according to a provisioning policy is a candidate for provisioning a VM for analyzing the problem and searches a provisioning database for an existing VM for a system environment and configuration according to a closeness criteria. The method applies required updates to the provisioned VM, and utilizes the provisioned VM with the required updates for problem analysis. The method also may automatically create a new baseline image in the database according to expected value policy criteria that exceeds predetermined criteria. | 2014-07-17 |
20140201573 | DEFECT ANALYSIS SYSTEM FOR ERROR IMPACT REDUCTION - An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to analyze a first set of data associated with a plurality of data sources. Analyzing the first set of data associated with the plurality of data sources determines a plurality of relationships among the first set of data. The processor is configured to store indications of the plurality of relationships among the first set of data. An indication of a relationship indicates a possible software defect. The processor is configured to generate rules based, at least in part, on the first set of data associated with a plurality of data sources. A rule indicates a possible software defect. | 2014-07-17 |
20140201574 | System and Method for Writing Checkpointing Data - In part, the invention relates to a system and method for writing checkpointing data to a computer having a standby virtual machine for each checkpointed component on a computer having an active virtual machine. In one embodiment, the checkpointing data is processed on a per virtual machine basis. This is performed in a way that allows checkpointing data packets from multiple sources to be transferred asynchronously, subsequently reassembled into a coherent checkpoint message, and applied asynchronously. | 2014-07-17 |
20140201575 | MULTI-CORE PROCESSOR COMPARISON ENCODING - Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores. | 2014-07-17 |
20140201576 | System and Method for Improving Solid State Storage System Reliability - A method of operating a storage system. The method includes a storage controller receiving a first life parameter of a first storage device and determining if the first life parameter indicates that the first storage device has a remaining life that is less than a pre-determined life parameter threshold. The method further includes, in response to the remaining life being less than the pre-determined life parameter threshold, designating the first storage device for replacement. | 2014-07-17 |
20140201577 | MANAGEMENT DEVICE, MANAGEMENT METHOD, AND MEDIUM STORING MANAGEMENT PROGRAM - A management device includes a node information storing unit which stores, for each of plural operation devices, an device state representing whether the operation device is in a working state or in a non-working state, the device state associated with an identifier of the operation device, a fault state acquiring unit which acquires a value representing whether or not a fault exists from each of the operation devices that are in the non-working state, and an instruction unit which sends, when a number of the operation devices is smaller than a predetermined value, a work instruction to the operation device from which the value representing that no fault exists is acquired and which is in the non-working state, among the plural operation devices which make a transition to the working state when receiving the work instruction while in the non-working state. | 2014-07-17 |
20140201578 | MULTI-TIER WATCHDOG TIMER - Due to software bugs, hardware bugs, power fluctuations, cosmic rays, and various other causes, computing systems may from time to time enter various types of error states. This disclosure relates generally to the field of watchdog timers configured to take corrective action when a computing system enters such an error state. In various embodiments, this disclosure provides systems, methods, apparatuses, and computer-readable media for multi-tier watchdog timers. Such multi-tier watchdog timers may be configured to take different levels of corrective action at different times and/or under different conditions. | 2014-07-17 |
20140201579 | METHODS AND CIRCUITS FOR DISRUPTING INTEGRATED CIRCUIT FUNCTION - Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays. The finite state machines are sensitive to a predetermined sequence of addresses sent to the memory array or the time between a series of memory array errors detected by an error detection circuit. Upon detection of the pre-set addresses or errors the finite state machines either (i) enable or disable specific circuit functions or (ii) disrupt the operation of the integrated circuit. | 2014-07-17 |
20140201580 | SYSTEMS AND METHODS TO UPDATE REFERENCE VOLTAGES IN RESPONSE TO DATA RETENTION IN NON-VOLATILE MEMORY - A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count. | 2014-07-17 |
20140201581 | DEVICE AND METHOD FOR PERFORMING TIMING ANALYSIS - A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result. | 2014-07-17 |
20140201582 | SCAN CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain. | 2014-07-17 |
20140201583 | System and Method For Non-Intrusive Random Failure Emulation Within an Integrated Circuit - The apparatus and methods allow random hardware failure emulation of an integrated circuit (IC) by emulation of potential defects to enable behavior evaluation of the rest of the design in such situation. This emulation can non-intrusively address multiple points of failure. The emulation is performed in a pseudo-functional mode in order to evaluate the IC behavior in its standard functional mode. The system allows creation of a failure, and tracking both the detection of this failure and the required time for this detection. The system further allows generation of a failure in different points of the IC, on a single or multipoint failure approaches. Failure detection and correction mechanisms for a product life cycle are therefore provided. In an embodiment the system checks the conformity of the safety function of an IC, and makes sure the safety control logic behaves as expected in case of data corruption in any register. | 2014-07-17 |
20140201584 | SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIATED RESET MULTIPLEXING CIRCUITRY - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises control circuitry configured to control selective application of at least a particular one of a plurality of reset signals to reset inputs of at least a subset of the scan cells of the scan chain. For example, the control circuitry may comprise a first reset multiplexer configured to select between a first functional mode reset signal and a first scan mode reset signal for application to reset inputs of respective scan cells of the scan chain, and an additional multiplexer configured to select between an additional functional mode reset signal and an additional scan mode reset signal for application to reset inputs of respective internal flip-flops of the additional circuitry. | 2014-07-17 |
20140201585 | State-Split Based Endec - Various embodiments of the present invention provide systems and methods for encoding and decoding data for constrained systems with state-split based encoders and decoders. | 2014-07-17 |
20140201586 | Latency - The invention relates to an apparatus including at least one processor and at least one memory including a computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to: prepare a transmission of a no-acknowledgement message to be conveyed to a node, when a part of a transport block has been received erroneously or an indication of inadequate quality of at least part of the transport block has been obtained. | 2014-07-17 |
20140201587 | FEC-BASED RELIABLE TRANSPORT CONTROL PROTOCOLS FOR MULTIPATH STREAMING - A client device includes one or more processors configured to receive, from a server device, forward-error corrected data via a plurality of parallel network paths, determine losses of the data over each of the network paths, and send data representing the losses of the data over each of the network paths to the server device. Additionally or alternatively, a client device includes one or more processors configured to receive a first set of encoding units for a first block, wherein the first set of encoding units includes fewer than a minimum number of encoding units needed to recover the first block, after receiving the first set of encoding units, receive a second set of encoding units for a second block, and after receiving the second set of encoding units, receive a third set of encoding units including one or more encoding units for the first block. | 2014-07-17 |
20140201588 | Low density parity check (LDPC) coding in communication systems - A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above). | 2014-07-17 |
20140201589 | SHARED ERROR PROTECTION FOR REGISTER BANKS - A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism. | 2014-07-17 |
20140201590 | Disk Drive with Distributed Codeword Blocks - Disk drives are described in which blocks of data spanning multiple sectors are encoded into a plurality of codewords which are then divided into segments that are physically separated (distributed) on the disk surface over multiple sectors in a distributed codeword block so that the codewords have an improved worst case SNR in comparison to individual sectors. This results in more even SNR performance for each codeword, which improves the performance for portions of a track which have lower than the average SNR. Embodiments are described in which the distributed codeword blocks span across tracks. | 2014-07-17 |
20140201591 | Syndrome Of Degraded Quantum Redundancy Coded States - An apparatus includes a device having n input ports and n output ports. The n input ports are configured to receive n corresponding physical objects of a physically processed, quantum redundancy coded state. The n output ports are configured to output the n physical objects in the physically processed, quantum redundancy coded state. The device is configured to measure bits of a syndrome of the physically processed, quantum redundancy coded state by passing the n physical objects through the device. The device is configured to measure a parity check bit for the measured bits of the syndrome by the passing the n physical objects through the device. | 2014-07-17 |
20140201592 | Very short size LDPC coding for physical and/or control channel signaling - A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above). | 2014-07-17 |
20140201593 | Efficient Memory Architecture for Low Density Parity Check Decoding - A low density parity check (LDPC) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The LDPC decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells. The first-type cells may be a first one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. The second-type cells may be a second one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. | 2014-07-17 |
20140201594 | Low-Power Low Density Parity Check Decoding - In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node. | 2014-07-17 |
20140201595 | RESOLVING TRAPPING SETS - Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for confidence levels associated with digits of the codeword. For a trapping set, the confidence levels associated with the digits corresponding to a failed parity check are adjusted. The method further includes attempting to decode a codeword using the adjusted value for the confidence levels of the digits corresponding to the failed parity check. | 2014-07-17 |
20140201596 | Adaptation of Analog Memory Cell Read Thresholds Using Partial ECC Syndromes - A method includes storing data that is encoded with an Error Correction Code (ECC) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds. The memory cells in the group are divided into two or more subsets. N partial syndromes of the ECC are computed, each partial syndrome computed over readout results that were read using a respective set of the read thresholds from a respective subset of the memory cells. For each possible N-bit combination of N bit values at corresponding bit positions in the N partial syndromes, a respective count of the bit positions in which the combination occurs is determined, so as to produce a plurality of counts. An optimal set of read thresholds is calculated based on the counts, and data recovery is performed using the optimal read thresholds. | 2014-07-17 |