29th week of 2014 patent applcation highlights part 53 |
Patent application number | Title | Published |
20140201397 | EXPANDABLE WIRELESS STORAGE DEVICE FOR STREAMING A MUJLTI-MEDIA FILE - An expandable wireless storage device is provided that includes an interface slot, internal memory, a wireless interface and an aggregated file system view providing component. An external memory, which stores a first subset of multi-media files, can be physically coupled with the expandable wireless storage device using the interface slot. A second subset of multi-media files can be stored on the internal memory. A multi-media file of the multi-media files can be streamed to a playing device using the wireless interface. The internal memory is used as a buffer when the multi-media file resides on the external memory. An aggregated file system view providing component provides an aggregated file system view of the multi-media files. | 2014-07-17 |
20140201398 | RATE CONTROLLED FIRST IN FIRST OUT (FIFO) QUEUES FOR CLOCK DOMAIN CROSSING - First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues. | 2014-07-17 |
20140201399 | USB HUB WITH AUTOMATIC COMMUNICATION MODE SWITCHING - A Universal Serial Bus (USB) hub for allowing communication between a host device and one or more peripheral devices. The USB hub is configured to allow the host device to communicate with the peripheral devices in at least two communication modes and to automatically switch between communication modes in response to the type of connection between the host device and the USB hub. In a first communication mode, the host device is wirelessly coupled to the USB hub and in a second communication mode, the host device is physically coupled (wired-connection) to the USB hub. | 2014-07-17 |
20140201400 | ELECTRONIC TOOL AND METHODS FOR MEETINGS - An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit comprising a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, said program leaving a zero footprint on termination. The user may trigger a transfer of said user selected arbitrary media content to said transmitter. | 2014-07-17 |
20140201401 | INFORMATION PROCESSING APPARATUS, DEVICE CONNECTION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM FOR CONNECTING DEVICE - An information processing apparatus includes: a connection port configured to be capable of attaching a device thereto; an acquisition unit configured to acquire, from a storage unit included in the device, bus-configuration information indicating a bus configuration of the device; and a setting unit configured to set a bus configuration of the connection port based on the bus-configuration information. | 2014-07-17 |
20140201402 | Context Switching with Offload Processors - A memory bus connected module with context switching capability is described. The module can include a memory bus connection compatible with a memory bus socket, a plurality of offload processors attached to the module and connected to a memory bus, with each offload processor having a cache with an associated cache state, a context memory attached to the module and connected to the offload processors, and a scheduling circuit configured to direct a transfer of a cache state between at least one of the offload processors and the context memory. | 2014-07-17 |
20140201403 | DEBUG CONTROL CIRCUIT - An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation. | 2014-07-17 |
20140201404 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory. | 2014-07-17 |
20140201405 | INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES - An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. | 2014-07-17 |
20140201406 | METHOD FOR CONTROLLING TRANSACTION EXCHANGES BETWEEN TWO INTEGRATED CIRCUITS - Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed. | 2014-07-17 |
20140201407 | INTERCONNECT, BUS SYSTEM WITH INTERCONNECT AND BUS SYSTEM OPERATING METHOD - Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master. | 2014-07-17 |
20140201408 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include at least one processor module, including an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a system memory bus; at least one memory; at least one offload processor mounted on the module, and configured to execute operations on data received over the system memory bus, and to output context data to the memory, and read context data from the memory; and hardware scheduling logic including an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the module and configured to control operations of the at least one processor. | 2014-07-17 |
20140201409 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A processor module can include an in-line module connector configured to physically connect to an in-line memory slot of a system memory bus; a data interface configured to receive write data from the system memory bus, via the in-line module connector, and according to a predetermined protocol; and at least one offload processor configured to process the write data according to instruction data within the write data; and wherein hardware scheduling logic mounted in the processor module include an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the in-line module and configured to control operations of the at least one offload processor. | 2014-07-17 |
20140201410 | METHOD AND APPARATUS FOR ADAPTING THE DATA TRANSMISSION SECURITY IN A SERIAL BUS SYSTEM - In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3). | 2014-07-17 |
20140201411 | DEFERRED INTER-PROCESSOR INTERRUPTS - A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI. | 2014-07-17 |
20140201412 | DATA PROCESSING APPARATUS - A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority. | 2014-07-17 |
20140201413 | Method and Apparatus for Backplane Support of 100/1000 Ethernet - A method and apparatus for backplane support of 100/1000 Ethernet. A communication card for use in a chassis system is provided that includes a 100BASE-TX physical layer device component, a 1000BASE-KX physical layer device component, and a backplane connector, which is configured for enabling communication by the communication card over a backplane of the chassis system. The communication card also includes a selection module (e.g., a multiplexer) that is configured to selectively couple one of the 100BASE-TX physical layer device component and the 1000BASE-KX physical layer device component to the backplane connector, wherein the selective coupling enables a selected one of the 100BASE-TX physical layer device component and the 1000BASE-KX physical layer device component to communicate with a second communication card via the backplane of the chassis system. | 2014-07-17 |
20140201414 | PORTABLE INSTRUMENT AND DOCKING STATION WITH DIVIDED UNIVERSAL SERIAL BUS COMMUNICATION DEVICE - A universal serial bus (USB) communication system includes a portable instrument and a docking station that communicate with a host device using a divided USB communication device. A first portion of the USB communication device is provided in the portable instrument. A second portion of the USB communication device is provided in the docking station. The first portion includes a non-USB communication device that communicates with the second portion in a non-USB format. The second portion converts the communications into a USB format suitable for the host device. | 2014-07-17 |
20140201415 | WIRELESS DOCKING SERVICE WITH DIRECT CONNECTION TO PERIPHERALS - In one example, a method includes receiving, from a user application and with a wireless docking service of a wireless docking communications stack executing on a computing device, a request to discover one or more peripheral functions within wireless communication range of the computing device. The method also includes, responsive to receiving the request, discovering, with the wireless docking service, the one or more peripheral functions without communicating with a wireless docking center. The method further includes consolidating the peripheral functions into a docking session for the user application. The method also includes, responsive to receiving the request, sending a docking session identifier and one or more respective references corresponding to the one or more peripheral functions to the user application. | 2014-07-17 |
20140201416 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A method can include receiving write data over a system memory bus via an in-line module connector, the write data including a metadata portion identifying a processing to be performed on at least a portion of the write data; performing the processing on at least a portion of the write data with at least one offload processor mounted on a module having the in-line module connector to generate processed data; and transmitting the processed data over the system memory bus; wherein the system memory bus is further connected to at least one processor connector configured to receive at least one host processor different from the at least one offload processor. | 2014-07-17 |
20140201417 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor. | 2014-07-17 |
20140201418 | Net-centric adapter for interfacing enterprises systems to legacy systems - A configurable system for translating, exchanging and integrating data and services among disparate software applications is provided. The system includes a first connection that interfaces with an enterprise system, a second connection that interfaces with a legacy system, and an adapter module coupled to the first and second connections. The adapter module is configured to receive data from the first connection and pass data to the second connection. The system may also include a transform module configured to manipulate data received at the second connection. The adapter module may be single-channel or multi-channel. A multi-channel adapter module is able to interface with multiple legacy systems and/or multiple enterprise systems. | 2014-07-17 |
20140201419 | EXECUTING VIRTUAL FUNCTIONS USING MEMORY-BASED DATA IN A PCI EXPRESS SR-IOV AND MR-IOV ENVIRONMENT - A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result. | 2014-07-17 |
20140201420 | TRANSMISSION INTERFACE SYSTEM WITH DETECTION FUNCTION AND METHOD - A transmission interface system includes a connector; a detecting unit, a control unit, a chipset and a resetting unit. The connector includes lots of transmission interfaces. The detecting unit detects the data type of the current transmitting data and outputs a detecting signal; the control unit receives the detecting signal and informs the resetting unit to output a resetting signal to the chipset. The chipset is reset after receiving the resetting signal, and then the control unit informs the chipset to output a data signal corresponding to the data type of the current transmitting data to the connector. | 2014-07-17 |
20140201421 | INDEXED PAGE ADDRESS TRANSLATION TO REDUCE MEMORY FOOTPRINT IN VIRTUALIZED ENVIRONMENTS - Embodiments of systems, apparatuses, and methods for performing guest logical memory address to host physical memory address translation are described. In some embodiments, a system receives the guest logical memory address and determines an index page reference from the guest logical memory address. The system further retrieves a page index corresponding to the virtual machine. In addition, the system retrieves a first part of the host physical memory address from index page using the page index and a second part of the host physical memory address from the guest logical memory address. The system generates the host physical memory address from the first and second parts of the host physical memory address. | 2014-07-17 |
20140201422 | DETERMINING POLICY ACTIONS FOR THE HANDLING OF DATA READ/WRITE EXTENDED PAGE TABLE VIOLATIONS - Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are described. In some embodiments, a system detects an indication of an attempt by the instruction to write to the protected memory region. In addition, the system determines if the instruction is allowed to write to the protected memory region based on a starting address and data length of the instruction. Furthermore, if the instruction is allowed to write to the protected memory region, the system updates the protected memory region with the instruction results. | 2014-07-17 |
20140201423 | SYSTEMS AND METHODS OF CONFIGURING A MODE OF OPERATION IN A SOLID-STATE MEMORY - Disclosed herein is an architecture that pairs a controller with a NVM (non-volatile memory) storage system. The NVM storage system includes a bridge device that communicates with the controller. In one embodiment, the bridge device allows for certain data locations (blocks, pages or units at any other granularity) in the flash dies to be (1) placed into a reserved mode where data access is prevented (2) assigned into an SLC (Single-Level Cell) mode or an MLC (Multi-Level Cell) mode in response to controller command, (3) made available for data access after the assignment of mode. This flexibility enables the controller to increase SLC mode or MLC mode data locations based on run-time conditions. In one embodiment, the assignment of the reserved data locations is performed in a way to ensure that warranty conditions imposed by the memory vendors are observed. | 2014-07-17 |
20140201424 | DATA MANAGEMENT FOR A DATA STORAGE DEVICE - Managing data stored in at least one data storage device (DSD) of a computer system where the at least one DSD includes at least one disk for storing data. A Linear Tape File System (LTFS) write or read command is generated including an LTFS block address. The LTFS block address is translated to a device address for the at least one DSD and data on a disk of the at least one DSD is written or read at the device address. | 2014-07-17 |
20140201425 | ORCHESTRATING MANAGEMENT OPERATIONS AMONG A PLURALITY OF INTELLIGENT STORAGE ELEMENTS - An apparatus and associated methodology contemplating a data storage system having a group of processor-controlled intelligent storage elements (ISEs). Each ISE in the group individually includes storage resources and a network interface. The storage resources of all the ISEs in the group collectively define a field of storage (FoS). A portion of the FoS is addressable by a remote device or by another ISE via the respective ISE's network interface. An ISE FoS structure (ISEFoS) is individually stored in nonvolatile memory within each of the ISEs in the group. Each ISEFoS contains parametric data pertaining to every ISE in the group. Orchestration logic executed by one of the ISEs of the group (a recipient ISE), in response to the recipient ISE receiving a storage management operation request via the network interface, queries the recipient ISE's ISEFoS in order to optimally determine which ISE in the group to use in executing the storage management operation request. | 2014-07-17 |
20140201426 | Page Allocation for Flash Memories - Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to write the multiple data elements to the flash memory. Example technologies may identify a correlation between a subset of the data elements based on correlation criteria. Example technologies may allocate neighboring pages of the flash memory for storing the subset of the data elements. Example technologies may write the subset of the data elements into the allocated pages. | 2014-07-17 |
20140201427 | STORAGE CONTROL APPARATUS, DATA STORAGE APPARATUS AND METHOD FOR STORAGE CONTROL - According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host. The second buffer controller is configured to independently transmit data of a second unit from the data buffer region corresponding to a bank prepared for transmission when data is written in the nonvolatile memory, and to independently transmit data of the second unit from a bank to be read to the data buffer region corresponding to the bank to be read when data is transmitted to the host. | 2014-07-17 |
20140201428 | CONSISTENT, DISK-BACKED ARRAYS - Disk-backed array techniques can, in some implementations, help ensure that the arrays contain consistent data. An alert can be provided if it is determined that the data in the array is, or may be, corrupted. | 2014-07-17 |
20140201429 | SSD-BLOCK ALIGNED WRITES - An SSD, comprising a mapping module and a controller, mapping module is capable of mapping a plurality of SSD-block aligned groups, each comprises a specific sequence of LBAs, to SSD blocks. The controller is capable of determining whether a LBA referenced in an incoming write request is a first LBA in a respective group, and if so, the controller is capable of: opening an ongoing SSD-block aligned write session; assigning a SSD block to the session; and recording in the session's data an indication of which LBA is associated with the write data that was saved to the SSD. In case the LBA referenced in the incoming write request is not the first LBA in the respective group, but is a successor of a latest-saved LBA of the group, storing the write data in sequence with a latest used segment of the SSD-block that was assigned to the group. | 2014-07-17 |
20140201430 | SNAPSHOTTING OF A PERFORMANCE STORAGE SYSTEM IN A SYSTEM FOR PERFORMANCE IMPROVEMENT OF A CAPACITY OPTIMIZED STORAGE SYSTEM - A system for storing data comprises a performance storage system for storing one or more data items. A data item of the one or more data items comprises a data file or a data block. The system further comprises a segment storage system for storing a snapshot of a stored data item of the one or more data items in the performance storage system. The taking of the snapshot of the stored data item enables recall of the stored data item as stored at a time of the snapshot. At least one newly stored segment is stored as a reference to a previously stored segment. | 2014-07-17 |
20140201431 | DISTRIBUTED PROCEDURE EXECUTION AND FILE SYSTEMS ON A MEMORY INTERFACE - Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a DRAM memory channel. Nonvolatile memory residing on a DRAM memory channel may be integrated into the existing file system structures of operating systems. The nonvolatile memory residing on a DRAM memory channel may be presented as part or all of a distributed file system. Requests and/or remote procedure call (RPC) requests, or information associated with requests and/or RPCs, may be routed to the memory modules over the DRAM memory channel in order to service compute and/or distributed file system commands. | 2014-07-17 |
20140201432 | PERSISTENT BLOCK STORAGE ATTACHED TO MEMORY BUS - A method of configuring a computer memory system includes receiving a request from customized software driver or a BIOS extension software or a customized legacy BIOS or a customized UEFI PMM extension software or a customized UEFI BIOS, scanning memory module sockets in response to the request, recognizing memory modules in the memory module sockets, the memory modules being made of, at least in part, persistent memory modules (PMMs), configuring the PMMs to be invisible to the OS, and storing the mapping information to a designated protected persistent memory area, and presenting the PMMs as a persistent block storage to the OS. | 2014-07-17 |
20140201433 | SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. | 2014-07-17 |
20140201434 | Managing Volatile File Copies - Persistent files are copied from persistent memory to volatile memory to yield volatile files. At least some requests to open for writing or to close to writing persistent files are redirected to the corresponding volatile files. Openings to writing and closings to writing of volatile files are tracked to yield a synchronization record. Persistent files are synchronized to volatile files based on the synchronization record. | 2014-07-17 |
20140201435 | HETEROGENEOUS MEMORY SYSTEMS, AND RELATED METHODS AND COMPUTER-READABLE MEDIA FOR SUPPORTING HETEROGENEOUS MEMORY ACCESS REQUESTS IN PROCESSOR-BASED SYSTEMS - Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage. | 2014-07-17 |
20140201436 | DRAM Memory Interface - It is proposed a DRAM memory interface ( | 2014-07-17 |
20140201437 | Modifying Logical Addressing at a Requestor Level - Method and apparatus for managing data in a memory. In accordance with some embodiments, a control circuit monitors access operations upon a set of data blocks in a memory of a data storage device. The data blocks have a first logical address by which the data blocks are identified by a requestor coupled to the data storage device. When the monitored access operations indicate a potential data degradation condition may arise with the data blocks, the requestor assigns a different, second logical address to the data block. | 2014-07-17 |
20140201438 | STORAGE SYSTEM, METHOD OF CONTROLLING A STORAGE SYSTEM AND MANAGEMENT SYSTEM FOR STORAGE SYSTEM - An example is a method of controlling a storage system for providing a virtual storage apparatus that includes virtual storage resources associated with real storage resources of real storage apparatus. It includes receiving a virtual storage resource control command of a predetermined type specifying a first virtual storage resource in the virtual storage apparatus and a second virtual storage resource associated with the first virtual storage resource; referring to management information for managing association relations between the virtual storage resources and the real storage resources, to identify a first real storage resource associated with the first virtual storage resource and a first real storage apparatus including the first real storage resource; and selecting a second real storage resource associated with the second virtual storage resource from real storage resources within the first real storage apparatus, or creating the second real storage resource within the first real storage apparatus. | 2014-07-17 |
20140201439 | STORAGE DEVICE AND STORAGE METHOD - According to an embodiment, a storage device includes a plurality of memory nodes and a control unit. Each of the memory nodes includes a storage unit including a plurality of storage areas having a predetermined size. The memory nodes are connected to each other in two or more different directions. The memory nodes constitute two or more groups each including two or more memory nodes. The control unit is configured to sequentially allocate data writing destinations in the storage units to the storage areas respectively included in the different groups. | 2014-07-17 |
20140201440 | EFFICIENT CONNECTION MANAGEMENT IN A SAS TARGET - A method includes pre-configuring a hardware-implemented front-end of a storage device with multiple contexts of respective connections conducted between one or more hosts and the storage device. Storage commands, which are received in the storage device and are associated with the connections having the pre-configured contexts, are executed in a memory of the storage device using the hardware-implemented front-end. Upon identifying a storage command associated with a context that is not pre-configured in the hardware-implemented front-end, software of the storage device is triggered to configure the context in the hardware-implemented front-end, and the storage command is then executed using the hardware-implemented front-end in accordance with the context configured by the software. | 2014-07-17 |
20140201441 | Surviving Write Errors By Using Copy-On-Write To Another System - In one embodiment, a method may include performing a copy-on-write in response to a write error from a first system, where the copy-on-write copies to a second system. The method may further include receiving a write request at the first system from a third system. The method may additionally include storing the data from the write request in a cache. The method may also include reporting successful execution of the write request. The method may further include writing data from the write request to a drive in the first system. The method may additionally include receiving the write error from the drive. In an additional embodiment, performing the copy-on-write may use the data stored in the cache. | 2014-07-17 |
20140201442 | CACHE BASED STORAGE CONTROLLER - Systems and techniques for continuously writing to a secondary storage cache are described. A data storage region of a secondary storage cache is divided into a first cache region and a second cache region. A data storage threshold for the first cache region is determined. Data is stored in the first cache region until the data storage threshold is met. Then, additional data is stored in the second cache region while the data stored in the first cache region is written back to a primary storage device. | 2014-07-17 |
20140201443 | INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM - In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network. | 2014-07-17 |
20140201444 | INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM - In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network. | 2014-07-17 |
20140201445 | INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM - In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network. | 2014-07-17 |
20140201446 | HIGH BANDWIDTH FULL-BLOCK WRITE COMMANDS - A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received. | 2014-07-17 |
20140201447 | DATA PROCESSING APPARATUS AND METHOD FOR HANDLING PERFORMANCE OF A CACHE MAINTENANCE OPERATION - A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation. | 2014-07-17 |
20140201448 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. | 2014-07-17 |
20140201449 | DATA CACHE WAY PREDICTION - In a particular embodiment, a method, includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively reading, based on identification of the one or more way prediction characteristics, a table to identify an entry of the table associated with the instruction that identifies a way of a data cache. The method further includes making a prediction whether a next access of the data cache based, on the instruction will access the way. | 2014-07-17 |
20140201450 | Optimized Matrix and Vector Operations In Instruction Limited Algorithms That Perform EOS Calculations - There is provided a system and method for optimizing matrix and vector calculations in instruction limited algorithms that perform EOS calculations. The method includes dividing each matrix associated with an EOS stability equation and an EOS phase split equation into a number of tiles, wherein the tile size is heterogeneous or homogenous. Each vector associated with the EOS stability equation and the EOS phase split equation may be divided into a number of strips. The tiles and strips may be stored in main memory, cache, or registers, and the matrix and vector operations associated with successive substitutions and Newton iterations may be performed in parallel using the tiles and strips. | 2014-07-17 |
20140201451 | METHOD, APPARATUS AND COMPUTER PROGRAMS PROVIDING CLUSTER-WIDE PAGE MANAGEMENT - A data processing system includes a plurality of virtual machines each having associated memory pages; a shared memory page cache that is accessible by each of the plurality of virtual machines; and a global hash map that is accessible by each of the plurality of virtual machines. The data processing system is configured such that, for a particular memory page stored in the shared memory page cache that is associated with two or more of the plurality of virtual machines, there is a single key stored in the global hash map that identifies at least a storage location in the shared memory page cache of the particular memory page. The system can be embodied at least partially in a cloud computing system. | 2014-07-17 |
20140201452 | FILL PARTITIONING OF A SHARED CACHE - Fill partitioning of a shared cache is described. In an embodiment, all threads running in a processor are able to access any data stored in the shared cache; however, in the event of a cache miss, a thread may be restricted such that it can only store data in a portion of the shared cache. The restrictions to storing data may be implemented for all cache miss events or for only a subset of those events. For example, the restrictions may be implemented only when the shared cache is full and/or only for particular threads. The restrictions may also be applied dynamically, for example, based on conditions associated with the cache. Different portions may be defined for different threads (e.g. in a multi-threaded processor) and these different portions may, for example, be separate and non-overlapping. Fill partitioning may be applied to any on-chip cache, for example, a L1 cache. | 2014-07-17 |
20140201453 | Context Switching with Offload Processors - A context switching cache system is disclosed. The system can include a plurality of offload processors connected to a memory bus, each offload processor having a cache with an associated cache state, a context memory coupled to the offload processors, and a scheduling circuit configured to direct transfer of a cache state between at least one of the offload processors and the context memory. | 2014-07-17 |
20140201454 | Methods And Systems For Pushing Dirty Linefill Buffer Contents To External Bus Upon Linefill Request Failures - Methods and systems are disclosed for recovering dirty linefill buffer data upon linefill request failures. When a linefill request failure occurs and the linefill buffer has been marked as dirty, such as due to a system bus failure, the contents of the linefill buffer are pushed back to the system bus. The dirty data within the linefill buffer can then be used to update the external memory. The disclosed embodiments are useful for a wide variety of applications, including those requiring low data failure rates. | 2014-07-17 |
20140201455 | METHOD FOR INCREASING CACHE SIZE - A method for increasing storage space in a system containing a block data storage device, a memory, and a processor is provided. Generally, the processor is configured by the memory to tag metadata of a data block of the block storage device indicating the block as free, used, or semifree. The free tag indicates the data block is available to the system for storing data when needed, the used tag indicates the data block contains application data, and the semifree tag indicates the data block contains cache data and is available to the system for storing application data type if no blocks marked with the free tag are available to the system. | 2014-07-17 |
20140201456 | Control Of Processor Cache Memory Occupancy - Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described. | 2014-07-17 |
20140201457 | IDENTIFYING AND RESOLVING CACHE POISONING - According to some embodiments, a method and apparatus are provided to receive, at a cache entity, a refresh request associated with a resource. A determination is made, via a processor, and based on the refresh request, to reload the resource from a server. The reloaded resource is replaced at the cache entity. | 2014-07-17 |
20140201458 | REDUCING CACHE MEMORY REQUIREMENTS FOR RECORDING STATISTICS FROM TESTING WITH A MULTIPLICITY OF FLOWS - A method reduces cache memory requirements for testing a multiplicity of flows. The method includes receiving data corresponding to a frame in a particular flow among the multiplicity of flows. In response to the frame received, the method updates a set of cached flow counters in cache memory for the particular flow. The method updates one or more regular operation counters and one or more conditional counters among the set of cached flow counters, including a last serviced counter. The method updates, responsive to any error conditions, one or more error condition counters among the set of cached flow counters. The method evaluates whether to transfer values from the cached flow counters to system accumulators in system memory using at least a value in the last serviced counter for the particular flow. Responsive to the evaluating, the method transfers the values from the cached flow counters to the system accumulators. | 2014-07-17 |
20140201459 | OPTIMIZED CACHING BASED ON HISTORICAL PRODUCTION PATTERNS FOR CATALOGS - A method, system and computer readable medium that predict times where cost of catalog caching is not efficient and deactivating catalog caching for that catalog during the predicted times. More specifically, an optimized catalog caching operation conducts historical analysis on catalog usage via records such as resource measurement facility (RMF) records and catalog statistical data. | 2014-07-17 |
20140201460 | DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor. | 2014-07-17 |
20140201461 | Context Switching with Offload Processors - A method for context switching of multiple offload processors coupled to receive data for processing over a memory bus is disclosed. The method can include directing storage of a cache state, via a bulk read from a cache of at least one of a plurality of offload processors into a context memory, by operation of a scheduling circuit, with any virtual and physical memory locations of the cache state being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing, by operation of the scheduling circuit. | 2014-07-17 |
20140201462 | Subtractive Validation of Cache Lines for Virtual Machines - A method and system for managing a cache for a host machine is disclosed. The method includes: indicating each cache line in the cache as being in a transitional meta-state when any virtual machine hosted on the host machine moves out of the host machine; each time a particular cache line is accessed, indicating that particular cache line as no longer in the transitional meta-state; and marking the cache lines still in the transitional meta-state as invalid when a virtual machine moves back to the host machine. | 2014-07-17 |
20140201463 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 2014-07-17 |
20140201464 | EPOCH-BASED RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure. | 2014-07-17 |
20140201465 | ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order. | 2014-07-17 |
20140201466 | DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor. | 2014-07-17 |
20140201467 | EPOCH-BASED RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure. | 2014-07-17 |
20140201468 | ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order. | 2014-07-17 |
20140201469 | SHARED OP-SYMMETRIC UPDATE-SENSITIVE VARIABLES - Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address. | 2014-07-17 |
20140201470 | SHARED OP-SYMMETRIC UPDATE-SENSITIVE VARIABLES - Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address. | 2014-07-17 |
20140201471 | Arbitrating Memory Accesses Via A Shared Memory Fabric - In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed. | 2014-07-17 |
20140201472 | INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM - In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network. | 2014-07-17 |
20140201473 | HOST CONTROLLED ENABLEMENT OF AUTOMATIC BACKGROUND OPERATIONS IN A MEMORY DEVICE - A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations. | 2014-07-17 |
20140201474 | ON-DISK MULTIMAP - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for storing data on in a storage medium. In one aspect, a method includes receiving a key-value pair including a key k and a value v. The method further includes encoding the key-value pair as (i) a first key-value pair including a first key k1 and first value v1, and (ii) a second key-value pair including a second key k2. The method further includes inserting the first key-value pair and the second key-value pair in a trie. | 2014-07-17 |
20140201475 | INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING THE SAME - An information processing system in which a plurality of information processing apparatuses are connected with each other, wherein each information processing apparatus includes a storage unit configured to store data according to each destination information processing apparatus, and a transmission control unit configured to transmit data to be transmitted in the same transmission direction and with the same number of hops collectively among the data stored in the storage unit. | 2014-07-17 |
20140201476 | EVENT-BASED EXECUTION BUFFER MANAGEMENT - Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed. | 2014-07-17 |
20140201477 | METHODS AND APPARATUS TO MANAGE WORKLOAD MEMORY ALLOCATION - Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements. | 2014-07-17 |
20140201478 | De-Duplication Aware Secure Delete - A mechanism is provided in a data processing system for de-duplication aware secure delete. Responsive to receiving a secure delete request for a file, the mechanism identifies a list of file blocks to be securely deleted from a physical disk device. Responsive to determining at least one virtual block of another file refers to a given disk block corresponding to a file block in the list, the mechanism copies the given disk block to generate a copied disk block in the physical disk device and updates a pointer of the at least one virtual block to refer to the copied disk block. The mechanism writes a secure delete pattern for each file block in the list of file blocks to a disk block in the physical disk device without performing de-duplication processing. | 2014-07-17 |
20140201479 | INTEGRATED CIRCUIT DEVICE, MEMORY INTERFACE MODULE, DATA PROCESSING SYSTEM AND METHOD FOR PROVIDING DATA ACCESS CONTROL - An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer. | 2014-07-17 |
20140201480 | Data Recovery Scheme Based on Data Backup Status - Machines, systems and methods for increasing data resiliency in a computing system, the method comprising distinguishing between first data and second data stored in one or more data storage mediums, wherein the first data is more vulnerable than the second data for the purpose of recovering lost data; and recovering the first data before recovering the second data. Increasing redundancy protection for the first data to increase chances for data recovery by way of data reconstruction; and decreasing redundancy protection for the first data, after the first data has been backed up at least once. | 2014-07-17 |
20140201481 | DOMAIN PROTECTION AND VIRTUALIZATION FOR SATA - Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the system processor and has commands from one or more VMs. | 2014-07-17 |
20140201482 | SELECTING FIRST DATA SETS IN A FIRST STORAGE GROUP TO SWAP WITH SECOND DATA SETS IN A SECOND STORAGE GROUP - Provided are a computer program product, system, and method for selecting first data sets in a first storage group to swap with second data sets in a second storage group. First data sets are stored in a first storage group and second data sets are stored in a second storage group. A determination is made for a value for each of at least one of the first data sets based on at least one priority of at least one job processing I/O activity at the first data set. At least one of the first data sets for which the value was determined is selected to migrate to the second storage group based on the value. | 2014-07-17 |
20140201483 | STORAGE DEVICE AND METHOD FOR BACKING UP SOURCE VOLUME - A storage device includes a source volume and a processor. The source volume includes a plurality of data blocks. The processor is configured to execute a full copy process of copying all data blocks of the source volume to form a full backup volume. The processor is configured to execute, at a generation change timing of changing from a current generation to a next generation, a difference copy process of copying a first data block that has been updated in the current generation into a corresponding region of the full backup volume. The processor is configured to execute a generation backup process of storing the first data block of a previous generation in a generation backup volume corresponding to the current generation. | 2014-07-17 |
20140201484 | DATA ACCESS AND MANAGEMENT SYSTEM AS WELL AS A METHOD FOR DATA ACCESS AND DATA MANAGEMENT FOR A COMPUTER SYSTEM - The present invention permits improved data access and improved data management in a computer system. To this end, data are divided into individual partial data (F) and stored in cells (Z) of storage devices (C) in such a way that the partial data (F) being accessed and managed are present in the computer system in a redundant manner. Computer units (CL) are able to access the redundantly stored data. The fact that they are stored in the storage devices (C) ensures that the computer units (CL) accessing said data are supplied more rapidly. This is achieved in particular owing to the fact that the redundantly stored data are accessed in accordance with parameters of data transmissions between the computer units (CL) and the data storage devices (C) and that, in accordance with said data transmission parameters, the redundantly stored data are moved to and from the data storage devices (C) by corresponding copy and delete operations. | 2014-07-17 |
20140201485 | PST FILE ARCHIVING - According to certain aspects, systems and methods for archiving and/or backing up PST files or other mail or calendar data, or the like (“off-line mail data”) are provided. Off-line mail data can be searched for in a client computer system, a copy of which may be transferred to secondary storage. Further, emails, contacts, calendar data, and/or the like (e.g., Microsoft Outlook data) contained in the transferred off-line mail data may be extracted, wherein it is determined whether copies of the data already exist backup data. Off-line mail data that already exists in backup can be deleted from the PST file. Following back-up of the off-line mail data, the backed up file may be deleted from the client system and/or the creation of future off-line mail files may be disabled. | 2014-07-17 |
20140201486 | CONTINUOUS DATA BACKUP USING REAL TIME DELTA STORAGE - A continuous data backup using real time delta storage has been presented. A backup appliance receives a backup request from a backup agent running on a computing machine to backup data on the computing machine. The computing machine is communicatively coupled to the backup appliance. Then the backup appliance performs block-based real-time backup of the data on the computing machine. The backup appliance stores backup data of the computing machine in a computer-readable storage device in the backup appliance. | 2014-07-17 |
20140201487 | SELECTING FIRST DATA SETS IN A FIRST STORAGE GROUP TO SWAP WITH SECOND DATA SETS IN A SECOND STORAGE GROUP - Provided are a computer program product, system, and method for selecting first data sets in a first storage group to swap with second data sets in a second storage group. First data sets are stored in a first storage group and second data sets are stored in a second storage group. A determination is made for a value for each of at least one of the first data sets based on at least one priority of at least one job processing I/O activity at the first data set. At least one of the first data sets for which the value was determined is selected to migrate to the second storage group based on the value. | 2014-07-17 |
20140201488 | EVENT-BASED EXECUTION BUFFER MANAGEMENT - Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed. | 2014-07-17 |
20140201489 | METHOD AND APPARATUS FOR DATA REDUCTION - Embodiments of the invention provide data reduction in storage systems. In one embodiment, a computer comprises: a memory; and a controller operable to manage information, which corresponds to a plurality of addresses, of one or more volumes provided from a storage system to the computer and including at least one set of multiple storage areas sharing same data to be stored in the storage system. The controller is operable to manage storing of the shared same data in the memory of the computer by using the information of the storage areas. | 2014-07-17 |
20140201490 | METHOD AND SYSTEM FOR DYNAMICALLY CHANGING PAGE ALLOCATOR - A method and a system of dynamically changing a page allocator are provided. The method includes determining a state of a page allocation system; and forking a child page allocator from a parent page allocator, or merging a child page allocator into a parent page allocator, based on the determination. | 2014-07-17 |
20140201491 | EFFICIENT ALLOCATION AND RECLAMATION OF THIN-PROVISIONED STORAGE - Embodiments of the inventions relate to granular management of data storage blocks in a data storage system. In one aspect, status values are employed to track “used”, “free”, and “claimed free” storage blocks. A storage block having stored data is identified as used, a storage block available to store data is identified as free, and a storage block having previously stored data removed that has not been reclaimed is identified as claimed free. These values are maintained on a map to track each data block within the data storage system. Available claimed free data blocks are prioritized for data block allocation over available free data blocks for efficient storage, including enabling efficient reclamation of data blocks and minimizing data movement needed for reclamation-oriented de-fragmentation. | 2014-07-17 |
20140201492 | EFFICIENT ALLOCATION AND RECLAMATION OF THIN-PROVISIONED STORAGE - Embodiments of the inventions relate to granular management of data storage blocks in a data storage system. In one aspect, status values are employed to track “used”, “free”, and “claimed free” storage blocks. A storage block having stored data is identified as used, a storage block available to store data is identified as free, and a storage block having previously stored data removed that has not been reclaimed is identified as claimed free. These values are maintained on a map to track each data block within the data storage system. Available claimed free data blocks are prioritized for data block allocation over available free data blocks for efficient storage, including enabling efficient reclamation of data blocks and minimizing data movement needed for reclamation-oriented de-fragmentation. | 2014-07-17 |
20140201493 | OPTIMIZING LARGE PAGE PROCESSING - Embodiments of the disclosure include a method for optimizing large page processing. The method includes receiving an indication that a real memory includes a first page. The first page includes a plurality of smaller pages. The method also includes determining a page frame table entry associated with a first smaller page of the first page and storing data associated with the first page in the page frame table entry associated with the first smaller page. The page frame table entry associated with the first smaller page of the first page is a data repository for the plurality of smaller pages of the first page. | 2014-07-17 |
20140201494 | OVERLAP CHECKING FOR A TRANSLATION LOOKASIDE BUFFER (TLB) - An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page. | 2014-07-17 |
20140201495 | PAGE MISS HANDLER INCLUDING WEAR LEVELING LOGIC - Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead. | 2014-07-17 |
20140201496 | RESERVING FIXED AREAS IN REAL STORAGE INCREMENTS - Embodiments of the disclosure include a method for reserving large pages in a large frame area (LFAREA) of a main memory. The method includes pre-scanning a plurality of storage increments and counting a number of available large pages that are online and issuing a message that indicates the number of available large pages. The method also includes receiving and parsing an LFAREA request including a target number of large pages to be reserved. The method further includes calculating an optimal number of large pages to be reserved, based upon the target number of available pages and a system limit. The method includes determining if the LFAREA request is valid and if the LFAREA request can be satisfied and scanning the plurality of the storage increments and reserving the optimal number of pages in the LFAREA. | 2014-07-17 |