29th week of 2015 patent applcation highlights part 42 |
Patent application number | Title | Published |
20150200102 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate. | 2015-07-16 |
20150200103 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate. | 2015-07-16 |
20150200104 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate. | 2015-07-16 |
20150200105 | PRODUCTION METHOD - A production methods includes providing a substrate including a lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle α from at least a first or second main surface region of the substrate, the first and second main surface regions extending parallel to each other; anisotropic etching, starting from the first main surface region, into the substrate so as to obtain an etching structure which includes, in a plane extending perpendicularly to the first main surface region, two different etching angles relative to the first main surface region; arranging a cover layer on the first main surface region, so that the cover layer lies against the etching structure in at least some sections; and removing, section-by-section, the material of the substrate starting from the second main surface region in the area of the deformed cover layer, so that the cover layer is exposed in at least one window region. | 2015-07-16 |
20150200106 | HIGH ASPECT RATIO ETCH WITH COMBINATION MASK - A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask. | 2015-07-16 |
20150200107 | DENSE FINFET SRAM - A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features. | 2015-07-16 |
20150200108 | SUBSTRATE TREATMENT METHOD AND SUBSTRATE TREATING APPARATUS - A hydrofluoric acid is supplied to a surface of a substrate, and a native oxide film formed on the surface is corroded to be removed, exposing silicon in the surface of the substrate. Then, a rinse solution such as alcohols is supplied to the surface of the substrate, and then, the hydrofluoric acid is washed off from the surface. After that, a dopant solution, which is a dopant-containing chemical solution, is supplied to the surface of the substrate. The dopant solution comes into contact with the surface of the substrate, which is not hydrogen-terminated and has silicon exposed, thereby forming a dopant-containing monolayer thin film on the surface in a short period of time. | 2015-07-16 |
20150200109 | MASK PASSIVATION USING PLASMA - A gas comprising hydrogen is supplied to a plasma source. Plasma comprising hydrogen plasma particles is generated from the gas. A passivation layer is deposited on a first mask layer on a second mask layer over a substrate using the hydrogen plasma particles. | 2015-07-16 |
20150200110 | Self-Aligned Double Patterning With Spatial Atomic Layer Deposition - Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition. | 2015-07-16 |
20150200111 | PLANARIZATION SCHEME FOR FINFET GATE HEIGHT UNIFORMITY CONTROL - Embodiments of the present invention provide improved methods for fabrication of finFETs. During finFET fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins. A fill layer is deposited on the film and planarized to form a flush surface. A recess or etch process is used to form a planar surface with all portions of the fill layer removed. A finishing process such as a gas cluster ion beam process may be used to further smooth the substrate surface. This results in a film having a very uniform thickness across the structure (e.g. a semiconductor wafer), resulting in improved within-wafer (WiW) uniformity and improved within-chip (WiC) uniformity. | 2015-07-16 |
20150200112 | METHODS OF FORMING CONDUCTIVE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal. | 2015-07-16 |
20150200113 | METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed. | 2015-07-16 |
20150200114 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 2015-07-16 |
20150200115 | WASHING DEVICE - A washing device is disclosed, which is capable of preventing damage of a substrate caused by drooping of the substrate. The washing device includes a plasma irradiating part supplied with a substrate from a substrate loading part to remove dirt from the substrate by irradiating plasma to the substrate; a dirt washing part supplied from the substrate from the plasma irradiating part to remove dirt remaining on the substrate; a finishing washing part supplied with the substrate from the dirt washing part to wash the substrate; a drying part supplied with the substrate from the finishing washing part to dry the substrate; and a substrate unloading part supplied with the substrate from the drying part to unload the substrate, wherein the plasma irradiating part includes a plasma irradiation unit that irradiates plasma to the substrate and a floating unit that maintains the substrate in a floating state. | 2015-07-16 |
20150200116 | CHEMICAL LIQUID TREATMENT APPARATUS AND CHEMICAL LIQUID TREATMENT METHOD - A chemical liquid treatment apparatus includes processing chambers; a chemical liquid feeding unit configured to cyclically feed a chemical liquid into the processing chambers; and a modifying unit. The modifying unit, when using a chemical liquid in which an effect thereof varies with a chemical liquid discharge time, is configured to calculate a variation of the effect of the chemical liquid based on the chemical liquid discharge time and is configured to modify the chemical liquid discharge time for each of the processing chambers based on the calculated variation of the effect of the chemical liquid and a cumulative time of the chemical liquid discharge time. | 2015-07-16 |
20150200117 | SEMICONDUCTOR CRYSTAL BODY PROCESSING METHOD AND SEMICONDUCTOR CRYSTAL BODY PROCESSING DEVICE - A semiconductor crystal body processing method includes providing a semiconductor crystal body, sandwiching the semiconductor crystal body between a pair of conductive pressurizing tools, applying a pulse-like current between the pair of pressurizing tools to heat the semiconductor crystal body to a target temperature equal to or higher than a temperature at which the semiconductor crystal body is plastically deformed by pressurization and lower than its melting point, and applying pressure and a pulse-like current between the pair of pressurizing tools to thereby maintain the temperature of the semiconductor crystal body at the target temperature and mold the semiconductor crystal body into a target shape by plastic deformation. | 2015-07-16 |
20150200118 | BONDING APPARATUS AND METHOD - A bonding apparatus includes a wafer stage, a first chip stage, a first transporting device, a second stage and a second transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second transporting device is used for transporting the second chip from the second chip stage onto the wafer. | 2015-07-16 |
20150200119 | LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND CLEAN SIDEWALL - In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation. | 2015-07-16 |
20150200120 | SYSTEMS AND METHOD FOR TRANSFERRING A SEMICONDUCTOR SUBSTRATE - In accordance with some embodiments, systems and methods for processing a semiconductor substrate are provided. The method includes loading a semiconductor substrate from a chamber to a transfer module, detecting a center and a notch of the semiconductor substrate by the transfer module, and transferring the semiconductor substrate from the transfer module to a process chamber. | 2015-07-16 |
20150200121 | SUPPPORTING DEVICE, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY - A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-fits is distributed in the glue layer. | 2015-07-16 |
20150200122 | SUBSTRATE TRANSFER APPARATUS AND METHOD, AND SUBSTRATE PROCESSING APPARATUS - Provided are a substrate transfer apparatus and method and a substrate processing apparatus. The substrate transfer apparatus includes: a body portion; an arm part coupled to the body portion, the arm part moving to allow the substrate to be transferred; a suction part provided with the arm portion, the suction part suctioning and fixing the substrate; and a control part controlling an operation of the substrate transfer apparatus, wherein the control part changes a suction point on the substrate to re-attempt suction when suction of the substrate by the suction part is unsuccessful. | 2015-07-16 |
20150200123 | METHOD AND APPARATUS FOR LIQUID TREATMENT OF WAFER SHAPED ARTICLES - An apparatus for treating a wafer-shaped article, comprises a spin chuck for holding a wafer-shaped article in a predetermined orientation, at least one upper nozzle for dispensing a treatment fluid onto an upwardly facing surface of a wafer-shaped article when positioned on the spin chuck, and at least one lower nozzle arm comprising a series of lower nozzles extending from a central region of the spin chuck to a peripheral region of the spin chuck. The series of nozzles comprises a smaller nozzle in a central region of the spin chuck and a larger nozzle in a peripheral region of the spin chuck. In the method according to the invention, a heated liquid is supplied through the series of nozzles so as to supply more heat to peripheral regions of a wafer than to central regions. | 2015-07-16 |
20150200124 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided by performing plasma processing on a substrate to be processed by using a plasma processing apparatus including a processing chamber, a lower electrode, an upper electrode, a plurality of lifter pins, a focus ring, a lifter pin for focus ring and an electrical connection mechanism. | 2015-07-16 |
20150200125 | FLOWABLE CARBON FILM BY FCVD HARDWARE USING REMOTE PLASMA PECVD - Embodiments of the present invention generally relate to methods for forming a flowable carbon-containing film on a substrate. In one embodiment, an oxygen-containing gas is flowed into a remote plasma region to produce oxygen-containing plasma effluents, and a carbon-containing gas is combined with the oxygen-containing plasma effluents in a substrate processing region which contains the substrate. A carbon-containing film is formed in trenches which are formed on the substrate and a low K dielectric material is deposited on the carbon-containing film in the trenches. The carbon-containing film is decomposed by an UV treatment and airgaps are formed in the trenches under the low K dielectric material. | 2015-07-16 |
20150200126 | Semiconductor Structure With Inlaid Capping Layer And Method Of Manufacturing The Same - A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer. | 2015-07-16 |
20150200127 | MECHANISMS FOR FORMING SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having an upper surface. The semiconductor device also includes a recess extending from the upper surface into the semiconductor substrate. The semiconductor device further includes an isolation structure in the recess, and the isolation structure has an upper portion and a lower portion. | 2015-07-16 |
20150200128 | METHODS OF FORMING ISOLATED GERMANIUM-CONTAINING FINS FOR A FINFET SEMICONDUCTOR DEVICE - Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material. | 2015-07-16 |
20150200129 | METHOD FOR PRODUCING HYBRID SUBSTRATES, AND HYBRID SUBSTRATE - A method for producing hybrid substrates which can be incorporated into a semiconductor production line involves: forming an ion-injection region ( | 2015-07-16 |
20150200130 | METHOD FOR FORMING DIFFERENT PATTERNS IN A SEMICONDUCTOR STRUCTURE USING A SINGLE MASK - The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a semiconductor structure including a substrate, a dielectric layer formed over the substrate, and a hard mask region formed over the dielectric layer; forming a first photoresist layer over the hard mask region; performing a first lithography exposure using a photomask to form a first latent pattern; forming a second photoresist layer over the hard mask region; and performing a second lithography exposure using the photomask to form a second latent pattern. The photomask includes a first mask feature and a second mask feature. The first latent pattern corresponds to the first mask feature, and the second latent pattern corresponds to the first mask feature and the second mask feature. | 2015-07-16 |
20150200131 | TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS BY MODIFIED RF POWER RAMP-UP - When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component. | 2015-07-16 |
20150200132 | Metal Capping Process And Processing Platform Thereof - Before depositing a metal capping layer on a metal interconnect in a damascene structure, a remote plasma is used to reduce native oxide formed on the metal interconnect. Accordingly, a remote plasma reducing chamber is integrated in a processing platform for depositing a metal capping layer. | 2015-07-16 |
20150200133 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm. | 2015-07-16 |
20150200134 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING - Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface. The semiconductor device structure also includes a first semiconductor substrate formed over the bottom surface of the first insulating layer. The semiconductor device structure further includes a conductive feature formed only adjacent to the side surface of the insulating layer on the first semiconductor substrate. In addition, the semiconductor device structure includes a second semiconductor substrate formed over the top surface of the insulating layer. The second semiconductor substrate includes a device-forming region formed directly over the insulating layer such that a projection region of the device-forming region is positioned inside the insulating layer. | 2015-07-16 |
20150200135 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire. | 2015-07-16 |
20150200136 | SEMICONDUCTOR DEVICE, METHOD FOR FORMING CONTACT AND METHOD FOR ETCHING CONTINUOUS RECESS - A method for forming a contact is provided. The method includes: forming a first dielectric layer over a substrate; forming a second dielectric layer over the first dielectric layer; patterning the second dielectric layer to form a first recess; patterning the first dielectric layer by a first etchant through the first recess to form a second recess, wherein the first etchant has a higher etching rate with respect to the first dielectric layer than with respect to the second dielectric layer and further wherein the second recess is aligned with the first recess; and forming a continuous contact plug in the first recess and the second recess. | 2015-07-16 |
20150200137 | SELF-ALIGNED CONTACT STRUCTURE - Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material. | 2015-07-16 |
20150200138 | METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR COMPONENTS, LEADFRAME ASSEMBLY AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT - In one embodiment, the method is configured for producing optoelectronic semiconductor components ( | 2015-07-16 |
20150200139 | EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN - Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors. | 2015-07-16 |
20150200140 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS USING LASER INTERFERENCE LITHOGRAPHY TECHNIQUES - A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions. | 2015-07-16 |
20150200141 | FIN ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - A fin arrangement and a method for manufacturing the same are provided. An example method may include: patterning a substrate to form an initial fin on a selected area of the substrate; forming, on the substrate, a dielectric layer to substantially cover the initial fin, wherein a portion of the dielectric layer located on top of the initial fin has a thickness substantially less than that of a portion the dielectric layer located on the substrate; and etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion of the initial fin is used as a fin. | 2015-07-16 |
20150200142 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH FULLY SILICIDED GATE ELECTRODE STRUCTURES - A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material. | 2015-07-16 |
20150200143 | SHORT TAIL RECOVERY TECHNIQUES IN WIRE BONDING OPERATIONS - A method of operating a wire bonding machine is provided. The method includes: detecting a short tail condition after formation of a wire bond formed using a wire bonding tool; providing a bond head assembly of a wire bonding machine at an xy location of the wire bonding machine, the bond head assembly carrying the wire bonding tool; lowering the bond head assembly toward a contact surface at the xy location with a wire clamp of the wire bonding machine closed; opening the wire clamp; decelerating the bond head assembly as it is lowered toward the contact surface such that a portion of a wire extends below a tip of the wire bonding tool; closing the wire clamp; and performing a test to determine if an end of the portion of the wire extending below the tip of the bonding tool is in contact with the contact surface. | 2015-07-16 |
20150200144 | CHUCK AND SEMICONDUCTOR PROCESS USING THE SAME - A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral. | 2015-07-16 |
20150200145 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME - A display substrate includes a base substrate including a display area and a peripheral area surrounding the display area, a switching element in the display area, a main-test-line in the peripheral area, extending in the second direction and electrically connected with a data line, a sub-test-line in the peripheral area, and a test pad in the peripheral area and electrically connected with the main-test-line and the sub-test-line. The switching element is electrically connected with a gate line extending in a first direction and the data line extending in a second direction crossing the first direction. The sub-test-line is electrically connected with the data line. The sub-test-line is in a different layer from the main-test-line. | 2015-07-16 |
20150200146 | Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes - Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes. | 2015-07-16 |
20150200147 | MINIATURIZED SMD DIODE PACKAGE AND PRSCESS FOR PRODUCING THE SAME - A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect. | 2015-07-16 |
20150200148 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided, wherein the semiconductor device comprises a carrier, wherein the carrier comprises a first portion configured to hold a semiconductor chip; and a second portion configured for mounting the semiconductor device to a support, the second portion further comprising a first feature configured to be connected to the support; and at least one second feature configured to facilitate transfer of heat away from the first portion, wherein the at least one second feature increases a surface area of the second portion. | 2015-07-16 |
20150200149 | THERMAL IMPROVEMENT FOR HOTSPOTS ON DIES IN INTEGRATED CIRCUIT PACKAGES - Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate. | 2015-07-16 |
20150200150 | Thermal Management In Electronic Apparatus With Phase-Change Material And Silicon Heat Sink - Embodiments of an electronic apparatus with a thermal management technique utilizing a silicon heat sink and/or a phase-change material, as well as an assembling method thereof, are described. In one aspect, the electronic apparatus comprises a main unit, a phase-change material and an enclosure enclosing the main unit and the phase-change material. The main unit comprises a substrate and at least one integrated-circuit (IC) chip disposed on the substrate. The phase-change material is in direct contact with each IC chip of the at least one IC chip to absorb and dissipate heat generated by the at least one IC chip. | 2015-07-16 |
20150200151 | DEVICE COMPRISING A THREE-DIMENSIONAL INTEGRATED STRUCTURE WITH SIMPLIFIED THERMAL DISSIPATION, AND CORRESPONDING FABRICATION METHOD - A device includes a support, a three-dimensional integrated structure above the support, and a lateral encapsulation region arranged around the structure. The lateral encapsulation region includes first channels configured to make it possible to circulate a cooling fluid. | 2015-07-16 |
20150200152 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a gate structure formed in the interlayer insulating layer, an isolation layer formed in the semiconductor substrate, a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer, and a first conduction type first impurity region coming in contact with the isolation layer and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate. | 2015-07-16 |
20150200153 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small. | 2015-07-16 |
20150200154 | STACKED SEMICONDUCTOR PACKAGE - Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip. | 2015-07-16 |
20150200155 | SEMICONDUCTOR DEVICE HAVING MIRROR-SYMMETRIC TERMINALS AND METHODS OF FORMING THE SAME - A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device. | 2015-07-16 |
20150200156 | MODULE HAVING MIRROR-SYMMETRIC TERMINALS AND METHODS OF FORMING THE SAME - A module having substantially mirror-symmetric terminals and methods of forming the same. In one embodiment, the module has first and second module terminals and includes a first semiconductor device with first and second terminals in a substantially mirror-symmetric arrangement on the first semiconductor device and coupled to a first common node of the first semiconductor device. The module also includes a second semiconductor device including third and fourth terminals in a substantially mirror-symmetric arrangement on the second semiconductor device and coupled to a second common node of the second semiconductor device. At least one of the first and second terminals is coupled to the first module terminal, and at least one of the third and fourth terminals are coupled to the second module terminal. The first and second module terminals are in a substantially mirror-symmetric arrangement on the module. | 2015-07-16 |
20150200157 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor-chip including a first electrode; a second semiconductor-chip including a second electrode; and a switch including a core element configured to contract and expand by a temperature change, a heat generation unit configured to heat the core element, a first metal element configured to cover the core element and connected to the first electrode, and a second metal element configured to cover the core element and connected to the second electrode, wherein, when the core element contracts, the first metal element and the second metal element come in contact with each other so that the first semiconductor-chip and the second semiconductor-chip are electrically connected with each other, and when the core element expands, the first metal element and the second metal element become in non-contact with each other so that the first semiconductor-chip and the second semiconductor-chip are electrically separated from each other. | 2015-07-16 |
20150200158 | Method of Manufacturing Semiconductor Device and Semiconductor Device - Characteristics of a semiconductor device are improved. An opening that exposes a pad region of a top-layer wiring containing aluminum is formed in a protection film over the wiring, and aluminum nitride is formed on a surface of the exposed wiring. Additionally, a silicon nitride film is formed on a back surface of a semiconductor substrate having the wiring. As described above, foreign substances generated over the pad region due to the silicon nitride film on the back surface of the semiconductor substrate can be prevented by providing an aluminum nitride film over the pad region. Particularly, even in a case of requiring time before an inspection step and a bonding step, after a formation step of the pad region, formation reaction of the foreign substances can be prevented in the pad region, and the characteristics of the semiconductor device can be improved. | 2015-07-16 |
20150200159 | DUPLICATE LAYERING AND ROUTING - In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance. | 2015-07-16 |
20150200160 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance. | 2015-07-16 |
20150200161 | E-FUSE CIRCUIT AND METHOD FOR PROGRAMMING THE SAME - An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array. | 2015-07-16 |
20150200162 | ISOLATION BETWEEN SEMICONDUCTOR COMPONENTS - In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package. | 2015-07-16 |
20150200163 | CHIP PACKAGE - A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections. | 2015-07-16 |
20150200164 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device comprises a workpiece including a conductive feature disposed in a first insulating material and a second insulating material disposed over the first insulating material, the second insulating material having an opening over the conductive feature. A graphene-based conductive layer is disposed over an exposed top surface of the conductive feature within the opening in the second insulating material. A carbon-based adhesive layer is disposed over sidewalls of the opening in the second insulating material. A carbon nano-tube (CNT) is disposed within the patterned second insulating material over the graphene-based conductive layer and the carbon-based adhesive layer. | 2015-07-16 |
20150200165 | MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS - A mark forming method includes: a step of forming a resist mark including recessed portion based on an image of a mark exposed on a wafer; a step of coating the recessed portion, in an area of the wafer in which the resist mark has been formed, with a polymer layer containing a block copolymer; a step of performing annealing for the polymer layer so as to allow the polymer layer to form a self-assembled area; a step of performing etching so as to selectively remove a portion of the self-assembled area; and a step of forming a wafer mark in the wafer by using the self-assembled area from which the portion thereof has been removed. When forming a circuit pattern by using the directed self-assemble of the block copolymer, a mark can be also formed, in parallel with the formation of the circuit pattern. | 2015-07-16 |
20150200166 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes thermally curing a thermosetting resin material layer formed on a semiconductor wafer at a first temperature of 100° C. to 200° C. to form a protective film, preheating the semiconductor wafer having the protective film formed therein at a second temperature and removing water on the surface of the protective film, bias sputtering on the preheated semiconductor wafer, then controlling the temperature of the semiconductor wafer to a third temperature of not more than 200° C., and sputtering a material selected from the group consisting of Ti, TiW, Ta, and a conductive Ti compound to form a first conductive underlayer on the protective film. | 2015-07-16 |
20150200167 | METHODS OF MANAGING METAL DENSITY IN DICING CHANNEL AND RELATED INTEGRATED CIRCUIT STRUCTURES - Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region. | 2015-07-16 |
20150200168 | ESD Clamp with a Layout-Alterable Trigger Voltage and a Holding Voltage Above the Supply Voltage - An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region. | 2015-07-16 |
20150200169 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring. | 2015-07-16 |
20150200170 | SEMICONDUCTOR DEVICE - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 2015-07-16 |
20150200171 | Packaging through Pre-Formed Metal Pins - A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region. | 2015-07-16 |
20150200172 | Package Having Substrate With Embedded Metal TraceOverlapped by Landing Pad - An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace. | 2015-07-16 |
20150200173 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace. | 2015-07-16 |
20150200174 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element. | 2015-07-16 |
20150200175 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring layer formed on a first surface of a first insulation layer and including an external connection pad and an internal connection pad located at an inner side of the external connection pad. A semiconductor element facing the first surface of the first insulation layer includes an electrode pad located corresponding to the internal connection pad, a bump formed on the electrode pad and connected to the internal connection pad, and a circuit element region defined in a first surface of the semiconductor element at an inner side of the electrode pad. A second insulation layer fills a gap between the first surfaces of the semiconductor element and the first insulation layer. A third insulation layer covers a second surface of the semiconductor element and the second insulation layer and includes an opening that exposes the external connection pad connected to an external connection terminal. | 2015-07-16 |
20150200176 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A mounting structure of a semiconductor device is configured by connecting (i) a first protruding electrode [a bump (A | 2015-07-16 |
20150200177 | WAFER LEVEL PACKAGE WITH REDISTRIBUTION LAYER FORMED WITH METALLIC POWDER - A semiconductor device is assembled where a signal redistribution layer is formed over a partially encapsulated semiconductor die. The distribution layer is formed by selectively coating a first electrical insulating layer over an active surface of the die and a surrounding portion of the encapsulation material, where die bonding pads on the active surface of the die are exposed through access apertures in the first electrical insulating layer. A layer of metallic powder is deposited onto the first insulating layer and then electrically conductive runners are formed from the layer of metallic powder. The runners are coated with a further electrical insulating layer. A mounting area of each runner is exposed through an external connection aperture. Solder balls may be attached to the mounting areas. | 2015-07-16 |
20150200178 | Connection Structure and Electronic Component - A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer. | 2015-07-16 |
20150200179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer. | 2015-07-16 |
20150200180 | PRESSURE SENSOR DEVICE WITH GEL RETAINER - A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer. | 2015-07-16 |
20150200181 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. | 2015-07-16 |
20150200182 | Packaging Methods for Semiconductor Devices, Packaged Semiconductor Devices, and Design Methods Thereof - Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies. | 2015-07-16 |
20150200183 | Stackable microelectronic package structures - A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package. | 2015-07-16 |
20150200184 | Full Bridge Rectifier Module - A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier. | 2015-07-16 |
20150200185 | PAD STRUCTURE DESIGN IN FAN-OUT PACKAGE - A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. | 2015-07-16 |
20150200186 | ELECTRONIC DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate; a first semiconductor chip disposed on a first surface of the substrate, the first semiconductor chip either the only semiconductor chip disposed on the first surface of the substrate or a bottom-most semiconductor chip formed on the first surface of the substrate; a plurality of external connection terminals disposed on a second surface of the substrate that is opposite to the first surface of the substrate; a stress buffer layer formed on the first surface of the substrate to vertically overlap at least one of the plurality of external connection members, wherein the stress buffer layer is formed on an edge part of the substrate and does not contact or vertically overlap the first semiconductor chip; and a sealing member covering the first chip and the stress buffer layer. | 2015-07-16 |
20150200187 | SEMICONDUCTOR PACKAGE INCLUDING STEPWISE STACKED CHIPS - A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region. | 2015-07-16 |
20150200188 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a semiconductor package is provided. The A semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body. | 2015-07-16 |
20150200189 | INTEGRATED CIRCUIT MODULE HAVING A FIRST DIE WITH A POWER AMPLIFIER STACKED WITH A SECOND DIE AND METHOD OF MAKING THE SAME - Disclosed is an integrated circuit module that includes a first die having a plurality of hot regions and at least one cool region when operating under normal conditions. The first die with a top surface includes at least one power amplifier that resides in the plurality of hot regions. The integrated circuit module also includes a second die. The second die has a bottom surface, which is adhered to the top surface of the first die, wherein any portion of the bottom surface of the second die that is adhered to the top surface of the first die resides exclusively on the at least one cool region. In at least one embodiment, the first die is an RF power amplifier die and the second die is a controller die having control circuitry configured to control the at least one power amplifier that is an RF power amplifier type. | 2015-07-16 |
20150200190 | Package on Packaging Structure and Methods of Making Same - A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer. | 2015-07-16 |
20150200191 | SEMICONDUCTOR INTERGRATED CIRCUIT APPARATUS AND MANUFACTURING METHOD FOR SAME - A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions. | 2015-07-16 |
20150200192 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench. | 2015-07-16 |
20150200193 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer. | 2015-07-16 |
20150200194 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors. The transistors include a pull-up transistor, a transfer gate transistor, and a pull-down transistor of a SRAM cell. The ion implantation is used to adjust threshold voltages of the transistors. Standard threshold voltage (SVt) ion implantation conditions are used to adjust a threshold voltage of the pull-up transistor and a threshold voltage of the transfer gate transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a threshold voltage of the pull-down transistor. | 2015-07-16 |
20150200195 | SPLIT PAGE 3D MEMORY ARRAY - A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines. | 2015-07-16 |
20150200196 | DUMMY END-GATE BASED ANTI-FUSE DEVICE FOR FINFET TECHNOLOGIES - An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device. | 2015-07-16 |
20150200197 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view. | 2015-07-16 |
20150200198 | High Voltage Double-Diffused MOS (DMOS) Device and Method of Manufacture - A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell. | 2015-07-16 |
20150200199 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate, a semiconductor pillar provided on the substrate to extend in a vertical direction, a plurality of first electrode films provided sideward of the semiconductor pillar to extend in a first direction. The plurality of first electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a plurality of second electrode films provided between the semiconductor pillar and the first electrode films. The plurality of second electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a first insulating film provided between the semiconductor pillar and the second electrode films, and a second insulating film provided between the second electrode film and the first electrode film. | 2015-07-16 |
20150200200 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers. | 2015-07-16 |
20150200201 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first selection gate insulating film surrounding a first pillar-shaped semiconductor layer, a first selection gate surrounding the first selection gate insulating film, a first bit line connected to the first pillar-shaped semiconductor layer, a layer including a first charge storage layer which surrounds a second pillar-shaped semiconductor layer, a first control gate surrounding the layer, a layer including a second charge storage layer which surrounds the second pillar-shaped semiconductor layer, a second control gate surrounding the layer, a first lower-portion internal line connecting the first and second pillar-shaped semiconductor layers, a layer including a third charge storage layer, a third control gate, a layer including a fourth charge storage layer, a fourth control gate, a second selection gate insulating film, a second selection gate, a first source line, and a second lower-portion internal line. | 2015-07-16 |