28th week of 2010 patent applcation highlights part 34 |
Patent application number | Title | Published |
20100178714 | Method of forming magnetic memory device - There are provided a magnetic memory device and a method of forming the magnetic memory device. The method of forming the magnetic memory device includes sequentially forming a first magnetic conductor, a tunnel barrier layer, and a second magnetic conductor on a substrate, forming a mask pattern on the second magnetic conductor, performing a primary etching of the second magnetic conductor by using the mask pattern as an etching mask, forming at least one spacer on sidewalls of the second magnetic conductor formed by the primary etching, and performing a secondary etching of the first magnetic conductor by using the mask pattern and the at least one spacers as an etching mask. | 2010-07-15 |
20100178715 | MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure. | 2010-07-15 |
20100178716 | METHOD AND APPARATUS TO REMOVE A SEGMENT OF A THIN FILM SOLAR CELL STRUCTURE FOR EFFICIENCY IMPROVEMENT - The present inventions relate to methods and apparatus for detecting and mechanically removing defects and a surrounding portion of the photovoltaic layer and the substrate in a thin film solar cell such as a Group IBIIIAVIA compound thin film solar cell to improve its efficiency. | 2010-07-15 |
20100178717 | METHOD OF MANUFACTURING MEMS DEVICE - A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside. | 2010-07-15 |
20100178718 | METHODS FOR IMPROVING PERFORMANCE VARIATION OF A SOLAR CELL MANUFACTURING PROCESS - A method for optimizing a solar cell manufacturing process is described. The method includes determining a reference finger spacing value and a reference bulk lifetime for the solar cell manufacturing process. The method also includes measuring an actual bulk lifetime of a wafer with an in-line measurement tool. The method further includes calculating an optimal finger spacing value with a computer coupled to the in-line measurement tool, the optimal finger spacing value being the product of the reference finger spacing value and a square root of the actual bulk lifetime divided by the square root of the reference bulk lifetime. The method further includes forming a junction on the wafer, and depositing a set of busbars and a set of fingers on the wafer with a metal deposition device, wherein a distance between a first finger and a second finger of the set of fingers is about the optimal finger spacing value. | 2010-07-15 |
20100178719 | Diamond LED Devices and Associated Methods - LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single cyrstal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 2010-07-15 |
20100178720 | Method of manufacturing semiconductor light emitting device - A method of manufacturing a semiconductor light emitting device may include forming an insulating layer on a substrate, forming a plurality of first holes in the insulating layer, forming a plurality of GaN rods in the plurality of first holes, and laterally growing an n-GaN layer on the plurality of GaN rods. | 2010-07-15 |
20100178721 | SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING AN ELECTRODE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type nitride semiconductor layer ( | 2010-07-15 |
20100178722 | METHODS AND APPLICATIONS OF NON-PLANAR IMAGING ARRAYS - System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface. | 2010-07-15 |
20100178723 | Method and Structure for Fabricating Solar Cells Using a Thick Layer Transfer Process - A photovoltaic cell device, e.g., solar cell, solar panel, and method of manufacture. The device has an optically transparent substrate comprises a first surface and a second surface. A first thickness of material (e.g., semiconductor material, single crystal material) having a first surface region and a second surface region is included. In a preferred embodiment, the surface region is overlying the first surface of the optically transparent substrate. The device has an optical coupling material provided between the first surface region of the thickness of material and the first surface of the optically transparent material. | 2010-07-15 |
20100178724 | ORGANIC ELECTROLUMINESCENT DISPLAY AND METHOD OF FABRICATING THE SAME - An organic electroluminescent display (“OELD”) includes an organic light-emitting diode (“OLED”), a circuit region, and an interlayer dielectric (“ILD”) layer. The OLED is disposed in each of a plurality of pixels arranged on a substrate. The circuit region includes two or more thin film transistors (“TFTs”) and a storage capacitor. The ILD layer has two or more insulating layers and includes a first region disposed between both electrodes of the storage capacitor and a second region covering the TFTs. At least one of the insulating layers has a window exposing the insulating layer directly beneath the at least one insulating layer so that that the ILD layer is thinner in the first region than in the second region. Accordingly, it is possible to reduce an occupation area of the storage capacitor while maintaining the necessary capacitance of the storage capacitor and expanding the area of the luminescent region. | 2010-07-15 |
20100178725 | SOLID STATE IMAGE PICKUP DEVICE - P type semiconductor well regions | 2010-07-15 |
20100178726 | Conductive Paste, Solar Cell Manufactured Using Conductive Paste, Screen Printing Method and Solar Cell Formed Using Screen Printing Method - The conductive paste contains a conductive metal powder and an organic vehicle. The conductive paste has characteristics that the viscosity falls within the range of 200 Pa·s to 350 Pa·s when the shear rate of 10 s | 2010-07-15 |
20100178727 | METHOD OF MANUFACTURING ORGANIC FILM TRANSISTOR - A method of fabricating an organic thin film transistor exhibiting excellent semiconductor performance by which an organic TFT can be formed continuously on a flexible base such as a polymer support through a simple coating process, and thus the fabrication cost can be reduced sharply, and an organic semiconductor layer thus formed has a high carrier mobility, In the method of fabricating an organic thin film transistor by forming a gate electrode, a gate insulation layer, an organic semiconductor layer, a source electrode and a drain electrode sequentially on a support, the organic semiconductor layer contains an organic semiconductor material having an exothermic point and an endothermic point in a differential scanning thermal analysis, and the organic semiconductor layer thus formed is heat-treated at a temperature not less than the exothermic point and less than the endothermic point. | 2010-07-15 |
20100178728 | ARYL DICARBOXYLIC ACID DIIMIDAZOLE-BASED COMPOUNDS AS N-TYPE SEMICONDUCTOR MATERIALS FOR THIN FILM TRANSISTORS - A process for fabricating a thin film semiconductor device includes the following steps, but not necessarily in the noted order. Firstly, a thin film of organic semiconductor material is deposited onto a substrate. This thin film of organic semiconductor material comprises organic semiconductor material that comprises one or more aryl dicarboxylic diimidazole-based compounds of claim | 2010-07-15 |
20100178729 | Resistance-Type Random Access Memory Device Having Three-Dimensional Bit Line and Word Line Patterning - Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes. | 2010-07-15 |
20100178730 | Direct-current plasma CVD apparatus and method for producing diamond using the same - The present invention is a direct-current plasma CVD apparatus comprising at least a fixed electrode and a substrate stage having a top flat face and combined with an electrode for placing a substrate, in which the substrate stage top face is not located on a line extended from a center of the fixed electrode in vertical direction, and an angle formed between a line of a length R connecting a center of the substrate stage top face with the center of the fixed electrode and the line extended in vertical direction from the center of the fixed electrode is 90° or less. As a result, there is provided a direct-current plasma CVD apparatus in which a high quality vapor phase growth film, such as diamond of a large area having few defects caused by the fall of the substances produced at the fixed electrode, can be obtained. | 2010-07-15 |
20100178731 | SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CONSTRUCTS - A semiconductor device includes a plurality of semiconductor constructs, each of the semiconductor constructs including a semiconductor substrate and external connection electrodes provided on an upper surface of the semiconductor substrate. The semiconductor substrates of the semiconductor constructs are different in a planar-size. The plurality of semiconductor constructs are stacked from bottom to top in descending order of planar-sizes of the semiconductor substrates included in the plurality of semiconductor constructs. An insulating film at least is provided around one semiconductor construct disposed on the top of the plurality of semiconductor constructs and on another semiconductor construct disposed under the one semiconductor construct. Each of the upper surfaces of the plurality of external connection electrodes is exposed from the one semiconductor construct and from the insulating film. | 2010-07-15 |
20100178732 | Laser Bonding for Stacking Semiconductor Substrates - Methods and structures using laser bonding for stacking semiconductor substrates are described. In one embodiment, a method of forming a semiconductor device includes forming a trench in a first substrate, and a bond pad on a second substrate comprising active circuitry. A top surface of the bond pad includes a first material. The first substrate is aligned over the second substrate to align the trench over the bond pad. An electromagnetic beam is directed into the trench to form a bond between the first material on the bond pad and a second material at a bottom surface of the first substrate. | 2010-07-15 |
20100178733 | Thin Quad Flat Package with No Leads (QFN) Fabrication Methods - Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material. | 2010-07-15 |
20100178734 | Leadless Semiconductor Package with Electroplated Layer Embedded in Encapsulant and the Method for Manufacturing the Same - A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages. Furthermore, the manufacturing processes include two half-etching steps to form the half-etched leadframe where a second half-etching step is performed after forming the encapsulant and before forming the electroplated layer. | 2010-07-15 |
20100178735 | Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps - A semiconductor device is made by providing a semiconductor die having bond pads formed on a surface of the semiconductor die, forming a UBM over the bond pads of the semiconductor die, forming a fusible layer over the UBM, providing a substrate having bond pads formed on a surface of the substrate, and forming a plurality of stud bumps containing non-fusible material over the bond pads on the substrate. Each stud bump includes a wire having a first end attached to the bond pad of the substrate and second end of uniform height. The method further includes electrically connecting the second end of the wire for each stud bump to the bond pads of the semiconductor die by reflowing the fusible layer or applying thermal compression bonding, depositing an underfill material between the semiconductor die and substrate, and depositing an encapsulant over the semiconductor die and substrate. | 2010-07-15 |
20100178736 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process. | 2010-07-15 |
20100178737 | Semiconductor IC and Its Manufacturing Method, and Module with Embedded Semiconductor IC and Its Manufacturing Method - A semiconductor IC includes a semiconductor IC main body having a predetermined circuit formed on a main surface, a metal layer selectively provided on substantially the whole back surface of the semiconductor IC main body excluding the periphery. According to the present invention, the metal layer provided on the semiconductor IC main body can dissipate heat at a high level. Because the metal layer is selectively provided, even when the semiconductor IC main body is thinned by polishing, warpage does not occur easily in a wafer state. The metal layer is selectively provided at the center of the back surface of the semiconductor IC. Therefore, a laminate of a semiconductor wafer and a thick metal does not need to be diced. As a result, chipping on the disconnected surface can be prevented effectively. | 2010-07-15 |
20100178738 | TRANSISTOR, METHOD OF FABRICATING THE SAME AND ORGANIC LIGHT EMITTING DISPLAY INCLUDING THE TRANSISTOR - A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer. | 2010-07-15 |
20100178739 | INTEGRATION SCHEME FOR AN NMOS METAL GATE - A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor. | 2010-07-15 |
20100178740 | BIPOLAR TRANSISTORS WITH RESISTORS - Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a bipolar transistor is implanted with a first dopant in an implantation process that implants source/drain regions of an MOS transistor, and is also implanted with a second dopant of same conductivity type in another implantation process that implants a body region of a resistor. The first and second dopants may optionally be the same dopant. The source/drain regions are implanted with the resistor body region covered by a first patterned mask; and the resistor body region is implanted with the MOS transistor source/drain regions covered by a second patterned mask. The implantations of the MOS transistor source/drain regions and of the resistor body region the source/drain regions can occur in any order, with the emitter region implanted during both implantations. | 2010-07-15 |
20100178741 | ACCESS TRANSISTOR FOR MEMORY DEVICE - An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element. | 2010-07-15 |
20100178742 | METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE - A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also. | 2010-07-15 |
20100178743 | METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS - A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted. | 2010-07-15 |
20100178744 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WHOSE GATE INSULATING FILM CONTAINS Hf AND O - An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film. | 2010-07-15 |
20100178745 | Flash Memory Device and Fabrication Method Thereof - The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation. | 2010-07-15 |
20100178746 | METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) - A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>. | 2010-07-15 |
20100178747 | Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme - Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed. | 2010-07-15 |
20100178748 | Methods of Etching Trenches Into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes - A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF | 2010-07-15 |
20100178749 | METHOD OF FABRICATING EPITAXIALLY GROWN LAYERS ON A COMPOSITE STRUCTURE - A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10 | 2010-07-15 |
20100178750 | METHOD FOR PRODUCING BONDED WAFER - A bonded wafer is produced by removing a part or all of native oxide films formed on each surface of both a wafer for active layer and a wafer for support substrate to be bonded; forming a uniform oxide film with a thickness of less than 5 nm on at least one surface of these wafers by a given oxide film forming method; bonding the wafer for active layer to the wafer for support substrate through the uniform oxide film; thinning the wafer for active layer; and subjecting the bonded wafer to a given heat treatment in a non-oxidizing atmosphere to substantially remove the uniform oxide film existing in the bonding interface. | 2010-07-15 |
20100178751 | LASER PROCESSING METHOD AND SEMICONDUCTOR CHIP - A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. | 2010-07-15 |
20100178752 | SEMICONDUCTOR DEVICE AND FUSE BLOWOUT METHOD - A fuse includes a fuse portion laid in such a manner that the direction of each turn of the fuse portion is parallel to the direction in which pads are arranged. The distance between the pads and the fuse portion is defined as the distance between the side of a pad facing the fuse portion and the pad nearest to the turn facing the particular side. The distance between the turn of the fuse portion and the nearest pad is the distance between the pads and the fuse portion. The pads and the fuse portion are distant from each other by a length at least ten times the width of the fuse. | 2010-07-15 |
20100178753 | SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface. | 2010-07-15 |
20100178754 | METHOD OF MANUFACTURING CMOS TRANSISTOR - A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented. | 2010-07-15 |
20100178755 | Method of fabricating nonvolatile memory device - A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively. | 2010-07-15 |
20100178756 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the side surfaces of the one or more convex portions of the first nitride semiconductor layer. | 2010-07-15 |
20100178757 | PROCESS SIMULATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND PROCESS SIMULATOR - A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data. | 2010-07-15 |
20100178758 | METHODS FOR FABRICATING DIELECTRIC LAYER AND NON-VOLATILE MEMORY - The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate. | 2010-07-15 |
20100178759 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 2010-07-15 |
20100178760 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of the grooves; a first interconnect part and a first bonding electrode part including a copper film formed on the first barrier metal; a second barrier metal formed on the first interconnect part and the first bonding electrode part; a second interconnect part including a metal film formed on the first interconnect part via the second barrier metal; a second bonding electrode part including a metal film formed on the first bonding electrode part via the second barrier metal; and a third interlayer insulating film formed on the second interlayer insulating film, the second interconnect part, and the second bonding electrode part, and including an opening that allows exposure of the surface of the second bonding electrode part. | 2010-07-15 |
20100178761 | Stacked Integrated Chips and Methods of Fabrication Thereof - Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion. | 2010-07-15 |
20100178762 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE SUITABLE FOR FORMING WIRINGS BY DAMASCENE METHOD AND SEMICONDUCTOR DEVICE - An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film. During the period until the barrier layer having also the function of enhancing tight adhesion, it becomes possible to retain sufficient tight adhesion of a wiring member and prevent peel-off of the wiring member. | 2010-07-15 |
20100178763 | METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: (a) forming an alloy film containing a precious metal on a substrate having a semiconductor layer or on a conductive film formed on the substrate; (b) heat-treating the substrate to allow the precious metal to react with silicon forming a silicide film containing the precious metal on the substrate or the conductive film; (c) removing an unreacted portion of the alloy film with a first chemical solution after the step (b); (d) forming a silicon oxide film on the top surface of the silicide film including a portion underlying a residue of the precious metal by exposing the substrate to an oxidative atmosphere; and (e) dissolving the residue of the precious metal with a second chemical solution. | 2010-07-15 |
20100178764 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes the steps of (a) forming a metal film containing a precious metal on a substrate having a semiconductor layer containing silicon or on a conductive film containing silicon formed on the substrate, (b) after step (a), heat-treating the substrate to allow the precious metal to react with silicon to form a silicide film containing the precious metal on the substrate or the conductive film, (c) after step (b), forming an oxide film on a portion of the silicide film underlying an unreacted portion of the precious metal using a first chemical solution, and (d) dissolving the unreacted portion of the precious metal using a second chemical solution. | 2010-07-15 |
20100178765 | Metal Polishing Slurry and Method of Polishing a Film to be Polished - The present invention provides a metal polishing liquid capable of CMP at a high Cu polishing rate and solving the problems: (a) generation of scratches attributable to solid particles, (b) generation of deteriorations in flatness such as dishing and erosion, (c) complexity in a washing process for removing abrasive particles remaining on the surface of a substrate after polishing, and (d) higher costs attributable to the cost of a solid abrasive itself and to waste liquid treatment, as well as a method of polishing a film to be polished by using the same. Disclosed are a metal polishing liquid which comprises a metal oxidizer, a metal oxide solubilizer, a metal anticorrosive, and a water-soluble polymer having an anionic functional group with a weight-average molecular weight of 8,000 or more and has pH 1 or more to 3 or less, and a method of polishing a film to be polished, which comprises supplying the above metal polishing liquid onto a polishing cloth of a polishing platen and simultaneously relatively moving the polishing platen and a substrate having a metallic film to be polished while the substrate is pressed against the polishing cloth. | 2010-07-15 |
20100178766 | HIGH-YIELD METHOD OF EXPOSING AND CONTACTING THROUGH-SILICON VIAS - An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores. The handler wafer is secured to the front side of the body of the main wafer. An additional step includes exposing the blind electrical vias on the back side. The blind electrical vias are exposed to various heights across the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side, to open the dielectric only adjacent the conductive cores of the vias. | 2010-07-15 |
20100178767 | CHEMICAL-MECHANICAL POLISHING COMPOSITION COMPRISING METAL-ORGANIC FRAMEWORK MATERIALS - The present invention relates to compositions for chemical-mechanical polishing comprising A 0.01% to 40% by weight based on the total amount of the composition of abrasive particles of at least one porous metal-organic framework material, wherein the framework material comprises at least one at least bidentate organic compound which is coordinately bound to at least one metal ion; B 40% to 99.8% by weight based on the total amount of the composition of a liquid carrier; and C 0.01% to 20% by weight based on the total amount of the composition of a polishing additive component. The invention further relates to the use of said composition as well as methods for chemical-mechanical polishing of a surface with the aid of said compositions. | 2010-07-15 |
20100178768 | CONTROLLING PASSIVATING FILM PROPERTIES USING COLLOIDAL PARTICLES, POLYELECTROLYTES, AND IONIC ADDITIVES FOR COPPER CHEMICAL MECHANICAL PLANARIZATION - The present invention provides for a copper CMP slurry composition which comprises a complexing agent, an oxidizer, an abrasive and a passivating agent. The present invention also provides for a method of chemical mechanical planarization of a copper conductive structure which comprises administering the copper CMP slurry composition during the planarization process. | 2010-07-15 |
20100178769 | SPACER FORMATION FOR ARRAY DOUBLE PATTERNING - A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area. | 2010-07-15 |
20100178770 | Method of etching a thin film using pressure modulation - A method for transferring a feature pattern to a thin film on a substrate is described. The method comprises disposing a substrate comprising one or more mask layers overlying a thin film in a plasma processing system, and forming a feature pattern in the one or more mask layers. The method further comprises transferring the feature pattern in the one or more mask layers to the thin film by: performing a first plasma etching process at a first pressure less than about 80 mtorr, and performing a second plasma etching process at a second pressure greater than about 80 mtorr. | 2010-07-15 |
20100178771 | Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks - Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers. | 2010-07-15 |
20100178772 | METHOD OF FABRICATING HIGH-K METAL GATE DEVICES - The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts. | 2010-07-15 |
20100178773 | METHOD OF FORMING SEMICONDUCTOR DEVICES EMPLOYING DOUBLE PATTERNING - A first material film is formed on a substrate. Linear second material film patterns are formed on the first material film. Spacer patterns are formed on sidewalls of the second material film patterns, and the second material film patterns are removed to expose portions of the first material film between the spacer patterns. The exposed portions of the first material film are removed to form first material film patterns. Third material film patterns are formed in trenches defined by the first material film patterns. Adjacent first portions of the second material film patterns proximate ends of the second material film patterns are separated by a distance less than twice a width of the individual spacer patterns. In some embodiments, the distance separating the adjacent first portions of the second material film patterns is greater than a minimum feature size, and a width of the individual spacer patterns is approximately equal to the minimum feature size. | 2010-07-15 |
20100178774 | PLASMA CONFINEMENT RINGS INCLUDING RF ABSORBING MATERIAL FOR REDUCING POLYMER DEPOSITION - Plasma confinement rings are adapted to reach sufficiently high temperatures on plasma-exposed surfaces of the rings to substantially reduce polymer deposition on those surfaces. The plasma confinement rings include an RF lossy material effective to enhance heating at portions of the rings. A low-emissivity material can be provided on a portion of the plasma confinement ring assembly to enhance heating effects. | 2010-07-15 |
20100178775 | SHOWER PLATE SINTERED INTEGRALLY WITH GAS RELEASE HOLE MEMBER AND METHOD FOR MANUFACTURING THE SAME - A shower plate is disposed in a processing chamber in a plasma processing apparatus, and plasma excitation gas is released into the processing chamber so as to generate plasma. A ceramic member having a plurality of gas release holes having a diameter of 20 μm to 70 μm, and/or a porous gas-communicating body having pores having a maximum diameter of not more than 75 μm communicating in the gas-communicating direction are sintered and bonded integrally with the inside of each of a plurality of vertical holes which act as release paths for the plasma excitation gas. | 2010-07-15 |
20100178776 | HEAT TREATMENT APPARATUS AND METHOD FOR HEATING SUBSTRATE BY LIGHT-IRRADIATION - A light-emission output of a flash lamp for performing a light-irradiation heat treatment on a substrate in which impurities are implanted is increased up to a target value L | 2010-07-15 |
20100178777 | ADAPTOR FOR MEMORY CARD - An adaptor for a memory card includes a printed circuit board (PCB) conversion board, a memory card connector, a serial interface connector, a signal convertor, and a parallel interface connector. When a motherboard is connected to the serial interface connector, serial signals output from the motherboard are transmitted to the signal convertor via the serial interface connector. The signal convertor converts the serial signals into parallel signals and transmits the parallel signals to the memory card. When the motherboard is connected to the parallel interface connector, parallel signals output from the motherboard are transmitted to the memory card via the PCB conversion board without any parallel-to-serial signal conversion. | 2010-07-15 |
20100178778 | RADIOFREQUENCY CONTACTOR - A radiofrequency contactor includes a testing circuit board having a dielectric substrate, a lower ground conductor on a lower surface of the dielectric substrate, and a radiofrequency signal wiring conductor on an upper surface of the dielectric substrate, a radiofrequency signal pin contactor located on the upper surface of the dielectric substrate and connected to the radiofrequency signal wiring conductor, a ground block located on the upper surface of the dielectric substrate and spaced apart from the radiofrequency signal wiring conductor and the radiofrequency signal pin contactor, and a first side ground conductor and a second side ground conductor provided on the upper surface of the dielectric substrate and spaced apart from the radiofrequency signal wiring conductor and the radiofrequency signal pin contactor. | 2010-07-15 |
20100178779 | ORTHOGONAL CONNECTOR SYSTEM - An orthogonal connector system for connecting a first circuit board and a second circuit board oriented orthogonally with respect to the first circuit board includes a receptacle assembly and a header assembly mated with the receptacle assembly. The receptacle assembly is connected to the first circuit board and the header assembly is connected to the second circuit board. The receptacle assembly and the header assembly both have a housing and contact modules held within the corresponding housing. The contact modules have contact tails extending from a mounting edge thereof, where the contact tails of the receptacle connector are connected to the first circuit board and the contact tails of the header assembly are connected to the second circuit board. The contact modules have mating contacts extending from a mating edge thereof, where the mating edges are generally orthogonal with respect to the mounting edges. The mating contacts of the receptacle assembly are directly connected to the mating contacts of the header assembly. The mounting edge of the receptacle assembly is generally orthogonal with respect to the mounting edge of the header assembly. | 2010-07-15 |
20100178780 | SOCKET ASSEMBLY INCORPORATED WITH ROTATIONALLY MOUNTED PRESSING MEMBER - A socket assembly, comprising a socket, a package received in the socket, a pressing member arranged upon the package and downwardly pressing the package and two heat pipes attached to the pressing member. The pressing member is formed with four arch grooves along a peripheral thereof, and the arch grooves allow linking members to pass therethrough and rotatablely retain the pressing member on a printed circuit board. Therefore, the pressing member can rotate in a certain range, by sliding the arch groove with respect to the linking member, to provide a flexible arrangement for heat pipes. | 2010-07-15 |
20100178781 | ELECTRICAL CONNECTOR ASSEMBLY FOR RETAINING MULTIPLE PROCESSING UNITS - An electrical connector assembly ( | 2010-07-15 |
20100178782 | CONNECTION BASE ASSEMBLY FOR AN IC TESTING APPARATUS - A connection base assembly for an IC testing apparatus has a base, a top cap and a conductive assembly. The base has a bottom board and an outer frame provided with multiple grooves. The grooves are defined in the top of and extend to the bottom of the outer frame to form multiple through holes in the bottom of the outer frame. The conductive assembly is mounted between the base and the top cap and has multiple conductive elements, multiple top resilient elements and multiple bottom resilient elements. The conductive elements are mounted respectively in the grooves in the outer frame of the base, and each conductive element has a contacting segment and a connecting segment. The top resilient elements and the bottom resilient elements are respectively mounted on and abut with the tops and the bottoms of the resilient elements. | 2010-07-15 |
20100178783 | STRADDLE MOUNT CONNECTOR FOR PLUGGABLE TRANSCEIVER MODULE - A pluggable module for mating with a receptacle connector of a host device. The pluggable module includes a housing having a front and a rear, a circuit board held by the housing that includes a mating edge and a plurality of contact pads arranged at the mating edge, and a straddle mount connector coupled to the mating edge of the circuit board. The straddle mount connector includes a plurality of contacts engaging corresponding contact pads. The contacts extend between a termination end coupled to the contact pads and a mating end configured to engage corresponding contacts of the receptacle connector. The straddle mount connector also includes a dielectric connector body having a platform for supporting the contacts. The platform includes a plurality of dividers between each of the contacts, where the dividers define a plurality of channels that receive the contacts. The dividers extend from the platform beyond the contacts such that the contacts are recessed below an outer surface of the dividers. | 2010-07-15 |
20100178784 | EARTH CONNECTION UNIT - An earth connection unit, in which the elastic engagement piece portion of the earth plate for locking the earth plate to the unit case is engaged with the engagement projection formed on the outer side surface of the unit case, and wherein the elastic engagement piece portion formed on the earth plate is covered with the engagement piece cover integrally interconnecting the plurality of opening covers, and is not exposed to the exterior. | 2010-07-15 |
20100178785 | WIRE CONNECTION UNIT - A wire connection unit includes a connector electrically connecting a first wire and a second wire, a first case and a second case. The second case is joined with the first case, and has an inner face opposing the first case. The inner face is formed with a first groove adapted to hold the first wire and the second wire, a second groove intersecting the first groove, and a first concave portion. The first concave portion is disposed at a part of the first groove except for a position where the second groove intersects the first groove, and accommodating the connector. One of a braided wire pulled out from the first wire and an earth wire electrically connected to the braided wire is accommodated in the second groove. The second groove communicates between a first outside face of the second case and a second outside face of the second case, the second outside case opposite to the first outside face. | 2010-07-15 |
20100178786 | Electric Device Assembly - An electric device assembly has a frame housing provided with electric connectors and an assembly housing containing electric and/or electronic components and adapted to be inserted into the frame housing. A plug connector that has at least one contact tube and at least one contact pin engaging the at least one contact tube is provided. A lock system acting on the plug connector has an actuator that is pivotable about a pivot axis. The actuator is non-detachably secured on the frame housing by a blocking device. The blocking device has a blocking member arranged on a support wall of the frame housing. The blocking member engages a blocking member receptacle that is disposed on the actuator. The actuator is pivotably connected to the support wall by a bearing part received in a bearing receptacle in the support wall. | 2010-07-15 |
20100178787 | Electric Device - An electric device has a plug connection provided with a plug that has at least one contact pin and further provided with a mating plug receptacle that has at least one contact tube. A closure device is arranged on the plug receptacle and has a closed position for protecting the at least one contact tube. The closure device is moved by the plug into an open position when the plug is inserted into the plug receptacle, wherein in the open position the at least one contact tube is released. | 2010-07-15 |
20100178788 | CONNECTOR COUPLING - An electrical power connector is disclosed, configured as either a plug connector or a receptacle connector, which includes at least one retractable lever that provides a mechanical advantage to the user to facilitate the coupling and uncoupling of a plug connector to a receptacle connector. In accordance with an important aspect of the invention, the retractable lever is suitable for applications in which space is relatively limited. The plug connector and the receptacle connector may be formed with a generally circular cross section. The plug connector and the receptacle connector are each connected to an electrical cable on one end. The opposing ends of the plug connector and the receptacle connector are configured to mate with each other so that there is a continuous electrical current path from the cable connected to the plug connector to the cable connected to the receptacle connector. In accordance with an important aspect of the invention, the retractable lever is rotatably connected to one or the other of the plug connector or the receptacle connector. The lever is configured to rotate about a pivot axis generally parallel to the axial axis of the connector. The connector is further configured to be rotatable from a storage position in which the lever rests against a coupling ring and an extended position in which the lever is extended radially outwardly from the coupling ring In the extended position, the lever provides a mechanical advantage to facilitate the coupling or uncoupling of the plug connector with respect to the receptacle connector. In one embodiment of the invention, a retractable lever for assisting in both the coupling and uncoupling directions. The retractable levers may be spring biased to return to the storage positions. | 2010-07-15 |
20100178789 | Connector - There is provided a connector that allows easy engagement even when visual judgment is not possible and that has superior durability as well. In a connector for connecting a first connecting cable connected to one end of a socket and a second connecting cable connected to one end of a plug, through engagement between the socket and the plug, the socket includes a cutout portion formed by cutting away at least one portion from one opening of a cylinder along the peripheral direction thereof, the cutout portion having a V-shape at its deepest portion, a first guiding portion projecting from at least one portion of the opening along the peripheral direction, the first guiding portion having a substantial V-shape at its leading end, and a retaining portion to be retained to a lateral face of the cylinder at the time of engagement with the plug, thus retaining this engagement. The plug includes a second guiding portion engageable into the cutout portion and having a substantial V-shape at its leading end and a pawl portion to be retained to the retaining portion at the time of the engagement with the socket. | 2010-07-15 |
20100178790 | RECEPTACLE CONNECTOR FOR A TRANSCEIVER ASSEMBLY - A receptacle connector includes a housing having a front, a rear, and a cavity configured to receive a mating connector through a slot at the front of the housing. A plurality of contacts are loaded into the cavity of the housing through the rear of the housing, and the contacts have channel portions aligned with one another. A retention plug is separately provided from the housing and securely coupled to the rear of the housing. The retention plug is received within the channel portions of the contacts and engages the contacts to hold the contacts within the cavity. | 2010-07-15 |
20100178791 | Electrical Connector - There is provided an electrical connector in which the retaining force of retaining a front cover is improved. Electrical connectors | 2010-07-15 |
20100178792 | CONNECTOR SYSTEM FOR CONNECTING CABLES TO A BATTERY - A connector system that connects cables to terminals of an electrical device. The connector system includes a first cable connector for terminating a first cable, a first terminal connector mateable with the first cable connector, a second cable connector for terminating a second cable, and a second terminal connector mateable with the second cable connector. The first terminal connector is configured to connect to a first terminal of the electrical device, and the second terminal connector is configured to connect to a second terminal of the electrical device. The first cable connector and the second cable connector are different so that the first cable connector is not mateable with the second terminal connector and the second cable connector is not mateable with the first terminal connector. | 2010-07-15 |
20100178793 | CONNECTING ASSEMBLY FOR CONNECTING ELECTRIC CONNECTOR AND CONTROL BOX - A connecting assembly for an electric cylinder and a control box includes an electric cylinder, an electric control box and a sheathing ring. The electric cylinder includes an actuator and a contractible pipe module perpendicularly connected to an end of the actuator. The electric control box is disposed on an internal side at a right-angled position with respect to the actuator and the contractible pipe module and slidably connected to a side of the actuator. The sheathing ring is sheathed onto a contractible pipe module and slidably connected to a side of the electric control box. The connecting assembly of the invention not only achieves a screwless application, but also provides a quick, simple, convenient and stable assembling process. | 2010-07-15 |
20100178794 | Piercing Terminal, Electric Connector and Their Production Process - This invention is about the electric connector and its processing technique. More specifically, it involves terminals with puncture structure, electric connector and their processing technique. The processing technique herein includes stamping terminal processing, winding displacement processing, injection upper cover, injecting lower cover, piercing processing, removal of material ribbon, front glue chip assembly, assembly of outer metal shell. Among them, the upper cover and lower cover are injected and molded in the middle and rear of the corresponding terminals in array. The processing technique has tackled the problems as unstable contact, poor contact, high electric resistance and micromation which cannot be solved by the current existing electric connector. There should be at least two tusks whose tips are intertwined molded in the electric connector of piercing terminal. The tusks are the pyramid shape with a cambered surface in the inner side; it reduces the electric resistance of electric connector. The upper and lower covers of piercing HDMI electric connector are respectively molded in the arrayed terminals. The rear end of the terminal has molded piercing tusk. The electric connector has become smaller and lighter, improving its performance in every aspect significantly. | 2010-07-15 |
20100178795 | SECURITY SYSTEM FOR A NETWORK DEVICE - A mounting system for a circuit receptacle is provided. The mounting system includes a socket and a circuit receptacle. The socket includes a locking recess that is disposable in an opening of an installation surface. The circuit receptacle includes a locking tab that engages the locking recess and secures the circuit receptacle to the socket. The locking tab may be configured to engage the locking recess in the opening of the installation surface, such that the locking tab is hidden. | 2010-07-15 |
20100178796 | Circuit device and method for manufacturing the same - A circuit device includes an element and a base body. The element has a pair of projections on an outer peripheral surface thereof. The base body has an engagement standing part extending in a standing direction. The element is assembled to the base body in a state, where each of contact surfaces of the engagement standing part is in press-contact with a corresponding projection. The engagement standing part has first and second tapered wall parts. The first tapered wall part has a first tapered surface angled by a first angle relative to the standing direction. The second tapered wall part has a second tapered surface angled by a second angle relative to the standing direction. The second angle is smaller than the first angle. One of the pair of projections is in press-contact with at least one of the first and second tapered surfaces to be deformed. | 2010-07-15 |
20100178797 | LATCHING POWER AND DATA CENTER - An expandable power and data center ( | 2010-07-15 |
20100178798 | CO-AXIAL CONNECTOR - A coaxial connector with an outer conductor having a first plug-side end and a second plug-side end, and an inner conductor having a first plug-side end and a second plug-side end. The inner conductor has a first inner conductor part forming the first plug-side end of the inner conductor and a second inner conductor part forming the second plug-side end of the inner conductor. The two inner conductor parts are arranged and configured such that they are mobile relative to each other in the axial direction, the inner conductor being configured as an inner conductor bellows between the two inner conductor parts. The inner conductor bellows is configured such that upon a change in length, a changing capacitance of the inner conductor bellows is compensated by a correspondingly changing opposite inductance of the inner conductor bellows such that the characteristic impedance of the coaxial connector remains substantially constant. | 2010-07-15 |
20100178799 | CONNECTOR FOR COAXIAL CABLE - A connector for a coaxial cable physically and electrically connects a coaxial cable with various kinds of electric members. The coaxial cable includes a hollow inner conductor and a corrugated outer conductor surrounding the inner conductor. A carrier terminal inserted into the inner conductor of the coaxial cable has a diameter elastically adjusted to an inner diameter of the inner conductor. | 2010-07-15 |
20100178800 | Coaxial Connector For Corrugated Cable - A coaxial cable connector includes an internal corrugated area, an internal clamping member, and a back nut. Axial advancement of the back nut causes at least a portion of the internal clamping member to compress radially inwardly. | 2010-07-15 |
20100178801 | Connector - A connector to be connected to a cable | 2010-07-15 |
20100178802 | Plug connector and multilayer board - The invention relates to a multipolar plug connector ( | 2010-07-15 |
20100178803 | Metal shell, connector and connector assembly - A connector is mounted on a printed circuit board (PCB) and has an insulative housing, a plurality of terminals and a metal shell. The PCB has a plurality of through holes. The metal shell covers the insulative housing and the terminals and has a plurality of mounting legs. The mounting legs are formed on the metal shell and each has two side edges and two solder notches defined respectively in the side edges and aligned with the through holes in the PCB. The through holes and the solder notches receive sufficient solder to securely hold the mounting legs in the through holes. | 2010-07-15 |
20100178804 | DUAL STACKED CONNECTOR - A connector has an insulative housing and two edge card-receiving slots disposed in a stacked arrangement with in the insulative housing. Each slot receives an edge card of an electronic module therein. The slots support conductive terminals that extend from a plurality of individual terminal assemblies. The housing may be positioned in a cage that includes receptacles on a front face of the cage. | 2010-07-15 |
20100178805 | SHIELDING CONNECTOR - A shielding connector has shielding electric wires ( | 2010-07-15 |
20100178806 | COAXIAL CABLE CONNECTOR WITH AN EXTERNAL SENSOR AND METHOD OF USE THEREOF - A coaxial cable connector structure is provided, the connector structure comprising: a connector; a physical parameter sensing circuit mechanically attached to the connector; and a status output component mechanically attached to the connector. The physical parameter sensing circuit configured to sense a condition of the connector. The status output component configured to report an ascertained physical parameter status to a location outside of the connector. A corresponding method of ascertaining a physical parameter status of a connector connection is disclosed. | 2010-07-15 |
20100178807 | CARD CONNECTOR - A card connector according to the present invention includes a bottom wall of a base member configured to support a plurality of contacts in a cantilever manner. A rectangular SIM card is inserted into the card connector in such a manner that the shorter side of the card is parallel to the direction of insertion. The plurality of contacts of the card connector are arranged to correspond to respective plural external contact points of the SIM card. Each of the contacts includes a contact portion, two elastic deformation portions, and a terminal portion. The two elastic deformation portions of the contact are coupled together so as to substantially form an isosceles triangle shape with a vertex angle θ | 2010-07-15 |
20100178808 | ELECTRICAL CONNECTOR FOR ELECTRONIC MODULES - An electrical contact includes a body extending along a longitudinal axis. The body includes a mating contact portion for electrical connection with an electronic module, an intermediate portion extending from the mating contact portion, and a mounting contact portion extending from the intermediate portion for electrical connection with a circuit board. The mounting contact portion extends from the intermediate portion at a bend. The mounting contact portion extends from the bend to an end portion. The body also includes a push surface formed when a carrier strip that initially connects the electrical contact to other electrical contacts is separated from the electrical contact. The push surface is offset from the bend along the longitudinal axis in a direction away from the mating contact portion. | 2010-07-15 |
20100178809 | ELECTRICAL CONNECTOR AND TERMINAL STRUCTURE THEREOF - An electrical connector includes a row of terminals and a plastic base having a row of terminal slots. The terminals are disposed in the slots. Each terminal has an elastically moveable portion having a connection point, a fixing portion fixed into the slot, and a pin portion extending out of the plastic base. An inserted electrical element may be connected to the connection point and elastically move the elastically moveable portion. The row of terminals is one of two rows of terminals formed by oppositely tearing and pressing a metal sheet. The terminals have oppositely torn and cut portions seamlessly oppositely connected together. When the row of terminals is developed into a plane and one of the terminals is reverse-backside joined between the two neighboring terminals, the oppositely torn and cut portion of the terminal is seamlessly jointed to the oppositely torn and cut portions of the two neighboring terminals. | 2010-07-15 |
20100178810 | Connecting Scheme for Orthogonal Assembly of Microstructures - In the present disclosure a device for sensing and/or actuation purposes is presented in which microstructures ( | 2010-07-15 |
20100178811 | Electrical Connector - An electrical connector includes a male electrical connector and a female electrical connector. The male electrical connector includes an electrical connector housing that receives a plurality of contact modules provided with first mating contacts. The female electrical connector includes an electrical connector housing that receives a plurality of contact modules provided with second mating contacts that mate with the first mating contacts. Each of the electrical connector housings has a plurality of electrically insulating plates. The electrically insulating plates extend in a plane substantially perpendicular to a plane of insertion of the contact modules into the electrical connector housings. The electrically insulating plates support at least the first mating contacts. | 2010-07-15 |
20100178812 | ELECTRICAL PLUG CONNECTOR WITH LOCKABLE INSULATING BODY THAT IS UNLOCKABLE WITHOUT TOOLS - An electrical plug connector with a tube-shaped housing section in which a multi-part insulating body with electrical contact elements is disposed, with the insulating body having at least one contact carrier with radially inserted contact elements and a contact carrier sleeve element for holding the contact elements that can be pushed onto the contact carrier. The pre-assembled insulating body can be inserted in the axial direction into the housing section from the side of the housing section that is opposite the plug-in side of the plug connector, with the contact carrier being non-permanently lockable with the contact carrier sleeve element and with the contact carrier sleeve element being non-permanently fixable on the housing section. The invention proposes to implement the contact carrier sleeve element with axially arranged spring arms at a rear sleeve end that faces away from the insertion side, with at least one first spring arm having an outer locking element protruding radially towards the housing section, and at least one second spring arm having an inner locking element projecting radially in the direction of the contact carrier. | 2010-07-15 |
20100178813 | LOW INDUCTANCE BUSBAR ASSEMBLY - A busbar assembly for electrically coupling first and second busbars to first and second contacts, respectively, on a power module is provided. The assembly comprises a first terminal integrally formed with the first busbar, a second terminal integrally formed with the second busbar and overlapping the first terminal, a first bridge electrode having a first tab electrically coupled to the first terminal and overlapping the first and second terminals, and a second tab electrically coupled to the first contact, a second bridge electrode having a third tab electrically coupled to the second terminal, and overlapping the first and second terminals and the first tab, and a fourth tab electrically coupled to the second contact, and a fastener configured to couple the first tab to the first terminal, and the third tab to the second terminal. | 2010-07-15 |