28th week of 2022 patent applcation highlights part 56 |
Patent application number | Title | Published |
20220223404 | CLEANING METHOD AND PROCESSING APPARATUS - A cleaning method for removing a silicon-containing film deposited in a temperature-adjustable process container by a heater and a cooler includes: stabilizing a temperature in the process container to a cleaning temperature; and removing the silicon-containing film by supplying a cleaning gas into the process container stabilized at the cleaning temperature; wherein in the removing the silicon-containing film, a heating capability of the heater and a cooling capability of the cooler are controlled based on the temperature in the process container. | 2022-07-14 |
20220223405 | Processing of Semiconductors Using Vaporized Solvents - Processes and apparatuses for the treatment of semiconductor workpieces are provided. In some embodiments, a method can include placing the workpiece into a process chamber; vaporizing a solvent to create a vaporized solvent; introducing the vaporized solvent into the process chamber; and exposing the workpiece to the vaporized solvent. | 2022-07-14 |
20220223406 | METHOD FOR MANUFACTURING GALLIUM OXIDE FILM - The present invention is a method for manufacturing a gallium oxide film where a mist generated by atomizing a raw-material solution or by forming a raw-material solution into droplets is conveyed using a carrier gas, the mist is heated, and the mist is subjected to a thermal reaction on the substrate to form a film, where as the raw-material solution, a raw-material solution containing at least a chloride ion and a gallium ion is used, and the mist is heated for 0.002 seconds or more and 6 seconds or less. This provides a method for manufacturing an α-gallium oxide film at low cost with excellent film forming speed. | 2022-07-14 |
20220223407 | METHOD AND DEVICE FOR FORMING GRAPHENE STRUCTURE - A method of forming a graphene structure, includes: providing a substrate; performing a preprocessing by supplying a first processing gas including a carbon-containing gas to the substrate while heating the substrate, without using plasma; and after the preprocessing, forming the graphene structure on a surface of the substrate through a plasma CVD using plasma of a second processing gas including a carbon-containing gas. | 2022-07-14 |
20220223408 | METHOD FOR DEPOSITING FILM AND FILM DEPOSITION SYSTEM - A method for depositing a silicon oxide film is provided. In the method, a silicon oxide film is deposited on a substrate by Atomic Layer Deposition with plasma while heating the substrate to a first temperature of 600° C. or higher. The silicon oxide film is annealed at a second temperature higher than the first temperature after completing the depositing the silicon oxide film. | 2022-07-14 |
20220223409 | LOW-K BORON CARBONITRIDE FILMS - Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5. | 2022-07-14 |
20220223410 | CD DEPENDENT GAP FILL AND CONFORMAL FILMS - A method of depositing a silicon-containing material is disclosed. Some embodiments of the disclosure provide films which fill narrow CD features without a seam or void. Some embodiments of the disclosure provide films which form conformally on features with wider CD. Embodiments of the disclosure also provide superior quality films with low roughness, low defects and advantageously low deposition rates. | 2022-07-14 |
20220223411 | METHODS FOR DEPOSITING GAP-FILLING FLUIDS AND RELATED SYSTEMS AND DEVICES - Methods and systems for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses. The recesses are at least partially filled with a gap filling fluid. The gap filling fluid comprises a Si—H bond. | 2022-07-14 |
20220223412 | METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for preparing a semiconductor structure includes: providing a substrate which includes a device region and a shallow trench isolation region surrounding the device region, in which the device region is exposed from a surface of the substrate; depositing a barrier layer on the substrate, the barrier layer at least covering the device region; forming an initial oxide which is located in the device region and in contact with the barrier layer; and removing part of the initial oxide to form a device oxide. | 2022-07-14 |
20220223413 | SEED LAYER FOR FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer. | 2022-07-14 |
20220223414 | ETCHING MASK, METHOD FOR FABRICATING THE SAME, AND METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING THE SAME - A method for fabricating a semiconductor structure includes: providing a substrate and a dielectric layer on the substrate; and forming an etching mask on the dielectric layer; and etching the dielectric layer using the etching mask to form at least one opening therein. The etching mask includes: a hard mask layer, a photoresist layer, and a hexamethyldisilazane (HMDS) layer. The photoresist layer is located over the hard mask layer, and the HMDS layer is located between the hard mask layer and the photoresist layer. | 2022-07-14 |
20220223415 | PATTERNING METHOD - According to an aspect there is provided a patterning method comprising:
| 2022-07-14 |
20220223416 | ANGLED ION IMPLANT TO REDUCE MOSFET TRENCH SIDEWALL ROUGHNESS - Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer. | 2022-07-14 |
20220223417 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a doped substrate, a barrier layer, a channel layer, and a doped semiconductor structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate and at a position lower than the channel layer, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween. | 2022-07-14 |
20220223418 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a doped substrate, a barrier layer, a channel layer, a doped semiconductor structure, and the conductive structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween. The conductive structure is disposed over the doped substrate and makes contact with the doped semiconductor structure, in which the conductive structure extends from the doped semiconductor structure to a position higher than the channel layer and the barrier layer. | 2022-07-14 |
20220223419 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure includes: forming a first diffusion film layer on a dielectric layer, a thickness of the first diffusion film layer being not less than a thickness of a doped layer; forming a hard mask on the first diffusion film layer; etching each film layer corresponding to a first region and a second region toward a substrate, until the first diffusion film layer corresponding to the first region is exposed; and next, removing a first metal oxide layer remaining on the dielectric layer corresponding to the second region. As a result of the presence of the doped layer, the hard mask corresponding to the second region has a relatively small thickness. | 2022-07-14 |
20220223420 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE - A manufacturing method for a semiconductor structure includes: a substrate is provided, the substrate including a first region and a second region; a dielectric layer is formed on the substrate; a first diffusion film layer having a first metal oxide layer is formed on the dielectric layer; the first diffusion film layer corresponding to the second region is removed; a second diffusion film layer is formed on the dielectric layer corresponding to the second region, the second diffusion film layer including a second metal oxide layer interfacing with the dielectric layer; and an annealing treatment is performed to diffuse a first metal element in the first metal oxide layer into the dielectric layer corresponding to the first region and diffuse a second metal element in the second metal oxide layer into the dielectric layer corresponding to the second region. | 2022-07-14 |
20220223421 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE - A manufacturing method for a semiconductor structure of the disclosure includes: a first stack layer is formed; a sacrificial layer is provided on the first stack layer; thermal annealing treatment is performed on the first stack layer and the sacrificial layer so that the first stack layer is formed into a second stack layer; the sacrificial layer and a work function composite layer and a first conductive layer of the second stack layer are removed, and a substrate, a second interface layer and a high-k layer of the second stack layer are retained; and a gate layer is formed on the high-k layer. | 2022-07-14 |
20220223422 | Surface Oxidation Control of Metal Gates Using Capping Layer - A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric. | 2022-07-14 |
20220223423 | SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND TWO SEMICONDUCTOR STRUCTURES - The present application provides a semiconductor structure manufacturing method and two semiconductor structures. The manufacturing method includes: providing a substrate and a silicon layer, the substrate exposing a top surface of the silicon layer; performing deposition to form an alloy layer on the silicon layer, the deposition being performed in a nitrogen-containing atmosphere, and a concentration of nitrogen atoms in the nitrogen-containing atmosphere increasing with an increase in deposition time; and annealing the alloy layer and the silicon layer. In embodiments of the present application, an increase in the concentration of nitrogen atoms can control a silicification reaction of the alloy layer, thereby preventing a line width effect and reducing the resistance of the semiconductor structure. | 2022-07-14 |
20220223424 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure. | 2022-07-14 |
20220223425 | BY-SITE-COMPENSATED ETCH BACK FOR LOCAL PLANARIZATION/TOPOGRAPHY ADJUSTMENT - A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones. | 2022-07-14 |
20220223426 | SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE MANUFACTURING DEVICE - A semiconductor structure manufacturing method includes: providing a substrate; forming a patterned photoresist layer on the substrate, and etching the substrate by using the patterned photoresist layer as a mask; performing, by using a plasma asher, plasma ashing treatment on the patterned photoresist layer and residues produced by etching after the substrate is etched; and performing the plasma ashing treatment in an oxygen-free environment. According to the embodiments of the present application, residues on a semiconductor structure can be removed without producing new residues, thereby improving electrical properties of the semiconductor structure. | 2022-07-14 |
20220223427 | PLASMA PROCESSING APPARATUS AND SYSTEM - A plasma processing apparatus includes a chamber; a substrate support disposed in the chamber and including a lower electrode; an upper electrode disposed above the substrate support; an RF source that supplies an RF power to the lower electrode or the upper electrode, the RF power having a plurality of power levels during a first sequence in a repeating time period, the plurality of power levels including a first power level during a first state and a second state, and a second power level during a third state and a fourth state; and a DC source that applies a DC voltage to the lower electrode, the DC voltage having a plurality of voltage levels during the first sequence in the repeating time period. | 2022-07-14 |
20220223428 | Method for Improved Critical Dimension Uniformity in a Semiconductor Device Fabrication Process - Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening. | 2022-07-14 |
20220223429 | N-POLAR III-N SEMICONDUCTOR DEVICE STRUCTURES - N-polar transistor structures have relied on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers as commercially viable wet etchants do not exist. The present disclosure reports on methods for the fabrication of N-polar III-N transistors using wet etches along with transistor structures that are enabled by the availability of wet-etches. | 2022-07-14 |
20220223430 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - A plasma etching method in an embodiment includes etching a silicon-containing film by using plasma of a hydrofluorocarbon gas. The hydrofluorocarbon gas contains, as a conjugated cyclic compound, hydrofluorocarbon having a composition represented by C | 2022-07-14 |
20220223431 | HIGH CONDUCTIVE PASSIVATION LAYERS AND METHOD OF FORMING THE SAME DURING HIGH ASPECT RATIO PLASMA ETCHING - Disclosed are methods for forming a high aspect ratio (HAR) structure during a HAR etch process in a substrate in a reaction chamber, the method comprising:
| 2022-07-14 |
20220223432 | CONDUCTIVE WIRE STRUCTURE - A conductive wire structure including a first conductive wire and a second conductive wire is provided. The second conductive wire is located on one side of the first conductive wire. The first conductive wire includes a first conductive wire portion and a first pad portion. The first conductive wire portion extends in a first direction and has a first end and a second end. The first pad portion is connected to the first end of the first conductive wire portion. The second conductive wire includes a second conductive wire portion and a second pad portion. The second conductive wire portion extends in a second direction and has a third end and a fourth end. The third end is adjacent to the first end, and the fourth end is adjacent to the second end. The second pad portion is connected to the fourth end of the second conductive wire portion. | 2022-07-14 |
20220223433 | WAFER-TO-WAFER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening. | 2022-07-14 |
20220223434 | METHOD FOR MAKING A RECESS OR OPENING INTO A PLANAR WORKPIECE USING SUCCESSIVE ETCHING - A method for making a recess or opening in a planar workpiece with a thickness of less than 3 millimeters includes successively etching a plurality of flaws to form the recess or opening such that a contour of the recess or opening has a sequence of widenings and constrictions as a result of the etching. | 2022-07-14 |
20220223435 | HEAT DISSIPATING SUBSTRATE FOR SEMICONDUCTOR AND PREPARATION METHOD THEREOF - Provided are a heat dissipating substrate and a preparation method thereof, which can form a precise pattern in a thick electrode metal plate and improve insulating strength and peel strength. heat dissipating substrate for semiconductor may include: an electrode metal plate having a plurality of electrode patterns which are electrically insulated from each other by a pattern space formed therebetween; a metal base disposed under the electrode metal plate, and configured to diffuse heat conducted from the electrode metal plate; an insulating layer formed between the electrode metal plate and the metal base; and an insulating material filled portion configured to fill the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, and support the electrode patterns while brought in direct contact with side surfaces of the plurality of electrode patterns. | 2022-07-14 |
20220223436 | ETCHING DEVICE AND ETCHING METHOD USING THE SAME - An etching device includes a nozzle unit including at least one nozzle including an etching solution injection hole, an etching solution collection hole, and a sealing part. The etching solution injection hole is configured to provide an etching solution to an etching object, the etching solution collection hole is configured to collect the etching solution, and the sealing part surrounds the etching solution injection hole and the etching solution collection hole to prevent the etching solution from leakage. | 2022-07-14 |
20220223437 | SELF-ASSEMBLY APPARATUS AND METHOD FOR SEMICONDUCTOR LIGHT-EMITTING DEVICES - A self-assembly apparatus and method of the present invention for semiconductor light-emitting devices can separate semiconductor light-emitting devices attached to each other by vibrating a fluid during self-assembly to thereby prevent mis-assembly and, for smooth assembly of the semiconductor light emitting devices, generate a flow of the fluid along the movement direction of a magnet. The self-assembly apparatus comprises: a chamber in which a plurality of semiconductor light-emitting devices comprising a magnetic substance and a fluid are accommodated; a transfer unit for transferring, to an assembly location, a substrate on which the semiconductor light-emitting devices are to be assembled; a magnet spaced apart from the chamber to apply a magnetic force to the semiconductor light-emitting devices; a location control unit for controlling a location of the magnet; and a vibration generation unit for generating vibration in the fluid to thereby separate the semiconductor light-emitting devices from each other. | 2022-07-14 |
20220223438 | HOLDING DEVICE - The object of the technique disclosed in this specification is to prevent or reduce the occurrence of chipping of a ceramic tubular member. | 2022-07-14 |
20220223439 | SUBSTRATE PROCESSING APPARATUS - The present disclosure provides a substrate processing apparatus including: a load lock chamber configured to accommodate a substrate and be sealed in a vacuum state; a reaction chamber configured to accommodate the load lock chamber; and an opening/closing member extending toward the load lock chamber accommodated in the reaction chamber and configured to open or close the load lock chamber. | 2022-07-14 |
20220223440 | RAPID TUNING OF CRITICAL DIMENSION NON-UNIFORMITY BY MODULATING TEMPERATURE TRANSIENTS OF MULTI-ZONE SUBSTRATE SUPPORTS - A substrate processing system includes a processing chamber, a substrate support including a plurality of heater zones arranged in the processing chamber, a gas delivery system configured to deliver process gases to the processing chamber, and a controller configured to communicate with the gas delivery system and the plurality of heater zones, initiate a first treatment step of a process during a transient temperature period after a substrate is arranged on the substrate support and prior to the substrate reaching a steady-state temperature of the substrate support, and adjust heating to each of the plurality of heater zones during the first treatment step based on average heat functions determined for corresponding ones of the plurality of heater zones during a period corresponding to the first treatment step. | 2022-07-14 |
20220223441 | PROCESS CONDITION SENSING APPARATUS - An enclosure assembly is disclosed, in accordance with one or more embodiment of the present disclosure. The enclosure assembly includes a top portion. The enclosure assembly further includes a bottom portion. The top portion is detachably connectable to the bottom portion via one or more coupling devices. The top portion is further reversibly, electrically couplable to the bottom portion via one or more electronic contacts. One or more electronic components are disposed within the enclosure assembly. | 2022-07-14 |
20220223442 | SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL METHOD THEREOF - A semiconductor manufacturing apparatus includes: a reaction chamber; a pipe connected to the reaction chamber; a vacuum pump that has an intake port and an exhaust port, and in which the intake port or the exhaust port is connected to the pipe; a first acoustic sensor provided in the pipe; and a control device including a determination unit configured to determine clogging of the pipe based on a first output of the first acoustic sensor. | 2022-07-14 |
20220223443 | STATE DETERMINATION DEVICE, STATE DETERMINATION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A state determination device determines the state of a drive mechanism configured to operate while holding a substrate in a substrate processing apparatus. The state determination part includes: an acquisition part configured to acquire operation data for the drive mechanism; a model generation part configured to generate a monitoring model for the drive mechanism by executing machine learning using an auto-encoder based on normal operation data that is derived from the operation data acquired by the acquisition part when the drive mechanism is operating normally; and a first determination part configured to determine the state of the drive mechanism based on first output data obtained by inputting, to the monitoring model, evaluation data that is derived from the operation data acquired by the acquisition part when the drive mechanism is being evaluated. | 2022-07-14 |
20220223444 | DYNAMIC DISPATCHING METHOD FOR SEMICONDUCTOR MANUFACTURING SYSTEM - A dynamic dispatching method for semiconductor manufacturing system relates to a dynamic dispatching rule based on self-organization for dispatching in a semiconductor manufacturing system, including S1: setting roles and parameters of self-organization units, and defining key nodes in a production environment; S2: constructing a negotiation mechanism between the self-organization units, and designing a decision-making and dispatching subject ESOU; S3: according to a decision instruction of the ESOU, designing a LSOU allocation dispatching unit for distinguishing single-batch processing and multi-batch processing; and S4: designing a dispatching mechanism based on the self-organization units to implement dynamic semiconductor dispatching. The dynamic dispatching method includes three aspects: role definitions of self-organization units, a negotiation mechanism between the self-organization units and a decision-making method thereof. The simulation based on a real industry benchmark production line shows that the method improves the work movement, throughput and on-time delivery rate by 4.9%, 9.06% and 20.23%. | 2022-07-14 |
20220223445 | FIB-SEM 3D Tomography for measuring shape deviations of HAR structures - A 3D tomographic inspection method for the inspection of semiconductor features in an inspection volume of a semiconductor wafer includes obtaining a 3D tomographic image, and selecting a plurality of 2D cross section images. The method also includes identifying contours of HAR structures, and extracting deviation parameters. The deviation parameters describe fabrication errors such as displacement, deviation in radius or diameter, area or shape. | 2022-07-14 |
20220223446 | TRANSPORT SYSTEM AND TRANSPORT CONTROL METHOD - A transport system includes a controller that controls a vehicle, wherein the controller assigns a first transport instruction instead of a transport instruction, to cause the vehicle to pick up an article at a pickup port and travel to a specified location on a downstream side of the pickup port in a traveling direction of the vehicle at which a route can be secured on the track when a route for the vehicle from a pickup port to an unloading port designated by the transport instruction cannot be secured, and the controller assigns a second transport instruction to cause the vehicle to travel from the specified location to the unloading port and unload the article at the unloading port when a route from the specified location to the unloading port can be secured at a point in time at which the vehicle approaches or reaches the specified location. | 2022-07-14 |
20220223447 | SUBSTRATE TRANSFER APPARATUS, SUBSTRATE TRANSFER METHOD, AND SUBSTRATE PROCESSING SYSTEM - A substrate transfer apparatus for transferring a substrate is disclosed. The apparatus comprises: a transfer unit including a substrate holder configured to hold a substrate, and a base having therein a magnet and configured to move the substrate holder; a planar motor including a main body, a plurality of electromagnetic coils disposed in the main body, and a linear driver configured to supply a current to the electromagnetic coils, and magnetically levitate and linearly drive the base; a substrate detection sensor configured to detect the substrate when the substrate held by the substrate holder passes by; and a transfer controller configured to calculate an actual position of the substrate held by the substrate holder based on detection data of the substrate detection sensor, calculate correction values for a logical position that has been set, and correct a transfer position of the substrate based on the correction values. | 2022-07-14 |
20220223448 | MULTIPLE TRANSPORT CARRIER DOCKING DEVICE - A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers. | 2022-07-14 |
20220223449 | TRANSPORT CARRIER DOCKING DEVICE - A transport carrier docking device may be capable of forming an air-tight seal around a transport carrier while a front portion of the transport carrier is inserted into a chamber of the transport carrier docking device. Semiconductor wafers in the transport carrier may be accessed by a transport tool while the air-tight seal exists around the transport carrier, which prevents and/or reduces the likelihood that contaminants in a semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers. | 2022-07-14 |
20220223450 | APPARATUS FOR PRODUCING SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - An apparatus ( | 2022-07-14 |
20220223451 | SYSTEMS AND METHODS FOR TRANSFERRING DEVICES OR PATTERNS TO A SUBSTRATE - The present disclosure relates to transferring system and methods and more specifically to transferring multiple patterns or devices from a transfer medium to a substrate. The transferring apparatus comprising a first holder to hold a substrate, a second holder to hold a transfer medium, wherein the transfer medium comprises one of a: device or pattern, a first alignment system coupled to the second holder while the second holder moves in a first direction relative to one dimension of the substrate to transfer the device or the pattern; and a second alignment system coupled to the second holder while the second holder moves in a second direction relative to another dimension of the substrate to transfer the device or the pattern to the substrate, wherein the transferring apparatus is operable to transfer a plurality of devices and patterns to the substrate. | 2022-07-14 |
20220223452 | CHUCK ASSEMBLY, SEMICONDUCTOR DEVICE FABRICATING APPARATUS INCLUDING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Disclosed are chuck assemblies, semiconductor device fabricating apparatuses, and methods of fabricating semiconductor devices. The chuck assembly comprises a chuck base including lower and upper bases, a ceramic plate on the upper base, an edge ring that surrounds the ceramic plate, a ground ring that surrounds an outer sidewall of the edge ring on an edge portion of the lower base, a coupling ring between the ground ring and the upper base and between the edge ring and the edge portion of the lower base, an upper heat sink between the coupling ring and the edge ring, and a sidewall heat sink between the coupling ring and the ground ring and between the coupling ring and the upper base. | 2022-07-14 |
20220223453 | ELECTROSTATIC CHUCK - Electrostatic chucks and methods of forming electrostatic chucks are disclosed. Exemplary electrostatic chucks include a ceramic body, a device embedded within the ceramic body, and an interface layer formed overlying the device. Exemplary methods include providing ceramic precursor material within a mold, providing a device, coating the device with an interface material to form a coated device, placing the coated device on or within the ceramic precursor material, and sintering the ceramic precursor material to form the electrostatic chuck and an interface layer between the device and ceramic material formed during the step of sintering. | 2022-07-14 |
20220223454 | SUBSTRATE FIXING DEVICE - A substrate fixing device includes: a base plate; an electrostatic adsorption member that adsorbs and holds a substrate; and a first adhesive layer that adhesively bonds the electrostatic adsorption member to the base plate. A storage modulus of the first adhesive layer is not less than 0.01 MPa and not more than 25 MPa within a temperature range of −110° C. to 250° C. | 2022-07-14 |
20220223455 | COMPOSITE SINTERED BODY, ELECTROSTATIC CHUCK MEMBER, ELECTROSTATIC CHUCK DEVICE, AND METHOD FOR MANUFACTURING COMPOSITE SINTERED BODY - A composite sintered body including: a metal oxide as a main phase; silicon carbide as a sub-phase; and silicate of a metal element that is included in the metal oxide, in which the average aggregation diameter of the silicate in the field of view of 600 μm | 2022-07-14 |
20220223456 | METAL FOIL WITH CARRIER AND USE METHOD AND MANUFACTURING METHOD THEREFOR - Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development. | 2022-07-14 |
20220223457 | DELAMINATION PROCESSES AND FABRICATION OF THIN FILM DEVICES THEREBY - Interfacial delamination processes for physically separating a film structure from a substrate, and processes of fabricating a thin-film electronic device. The processes entail providing the substrate with an electrically-conductive separation layer on a surface of the substrate and optionally providing a pin hole free barrier layer on the electrically-conductive separation layer, forming a film structure on the electrically-conductive separation layer or, if present, the barrier layer, to yield a multilayer structure, and separating the film structure from the substrate by subjecting the multilayer structure to interfacial debonding that comprises contacting at least an interface between the film structure and the electrically-conductive separation layer or, if present, the barrier layer, with water or an electrolyte solution. | 2022-07-14 |
20220223458 | 3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH A SINGLE-CRYSTAL LAYER - A 3D semiconductor device including: a first single-crystal layer including a plurality of first transistors; at least one first metal layer disposed atop the plurality of first transistors; a second metal layer disposed atop the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed atop the plurality of fourth transistors; a fourth metal layer disposed atop the third metal layer; a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error. | 2022-07-14 |
20220223459 | METHOD FOR PRODUCING 3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH A SINGLE-CRYSTAL LAYER - A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed on top of the control circuits; performing a first etch step including etching first holes within the second level; and performing additional processing steps (including Atomic Layer Deposition) to form a plurality of memory cells within the second level, where each memory cell includes at least one second transistor, where making the second level includes forming lithography holes atop of the first alignment marks which enables performing lithography steps aligned to the first alignment marks, including at least the first etch step above. | 2022-07-14 |
20220223460 | TRANSFERRING APPARATUS AND METHOD FOR TRANSFERRING ELECTRONIC COMPONENT - A transferring apparatus configured to transfer a plurality of electronic components on a carrier film to a substrate. The transferring apparatus includes a controller and an abutting module. The abutting module is electrically connected to the controller, and includes an abutting element and a negative pressure generating device. The controller is configured to control the abutting element to move towards the substrate so as to abut the carrier film but not to penetrate through the carrier film, whereby the abutting element pushes the carrier film so as to push at least one of the electronic components to the substrate. The controller is configured to control the negative pressure generating device to suck air towards a direction opposite to a direction of the abutting element pushing the carrier film, so as to generate negative pressure to suck the carrier film. A method for transferring an electronic component is also provided. | 2022-07-14 |
20220223461 | SUBSTRATE TRANSPORTATION HAND, SUBSTRATE TRANSPORTATION SYSTEM, STORAGE MEDIUM, AND METHOD FOR PRODUCING ARTICLE - A substrate transportation hand for transporting a substrate includes: at least one first holding part provided on an upper surface side of the substrate transportation hand and capable of sucking and holding the substrate; at least one second holding part provided on a lower surface side of the substrate transportation hand and capable of sucking and holding the substrate; and a drive unit for independently turning on/off sucking using the first holding part and the second holding part, in order to provide a substrate transportation hand which can efficiently transport while preventing dust in accordance with a form of a substrate. | 2022-07-14 |
20220223462 | USING CONTROLLED GAS PRESSURE FOR BACKSIDE WAFER SUPPORT - Embodiments described herein provide substrate support assemblies for retaining a surface of a substrate having one or more devices disposed on one or more surfaces of the substrate without contacting the one or more devices and preventing changes in profile of the substrate. The substrate support assembly allows for control of the substrate. The substrate support assembly includes a gas nozzle disposed through a body of the substrate support assembly. The gas nozzle provides a gas to the substrate. The gas is operable to provide pressure to the substrate to reduce contact on the substrate and to control the profile of the substrate. | 2022-07-14 |
20220223463 | DEPOSITION APPARATUS AND DEPOSITION METHOD - A deposition apparatus includes a processing chamber, and a susceptor provided in the processing chamber. The susceptor has a recess on a surface of the susceptor. The recess includes a support and a groove, the support supports a region that includes a center of a substrate and that does not include an edge of the substrate, the groove is located around the support, and the groove is recessed relative to the support. The deposition apparatus further includes a process gas supply configured to supply a process gas to the surface of the susceptor and a purge gas supply configured to supply a purge gas to the groove. | 2022-07-14 |
20220223464 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region. | 2022-07-14 |
20220223465 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap. | 2022-07-14 |
20220223466 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate provided therein with shallow trenches and active regions defined by the shallow trenches, the shallow trenches having, in a predetermined direction, first regions and second regions which are alternately arranged, a width of the first region being greater than a width of the second region; and a shallow trench isolation structure filled in the shallow trench, the shallow trench isolation structure at least including, in the first region, a first filling layer and a second filling layer which are sequentially arranged, wherein the second filling layer is configured as a low-K dielectric layer; in the second region, the shallow trench isolation structure at least including the first filling layer. | 2022-07-14 |
20220223467 | METHOD FOR DIRECT HYDROPHILIC BONDING OF SUBSTRATES - A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and/or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface. | 2022-07-14 |
20220223468 | SEMICONDUCTOR STRUCTURE AND ITS MANUFACTURING METHOD - Embodiments of the present application provide a semiconductor structure and its manufacturing method. The method for manufacturing a semiconductor structure includes: providing a substrate and a dielectric layer located on the substrate, the substrate being provided therein with a conductive structure; etching a certain thickness of the dielectric layer to form a first groove; performing an isotropic etching process on the dielectric layer located at the bottom of the first groove to form a second groove, a maximum width of the second groove being greater than a bottom width of the first groove in a direction parallel with a surface of the substrate; and etching the dielectric layer located at the bottom of the second groove to form a third groove exposing the conductive structure. | 2022-07-14 |
20220223469 | METHODS FOR FORMING STAIRS IN THREE-DIMENSIONAL MEMORY DEVICES - The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process. | 2022-07-14 |
20220223470 | METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS - A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask. | 2022-07-14 |
20220223471 | LOW RESISTIVITY FILMS CONTAINING MOLYBDENUM - Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer. | 2022-07-14 |
20220223472 | Ruthenium Reflow For Via Fill - A method for forming conductive structures for a semiconductor device includes depositing a reflow material in features, e.g. vias, formed in a dielectric layer. A high melting point material is deposited in the feature and is reflowed and annealed in an ambient comprising one or more of hydrogen molecules, hydrogen ions, and hydrogen radicals at a temperature greater than 300° C. to fill the feature with a reflow material. | 2022-07-14 |
20220223473 | TOP VIA ON SUBTRACTIVELY ETCHED CONDUCTIVE LINE - A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line. | 2022-07-14 |
20220223474 | Methods for Forming Self-Aligned Interconnect Structures - The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer. | 2022-07-14 |
20220223475 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM - A substrate processing method of processing a processing target substrate having a device formed on a front surface thereof includes preparing, in a first separation substrate on a side with the device and a second separation substrate on a side without the device separated from a device substrate, the second separation substrate; and bonding, by reusing the second separation substrate, the second separation substrate to a processing target substrate. A substrate processing system configured to process the processing target substrate having the device formed on the front surface thereof includes a bonding device configured to bond, in the first separation substrate on the side with the device and the second separation substrate on the side without the device separated from the device substrate, the second separation substrate to the processing target substrate by reusing the second separation substrate. | 2022-07-14 |
20220223476 | CRYSTAL EFFICIENT SIC DEVICE WAFER PRODUCTION - There is provided a method for manufacturing a SiC device wafer comprising the steps: a) slicing and polishing a SiC boule to thicker substrates compared to the usual thickness in the prior art, b) creating a device wafer on the substrate, c) removing the device wafer from the remaining substrate, d) adding SiC to the remaining substrate so that the original thickness of the substrate is essentially restored, and repeating steps b)-d). The removal of the device wafer can be made for instance by laser slicing. Advantages include that the SiC material loss is significantly decreased and the boule material used for device wafers is considerably increased, the substrates become more stable especially during high temperature processes, the warp and bow is reduced, the risk of breakage is decreased. | 2022-07-14 |
20220223477 | TWO-DIMENSIONAL VERTICAL FINS - A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate. | 2022-07-14 |
20220223478 | GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer. | 2022-07-14 |
20220223479 | METHOD AND DEVICE FOR PREDICTING INCLINATION ANGLE, AND METHOD AND DEVICE FOR MONITORING ETCHING DEVICE - A method for predicting an inclination angle of an etched hole can include operations as follows. A preset change range of an etching rate of an etching device for an object to be etched on a surface of a monitored sample in different operation stages is determined. An etching rate change curve of the etching device for the object to be etched on the surface of a monitored sample in a current operation stage is acquired. When the etching rate change curve exceeds the preset change range, it is determined that an inclination angle of an etched hole of an etched product currently etched by the etching device exceeds a preset angle. | 2022-07-14 |
20220223480 | WAFER MEASUREMENT METHOD AND APPARATUS, MEDIUM, AND ELECTRONIC DEVICE - A wafer measurement method and apparatus, a medium, and an electronic device are provided. The measurement method includes: acquiring a wafer measurement region image; identifying a characteristic marker in the wafer measurement region image; determining an actual position of the characteristic marker in the wafer measurement region image; determining a deviation amount of the characteristic marker according to the actual position of the characteristic marker and a standard position of the characteristic marker; and determining a deviation amount of a measurement point in the wafer measurement region image according to the deviation amount of the characteristic marker. | 2022-07-14 |
20220223481 | METHOD AND SYSTEM FOR AUTOMATICALLY DETECTING AND CONTROLLING DEFECTS ON WAFER - The present disclosure provides a method and a system for automatically detecting and controlling defects on a wafer. The method includes the following steps: providing at least one stacked wafer; constructing a defect distribution map based on a defect information on each of the at least one wafer, wherein, the defect information includes the number of defects, types of the defects, and locations of the defects; partitioning at least one predetermined region in the defect distribution map; determining the number of predetermined defects in each of the at least one predetermined region based on the locations of the defects; comparing the number of the predetermined defects in the each of the at least one predetermined region with a set threshold, and determining detection results based on comparison results. | 2022-07-14 |
20220223482 | EVALUATION METHOD AND MANUFACTURING METHOD OF SiC EPITAXIAL WAFER - A SiC epitaxial wafer including a high-concentration epitaxial layer having an impurity concentration of 1×10 | 2022-07-14 |
20220223483 | AN ALIGNMENT PROCESS FOR THE TRANSFER SETUP - A method of aligning a first substrate and a second substrate comprises positioning the first substrate having at least a first alignment mark in close proximity to the second substrate having at least a second alignment mark, measuring an alignment value between the first and second alignment marks of both the first and second substrate; and adjusting the position of the first substrate and the second substrate based on the measured alignment value. | 2022-07-14 |
20220223484 | Assembly and Method for Performing In-Situ Endpoint Detection When Backside Milling Silicon Based Devices - An assembly for monitoring a semiconductor device under test comprising a mill configured to mill the device, a sensor configured to measure an electrical characteristic of the device, and a computer configured to determine the amount of strain in the device from the electrical characteristic when the mill is milling the device and detect an endpoint of milling at a circuit within the device. In use the endpoints of the milling process of the semiconductor device are detected measuring an electrical characteristic of the device with a sensor during milling determining the amount of strain in the device from the electrical characteristic and detecting an endpoint of the milling process within the device based on the amount of strain. | 2022-07-14 |
20220223485 | SEMICONDUCTOR DEVICES INCLUDING SCRIBE LANE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall. | 2022-07-14 |
20220223486 | SEMICONDUCTOR PACKAGES WITH ENGAGEMENT SURFACES - An example semiconductor package includes a semiconductor die configured to detect a force. In addition, the semiconductor package includes a mold compound covering the semiconductor die. Further, the semiconductor package includes an engagement surface including a pattern of projections adapted to engage with a mounting surface on a member of interest. | 2022-07-14 |
20220223487 | EMBEDDED COMPONENT AND METHODS OF MAKING THE SAME - Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material. | 2022-07-14 |
20220223488 | SEMICONDUCTOR PACKAGES INCLUDING INTERFACE MEMBERS FOR WELDING - An example semiconductor package includes a semiconductor die. In addition, the semiconductor package includes a mold compound having a first side, a second side opposite the first side, and an axis extending between the first side and the second side, the mold compound covering the semiconductor die. Further, the semiconductor package includes an interface member including a first portion and a second portion, the first portion is coupled to the second portion. The first portion is positioned along the first side, the second portion is positioned along the second side, and an engagement of a welding horn with the first portion is adapted to weld the second portion to a surface. | 2022-07-14 |
20220223489 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed. | 2022-07-14 |
20220223490 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a semiconductor die including a sensing component, an encapsulant laterally covering the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant, a patterned dielectric layer disposed on the top surfaces of the encapsulant and the semiconductor die, a conductive pattern disposed on and inserted into the patterned dielectric layer to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV. The top surface of the encapsulant is above and rougher than a top surface of the semiconductor die, and the sensing component is accessibly exposed by the patterned dielectric layer. | 2022-07-14 |
20220223491 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader. | 2022-07-14 |
20220223492 | COPPER/CERAMIC JOINED BODY, INSULATING CIRCUIT SUBSTRATE, COPPER/CERAMIC JOINED BODY PRODUCTION METHOD, AND INSULATING CIRCUIT SUBSTRATE PRODUCTION METHOD - This copper/ceramic bonded body includes: a copper member made of copper or a copper alloy; and a ceramic member made of silicon nitride, wherein the copper member and the ceramic member are bonded to each other, a Mg—N compound phase extending from a ceramic member side to a copper member side is present at a bonded interface between the copper member and the ceramic member, and at least a part of the Mg—N compound phase enters into the copper member. | 2022-07-14 |
20220223493 | INSULATION CIRCUIT BOARD WITH HEAT SINK - An insulated circuit board which is obtained by bonding a circuit layer onto one side of a ceramic substrate, and bonding a metal layer made of copper or copper alloy onto the other side of the ceramic substrate; and a heat sink which is bonded to the metal layer are included; the heat sink has a first metal layer made of aluminum or aluminum alloy joined to the metal layer, a ceramic board material joined to the first metal layer at an opposite side to the metal layer, and a second metal layer made of aluminum or aluminum alloy joined to the ceramic board material at an opposite side to the first metal layer; a thickness T1 of the first metal layer and a thickness T2 of the second metal layer are 0.8 mm to 3.0 mm inclusive; and a thickness ratio T1/T2 is 1.0 or more. | 2022-07-14 |
20220223494 | MICRO HEAT PIPE FOR USE IN SEMICONDUCTOR IC CHIP PACKAGE - A micro heat transfer component includes a bottom metal plate; a top metal plate; a plurality of sidewalls each having a top end joining the top metal plate and a bottom end joining the bottom metal plate, wherein the top and bottom metal plates and the sidewalls form a chamber in the micro heat transfer component; a plurality of metal posts in the chamber and between the top and bottom metal plates, wherein each of the metal posts has a top end joining the top metal plate and a bottom end joining the bottom metal plate; a metal layer in the chamber, between the top and bottom metal plates and intersecting each of the metal posts, wherein a plurality of openings are in the metal layer, wherein a first space in the chamber is between the metal layer and bottom metal plate and a second space in the chamber is between the metal layer and top metal plate; and a liquid in the first space in the chamber. | 2022-07-14 |
20220223495 | READILY ASSEMBLED/DISASSEMBLED COOLING ASSEMBLY FOR IMMERSION COOLED SEMICONDUCTOR CHIP PACKAGE - A cooling assembly is described. The cooling assembly includes a semiconductor chip package having input/outputs (I/Os) on a first surface and a package lid that is opposite the first surface, the semiconductor chip package has sides between the first surface and the package lid. The cooling assembly includes a structured element. The structured element has a structured surface to nucleate bubbles in a bath of coolant. The structured element has fixturing elements to secure the structured element to at least first and second ones of the sides of the semiconductor chip package. The structured element has a first thermal resistance. The cooling assembly has a thermal interface material between the package lid and the structured element. The thermal interface material has a second thermal resistance that is greater than the first thermal resistance and within an order of magnitude of the first thermal resistance. | 2022-07-14 |
20220223496 | INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING - A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane. | 2022-07-14 |
20220223497 | INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING - A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat. | 2022-07-14 |
20220223498 | BACKSIDE OR FRONTSIDE THROUGH SUBSTRATE VIA (TSV) LANDING ON METAL - Some embodiments relate to a semiconductor structure including a semiconductor substrate, and n interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a dielectric structure and a plurality of metal lines that are stacked over one another in the dielectric structure. A through substrate via (TSV) extends through the semiconductor substrate to contact a metal line of the plurality of metal lines. A protective sleeve is disposed along outer sidewalls of the TSV and separates the outer sidewalls of the TSV from the dielectric structure of the interconnect structure. | 2022-07-14 |
20220223499 | SUBSTRATE COMPRISING INTERCONNECTS IN A CORE LAYER CONFIGURED FOR SKEW MATCHING - A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching. | 2022-07-14 |
20220223500 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure includes a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate including a first area and a second area, a vertical insulating film passing through the substrate between the first area of the substrate and the second area of the substrate, an interlayer insulating structure disposed on the substrate, and a conductive pad formed on the interlayer insulating structure and overlapping the first area of the substrate. The semiconductor device also includes a through electrode passing through the conductive pad, the interlayer insulating structure, and the substrate in the first area. | 2022-07-14 |
20220223501 | SEMICONDUCTOR MODULE - A semiconductor module includes: semiconductor elements having a gate electrode, a first electrode and a second electrode; a resin mold; and conductive members connected to at least one of the semiconductor elements and having a common wiring electrode exposed from the resin mold and connected to the first electrode or the second electrode and a non-common wiring electrode exposed from the resin mold and connected to an electrode of the semiconductor element different from the common wiring electrode. A width of a common wiring connected to the common wiring electrode is wider than the non-common wiring electrode. The common wiring is arranged from one side to an opposite side on a surface of the resin mold, on which the common wiring electrode is exposed, without being electrically connected to the non-common wiring electrode. | 2022-07-14 |
20220223502 | SEMICONDUCTOR MODULE - A semiconductor module includes: two semiconductor elements stacked in a vertical direction to overlap at least a part of the semiconductor elements; a conductive member stacked on the semiconductor elements and electrically connected to at least one of the semiconductor elements; and a resin mold integrally sealing the semiconductor elements and the conductive member. A lower semiconductor element has at least observable positions of both ends of two sides substantially orthogonal to each other when viewed from above in the vertical direction without arranging the resin mold. | 2022-07-14 |
20220223503 | SPRING BAR LEADFRAME, METHOD AND PACKAGED ELECTRONIC DEVICE WITH ZERO DRAFT ANGLE - A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another. | 2022-07-14 |