28th week of 2013 patent applcation highlights part 54 |
Patent application number | Title | Published |
20130179620 | Administering Connection Identifiers For Collective Operations In A Parallel Computer - Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold. | 2013-07-11 |
20130179621 | EXTENSIBLE DAISY-CHAIN TOPOLOGY FOR COMPUTE DEVICES - Devices, systems and methods for providing a daisy-chain topology for networking compute devices having PCIe bridges are disclosed. The daisy-chain topology is an extensible PCIe or similar standard solution that allows for a variable number of nodes. The topology has no chassis and no fixed slots, and there is no single device or bridge designated as the PCIe root. This topology allows additional devices to be added to the daisy-chain without construction of a new chassis. Some or all of can be mechanically coupled to provide a common communication channel. Once connected on the expansion link, any device has the ability to communicate to any other device on the daisy-chain. The devices on the daisy-chain are able to let their CPU or processors directly talk to those of another device. This results in a master/master relationship rather than one device serving as the master and the remaining devices the slaves. | 2013-07-11 |
20130179622 | SYSTEM AND METHOD FOR TRANSMITTING AND RECEIVING DATA USING AN INDUSTRIAL EXPANSION BUS - A system for transmitting and receiving data using an industrial expansion bus connected to a chassis is provided, the industrial expansion bus having a plurality of module slots, the system having a programmable logic controller (PLC) control rack and a PLC remote rack. The PLC control rack has a first embedded central processing unit (CPU), and a first peripheral component interconnect express (PCIe) module adapted to send and receive PCIe compliant signals. The PLC remote rack has a second PCIe module adapted to send and receive PCIe compliant signals, and a second embedded CPU. The first PCIe module and the second PCIe module are communicatively coupled with cable to provide an interface between the first and second CPUs. A method for polling a local peripheral and a distant peripheral is also provided. | 2013-07-11 |
20130179623 | Buffer Managing Method and Buffer Controller thereof - By assigning a slave unit and at least one master unit in a buffer controller, clocks of the at least one master unit can be unified with a clock of the slave unit. A buffer status array is assigned for the slave unit in a buffer, and either a range status array or a queue status array is assigned for the master unit in the buffer for performing operations of the buffer controller in an accessing-by-block manner or in an accessing-by-spaced-interval manner. The master unit cooperated with the slave unit is determined from the at least one master unit by using a starvation-preventing algorithm. | 2013-07-11 |
20130179624 | SYSTEMS AND METHODS FOR TRACKING AND MANAGING NON-VOLATILE MEMORY WEAR - Systems and methods are disclosed that may be implemented to manage operation and tracking memory wear of flash devices, such as relatively large mixed use embedded NAND flash devices or other non-volatile memory (NVM) devices employed in information handling systems such as servers. The disclosed systems and methods may advantageously be implemented to perform tasks such as tracking and/or predicting actual wear for NVM devices, and optionally controlling write operations to a NVM device. The disclosed systems and methods may also be optionally implemented to generate wear alerts based on tracked or predicted wear of such NVM devices. | 2013-07-11 |
20130179625 | Security System Storage of Persistent Data - A security system including devices generating persistent data, a local control system (LCS) including a microprocessor and non-volatile memory and receiving persistent data from the devices, and a server remote from the LCS. The remote server is in communication with the LCS microprocessor which periodically transmits logical portions of persistent data (each including a timestamp) to the remote server where it is saved. The microprocessor also periodically saves the persistent data portions in LCS non-volatile memory less frequently than the persistent data portions are periodically saved in the remote data storage, and saves the timestamp in the local data storage for each persistent data portion saved only at the remote server. When rebooting the LCS, the microprocessor retrieves from the remote data storage only the persistent data portions having timestamps subsequent to the timestamp saved in the local data control system non-volatile memory. | 2013-07-11 |
20130179626 | DATA PROCESSING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data processing method for a memory storage apparatus having physical blocks is provided. The method includes: grouping the physical blocks into a data area, a spare area and a system area; configuring a plurality of logical addresses which would be formatted into a file allocation table area having cluster entry fields, a root directory area having directory entry fields and a file area having clusters; storing a communication file from the K | 2013-07-11 |
20130179627 | METHOD FOR MANAGING BUFFER MEMORY, MEMORY CONTROLLOR, AND MEMORY STORAGE DEVICE - A method for managing a buffer memory in a memory storage device is provided, wherein the memory storage device has a rewritable non-volatile memory module. The method includes transmitting temporary data from the buffer memory to a buffer area of the rewritable non-volatile memory module by using a pre-programmed command set, wherein the temporary data is not programmed into a storage area of the rewritable non-volatile memory module. The method also includes releasing a storage space storing the temporary data in the buffer memory and reloading the temporary data from the buffer area into the storage space of the buffer memory. Thereby, the method can temporarily increase available storage space of the buffer memory to meet the demand of additional operations. | 2013-07-11 |
20130179628 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory and a controller. The controller controls the memory, communicates with a host device via a first signal line and a second signal line, and receives data items to be written in the memory from the host device on the first and second signal lines in a first period. The same group number is assigned to two data items which flow in parallel on the first and second signal lines. The controller transmits to the host device a response packet including an indication of a group number assigned to an unsuccessfully received one of the data items. | 2013-07-11 |
20130179629 | METHOD OF CONTROLLING MEMORY SYSTEM IN THE EVENT OF SUDDEN POWER OFF - A method of controlling a memory system that comprises a first flash memory device and a memory controller, the method comprising counting a first timeout when a sudden power off occurs, resetting the first flash memory device when the first timeout expires, and dumping data to the first flash memory device. | 2013-07-11 |
20130179630 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data. | 2013-07-11 |
20130179631 | SOLID-STATE DISK (SSD) MANAGEMENT - SSD wear-level data ( | 2013-07-11 |
20130179632 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OPTIMIZATION OF HOST SEQUENTIAL READS OR WRITES BASED ON VOLUME OF DATA TRANSFER - A method for optimization of host sequential reads based on volume of data includes, at a mass data storage device, pre-fetching a first volume of predicted data associated with an identified read data stream from a data store into a buffer memory different from the data store. A request for data from the read data stream is received from a host. In response, the requested data is provided to the host from the buffer memory. While providing the requested data to the host from the buffer memory, it is determined whether a threshold volume of data has been provided to the host from the data buffer memory. If so, a second volume of predicted data associated with the identified read data stream is pre-fetched from the data store and into the buffer memory. If not, additional predicted data is not pre-fetched from the data store. | 2013-07-11 |
20130179633 | SCATTER-GATHER INTELLIGENT MEMORY ARCHITECTURE FOR UNSTRUCTURED STREAMING DATA ON MULTIPROCESSOR SYSTEMS - A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion. | 2013-07-11 |
20130179634 | SYSTEMS AND METHODS FOR IDLE TIME BACKUP OF STORAGE SYSTEM VOLUMES - Methods and systems for backing up data of a RAID 0 volume. The system includes a plurality of storage devices implementing a logical volume in a Redundant Array of Independent Disks (RAID) level 0 configuration. The system also includes a storage controller. The storage controller is adapted to manage Input/Output (I/O) operations directed to the RAID 0 volume. The storage controller is further adapted to duplicate data stored on the RAID 0 volume to unused portions of other storage devices during an idle time of the storage controller. | 2013-07-11 |
20130179635 | METHOD AND DEVICE FOR TRIGGERING DATA MIGRATION - The present invention provides a method and device for triggering data migration; the method includes: a host receives a migration object and a target disk, and the migration object includes a specified file or a specified directory or data accessed by a specified application in a storage system; the host resolves a block address of the migration object; and the host sends a migration instruction to a disk array controller in the SAN storage system, to instruct the disk array controller to migrate the migration object from a source disk to the target disk according to the block address of the migration object. The host of the present invention instructs the disk array controller to carry out data migration, and resolves the block address of the migration object, so the storage system can achieve the objective of migrating specified data according to a user requirement. | 2013-07-11 |
20130179636 | MANAGEMENT APPARATUS AND MANAGEMENT METHOD OF COMPUTER SYSTEM - To improve the performance of a computer system and user-friendliness for an administrator. A storage system | 2013-07-11 |
20130179637 | DATA STORAGE BACKUP WITH LESSENED CACHE POLLUTION - Control of the discard of data from cache during backup of the data. In a computer-implemented system comprising primary data storage; cache; backup data storage; and at least one processor, the processor is configured to identify data stored in the primary data storage for backup to the backup data storage, where the identified data is placed in the cache in the form of portions of the data, and where the portions of data are to be backed up from the cache to the backup storage. Upon backup of each portion of the identified data from the cache to the backup storage, the processor marks the backed up portion of the identified data for discard from the cache. Thus, the backed up data is discarded from the cache right away, lessening cache pollution. | 2013-07-11 |
20130179638 | Streaming Translation in Display Pipe - In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page. | 2013-07-11 |
20130179639 | TECHNIQUE FOR PRESERVING CACHED INFORMATION DURING A LOW POWER MODE - A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache. | 2013-07-11 |
20130179640 | INSTRUCTION CACHE POWER REDUCTION - In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array. | 2013-07-11 |
20130179641 | MEMORY SYSTEM INCLUDING A SPIRAL CACHE - An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by the proximity of the requested values to the particular storage location. The cache supports multiple outstanding in-flight requests directed to the same address using an issue table that tracks multiple outstanding requests and control logic that applies the multiple requests to the same address in the order received by the cache memory. The cache also includes a backing store request table that tracks push-back write operations issued from the cache memory when the cache memory is full and a new value is provided from the external interface, and the control logic to prevent multiple copies of the same value from being loaded into the cache or a copy being loaded before a pending push-back has been completed. | 2013-07-11 |
20130179642 | Non-Allocating Memory Access with Physical Address - Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered. | 2013-07-11 |
20130179643 | OBSCURING MEMORY ACCESS PATTERNS IN CONJUNCTION WITH DEADLOCK DETECTION OR AVOIDANCE - Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed. | 2013-07-11 |
20130179644 | PARALLEL PROCESSING PROCESSOR SYSTEM - A parallel processing processor system includes multiple processor elements, a main memory, and a shared memory, whose latency with the processors is less than the latency between the main memory and the processors. Each of the multiple processor elements has a DSP (Digital Signal Processor) and an instruction cache. Firmware executed by the DSPs is transferred from the main memory to the shared memory and is shared by the DSPs. Updating of the instruction caches in the case where a cache miss has occurred is performed by, for example, copying, into the instruction caches, the content of the shared memory corresponding to an address accessed by a DSP. | 2013-07-11 |
20130179645 | EQUALIZING BANDWIDTH FOR MULTIPLE REQUESTERS USING A SHARED MEMORY SYSTEM - A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed. | 2013-07-11 |
20130179646 | STORAGE CONTROL DEVICE, STORAGE DEVICE, AND CONTROL METHOD FOR CONTROLLING STORAGE CONTROL DEVICE - A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read. | 2013-07-11 |
20130179647 | STORAGE DEVICE AND DATA MANAGEMENT METHOD THEREOF - Disclosed is a data managing method of a storage device which includes at least one nonvolatile memory device and a controller controlling the nonvolatile memory device. The data managing method includes receiving an input/output request and generating a section directing logical addresses based on the input/output request. The section is managed using section information, and the section information includes a start logical address corresponding to the input/output request, spatial locality information having the number of the directed logical addresses, and historical request information. | 2013-07-11 |
20130179648 | MANAGEMENT APPARATUS AND MANAGEMENT METHOD FOR COMPUTER SYSTEM - To provide a user of a virtual volume with a performance commensurate with a fee. A management apparatus | 2013-07-11 |
20130179649 | Offload Read and Write Offload Provider - Aspects of the subject matter described herein relate to an offload provider. In aspects, an offload provider may provide a token that represents data. The offload provider may be expected to ensure that the data the token represents will not change while the token is valid. The offload provider may take actions to ensure the immutability of the data. The actions may be taken, for example, in conjunction with receiving an offload read and/or offload write, and/or in conjunction with receiving another write that, if allowed to proceed, would otherwise change the data represented by the token. | 2013-07-11 |
20130179650 | DATA SHARING USING DIFFERENCE-ON-WRITE - When a virtual machine writes to a page that is being shared across VMs, a share value is calculated to determine how different the page would be if the write command were implemented. If the share value is below a predefined threshold (meaning that the page would not be “too different”), then the page is not copied (as it would be in a standard copy-on-write operation). Instead, the difference between the contents of the pages is stored as a self-contained delta. The physical to machine memory map is updated to point to the delta, and the delta contains a pointer to the original page. When the VM needs to access the page that was stored as a delta, the delta and the page are then fetched from memory and the page is reconstructed. | 2013-07-11 |
20130179651 | TECHNIQUES FOR HANDLING MEMORY ACCESSES BY PROCESSOR-INDEPENDENT EXECUTABLE CODE IN A MULTI-PROCESSOR ENVIRONMENT - In a computing system where a plurality of processing units may execute a shared code independently, it is necessary to address data issues related to execution of the shared code and separate data. According to various embodiments disclosed herein, the per-processing unit data can be efficiently addressed in a program counter relative mode where data is accessed using a data offset value for each processing unit when the data blocks are positioned at spaces of a predetermined offset value. Further, the per-processing unit of common code in different virtual addresses is mapped to a common physical address. As a result, while each of the processing units access the exact same instruction code in physical memory it accesses a different area in memory for manipulation of data. | 2013-07-11 |
20130179652 | SUPPORT FOR SYNCHRONIZATION OF DATA EDITED IN PARALLEL - Fundamental methods, memory systems and processors systems to synchronize replicas of data by exchanging editing plans to replicas are first explained in Section 1. Other sections show derived methods and systems. Each derived method and system is expressed as an independent claim. Section 2 shows synchronization supported by server providing relay function. Updating of replica is performed, using editing plans arranged in a sequence determined by the server. Section 3 shows synchronization supported by server providing ordinal numbers. Updating of replica is performed, using editing plans arranged in a sequence of ordinal numbers provided by the server. Section 4 shows synchronization keeping reference consistency. Section 5 shows synchronization of edited data and edited definition of data. Section 6 shows synchronization by version control, which removes editing plans to a replica with old version before updating of replicas. | 2013-07-11 |
20130179653 | APPARATUS AND METHOD FOR PARTITIONING MEMORY AREA FOR APPLICATION PRELOADING IN A WIRELESS TERMINAL - An apparatus and method for partitioning a memory area for application preloading in a wireless terminal so as to efficiently utilize the customer areas of a memory includes a memory including a customer area, which is partitioned into two areas in which different types of applications are respectively stored and is variably adjustable according to an amount of the applications stored in the two areas; and a controller for installing the applications stored in the two areas partitioning the customer area in a user area of the memory in a booting mode of the wireless terminal. | 2013-07-11 |
20130179654 | METHOD FOR AUTOMATICALLY BACKING UP DIGITAL DATA PRESERVED IN MEMORY IN A COMPUTER INSTALLATION AND DATA MEDIUM READABLE BY A COMPUTER HAVING THE ASSOCIATED INSTRUCTIONS STORED IN THE MEMORY THEREOF - The invention relates to a method for automatically backing up digital data preserved in memory in a computer installation to a remote backup system accessible through the computer installation via a data transmission network. This method comprises extracting and analyzing information regarding the operation of the computer installation and determining parameters of a data backup application for saving data to the backup system. Based on the result of this analysis, the digital data preserved in memory is analyzed and the digital data analyzed is classified into a plurality of classes of different priorities. The backup application is also executed on at least part of the digital data based on the parameters and classes of priorities determined. | 2013-07-11 |
20130179655 | METHOD AND SYSTEM FOR OPTIMIZING LIVE MIGRATION OF PERSISTENT DATA OF VIRTUAL MACHINE USING DISK I/O HEURISTICS - Techniques for migrating persistent data between and across data stores are implemented using monitoring methods. The method includes classifying frequently updated blocks of persistent data to distinguish those blocks from less frequently updated blocks of persistent data. The less frequently updated blocks are copied from the source data store to the destination data store, such that persistent data is copied to the destination data store in the absence of the persistent data of the frequently updated blocks. The method further includes identifying a modified set of the less frequently updated blocks that are modified during the copying. The modified set of less frequently updated blocks is copied from the source data store to the destination data store, without copying the frequently updated blocks. It is then determined whether to copy the frequently updated blocks of persistent data from the source data store to the destination data store. | 2013-07-11 |
20130179656 | RELOCATING RELATED RESOURCE PARTITIONS - The method for relocating related resource partitions includes detecting a relocation event to relocate a first resource partition operating in a first division from the first division to a second division. The first division includes a second resource partition. The first resource partition and the second resource partition are each distinct operating environments. The method also includes determining that the second resource partition is sufficiently related to the first resource partition. The method includes relocating the second resource partition to the second division with the first resource partition in response to determining that the second resource partition is sufficiently related to the first resource partition. | 2013-07-11 |
20130179657 | COMPUTER SYSTEM MANAGEMENT APPARATUS AND MANAGEMENT METHOD - An object of the present invention is to efficiently use a hierarchical pool. A management server manages performance information of multiple host computers, and based on each performance information, determines whether a prescribed host computer, which comprises a load of equal to or larger than a preconfigured prescribed threshold, exists among the multiple host computers. The management server creates a reallocation plan, which stipulates an allocation amount of a real storage area for each of multiple storage tiers, with respect to a prescribed virtual logical volume used by the prescribed host computer. Based on the reallocation plan, the management server decides a corresponding relationship between each logical storage area and each real storage area of each storage tier, and notifies a storage apparatus of this corresponding relationship. | 2013-07-11 |
20130179658 | SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing. | 2013-07-11 |
20130179659 | DATA STORAGE DEVICE WITH SELECTIVE DATA COMPRESSION - A memory controller comprises a host interface block comprising a compression ratio calculator configured to determine whether a compression ratio of input data exceeds a predetermined compression ratio, and a compression block configured to compress the input data as a consequence of the host compression ratio calculator determining that the compression ratio exceeds the predetermined compression ratio. | 2013-07-11 |
20130179660 | Virtual Logical Volume for Overflow Storage of Special Data Sets - System embodiments for facilitating overflow storage of special data sets that reside on a single logical volume are provided. A virtual logical volume is created from unallocated memory units across a plurality of logical volumes in a volume group. The virtual logical volume appears the same as any one of the logical volumes in the volume group to an external client. Upon receipt of a special data set that must reside in a single logical volume, an attempt is first made to allocate the special data set to one of the logical volumes in the volume group. If that allocation attempt fails, the special data set is allocated to the virtual logical volume. The virtual logical volume may be created only upon the failure to allocate the special data set to one of the logical volumes, and may be destroyed if sufficient space in one of the logical volumes is freed up to transfer the special data set. Creation of the virtual logical volume may be reserved for only critical special data sets whose failure would result in a storage system outage. | 2013-07-11 |
20130179661 | Performing A Multiply-Multiply-Accumulate Instruction - In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed. | 2013-07-11 |
20130179662 | Method and System for Resolving Thread Divergences - An address divergence unit detects divergence between threads in a thread group and then separates those threads into a subset of non-divergent threads and a subset of divergent threads. In one embodiment, the address divergence unit causes instructions associated with the subset of non-divergent threads to be issued for execution on a parallel processing unit, while causing the instructions associated with the subset of divergent threads to be re-fetched and re-issued for execution. | 2013-07-11 |
20130179663 | INFORMATION HANDLING SYSTEM INCLUDING HARDWARE AND SOFTWARE PREFETCH - A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time. | 2013-07-11 |
20130179664 | DIVISION UNIT WITH MULTIPLE DIVIDE ENGINES - Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit. | 2013-07-11 |
20130179665 | RESTORING A REGISTER RENAMING MAP - A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer whilst the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs. | 2013-07-11 |
20130179666 | MULTI-CORE PROCESSOR SYSTEM, SYNCHRONIZATION CONTROL SYSTEM, SYNCHRONIZATION CONTROL APPARATUS, INFORMATION GENERATING METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor; an identifying unit that refers to a table identifying a combination of a thread and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected; a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value. | 2013-07-11 |
20130179667 | METHODS AND SYSTEMS FOR STATE SWITCHING - Disclosed are methods and systems for state switching. The method is applied to a first hardware system. The first hardware system is connected with a second hardware system. The first hardware system has a first operation state and a second operation state. The second hardware system includes a memory unit. The memory unit has a first access state and a second access state. The memory unit is in the first access state currently. The method includes: the first hardware system sends an access state switching instruction to the second hardware system when the first hardware system enters the second operation state from the first operation state, wherein, the access state switching instruction is adapted to switch the memory unit of the second hardware system from the first access state to the second access state. The application of the present invention can ensure the security of key data, avoid the access of key data by malicious software, reduce the implementation costs and has a higher extensibility. | 2013-07-11 |
20130179668 | LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY - In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed. | 2013-07-11 |
20130179669 | TRUSTED NETWORK BOOTING SYSTEM AND METHOD - A system for trusted network booting of a server. The system may include a booting server that may contain a booting image and a network server that may boot with the booting image from the booting server. The network server may include a trust anchor that measures the booting image. The system may further include a network controller that controls access to a network. The network controller may verify the measurement of the booting image before allowing the network server to access the network. | 2013-07-11 |
20130179670 | BOOTING METHOD OF MULTIMEDIA DEVICE AND MULTIMEDIA DEVICE - A booting method of a multimedia device and the multimedia device are provided. The multimedia device includes a storage media, and the booting method of the multimedia device includes following steps. After the multimedia device is powered on, a boot loader is executed to initialize a plurality of primary components of the multimedia device. A snapshot information is read from the storage media, wherein the snapshot information includes a plurality of state information of an operating system (OS) and a plurality of applications of the multimedia device. The snapshot information is loaded into the multimedia device to allow the multimedia device to run the OS and the applications. Thereby, the number of booting steps of the multimedia device is reduced, and the booting time of the multimedia device is effectively shortened. | 2013-07-11 |
20130179671 | SUPER I/O MODULE AND CONTROL METHOD THEREOF - A super input/output (I/O) module for controlling a universal serial bus (USB) port of a computer system is provided. The super I/O module includes a USB host, a switch and a processor. The switch selectively couples the USB port of the computer system to the USB host or a controller of the computer system according to a switching signal. When a trigger event occurs, the processor provides the switching signal to control the switch, so as to couple the USB port of the computer system to the USB host and to transmit a basic input/output system (BIOS) code to a flash memory of the computer system via the switch and the USB port. | 2013-07-11 |
20130179672 | COMPUTER AND QUICK BOOTING METHOD THEREOF - A computer and a quick booting method thereof are disclosed. The computer includes a central processing unit (CPU), a volatile memory, a basic input/output system (BIOS) and a power module. The volatile memory is coupled to the CPU and stores operation status data when the computer is power on before the computer executes a shutdown process. the BIOS is coupled to the CPU, reads the operation status data from the volatile memory when the computer executes a booting process, and initialize the computer according to the operation status data. The power module is coupled to the volatile memory and provides power to the volatile memory when the computer finishes the shutdown process. Since the operation status data stored in the volatile memory do not disappear after the computer finishes the shutdown process, they can be used to boot up the computer quickly. | 2013-07-11 |
20130179673 | METHODS AND SYSTEMS FOR PROVIDING A MODIFIABLE MACHINE BASE IMAGE WITH A PERSONALIZED DESKTOP ENVIRONMENT IN A COMBINED COMPUTING ENVIRONMENT - A method and system for modifying, in a combined computing environment, a machine base image having a personalized desktop environment includes executing an operating system associated with a base disk; intercepting, by a filter driver, an instruction from at least one of a plurality of resources to modify a setting stored in at least one of a file system and a registry, the plurality of resources executing inside an isolation environment; storing, in a delta disk, a copy of the modified setting; restarting the operating system; replacing the setting stored in the at least one of the file system and the registry with the copy of the modified setting stored on the delta disk; and restarting at least one operating system process incorporating the modified setting. | 2013-07-11 |
20130179674 | APPARATUS AND METHOD FOR DYNAMICALLY RECONFIGURING OPERATING SYSTEM (OS) FOR MANYCORE SYSTEM - An apparatus and method for dynamically reconfiguring an Operating System (OS) for a manycore system are provided. The apparatus may include an application type determining unit to determine a type of an executed application, and an OS reconfiguring unit to activate only at least one function in an OS, based on the determined type of the application, and to reconfigure the OS. | 2013-07-11 |
20130179675 | COMPOSITE SYSTEM, METHOD, AND STORAGE MEDIUM - In a composite system that includes a main system that operates with a main program and a plurality of sub-systems that operate both with sub-programs and under the control of the main system attachably and detachably connected with each other via a predefined bus, the main system transfers each fragment of divided target data to the sub-system, and the sub-system includes a receiving buffer that can read and write the fragment of data received from the main system temporarily. An encrypting process can be executed with the main system and the sub-system regardless of the size of target data to be encrypted, the size of memory in the sub-system, and data transfer capability between the main system and the sub-system even if the size of the target data in the main system is bigger than the size of the receiving buffer in the sub-system. | 2013-07-11 |
20130179676 | CLOUD-BASED HARDWARE SECURITY MODULES - A cloud-based hardware security device (HSM) providing core security functions of a physically controlled HSM, such as a USB HSM, while allowing user access within the cloud and from a user device, including user devices without input ports capable of direct connection to the HSM. The HSMs can be connected to multi-HSM appliances on the organization or user side of the cloud network, or on the cloud provider side of the cloud network. HSMs can facilitate multiple users, and multi-HSM appliances can facilitate multiple organizations. | 2013-07-11 |
20130179677 | SECURE DATA EXCHANGE BETWEEN DATA PROCESSING SYSTEMS - A data transfer method performed at a proxy server includes intercepting a data request from a client computer that is directed to a target server, encrypting profile information, augmenting the data request by adding the encrypted profile information to the data request, and sending the augmented data request to the target server. A data transfer method that is performed at an information server includes receiving a data request from a proxy server, extracting profile information added to the data request by the proxy server, using the extracted profile information to generate a response, and sending the response to the proxy server. | 2013-07-11 |
20130179678 | Stateless Cryptographic Protocol-based Hardware Acceleration - According to one embodiment of the invention, a method comprises an operation of commencing a first phrase and passing control of an authentication handshaking protocol. The first phase is commenced for establishing a secure communication path by a data path processor within a first network device. The first phrase comprises an exchange of data during an authentication handshaking protocol. The passing of control for authentication handshaking protocol by the data path processor to a control path processor is conducted to complete the authentication handshaking protocol. | 2013-07-11 |
20130179679 | Methods And Apparatuses For Secure Information Sharing In Social Networks Using Randomly-Generated Keys - There can be problems with the security of social networking communications. For example, there may be occasions when a number of friends wish to communicate securely through a social network infrastructure, such that non-trusted 3 | 2013-07-11 |
20130179680 | DIGITAL RIGHTS DOMAIN MANAGEMENT FOR SECURE CONTENT DISTRIBUTION IN A LOCAL NETWORK - Systems and methods for secure content distribution to playback devices connected to a local network via a residential gateway using secure links are disclosed. One embodiment of the invention includes a content server, a rights management server, a residential gateway configured to communicate with the content server and the rights management server via a network, and a playback device configured to communicate with the residential gateway via a local network. In addition, the residential gateway is configured to receive protected content from the content server, the playback device is configured to request access to the protected content from the residential gateway, the residential gateway is configured to request access to the protected content from the rights management server and the request includes information uniquely identifying the playback device, the rights management server is configured to provide access information to the residential gateway when the information uniquely identifying the playback device satisfies at least one predetermined criterion with respect to playback devices associated with the residential gateway, the residential gateway and the playback device are configured to create a secure link between the residential gateway and the playback device via the local network, and the residential gateway is configured to decrypt the protected content using the access information provided by the rights management server and to encrypt the decrypted content for distribution to the playback device via the secure link. | 2013-07-11 |
20130179681 | System And Method For Device Registration And Authentication - Systems and methods for device registration and authentication are disclosed. In one embodiment, a method for authentication of a device may include (1) receiving, at a mobile device, a first credential; (2) transmitting, over a network, the first credential to a server; (3) receiving, from the server, a first key and a first value, the first value comprising a receipt for the first credential; (4) receiving, at the mobile device, a data entry for a second credential; (5) generating, by a processor, a second key from the data entry; (6) retrieving, by the mobile device, a third credential using the first key and the second key; (7) signing, by the mobile device, the first value with the third credential; and (8) transmitting, over the network, the signed third value to the server. | 2013-07-11 |
20130179682 | GENERATION OF RELATIVE PRIME NUMBERS FOR USE IN CRYPTOGRAPHY - The disclosed technology generates two relative prime numbers and, then, using the relative prime numbers converts a super-increasing (SI) knapsack into a non-super-increasing (NSI) knapsack. The NSI knapsack becomes a public key and the corresponding SI knapsack, along with the two relative prime numbers, becomes a private key. A message is encrypted using a subset S of the private key that totals a number N. The message, the public key and the number N are transmitted to a recipient, who knows the value of the two relative prime numbers. The recipient uses the relative prime numbers to convert the public key into the private key and, then, generates the subset S by solving the private key with respect to the number N. Using the subset, the message is decrypted. | 2013-07-11 |
20130179683 | SECURE REGISTRATION TO A SERVICE PROVIDED BY A WEB SERVER - To check a secure registration to a service provided by a web server from a communication terminal (TC), the web server (SW) saves a dynamically generated code matching the terminal (TC)'s IP address and transmits a message containing the code (CodC) to an e-mail address. This address is provided by the user in response to the terminal's connection to the web server. The server transmits to the terminal an application (App) capable of generating an automated test in order to tell computers apart from humans. The answer provided by the user is encrypted with the terminal's IP address and the code contained in the message transmitted to the e-mail address, and is directly transmitted by the application to the server, which decrypts it and compares it with an expected answer in order to enable access to the Web server if the decrypted answer matches the expected answer. | 2013-07-11 |
20130179684 | ENCRYPTED DATABASE SYSTEM, CLIENT TERMINAL, ENCRYPTED DATABASE SERVER, NATURAL JOINING METHOD, AND PROGRAM - A client terminal is provided with a column encryption unit that, from an encryption key, a table identifier, and a column identifier, generates a column private key, a column public key, and a comparison value, from which the unit generates a concealed comparison value and a ciphertext, encrypting a particular column; and an encrypted table natural joining request unit that issues a natural joining request text that requests natural joining with regards to columns encrypted from the encryption key, the table identifier, and the column identifier. The natural joining request text contains as a table joining key the column private key generated by a group of generating elements and the encryption key from the table identifier of a first and second table and the column identifier of an a-th column and a b-th column. An encrypted database server executes natural joining using the table joining key, and returns the results. | 2013-07-11 |
20130179685 | SECURE REMOTE PERIPHERAL ENCRYPTION TUNNEL - A Secure Remote Peripheral Encryption Tunnel (SeRPEnT) can be implemented in a portable embedded device for the Universal Serial Bus (USB) with a much more restricted attack surface than a general purpose client computer. The SeRPEnT device can comprise a small, low-power “cryptographic switchboard” that can operate in a trusted path mode and a pass-through mode. In the trusted path mode, the SeRPEnT device can tunnel connected peripherals through the client to a server with Virtual Machine (VM)-hosted applications. In the pass-through mode, the SeRPEnT device can pass-through the connected peripherals to the client system, allowing normal use of the local system by the user. SeRPEnT can also enable secure transactions between the user and server applications by only allowing input to the VMs to originate from the SeRPEnT device. | 2013-07-11 |
20130179686 | Transaction Verification on RFID Enabled Payment and Transaction Instruments - A display enabled RFID tag (DERT) receives transaction details from the reader. DERT verifies that the details match their counterparts in the reader public key certificate. The process is aborted in case of a mismatch. DERT extracts and displays user-verifiable data. It then enters a countdown stage that lasts for a predetermined duration. A user observes the transaction information and, if the transaction amount and other details are deemed correct, presses an accept button provided on the DERT before the timer runs out. DERT signs the time-stamped transaction statement and sends it to the reader. This signed statement is then sent to the payment gateway and eventually to the financial institution that issued the payment DERT. | 2013-07-11 |
20130179687 | METHOD AND APPARATUS FOR AUTHENTICATING MULTICAST MESSAGES - The last link in an initialization hash chain, calculated by a transmitter based on its anchor value, is distributed as an initialization function value to a receiver in an initialization phase. Subsequently, a multicast message is received and stored by a receiver and an authentication key release message, containing a cryptographic authentication key, is received from the transmitter by the receiver. A cryptographic function value h, calculated by the receiver for the cryptographic authentication key using a prescribed cryptographic function, is compared with the initialization function value to check the validity of the cryptographic authentication key in the authentication key release message. The multicast message is authenticated by the receiver using the cryptographic authentication key which has been recognized as valid. | 2013-07-11 |
20130179688 | SYSTEM AND METHOD FOR ISSUING AN AUTHENTICATION KEY FOR AUTHENTICATING A USER IN A CPNS ENVIRONMENT - The present invention relates to a system and method for issuing an authentication key for authenticating a user in a CPNS environment. The system comprises a user terminal, a gateway and a CPNS device. The user terminal is equipped with a short-range wireless communication function, requests the gateway to register terminal information including an ID and password, encrypts the terminal information including the ID and password using the password, transmits an authentication request signal including the encrypted terminal information to the gateway, and receives an authentication key generated by a CPNS device. The CPNS device stores the terminal information, performs user authentication by decrypting the encrypted terminal information in response to the authentication request, generates an authentication key for the CPNS when a user is authenticated, encrypts the generated authentication key using the password, and transmits the encrypted authentication key to the user terminal through the gateway. | 2013-07-11 |
20130179689 | INFORMATION DISTRIBUTION METHOD, INFORMATION DISTRIBUTION SYSTEM AND IN-VEHICLE TERMINAL - [Objective] When installing software into an in-vehicle terminal from a server, it is required to prevent the software from being installed into an unsuitable terminal, and to reduce time and efforts for data input and download, thereby improving the convenience of the user. | 2013-07-11 |
20130179690 | METHOD AND APPARATUS FOR FAST IMAGE ENCRYPTION AND INVISIBLE DIGITAL WATERMARK - The invention is for a method and system for encrypting and decrypting image/signal, based on new column and/or row operation of the image/signal, and a new digital watermark system, based on the new encryption/decryption system. The column and row operation are introduced for creating a chaotic image/signal so that the resulting image/signal is unreadable/inaudible with a fast computational speed. The new digital watermark technology can sustain cropping damage for verification. | 2013-07-11 |
20130179691 | SIGNATURE GENERATION APPARATUS, SIGNATURE GENERATION METHOD, AND STORAGE MEDIUM - e and n are public information and d is private information. An electronic signature is generated based on a calculated value of e×d mod n. A signature generation apparatus | 2013-07-11 |
20130179692 | SYSTEMS AND METHODS FOR THREE-FACTOR AUTHENTICATION - In one aspect, systems and methods for three-factor authentication include receiving a user's identification and password transmitted from the user's mobile device, generating a One Time Password (OTP), encrypting the OTP, and encoding the encrypted OTP in a two-dimensional barcode. The two-dimensional barcode of the encrypted OTP is transmitted to a computing device of the user, and an image of the two-dimensional barcode of the encrypted OTP displayed on the user's computing device is captured using the user's mobile device. The two-dimensional barcode of the encrypted OTP is decoded using the user's mobile device to obtain the encrypted OTP. The encrypted OTP is decrypted using the user's mobile device and displayed. The OTP then is spoken by the user, and the user's voice and the OTP are recognized to authenticate the user. | 2013-07-11 |
20130179693 | Providing Integrity Verification And Attestation In A Hidden Execution Environment - In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed. | 2013-07-11 |
20130179694 | SYSTEM AND METHOD FOR ELECTRONIC CERTIFICATION AND AUTHENTICATION OF DATA - A system and method for authenticating data. Data may be received that is individually encrypted in a first encryption layer by each of a plurality of users using user-specific private keys. The received data may be encrypted together in a second encryption layer to create multi-layered encrypted data. The multi-layered encrypted data may be transferred to a beneficiary device to determine if the encrypted data is authentic. At the beneficiary device, the second encryption layer may be decrypted to expose the first encryption layer. Then, the first encryption layer may be decrypted using public keys that only decrypt data encrypted by private keys assigned to a plurality of authorizers pre-designated to authenticate the data. If the first encryption layer is properly decrypted using the authorizers' decryption keys, it may be determined that the users are the pre-designated authorizers. | 2013-07-11 |
20130179695 | VERIFYING AUTHENTICITY OF PLAYBACK DEVICE - One embodiment of the invention sets forth a mechanism for verifying the authenticity of a device before transmitting digital content to the device. In operation, the device stores a device key that is generated at manufacture-time using a pre-determined cryptographic key and the device identifier. In operation, the device generates a proof of possession from the application data and the stored device key. When verifying the device authenticity, a device key is derived from the master key and the device identifier then a proof of possession is derived from the derived device key and the application data obtained from the device. If the derived proof of possession matches the received proof of possession, then the authenticity of the device can be verified. | 2013-07-11 |
20130179696 | Secure Removable Drive System - A data storage system comprises a removable drive with memory for storing data, and an identifier for identifying the removable data cartridge. A host computer can be coupled in data communication with the removable data cartridge, with a driver for performing data operations thereon. The driver is configured to perform the data operations with encryption, in the presence of the identifier, and to perform the data operations without the encryption, in the absence of the identifier. | 2013-07-11 |
20130179697 | CONTINUOUSLY POWERED FIELD DEVICE - A continuously powered field device for use in a process control system includes a field device housing, a primary power port disposed within or connected to the field device housing, and a power source switching module comprising a first power terminal, a second power terminal, and a third power terminal. The first power terminal is coupled to the primary power port, and the third power terminal is configured to deliver power applied to the third power terminal to at least a portion of the field device. The power source switching module is operable in a first state of operation to couple the first power terminal to the third power terminal, and the power source switching module is operable in a second state of operation to couple the second power terminal to the third power terminal. | 2013-07-11 |
20130179698 | SYSTEMS AND METHODS FOR OPTIONS RELATING TO POWER-ON OF A USER EQUIPMENT DEVICE - Systems and methods for setting up a power-on state of a user equipment device using a media guidance application are provided. A power-on state may specify media content related actions to be performed by the user equipment device when the user equipment device next powers on. In particular, in response to a user request to power off the user equipment device, the user may be presented with multiple power-on state options on a power-off screen. A user selection of a power-on state option may be received and a start-up routine of the user equipment device may be configured such that the user equipment device performs the media content related actions specified by the selected power-on state when it powers on. | 2013-07-11 |
20130179699 | POWER CONTROL APPARATUS - There is provided a power control apparatus including a power supply control unit that executes power supply control with respect to a device connected to a power supply line, a connector that is connected to a cable to perform versatile communication between the power supply control unit and an external device, and a switch that is provided at a predetermined position of a circumferential portion of the connector and physically intercepts the versatile communication between the power supply control unit and the external device. | 2013-07-11 |
20130179700 | COMMUNICATION DEVICE, CONTROL METHOD FOR COMMUNICATION DEVICE, AND STORAGE MEDIUM - A communication device includes a main control part configured to receive and process an image signal; a first network control part configured to convert data input from an external device into the image signal and provide the main control part with the image signal; a sub control part configured to detect a power-on command; and a second network control part configured to control communications with the external device via a network to provide the first network control part with data input from the external device. Power supplies to the main control part, the sub control part, the first network control part and the second network control part are independently controlled. | 2013-07-11 |
20130179701 | SEPARATE DEBUG POWER MANAGEMENT - The power consumption of embedded debug functions in ultra low power SoC sytems is minimized by seggregating the debug logic into separate power domains, and allocating separate power pins to the debug power sources. Debug power may be supplied from an external power source, from the system power source or from a functional communication interface such as USB, JTAG or cJTAG. | 2013-07-11 |
20130179702 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator. | 2013-07-11 |
20130179703 | Increasing Power Efficiency Of Turbo Mode Operation In A Processor - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 2013-07-11 |
20130179704 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 2013-07-11 |
20130179705 | Controlling A Turbo Mode Frequency Of A Processor - In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. | 2013-07-11 |
20130179706 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 2013-07-11 |
20130179707 | ELECTRONIC CONTROL APPARATUS AND ONBOARD INFORMATION EQUIPMENT - In response to an external interrupt signal input from a disk eject button | 2013-07-11 |
20130179708 | PROCESSING DEVICE - A processing device includes a plurality of input units configured to input a process request; a plurality of processing units configured to execute a process corresponding to the process request input by the plurality of input units; a power control unit configured to transfer the processing device into a power saving state and to transfer the processing device back to a regular state from the power saving state; and an operation suppression control unit configured to send an operation suppression request to the plurality of input units and the plurality of processing units before the power control unit transfers the processing device into the power saving state, and to send an operation suppression release request to the plurality of input units and the plurality of processing units when the power control unit transfers the processing device back to the regular state from the power saving state. | 2013-07-11 |
20130179709 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed. | 2013-07-11 |
20130179710 | MULTI-CORE PROCESSOR SYSTEM, DYNAMIC POWER MANAGEMENT METHOD THEREOF AND CONTROL APPARATUS THEREOF - A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off. | 2013-07-11 |
20130179711 | GRAPHICS PROCESSOR CLOCK SCALING BASED ON IDLE TIME - A method for graphics processor clock scaling comprises the following steps. A percentage of idle-time is calculated, based upon an elapsed idle-time and an elapsed active time. A graphics processor clock rate is reduced if the percentage of idle time is higher than a high limit threshold. The graphics processor clock rate is increased if the percentage of idle time is lower than a low limit threshold. | 2013-07-11 |
20130179712 | All-in-one Computer and Power Management Method thereof - An all-in-one computer includes a display module and a host provided in a housing of the display module. The host includes a power module, a cell module and a circuit board electrically connected with the power module, the cell module and a panel of the display module respectively. A processing unit and a control unit are provided on the circuit board. The processing unit is configured to optionally receive the power from the power module and operating at a first frequency or receive the power from the cell module and operate at a second frequency lower than the first frequency. The control unit is configured to disable the power module and enable the cell module according to a voltage level of the power module and cause the processing unit to operate at a reduced frequency for decreasing power consumption thereof are provided. | 2013-07-11 |
20130179713 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 2013-07-11 |
20130179714 | BACKUP POWER SUPPLY CIRCUIT AND METHOD - A backup power supply circuit includes a backup power supply unit, a delay unit, and a power supply chip. The backup power supply unit is connected to a computer system. The backup power supply unit supplies power to the computer system when a cutoff of an external power source of the computer system occurs. The power supply chip sets the computer system into an idle state when the cutoff of the external power of the computer system occurs. The delay unit sets a delay time. The delay unit countdowns the delay time at a beginning of the cutoff of the external power of the computer system, and controls the power supply chip to revive the computer system when the countdown is completed. | 2013-07-11 |
20130179715 | SYSTEMS AND METHODS FOR REDUCING ENERGY CONSUMPTION IN SENSOR NETWORKS - A system includes a volatile memory and state information management logic. The volatile memory includes a plurality of volatile storage locations. The state information management logic includes memory write tracking circuitry coupled to the volatile memory. The memory write tracking circuitry is configured to identify locations of the memory written subsequent to restoration of state information to the volatile memory on exit of a low-power mode of operation, and to store indicia of the identified locations. | 2013-07-11 |
20130179716 | Dynamically Adjusting Power Of Non-Core Processor Circuitry - In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed. | 2013-07-11 |
20130179717 | ELECTRONIC SYSTEM WITH POWER SAVING FUNCTION - The present invention provides an electronic system with power saving function. In a first embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface, and the storage device is coupled to the processing unit via the transmission interface, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the transmission interface. In a second embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface and an independent signal pin, and the storage device is coupled to the processing unit via the transmission interface and the independent signal pin, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the independent signal pin. | 2013-07-11 |
20130179718 | SERVER RACK SYSTEM AND POWER MANAGEMENT METHOD APPLICABLE THERETO - A server rack system including a plurality of power supply units, a monitoring circuit, a rack management controller (RMC), and a plurality of server nodes is provided. The monitoring circuit is for monitoring the power supply units. The RMC is for monitoring the power supply units. When the monitoring circuit and/or the RMC finds that at least one of the power supply units failed to output a normal voltage, an operation status of the server nodes is lowered or at least one of the server nodes is forcibly shut down. | 2013-07-11 |
20130179719 | POWER SUPPLY SYSTEM AND METHOD - An exemplary power supply system for feeding electric power to an electronic device is provided. The power supply system includes an internal battery installed inside the electronic device and an external battery connected to the internal battery through a first switch. When the internal battery is above a set energy level, the first switch is turned off and the internal battery outputs electric power to the electronic device. When the internal battery falls below the first set energy level, the first switch is turned on and the external battery outputs electric power to the electronic device. A power supply method based upon the power supply system is also provided. | 2013-07-11 |