28th week of 2013 patent applcation highlights part 38 |
Patent application number | Title | Published |
20130178014 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE - This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc. | 2013-07-11 |
20130178015 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith. | 2013-07-11 |
20130178016 | METHODS OF FABRICATING A PACKAGE-ON-PACKAGE DEVICE AND PACKAGE-ON-PACKAGE DEVICES FABRICATED BY THE SAME - Methods of fabricating a package-on-package device and package-on-package devices fabricated by the same may be provided. According to inventive concepts, a back-grinding of a semiconductor chip to a target thickness may be performed after the semiconductor chip is molded by a molding layer. Accordingly, the semiconductor chip is relatively thick while forming a molding layer, and thus less susceptible to a warpage phenomenon, which for instance may occur during the forming a molding layer. Thus, relatively thin package-on-package device, which is less susceptible to the warpage phenomenon, may be achieved. | 2013-07-11 |
20130178017 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS FROM A SEMICONDUCTOR WAFER - A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame. | 2013-07-11 |
20130178018 | SEMICONDUCTOR MODULE, MOLDING APPARATUS, AND MOLDING METHOD - A semiconductor module includes a plurality of semiconductor elements, a first tabular electrode coupled to one face side of the plurality of semiconductor elements, a second tabular electrode coupled to the other face side of the plurality of semiconductor elements, and a molding material that encapsulates the plurality of semiconductor elements between the first electrode and the second electrode. A protrusion extending toward the second electrode is provided in a circumferential edge portion of the first electrode, and the protrusion surrounds the molding material. | 2013-07-11 |
20130178019 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region. | 2013-07-11 |
20130178020 | FINFET WITH FULLY SILICIDED GATE - A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions. | 2013-07-11 |
20130178021 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 2013-07-11 |
20130178022 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer. | 2013-07-11 |
20130178023 | ETCHING SOLUTION COMPOSITION AND METHOD OF ETCHING USING THE SAME - An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH | 2013-07-11 |
20130178024 | In Situ Doping and Diffusionless Annealing of Embedded Stressor Regions in PMOS and NMOS Devices - Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions. | 2013-07-11 |
20130178025 | Methods Of Fabricating A Memory Device - A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced. | 2013-07-11 |
20130178026 | METHOD FOR FABRICATING A FIELD SIDE SUB-BITLINE NOR FLASH ARRAY - Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density. | 2013-07-11 |
20130178027 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer. | 2013-07-11 |
20130178028 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - A semiconductor device having a vertical channel transistor and a method for manufacturing the same are provided. In the semiconductor device, a metal bit line is formed between vertical channel transistors, and the metal bit line is connected to only one of the vertical channel transistors through an asymmetric bit line contact. Through such a structure, the resistance of the bit line can be improved and the process margin for formation of the bit line can be secured. | 2013-07-11 |
20130178029 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 2013-07-11 |
20130178030 | METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW - An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer. | 2013-07-11 |
20130178031 | INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate. | 2013-07-11 |
20130178032 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 2013-07-11 |
20130178033 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 2013-07-11 |
20130178034 | Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process - Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region. | 2013-07-11 |
20130178035 | STRUCTURE AND METHOD TO ENABLING A BORDERLESS CONTACT TO SOURCE REGIONS AND DRAIN REGIONS OF A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) TRANSISTOR - A semiconductor device that includes a gate structure on a channel region of a semiconductor substrate. A first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure. At least one spacer is present on the sidewalls of the gate structure. The at least one spacer includes a first spacer and a second spacer. The first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region. The second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region. | 2013-07-11 |
20130178036 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 2013-07-11 |
20130178037 | METHOD OF MANUFACTURING HETEROJUNCTION BIPOLAR TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTOR - A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; | 2013-07-11 |
20130178038 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer, forming a first ferroelectric film on the lower electrode layer, forming on the first ferroelectric film a second ferroelectric film in an amorphous state containing iridium inside, thermally treating the second ferroelectric film in an oxidizing atmosphere to crystallize the second ferroelectric film and to cause iridium in the second ferroelectric film to diffuse into the first ferroelectric film, forming an upper electrode layer on the second ferroelectric film, and processing each of the upper electrode layer, the second ferroelectric film, the first ferroelectric film, and the lower electrode layer to form the capacitor structure. With such a structure, the inversion charge amount in a ferroelectric capacitor structure is improved without increasing the leak current pointlessly, and a high yield can be assured, thereby realizing a highly reliable FeRAM. | 2013-07-11 |
20130178039 | INTEGRATED CIRCUIT RESISTOR FABRICATION WITH DUMMY GATE REMOVAL - Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate. | 2013-07-11 |
20130178040 | REPROCESSING METHOD OF A SEMICONDUCTOR DEVICE - A reprocessing method of a semiconductor device, the reprocessing method includes adjusting a resistance value of a first resistor by first trimming the first resistor, wherein the first resistor is electrically connected between a first pad and a second pad, forming a second resistor on the first trimmed first resistor, and adjusting a resistance value of the second resistor by second trimming the second resistor. | 2013-07-11 |
20130178041 | BACK-END-OF-LINE PLANAR RESISTOR - A stack of an interconnect-level dielectric material layer and a disposable dielectric material layer is patterned so that at least one recessed region is formed through the disposable dielectric material layer and in an upper portion of the interconnect-level dielectric material layer. A dielectric liner layer and a metallic liner layer is formed in the at least one recessed region. At least one photoresist is applied to fill the at least one recessed region and lithographically patterned to form via cavities and/or line cavities in the interconnect-level dielectric material layer. After removing the at least one photoresist, the at least one recessed region, the via cavities, and/or the line cavities are filled with at least one metallic material, which is subsequently planarized to form at least one planar resistor having a top surface that is coplanar with top surfaces of metal lines or metal vias. | 2013-07-11 |
20130178042 | METHOD FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT - Provided is a method for manufacturing a variable resistance element, the method including: forming a first electrode material layer above a substrate; forming a first tantalum oxide material layer; forming a second tantalum oxide material layer; forming a second electrode material layer; and annealing at least the first tantalum oxide material layer after forming the first tantalum oxide material layer and before forming the second electrode material layer, wherein an oxygen content percentage of one of the first tantalum oxide material layer and the second tantalum oxide material layer is higher than an oxygen content percentage of the other. | 2013-07-11 |
20130178043 | Integrated Circuit Including DRAM and SRAM/Logic - A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region. | 2013-07-11 |
20130178044 | SEMICONDUCTOR DEVICES COMPRISING A PLURALITY OF GATE STRUCTURES - Methods for forming semiconductor memory structures including a gap between adjacent gate structures are provided. The methods may include forming an insulation layer between the adjacent gate structures. In some embodiments, the methods may include subsequently removing a portion of the insulation layer to leave the gap between the adjacent gate structures. | 2013-07-11 |
20130178045 | Method of Forming Transistor with Increased Gate Width - Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess. | 2013-07-11 |
20130178046 | METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 10 | 2013-07-11 |
20130178047 | Highly Luminescent II-V Semiconductor Nanocrystals - A population of semiconductor nanocrystals can include cores including a II-V semiconductor material, e.g., Cd | 2013-07-11 |
20130178048 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING AND RELATED DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer. | 2013-07-11 |
20130178049 | METHOD OF MANUFACTURING SUBSTRATE - The present invention is directed to a method of manufacturing a substrate, which includes loading a base substrate into a reaction furnace; forming a buffer layer on the base substrate; forming a separation layer on the buffer layer; forming a semiconductor layer on the separation layer at least two; and separating the semiconductor layer from the base substrate via the separation layer through natural cooling by unloading the base substrate from the reaction furnace. | 2013-07-11 |
20130178050 | METHOD FOR MANUFACTURING GALLIUM NITRIDE WAFER - A method for manufacturing a gallium nitride (GaN) wafer is provided. In the method for manufacturing the GaN wafer according to an embodiment, an etch stop layer is formed on a substrate, and a first GaN layer is formed on the etch stop layer. A portion of the first GaN layer is etched with a silane gas, and a second GaN layer is formed on the etched first GaN layer. A third GaN layer is formed on the second GaN layer. | 2013-07-11 |
20130178051 | Method of Impurity Introduction and Controlled Surface Removal - A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants. | 2013-07-11 |
20130178052 | METHOD FOR FABRICATING SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS - A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap. | 2013-07-11 |
20130178053 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 2013-07-11 |
20130178054 | METHODS OF MAKING LOGIC TRANSISTORS AND NON-VOLATILE MEMORY CELLS - Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned. | 2013-07-11 |
20130178055 | Methods of Forming a Replacement Gate Electrode With a Reentrant Profile - Disclosed herein are methods of forming a replacement gate structure having a reentrant profile. In one example, the method includes forming a layer of material for a sacrificial gate electrode, wherein the layer of material includes at least one impurity that changes the etch rate of the layer of material as compared to an etch rate for the layer of material without the impurity, and wherein a concentration of the at least one impurity varies along a direction that corresponds to a thickness of the layer of material, and performing another etching process on the layer of material to define a sacrificial gate electrode. The method concludes with the steps of performing another etching process to remove the sacrificial gate electrode so as to at least partially define a gate opening in a layer of insulating material and forming a replacement gate structure in the gate opening. | 2013-07-11 |
20130178056 | FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE - The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge. | 2013-07-11 |
20130178057 | Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique - Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench. | 2013-07-11 |
20130178058 | INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER - A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure. | 2013-07-11 |
20130178059 | MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF DEVICE - A manufacturing method of a device including: a first process in which a barrier film is formed on a substrate with a concave portion provided on one surface thereof so as to cover an inner wall surface of the concave portion; a second process in which a conductive film is formed so as to cover the barrier film; and a third process in which the conductive film is melted by a reflow method, wherein the method includes a process α between the second process and the third process, in which the substrate with the barrier film and the conductive film laminated thereon in this order is exposed to an atmosphere under a pressure A for a time period B, and wherein in the process α, control is carried out such that a product of the pressure A and the time period B is not greater than 6×10 | 2013-07-11 |
20130178060 | Method for Manufacturing a Barrier Layer on a Substrate and a Multi-Layer Stack - A method for manufacturing a barrier layer ( | 2013-07-11 |
20130178061 | METHOD OF MANUFACTURING POROUS FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - First, a porous insulating film | 2013-07-11 |
20130178062 | 3D IC METHOD AND DEVICE - A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding. | 2013-07-11 |
20130178063 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SILICON THROUGH VIA - A method of manufacturing semiconductor device having silicon through via is disclosed, and conductor can be fully filled in the silicon through via. First, a silicon substrate is provided. Then, the silicon substrate is etched to form a through silicon via (TSV), and the through silicon via extends down from a surface of the silicon substrate. Next, a barrier layer is formed on the silicon substrate and in the through silicon via. Then, a seed layer is formed on the barrier layer and in the through silicon via. Afterward, a wet treatment is performed on the seed layer over the silicon substrate and within the through silicon via. The through silicon via is then filled with a conductor. | 2013-07-11 |
20130178064 | POLISHING SLURRY AND CHEMICAL MECHANICAL PLANARIZATION METHOD USING THE SAME - A polishing slurry for a chemical mechanical planarization process includes polishing particles and polyhedral nanoscale particles having a smaller size than the polishing particles and including a bond of silicon (Si) and oxygen (O). | 2013-07-11 |
20130178065 | Method and Composition for Chemical Mechanical Planarization of a Metal - A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low within a wafer non-uniformity values and low residue levels remaining after polishing. | 2013-07-11 |
20130178066 | METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL-STRUCTURE MEMORY DEVICE - Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH | 2013-07-11 |
20130178067 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns. | 2013-07-11 |
20130178068 | DUAL DAMASCENE PROCESS AND APPARATUS - A method comprising providing at least one dielectric layer above a semiconductor substrate, the at least one dielectric layer having a top surface and a bottom surface; forming a photoresist layer on the top surface of the at least one dielectric layer; providing a single photomask having at least one first pattern corresponding to a conductive via and at least one second pattern corresponding to a conductive trace; patterning the photoresist layer using the single photomask, for forming a trench in the photoresist corresponding to the conductive trace and an opening in a bottom surface of the trench corresponding to the via with a single photo exposure step; and etching the dielectric through the photoresist layer to form the trench and via therein. This application also relates to photomasks for use in the methods of this application. | 2013-07-11 |
20130178069 | SILICON ETCHING FLUID AND METHOD FOR PRODUCING TRANSISTOR USING SAME - The present invention relates to a silicon etching solution which is used for selectively etching a dummy gate made of silicon in a process for producing a transistor including a laminate formed of at least a high dielectric material film and a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten by the method of removing the dummy gate made of silicon to replace the dummy gate with the metal gate and which includes 0.1 to 40% by weight of at least one alkali compound selected from the group consisting of ammonia, a diamine and a polyamine represented by the general formula (1), 0.01 to 40% by weight of at least one polyhydric alcohol selected from the group consisting of specific polyhydric alcohols and a non-reducing sugar, and 40 to 99.89% by weight of water, and a process for producing a transistor using the silicon etching solution. | 2013-07-11 |
20130178070 | ATOMIC LAYER DEPOSITION APPARATUS - An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas. | 2013-07-11 |
20130178071 | THERMAL OXIDE FILM FORMATION METHOD FOR SILICON SINGLE CRYSTAL WAFER - Disclosed is a method of forming a thermal oxide film on a silicon single crystal wafer, which includes throwing the silicon single wafer into a heat treatment furnace; elevating temperature of the heat treatment furnace up to a temperature T1 where a thermal oxide film is formed to form a thermal oxide film having a thickness d1; subsequently lowering the temperature of the heat treatment furnace down to a temperature lower than the temperature T1; and thereafter elevating the temperature of the heat treatment furnace up to a temperature T2 higher than the temperature T1 to additionally form a thermal oxide film having a thickness d2 thicker than the thickness d1. Thus, there is provided a thermal oxide film formation method to suppress occurrence of slip dislocation and/or crack of the silicon single wafer during formation of the thermal oxide film. | 2013-07-11 |
20130178072 | IN-SITU CHAMBER CLEANING FOR AN RTP CHAMBER - A method of cleaning a chamber used for annealing doped wafer substrates. In one embodiment the method provides removing dopants deposited in an annealing chamber after an annealing process of a doped substrate by flowing one or more volatilizing gases into the annealing chamber, applying heat to volatilize the deposited dopants in the annealing chamber, and exhausting the chamber to remove volatilized dopants from the annealing chamber. | 2013-07-11 |
20130178073 | COMBINATIVE TYPE SLIP RING - A slip ring includes a spindle and a plurality of insulating rings and conductive rings alternately fitted to the spindle. Each conductive ring is connected with a wire, and the wire extends out of the slip ring through a wire hole of the spindle. The insulating rings engage the spindle so that the insulating rings are unable to rotate relative to the spindle. The conductive rings engage the spindle or the neighboring insulating ring so that conductive rings are unable to rotate relative to the insulating ring. The number and size of the insulating rings and conductive rings are selectable to be fitted to the spindle. | 2013-07-11 |
20130178074 | DETECTION SIGNAL OUTPUT DEVICE - A detection signal output device includes connector terminals adapted to be connected by a cable to an external device. Fixed contacts are spaced apart from the connector terminals and output information indicating detector states. An integrated circuit includes a box-shaped package having different first and second side surfaces. First IC terminals are arranged on the first side surface and electrically connected to the fixed contacts. Second IC terminals are arranged on the second side surface and electrically connected to the connector terminals. The integrated circuit generates an information signal, in accordance with information indicating the detector states obtained through the first IC terminals, and outputs the information signal from one of the second IC terminals. The fixed contacts are arranged in correspondence with the first side surface, and the connector terminals are arranged in correspondence with the second side surface. | 2013-07-11 |
20130178075 | ELECTRICAL CONNECTOR AND ELECTRONIC APPARATUS USING THE SAME - An electrical connector and electronic apparatus using the same are provided. The electrical connector includes a first set of terminals, a second set of terminals and an insulating body. The insulating body has a first mating portion and a second mating portion. First mating portion includes an inward wall surface. First contacts of the first set of terminals and first contacts of the second set of terminals are disposed in the inward wall surface of first mating portion. Second mating portion has an outward wall surface. Second contacts of the first set of terminals and second contacts of the second set of terminals are arranged on the outward wall surface of the second mating portion. The first contacts of the first set of terminals and the first contacts of the second set of terminals elastically contact to the corresponding pads of the PCB board without bonding. | 2013-07-11 |
20130178076 | BOARD-TO-BOARD CONNECTOR - A board-to-board connector includes a male board connector and a female board connector mated with each other and having the same structure. Each board connector includes an insulating housing defining a row of first terminal grooves and a row of second terminal grooves. A plurality of first terminals is retained in the first terminal grooves respectively. A plurality of second terminals is positioned in the second terminal grooves respectively. The male board connector and the female board connector are engaged with each other to make the first terminal and the corresponding second terminal electrically interconnected steadily. The male board connector and the female board connector have the same structure. According to the present invention, it needs only one mold to produce the board-to-board connector and the cost of production will be accordingly lowered. | 2013-07-11 |
20130178077 | CONNECTORS - An electrical connector, which is adapted to a printed circuit board (PCB) with a first connection port, comprises a bottom having a base and a conductive element mounted in an opening of the base, a second connection port disposing on the base, and a housing covering the bottom. When the bottom is disposed on the PCB, the first connection port is accommodated in the opening of the base, and an elastic strip of the conductive element presses on the first connection port toward a direction parallel to the PCB for combining the electrical connector and the first connection port on the PCB, and preventing the separation or loose connection of the electrical connector from the first connection port or the PCB. | 2013-07-11 |
20130178078 | INTER-BOARD CONNECTION TERMINAL AND INVERTER AND ELECTRIC COMPRESSOR EMPLOYING THE SAME - Provided are an inter-board connection terminal with which electrical connection between two boards can be simplified, the operability and productivity thereof can be enhanced, and reliability of electrical connection can also be ensured, as well as an inverter and an electric compressor employing the same. An inter-board connection terminal includes a group of numerous metal terminals which is inserted, individually at both tips thereof, into through-holes in boards to electrically connect two boards, wherein paired resin linking members are provided, which have a predetermined space therebetween with respect to the group of metal terminals and which join the group of metal terminals into a single unit by linking the terminals in the form of a row at both tips thereof near the bases of portions to be inserted into the through-holes in the boards. | 2013-07-11 |
20130178079 | COMBINATION OF THIN TYPE BATTERY AND CIRCUIT BOARD - A combination of a thin type battery and a circuit board is provided, including a thin type battery, a circuit board, and a joint connector. The thin type battery includes a shell body, a soft packaging cell, and an electric connector. The joint connector is disposed at the circuit board and connected electrically to a circuit of the circuit board. The soft packaging cell of the thin type battery is disposed in the shell body and includes a battery body and a top sealing area. The electric connector is connected electrically to the soft packaging cell. The electric connector can be plugged into the joint connector in a first direction or a second direction, so that the thin type battery can be plugged into the mobile electronic device through the electric connector in the first direction or second direction, to supply power. | 2013-07-11 |
20130178080 | SOLDERED ELECTRONIC COMPONENTS MOUNTED SOLELY ON THE TOP SURFACE OF A PRINTED CIRCUIT BOARD - An electrical connector is securable to a top surface of a printed circuit where other electronic components are mounted. The electrical connector has one or more contact legs that are insertable through apertures in the printed circuit board from the top surface and extending through the bottom surface. A bottom portion of the contact legs may engage with a larger electrical system. The top portion of the contact legs include a shoulder and an anchor pin that mechanically assist in securing the electrical connector to the printed circuit board. | 2013-07-11 |
20130178081 | SIGNAL CONNECTOR ANTI-THEFT DEVICE SET - A signal connector anti-theft device set includes a cap, a rotating member defining multiple through holes and rotatably set in the cap, a locking member abutted against the rotating member in the cap and having a driven structure facing toward the through holes of the rotating member, and a hand tool having a working tip for rotating the rotating member into accurate alignment with the driven structure of the rotating member and then inserting through the through holes of the rotating member into the driven structure to rotate the locking member between a locking position and an unlocking position. | 2013-07-11 |
20130178082 | SWITCHING HUB DEVICE AND CONNECTOR LOCK RELEASING TOOL - A switching hub device includes a connector group including a plurality of connectors, the plurality of connectors each having a hole to insert a cable and including a locking unit to lock the cable inserted into the hole, a plurality of lock releasing members each to release the cable from the locking unit of each of the connectors by pressing a lock releasing unit provided in the cable, a supporting member to pivotally support each of the lock releasing members facing the lock releasing unit, and a handle having a fitting portion to fit with each of the lock releasing members supported by the supporting member, the handle gripping each of the lock releasing members fitted with the fitting portion. | 2013-07-11 |
20130178083 | Terminal Box and Terminal Box Fixing Arrangement - A terminal box includes a box body having a bottom portion, a terminal portion fixed to the box body, a pressing portion, a holding portion and a slide mechanism The bottom portion has an opening portion capable of receiving a terminal inserted therein from the outside. The terminal portion is capable of establishing electric conduction between the terminal portion and the terminal upon contact therewith. The pressing portion is switchable between a contacting state in which the pressing portion clamps the terminal with the terminal portion for establishing electric conduction between the terminal portion and the terminal and a spaced state spaced apart from the terminal portion. The holding portion holds the pressing portion integrally and is slidable on the box body in the direction of movement of the pressing portion to/away from the terminal portion. | 2013-07-11 |
20130178084 | LAMP HOLDER CONNECTOR - A lamp holder connector adapted for connecting with a lamp includes a first holder, a second holder, a connecting part, at least two buckling ears, a first terminal assembled in the first holder and a second terminal assembled in the second holder to electrically connect with the first terminal. Two opposite sides of the first holder defines two restraining arms. The second holder defines an accommodating chamber for receiving the connecting part therein. The connecting part defines an accommodating space for receiving the first holder therein. The two buckling ears are pivotally fastened to two sides of the connecting part. Two tops of the two buckling ears are matched with the restraining arms. Each buckling ear has at least one propping portion projecting into the accommodating space to prop up the first holder under rotating actions of the buckling ears when the lamp holder connector is disassembled. | 2013-07-11 |
20130178085 | SWITCHING CONTACTOR - A switching electrical power contactor having a bi-blade type switch, has ferrous plates attached to the blades to increase the current carrying capacity and reduce the resistance of the switch. | 2013-07-11 |
20130178086 | SWITCHING CONTACTOR - A switching electrical power contactor having a bi-blade type switch, has ferrous plates attached to the blades to increase the current carrying capacity and reduce the resistance of the switch. Flexible tangs formed at the distal end of the blades cooperate with a movable member to hold the contacts closed when the contactor is in the closed state. | 2013-07-11 |
20130178087 | CONNECTOR DRIP-PROOF MEMBER AND CABLE STRUCTURE - A connector drip-proof member includes a cylinder part configured to be attached to a cable whose end is connected to a connector so as to cover a part of the cable, and a barb portion linked to the cylinder part and configured to prevent droplets on the cable from reaching the connector. The barb portion includes an upper surface configured to face to a back end side of the cable, and an under surface configured to face to an end side of the cable. The cylinder part penetrates the barb portion from the upper surface to the under surface. The upper surface is concave. A connector drip-proof member and cable structure is provided which can be applied to a narrow space, reduce workload for attaching, and be manufactured at low costs. | 2013-07-11 |
20130178088 | Foreign Object Damage Protecting Electrical Connector Backshell Adaptor - A foreign object damage protecting electrical connector backshell adaptor including a nipple having a forward end, a rearward end, a hollow bore, and a wall surrounding the hollow bore; an adaptor mounting coupling nut fixedly attached to the nipple's forward end; a retention flange, the retention flange being fixedly attached to or formed wholly with the nipple's rearward end, the retention flange having a seam dividing the retention flange at least into a movable clamp jaw segment and an opposing clamp jaw segment; clamp actuating screws connected operatively to the retention flange for drawing the movable clamp jaw segment from a cable receiving position to a cable clamping position; a tubular sheath and receptacle extending rearwardly from and annularly about the retention flange; and an annular clamping band engaging the tubular sheath forwardly from the retention flange. | 2013-07-11 |
20130178089 | PLUG, ELECTRONIC APPARATUS, AND PLUG RECEPTACLE - There is provided a plug which includes electrodes that transmit direct-current power and an electrode cover that covers the electrodes. The electrode cover includes a lock detection unit that electrically detects that the electrode cover is locked. | 2013-07-11 |
20130178090 | LATCHING MECHANISM FOR A MODULE - One embodiment includes a latching mechanism having a latch, a cam and a slider. The cam is configured to rotate about an axis of rotation. The cam is also configured to displace an end of the latch when the cam is rotated about the axis of rotation. The slider is operably connected to the cam and is configured to cause the cam to rotate about the axis of rotation. | 2013-07-11 |
20130178091 | BUSBAR MODULE AND POWER SUPPLY UNIT INCLUDING SAME BUSBAR MODULE - In a busbar module for connecting a plurality of batteries of a battery unit, the batteries are arranged so that electrodes of each of the batteries having different polarities are disposed adjacent to each other. The busbar module includes a plurality of busbars, a plurality of terminals, a plurality of wires, a plurality of plates and a connector. The busbars connect the electrodes adjacent to each other. The terminals are connected to the busbars respectively to detect a voltage of the batteries. The wires are connected to the terminals respectively. The plates accommodate the busbar, the terminals and the wires, and provided above the battery unit. The connector connects the plates together. | 2013-07-11 |
20130178092 | IMPLEMENTING ENHANCED DIMENSIONAL STABILITY WITH GRAPHITE NANOTUBE HYBRID SOCKET - A method and structure for implementing enhanced dimensional stability with a graphite nanotube hybrid socket. A socket housing wall includes a plurality of aligned graphite nanofibers. The plurality of aligned graphite nanofibers distributing heat and providing enhanced dimensional stability. For example, the plurality of aligned graphite nanofibers more evenly distributes heat when the socket is undergoing solder reflow processes, thereby reducing strain. | 2013-07-11 |
20130178093 | Multifunction Networkable Controller Plug and Methods of Operation Thereof - A compact electrical plug characterized as a receptacle with a self-contained programmable, networkable controller which can be installed directly onto an electromechanical valve or relay. The plug has a controller built into the receptacle housing. It can be configured to run autonomously based on an internal closed loop feedback algorithm or manually controlled based on commands received remotely by a computer or custom control interface. The invention can be networked with other plugs like it providing a streamlined network where multiple electromechanical valves and\or relays can be controlled at one time. The plug has multiple visual indications providing the operating status and error states of the connected component and contained controller. | 2013-07-11 |
20130178094 | RECEPTACLE CONNECTOR - A receptacle connector matched with a plug connector includes an insulating housing, a plurality of upper and lower terminals, a locating element and a shielding shell surrounding the insulating housing. The insulating housing defines an accommodating space, and a plurality of upper and lower terminal grooves communicating with the accommodating space. Each upper terminal disposed in the upper terminal groove has a first fastening portion, a first contact portion contacting with the plug connector, and a first soldering portion. Each lower terminal disposed in the lower terminal groove has a second fastening portion, a second contact portion contacting with the plug connector, and a second soldering portion. The locating element positioned in the accommodating space defines a plurality of through-holes aligned with the upper and lower terminal grooves respectively. The first and second soldering portions further pass through the through-holes to be soldered with a circuit board. | 2013-07-11 |
20130178095 | WATERPROOF BNC CONNECTOR - A pH meter and probe with a screw-down connector that converts a standard BNC pH probe connector into an IP67 waterproof connection. | 2013-07-11 |
20130178096 | QUICK MOUNT CONNECTOR FOR A COAXIAL CABLE - A post-less coaxial cable connector includes a body, a shell, a compression ring, and a coupling portion. The shell has a collapsible groove that, when the post-less coaxial cable connector is axially compressed, collapses and engages the coaxial cable. This provides pull strength and electrical communication in the post-less coaxial cable connector. The compression ring has projections, that when the post-less coaxial cable connector is axially compressed, engage the coaxial cable jacket, providing sealing at the back end and rotation torque. | 2013-07-11 |
20130178097 | COMPRESSION CONNECTOR FOR CLAMPING/SEIZING A COAXIAL CABLE AND AN OUTER CONDUCTOR - A connector comprising a connector body having a first end and a second end, the connector body configured to receive a prepared coaxial cable, the prepared coaxial cable including an outer conductor and a center conductor, a clamp disposed within the connector body, the clamp including an internally threaded portion and a ramped surface, wherein the clamp threadably engages the prepared coaxial cable, a moveable ramped component disposed within the connector body, the moveable ramped component including an internally ramped surface, and a compression member configured for axial movable engagement with the connector body, wherein, upon axial compression of the compression member, the outer conductor flares out and is pressed between the ramped surface of the clamp and the internally ramped surface of the moveable ramped component is provided. Furthermore, a clamp and an associated method are also provided. | 2013-07-11 |
20130178098 | Connector And Connector Assembly - The connector includes a pin contact, a housing, a sealing member, and a limitation member. The pin contact is rod-shaped and makes contact with a mating contact. The housing includes a through hole through which the pin contact extends from a top of the housing to a bottom of the housing, with parts of the pin contact protruding from both of the top of the housing and the bottom of the housing. The sealing member seals the space between through hole and the pin contact. The limitation member applies a reaction force against a force experienced by the pin contact through a contact of the mating contact, so as to limit inclination of the pin contact. | 2013-07-11 |
20130178099 | HIGH-DENSITY DUAL-SOCKET CONNECTOR - The high-density connector contains an insulating body having at least two socket pieces extended towards a front direction. Each socket piece contains an accommodation space and, along a top side and a bottom side of the accommodation space, there is an array of terminals, respectively. A first terminal hole is configured on the body connecting the accommodation space. A terminal positioning seat with a second terminal hole is configured on the back side of the body. For each terminal, one of its ends penetrates the first terminal hole into the accommodation space and the other end penetrates the second terminal hole into the terminal positioning seat. The high-density connector with two sockets is capable of connecting two cables so as to achieve reduced space footprint and cost. | 2013-07-11 |
20130178100 | CONNECTOR AND ELECTRONIC DEVICE - A connector is provided in which a connector member is secured to a case and a shielding effect can be maintained even if a mating plug-type connector to be engaged therewith has a flat insulating plate with connecting portions on both of its faces, forming mutually parallel arrays of pluralities of upper terminals and lower terminals, which are strips of conductive segments. The connector member and the case are included. The connector member includes an inner shield cover that includes engaging portions having press-fractured faces, formed in its rear end. The case has resin springs which are disposed inside the tube-shaped portion of the case and extend toward the back and fixing stops which are disposed at free ends of the resin springs and increase in thickness inward from back to front. | 2013-07-11 |
20130178101 | ELECTRICAL CONNECTOR WITH GROUNGING PLATE - An electrical connector | 2013-07-11 |
20130178102 | CABLE ASSEMBLY HAVING SHIELDING PLATES BETWEEN CONDUCTIVE WIRES FOR CROSSTALK REDUCTION - A cable assembly comprises a metallic housing defining a receiving room and a number of protruding plates formed in the receiving room, and a printed circuit board received into the receiving room. The printed circuit board defines a front mating portion and a rear terminating portion defining a number of slits formed thereon for the protruding plates to pass through. And a cable comprises a plurality conductive wires electrically connected with the printed circuit board and spaced apart from each other by the protruding plates. | 2013-07-11 |
20130178103 | SAFETY PLUG ASSEMBLY - A safety plug assembly has a plug head, two resilient conductive members, two conductive bodies and a plug base. The plug head is insulated and has a plug cavity and two holding recesses. The plug cavity is defined in the front side. The holding recesses are defined longitudinally in the bottom of the plug cavity. The resilient conductive members are mounted respectively in the holding recesses. The wires are connected respectively with the resilient conductive members. The conductive bodies are respectively mounted slidably in the holding recesses in the plug head and abut respectively with the resilient conductive members. At least one of the conductive bodies is a fuse. The plug base is insulated, is mounted detachably in the plug cavity and has two plug plates abutting respective with the conductive bodies. | 2013-07-11 |
20130178104 | ELECTRONIC DEVICE PACKAGE BOX - An electronic device package box includes a base having a pin-protruding face and a first mounting face for mounting a plurality of electronic components thereto, a plurality of first pins mounted to the base for electrical connection with the electronic components and each including a first connection section protruding from the pin-protruding face, a cover connected to and cooperating with the base to define a packaging space, and a plurality of second pins mounted to the cover for electrical connection with a plurality of electronic components. The cover has a second mounting face for mounting the electronic components thereto. Each second pin includes a second connection section protruding from one of the base and the cover. | 2013-07-11 |
20130178105 | ELECTRICAL CONNECTOR AND ASSEMBLING METHOD THEREOF - The present disclosure relates to an electrical connector and an assembling method thereof. The electrical connector includes a first insulating housing, a step-shaped second insulating housing, a plurality of first contacts, a plurality of second contacts, and a plurality of third contacts. The first and third contacts are exposed over the second insulating housing and face the same direction. The second contacts are exposed over the second insulating housing and face an opposite direction. The exposed first, second, and third contacts are capable of being soldered to a transmission cable. | 2013-07-11 |
20130178106 | RECEPTACLE CONNECTOR AND ASSEMBLING METHOD THEREOF - A receptacle connector including a ladder-like insulative body, a plurality of first conductive contacts and a plurality of second conductive contacts. The first conductive contacts and the second conductive contacts are exposed toward the same side over one end of the insulative body. The first conductive contacts and the second conductive contacts can be soldered to a transmission wire for data transmission. The instant disclosure further comprises an assembling method of a receptacle connector. | 2013-07-11 |
20130178107 | CONNECTOR ASSEMBLY FOR INTERCONNECTING ELECTRICAL CONNECTORS HAVING DIFFERENT ORIENTATIONS - An electrical connector assembly including an electrical connector that has a connector body with mating and interior sides facing in opposite directions. The electrical connector also includes electrical contacts that are held by the connector body. The connector assembly also includes an interposer having a connector side, an opposite board side, and plated vias that extend into the interposer from at least one of the connector or board sides. The connector side engages the interior side of the electrical connector. The electrical contacts of the electrical connector are electrically coupled to corresponding vias. The connector assembly also includes board contacts that extend from the board side of the interposer and are electrically coupled to corresponding vias. The board contacts are communicatively coupled to the electrical contacts through the interposer. | 2013-07-11 |
20130178108 | Through-Board Card Edge Connector and Component Assembly - A through-board card edge connector has an insulative body defining a top end and a male plug portion extending transversely from the top end. The male plug portion has outer circumferential dimensions so as to extend through a mounting hole in a first electronic component, such as a PCB. An open socket is defined in an end of the male plug portion opposite from the top end and defines a first slot having first dimensions for receipt of a first card edge, and a second slot having second dimensions for receipt of a second card edge having dimensions different than the first card edge. A spring biased connector element is disposed within the open socket and is configured to make electrical contact with an edge terminal of either of a first or second card edge inserted into either of the first or second slots. | 2013-07-11 |
20130178109 | CONNECTOR - An electrical connection device comprises an electrical connector, a receiving portion, and a limiting element. The electrical connector comprises a housing, a plurality of terminals supported by the housing, and a mounting face positioned at a bottom side thereof. The receiving portion is provided to the bottom side of the electrical connector and positioned in front of the mounting face and has a receiving groove extending in a front-rear direction. The limiting element is provided through the receiving groove and positioned in the receiving portion and has an abutting-retaining face inclined to the ground and facing the mounting face. When the electrical connection device is mounted to a circuit board, the mounting face is mounted to an upper surface of a circuit board, and the abutting-retaining face abuts against a front edge of a lower surface of the circuit board. | 2013-07-11 |
20130178110 | PLUG CONNECTOR - A plug connector includes an insulating housing, a plurality of first terminals, a plurality of second terminals and an artistic terminal which are inserted forward in the insulating housing. The first terminal has a first soldering portion bending sideward and then extending rearward at a rear end thereof. The second terminal has a second soldering portion bending towards one side opposite to the first soldering portion and then extending rearward at a rear end thereof. A positioning bracket is mounted to a rear of the insulating housing and has a base body with a plurality of positioning fillisters apart opened in a top surface thereof. The first soldering portions and the second soldering portions are positioned in the positioning fillisters respectively. A metal shell sheathes the insulating housing. | 2013-07-11 |
20130178111 | CONNECTOR AND ELECTRONIC APPARATUS SYSTEM - A connector is disclosed. The connector includes a first connection component and a second connection component. The first connection component includes two groups of contact pins and the second connection component includes two groups of corresponding pins. The two groups of contact pins are arranged in an opposite order and the two groups of corresponding pins are also arranged in an opposite order. | 2013-07-11 |
20130178112 | Connection Interface and Cable - The invention discloses a connection interface. The connection interface includes a first set of pins, including a plurality of pins corresponding to Universal Serial Bus (USB) 3.0 specifications; and a second set of pins, including a plurality of pins corresponding to USB 2.0 specifications; wherein the first set of pins and the second set of pins are arranged side-by-side with each other, and the second set of pins are arranged according to a front panel header definition of the USB 2.0 specifications. | 2013-07-11 |
20130178113 | METHOD AND ADJUSTMENT DEVICE FOR ORIENTATING CONTACT PINS OF AN ELECTRIC COMPONENT AND ELECTRIC COMPONENT - The invention relates to a method ( | 2013-07-11 |