28th week of 2015 patent applcation highlights part 47 |
Patent application number | Title | Published |
20150194431 | STATIC RANDOM ACCESS MEMORY CELL AND FORMING METHOD THEREOF - A SRAM cell and a forming method thereof are provided. The SRAM cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor. The method includes: providing a semiconductor substrate; forming a pull-up transistor, a pull-down transistor and a pass gate transistor on the semiconductor substrate; forming a tensile stress film covering the pull-up and pull-down transistors; and forming an interlayer dielectric isolating layer covering the tensile stress film and the pass gate transistor. Write margin of the SRAM cell may be increased and an area of the SRAM cell may be reduced. | 2015-07-09 |
20150194432 | BUTTED CONTACT SHAPE TO IMPROVE SRAM LEAKAGE CURRENT - The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current. | 2015-07-09 |
20150194433 | GATE SUBSTANTIAL CONTACT BASED ONE-TIME PROGRAMMABLE DEVICE - A field-effect transistor (FET) based one-time programmable (OTP) device is discussed. The OTP device includes a fin structure, a gate structure, a first contact region, and a second contact region. The first contact region includes an insulating region and a conductive region and is configured to be electrically isolated from the gate structure. While, the second contact region includes the conductive region and is configured to be electrically coupled to at least a portion of the gate structure. The OTP device is configured to be programmed by disintegration of the insulating region in response to a first voltage being applied to the first contact and a second voltage being applied to the second contact region simultaneously, where the second voltage is higher than the first voltage by a threshold value. | 2015-07-09 |
20150194434 | MEMORY DEVICE AND METHODS OF FORMING MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A method of forming a memory device is provided. A first conductive layer is formed on a substrate. The first conductive layer is patterned to form at least two trenches extending along a first direction therein. An insulating layer is formed on surfaces of the trenches and on a surface of the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form at least one control gate extending along a second direction different from the first direction. The first conductive layer is patterned to form at least one floating gate below the control gate and to form a select gate adjacent to the control gate. | 2015-07-09 |
20150194435 | VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES HAVING DUMMY CHANNEL HOLES - A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed. | 2015-07-09 |
20150194436 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME - Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell | 2015-07-09 |
20150194437 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions. | 2015-07-09 |
20150194438 | Semiconductor Device Having Positive Fixed Charge Containing Layer - A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively. | 2015-07-09 |
20150194439 | Embedded NVM in a HKMG Process - A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells ( | 2015-07-09 |
20150194440 | Nonvolatile Memory Devices And Methods Of Fabricating The Same - A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer. | 2015-07-09 |
20150194441 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is method of manufacturing a semiconductor device. The method includes: forming an insulating film on one side of a substrate; forming a carbon film on the insulating film formed in the forming of the insulating film; forming an insulating film-carbon film laminate including a plurality of insulating films and carbon films alternately laminated on the one side of the substrate, by repeating the forming of the insulating film and the forming of the carbon film multiple times; removing the carbon films included in the insulating film-carbon film laminate; and forming electrode films in regions from which the carbon films are removed in the removing of the carbon films to obtain an insulating film-electrode film laminate in which the insulating films and the electrode films are laminated in a plurality of layers. | 2015-07-09 |
20150194442 | GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE - Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 μm or more. A sheet resistance of a group III-nitride-film-side main surface is 200 Ω/sq or less. | 2015-07-09 |
20150194443 | Display Circuitry with Reduced Metal Routing Resistance - A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions. | 2015-07-09 |
20150194444 | DISPLAY DEVICE - Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver. | 2015-07-09 |
20150194445 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable display device which has high aperture ratio and includes a transistor with stable electrical characteristics is manufactured. The display device includes a driver circuit portion and a display portion over the same substrate. The driver circuit portion includes a driver circuit transistor and a driver circuit wiring. A source electrode and a drain electrode of the driver circuit transistor are formed using a metal. A channel layer of the driver circuit transistor is formed using an oxide semiconductor. The driver circuit wiring is formed using a metal. The display portion includes a pixel transistor and a display portion wiring. A source electrode and a drain electrode of the pixel transistor are formed using a transparent oxide conductor. A semiconductor layer of the pixel transistor is formed using the oxide semiconductor. The display portion wiring is formed using a transparent oxide conductor. | 2015-07-09 |
20150194446 | Display Device and Driving Method Thereof - To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a third period, a voltage based on a video signal voltage and the threshold voltage of the first transistor is held in the first and second storage capacitors; and in a fourth period, voltages held in the first and second storage capacitors are applied to a gate terminal of the first transistor to supply a current to a light-emitting element, so that the light-emitting element emits light. Through the operation process, a current obtained by compensating variations in the threshold voltage of the first transistor can be supplied to the light-emitting element, thereby variations in luminance can be suppressed. | 2015-07-09 |
20150194447 | Display Device And Semiconductor Device - An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased. | 2015-07-09 |
20150194448 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer. | 2015-07-09 |
20150194449 | PIXEL SUBSTRATE AND FABRICATION METHOD THEREOF - A pixel substrate and a fabrication method thereof are provided. The method includes: forming a gate and a lower pad on a substrate; forming a gate insulating layer overlaying the gate and the lower pad; forming a channel layer and a first electrode layer on the gate insulating layer, in which the projection areas of the channel layer and the gate on the substrate are overlapped; forming an etching-barrier material layer on the substrate and simultaneously forming a contact opening at the gate insulating layer to expose the lower pad; forming a source, a drain and an upper pad on the substrate; forming a protective layer; forming a second electrode layer with multiple slits on the protective layer, in which one of the first and second electrode layers is electrically connected to the drain. The invention can simplify the process steps and reduce fabrication time. | 2015-07-09 |
20150194450 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - Embodiments of the disclosure provide a thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device. The thin film transistor comprises a substrate ( | 2015-07-09 |
20150194451 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATION FOR THE SAME - A liquid crystal display device is disclosed. The device includes: a first substrate, a thin film transistor formed in a first, non-transmissive region on the first substrate, including a gate electrode, a source electrode and a drain electrode, and a storage capacitor formed in a second, transmissive region on the first substrate, where a first electrode and a second electrode of the storage capacitor are made of a transparent conductive material | 2015-07-09 |
20150194452 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE PHOTOELECTRIC CONVERSION APPARATUS - In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region. | 2015-07-09 |
20150194453 | SEMICONDUCTOR STRUCTURE FOR SUPPRESSING HOT CLUSTER - A semiconductor structure for suppressing a hot cluster is disclosed. An isolation well region which has an extension tip extending toward a substrate is formed in an epitaxial layer disposed on the substrate are of a first conductive type. A first element region and a second element region are disposed in the epitaxial layer to sandwich the isolation well region. The extension tip and the substrate together suppresses a leak current which forms a hot cluster and flows from the first element region via the extension tip to the second element region. | 2015-07-09 |
20150194454 | VISION SENSOR CHIP WITH OPEN-LOOP AMPLIFIER, OPERATING METHOD, AND DATA PROCESSING SYSTEM INCLUDING SAME - A vision sensor chip includes a photoelectric conversion element that generates a current based on an incident light, a current-voltage (I-V) converter that converts the current into a voltage, an AC coupling capacitor directly connected to the I-V converter, an open-loop amplifier that includes a reset switch and amplifies a voltage provided by the I-V converter via the AC coupling capacitor. An event detection block detects motion according to a change in the amplified output voltage and generates first and second detection signals. A reset signal generator generates a reset signal controlling operation of the reset switch in response to first and second control signals respectively related to the first and second detection signals. | 2015-07-09 |
20150194455 | 3DIC Seal Ring Structure and Methods of Forming Same - A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip. | 2015-07-09 |
20150194456 | IMAGE SENSOR WITH HYBRID HETEROSTRUCTURE - An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter. | 2015-07-09 |
20150194457 | SOLID-STATE IMAGING DEVICE, CAMERA, AND DESIGN METHOD FOR SOLID-STATE IMAGING DEVICE - A solid-state imaging device including two semiconductor substrates arranged in layers is provided. Each semiconductor substrate has a semiconductor region in which a circuit constituting a part of a pixel array is formed. The circuits in the two semiconductor substrates are electrically connected to each other. Each semiconductor substrate includes one or more contact plugs for supplying a voltage to the semiconductor region. The number of the contact plugs of one semiconductor substrate in the pixel array is different from the number of the contact plugs of the other semiconductor substrate in the pixel array. | 2015-07-09 |
20150194458 | SOLID-STATE IMAGE SENSING DEVICE - A solid-state image sensing device is configured such that a first voltage is applied to a first conductivity type semiconductor region and a second voltage is applied to source-drain regions having a second conductivity type of the MOS capacitance to apply inverse bias between the semiconductor region and the source-drain regions of the MOS capacitance. | 2015-07-09 |
20150194459 | RADIATION DETECTORS AND METHODS OF FABRICATING RADIATION DETECTORS - Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps. The method also includes growing a passivation oxide layer on a top of the polished first surface and depositing patterned metal contacts on a top of the passivation oxide layer. The method further includes applying a protecting layer on the patterned deposited metal contacts, etching a second surface of the semiconductor and applying a monolithic cathode electrode on the etched second surface of the semiconductor. The method additionally includes removing the protecting layer from the patterned metal contacts on the first surface, wherein the patterned metal contacts are formed from one of (i) reactive metals and (ii) stiff-rigid metals for producing inter-band energy-levels in the passivation oxide layer. | 2015-07-09 |
20150194460 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing procedure of a semiconductor device is simplified. In a manufacturing method of a semiconductor device, in each of regions AR with pixels for detecting different colored lights, a liner film LF | 2015-07-09 |
20150194461 | METHOD FOR FABRICATING SENSOR - A method for fabricating a sensor, comprising: forming a pattern of a bias line on a base substrate by using a first patterning process; forming a pattern of a transparent electrode, a pattern of a photodiode, a pattern of a receive electrode, a pattern of a source electrode, a pattern of a drain electrode, a pattern of a data line and a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer, a pattern of a first passivation layer, a pattern of a gate electrode and a pattern of a gate line by using a third patterning process. The above method reduces the number of used mask in the fabrication processes as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the yield rate. | 2015-07-09 |
20150194462 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor includes forming a resist film with a thickness of not less than 7 μm on a semiconductor substrate including an active region and an element isolation region, forming a resist pattern including an opening by performing a photolithography process on the resist film, and implanting ions into a pixel array region on the semiconductor substrate through the opening, wherein the opening of the resist pattern includes a corner portion, and the corner portion is positioned not above the element isolation region but above the active region. | 2015-07-09 |
20150194463 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing an image sensor includes forming a resist film with a thickness of not less than 7 μm on a substrate having an effective region including a pixel array region and a peripheral region, and a non-effective region, forming a resist pattern including first, second and third openings from the resist film, and implanting ions into the pixel array region through the first, second and third openings. The first opening is arranged in the effective region to implant the ions into the pixel array region, the third opening is arranged in the non-effective region, and at least a part of the second opening is arranged between the first opening and the third opening, and a minimum curvature radius of an edge of the second opening is larger than that of the third opening. | 2015-07-09 |
20150194464 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE - A light receiving layer is formed with an array of photodiodes for accumulating signal charge produced by photoelectric conversion of incident light. A wiring layer provided with electrodes and wiring for controlling the photodiodes is formed behind the light receiving layer in a traveling direction of the incident light. In the light receiving layer, there is formed a projection and depression structure in which a pair of inclined surfaces have symmetric inclination directions and each inclined surface corresponds to each photodiode. Each inclined surface makes the incident light enter each photodiode by a light amount corresponding to an incident angle. | 2015-07-09 |
20150194465 | Pad Structures Formed in Double Openings in Dielectric Layers - An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening. | 2015-07-09 |
20150194466 | LIGHT-EMITTING DEVICE HAVING A PLURALITY OF CONCENTRIC LIGHT TRANSMITTING AREAS - The light-emitting device of the present invention includes LED chips provided on a ceramic substrate and a sealing material in which the LED chips are embedded. The sealing material contains a fluorescent substance and divided into a first fluorescent-substance-containing resin layer and a second fluorescent-substance-containing resin layer by a first resin ring and a second resin ring. | 2015-07-09 |
20150194467 | DOUBLE-SIDED DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A double-sided display apparatus and a method of manufacturing the same are provided. The double-sided display apparatus includes a first substrate and a second substrate arranged opposite to each other; a first transparent electrode and a second reflective electrode arranged on the first substrate; a first reflective electrode opposed to the first transparent electrode on the first substrate and a second transparent electrode opposed to the second reflective electrode on the first substrate arranged on the second substrate; and a quantum light-emitting layer arranged between the respectively corresponded transparent electrodes and reflective electrodes, the quantum light-emitting layer including charge transport particles and QD light-emitting material mixed therein. The provided double-sided display apparatus is lighter, thinner, more portable, and of low cost. | 2015-07-09 |
20150194468 | HIGH CURRENT CAPABLE ACCESS DEVICE FOR THREE-DIMENSIONAL SOLID-STATE MEMORY - The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element. | 2015-07-09 |
20150194469 | SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - Provided is a solid-state image pickup device that makes it possible to enhance image quality, and a manufacturing method thereof, and an electronic apparatus. A solid-state image pickup device includes a pixel section that includes a plurality of pixels, the pixels each including one or more organic photoelectric conversion sections, wherein the pixel section includes an effective pixel region and an optical black region, and the organic photoelectric conversion sections of the optical black region include a light-shielding film and a buffer film on a light-incidence side. | 2015-07-09 |
20150194470 | DISPLAY APPARATUS, METHOD OF IMAGE DISPLAY AND TOUCH SENSE THEREOF - The present invention discloses a display apparatus, comprising: a control unit, employed for setting an image display period and a touch sense period and generating image display data, a first control signal and a second control signal; a display panel, employed for displaying images and generating a touch sense signal. The present invention also discloses a method of image display and touch sense of a display apparatus. The present invention integrates the image display function and the touch sense function without stacking the touch panel and promotes the display quality. | 2015-07-09 |
20150194471 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an organic light emitting display device having excellent lifespan and current efficiency characteristics, as well as high luminance to provide increased resolution and improved reliability, and a method for manufacturing the same. The organic light emitting display device comprises a substrate having first, second, and third pixel regions; a first electrode arranged on the substrate; a second electrode arranged on the first electrode; and an organic layer arranged between the first electrode and the second electrode. The organic layer includes first, second and third organic layers on the first, second and third pixel regions, respectively. Each of the first, second and third organic layers includes a plurality unit organic layers and at least one charge generating layer arranged between the plurality of unit organic layers. | 2015-07-09 |
20150194472 | PIXEL STRUCTURE FOR DISPLAY PANEL AND DISPLAY PANEL - The present disclosure provides a pixel structure for a display panel and a display panel. The pixel structure includes a pixel, a first scan line, a second scan line, a first data line and a second data line. The pixel includes a first sub-pixel, a second-sub pixel and a third sub-pixel. The first scan line is coupled to the first sub-pixel and the second sub-pixel; the second scan line is coupled to the third sub-pixel; the first data line is coupled to the first sub-pixel and the third sub-pixel; and the second data line is coupled to the second sub-pixel. By employing the pixel structure for a display panel according to the present disclosure, a layout of three sub-pixels are more reasonable, and the problem that the existing RGB arrangement structure of pixels results in too small traverse width of sub-pixels is solved. | 2015-07-09 |
20150194473 | Device Comprising Deuterated Organic Interlayer - The present invention relates to devices that can be manipulated or controlled with a magnetic field, such as a spin-valve device, an organic light-emitting device, a compass, or a magnetometer. The devices of the invention comprise an organic interlayer comprising a deuterated organic material. | 2015-07-09 |
20150194474 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode display panel including an upper substrate, an organic light emitting device facing the upper substrate and emitting a light to the upper substrate, and a light extraction layer disposed between the upper substrate and the organic light emitting device, including first and second optical layers each having a polymer network liquid crystal and having different optical properties, and exiting the light to the outside of the upper substrate. The optical property of the polymer network liquid crystal in the first optical layer differs from the optical property of the polymer network liquid crystal in the second optical layer. | 2015-07-09 |
20150194475 | THIN-FILM SEMICONDUCTOR DEVICE, ORGANIC EL DISPLAY DEVICE, AND MANUFACTURING METHODS THEREOF - A thin-film semiconductor device includes a substrate, a second protection layer, and an oxide semiconductor layer between the substrate and the second protection layer. The second protection layer has provided therein at least one through-hole in which an extraction electrode is embedded, the extraction electrode being electrically connected with the oxide semiconductor layer. The second protection layer has film density of 2.80 g/cm | 2015-07-09 |
20150194476 | METHOD FOR MANUFACTURING DISPLAY DEVICE - It is an object of the present invention to provide a technique for manufacturing a highly reliable display device at low cost with high yield. A first electrode layer is formed by a sputtering method using a gas containing hydrogen or H | 2015-07-09 |
20150194477 | Semiconductor Device and Method of Driving the Semiconductor Device - Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT ( | 2015-07-09 |
20150194478 | Capacitors and Methods of Forming Capacitors - A method of forming a capacitor includes forming an elevationally elongated and elevationally inner capacitor electrode that comprises different composition laterally-outermost and laterally-innermost conductive portions that have different respective intrinsic residual mechanical stress. The innermost conductive portion is formed to have greater mechanical stress in the compressive direction than the outermost conductive portion. A capacitor dielectric is formed over the inner capacitor electrode and an elevationally outer capacitor electrode is formed over the capacitor dielectric. A capacitor construction independent of the method formed is disclosed. | 2015-07-09 |
20150194479 | SEMICONDUCTOR DEVICE, OR CRYSTAL - There is provided a semiconductor device including corundum crystal films of good quality. There is provided a semiconductor device including a base substrate, a semiconductor layer, and an insulating film each having a corundum crystal structure. Materials having a corundum crystal structure include many types of oxide films capable of functioning as an insulating film. Since all the base substrate, the semiconductor layer, and the insulating film have a corundum crystal structure, it is possible to achieve a semiconductor layer and an insulating film of good quality on the base substrate. | 2015-07-09 |
20150194480 | Compressive Polycrystalline Silicon Film and Method of Manufacture Thereof - In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C. | 2015-07-09 |
20150194481 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress. | 2015-07-09 |
20150194482 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling. | 2015-07-09 |
20150194483 | SEMICONDUCTOR DEVICE - An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode. | 2015-07-09 |
20150194484 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 2015-07-09 |
20150194485 | MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL - A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized. | 2015-07-09 |
20150194486 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided herein. A semiconductor device includes a conductor concentrically surrounding an insulator, and the insulator concentrically surrounding a column. The conductor, the insulator and the conductor are alternately configured to be a transistor, a resistor, or a capacitor. The column also functions as a via to send signals from a first layer to a second layer of the semiconductor device. The combination of via and at least one of a transistor, a capacitor, or a resistor in a semiconductor device decreases an area penalty as compared to a semiconductor device that has vias formed separately from at least one of a transistor, a capacitor, or resistor. | 2015-07-09 |
20150194487 | Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric - Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material. | 2015-07-09 |
20150194488 | TRANSISTOR AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a transistor includes: a structural body; an insulating film; a control electrode; a first electrode; and a second electrode. The structural body includes a first through a third semiconductor regions, and includes a compound semiconductor having a first and a second elements. The first electrode is electrically continuous with the third semiconductor region. The second electrode is electrically continuous with the first semiconductor region. The structural body has a first region provided above a lower end of the second semiconductor region and a second region other than the first region. The first region is a region formed by making a ratio of concentration of source gas of the second element to concentration of source gas of the first element larger than 1.0. Impurity concentration of the first conductivity type in the first region is higher than that in the second region. | 2015-07-09 |
20150194489 | NANOWIRE SEMICONDUCTOR DEVICE PARTIALLY SURROUNDED BY A GRATING - A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20. | 2015-07-09 |
20150194490 | Tuning Doping Concentration in III-V Compound Semiconductor through Co-Doping - A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type. | 2015-07-09 |
20150194491 | Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device - Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer. | 2015-07-09 |
20150194492 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film. | 2015-07-09 |
20150194493 | NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor epitaxial wafer includes a substrate, and a nitride semiconductor layer formed on the substrate, the nitride semiconductor layer including a (002) plane in an upper surface thereof. An in-plane dispersion of a full width half maximum (FWHM) of an X-ray rocking curve in the (002) plane or a (100) plane of the nitride semiconductor layer is not more than 30%. The wafer is not less than 100 μm in thickness and not less than 50 mm in diameter. | 2015-07-09 |
20150194494 | FIELD-EFFECT TRANSISTOR FOR HIGH VOLTAGE DRIVING AND MANUFACTURING METHOD THEREOF - Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased. | 2015-07-09 |
20150194495 | MOSFET TERMINATION TRENCH - A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon can be deposited into the termination trench. A second oxide can be deposited above the first polysilicon. A mask can be deposited above the second oxide and the termination trench. The first oxide can be removed from the core trench. A third oxide can be deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench. | 2015-07-09 |
20150194496 | CONTACT RESISTANCE REDUCTION IN FINFETS - A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins. | 2015-07-09 |
20150194497 | METHOD OF FORMING CHANNEL OF GATE STRUCTURE - A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench. | 2015-07-09 |
20150194498 | THIN-FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - Embodiments of the invention provide a thin-film transistor and a fabrication method thereof, an array substrate and a display device. The thin-film transistor comprises a gate electrode ( | 2015-07-09 |
20150194499 | VARIED SILICON RICHNESS SILICON NITRIDE FORMATION - A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness. | 2015-07-09 |
20150194500 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES USING SELF-ALIGNED PROCESS TO INCREASE DEVICE PACKING DENSITY - A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure. | 2015-07-09 |
20150194501 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprising: forming a gate stack structure and gate spacers on the substrate; forming the raised S/D regions on the substrate on both sides of the gate stack structure and the gate spacers; depositing a lower interlayer dielectric layer on the entire device, and planarizing the lower interlayer dielectric layer and the gate stack structure until the raised S/D regions are exposed; selective epitaxial growing to form the S/D extension regions in the raised S/D regions; forming an upper interlayer dielectric layer on the S/D extension regions; etching the upper interlayer dielectric layer until the S/D extension regions to form an S/D contact hole; forming a metal silicide in the S/D contact hole. | 2015-07-09 |
20150194502 | MANUFACTURING METHOD OF LOW TEMPERATURE POLYSILICON, LOW TEMPERATURE POLYSILICON FILM AND THIN FILM TRANSISTOR - A method of manufacturing low temperature polysilicon is provided, comprising: depositing a buffer layer ( | 2015-07-09 |
20150194503 | Fin Structure of Semiconductor Device - Semiconductor devices and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacturing a semiconductor device comprises forming a fin structure over a substrate. The fin structure may comprise a lower portion protruding from a major surface of the substrate, an upper portion, and a middle portion between the lower portion and the upper portion, wherein the lower portion and the middle portion differ in composition. The method may further include forming an isolation structure surrounding the fin structure and oxidizing the fin structure. The oxidizing may form a pair of notches extending from sidewalls of the fin structure into the middle portion of the fin structure. | 2015-07-09 |
20150194504 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins. | 2015-07-09 |
20150194505 | Manufacture of a Variation Resistant Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) - Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate. | 2015-07-09 |
20150194506 | METHOD OF FORMING INTEGRATED CIRCUIT HAVING MODIFIED ISOLATION STRUCTURE - A method includes forming an isolation structure partially buried in a substrate. A portion of the isolation structure protrudes from an upper surface of the substrate. The isolation structure is partially removed, thereby forming a modified isolation structure. An upper surface of the modified isolation structure is lower than the upper surface of the substrate. A gate dielectric structure is formed to be partially on the substrate and partially on the upper surface of the modified isolation structure. | 2015-07-09 |
20150194507 | SILICON-ON-NOTHING FINFETS - A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material. | 2015-07-09 |
20150194508 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced. | 2015-07-09 |
20150194509 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device including a semiconductor element which has favorable characteristics. A manufacturing method of the present invention includes the steps of: forming a first conductive layer which functions as a gate electrode over a substrate; forming a first insulating layer to cover the first conductive layer; forming a semiconductor layer over the first insulating layer so that part of the semiconductor layer overlaps with the first conductive layer; forming a second conductive layer to be electrically connected to the semiconductor layer; forming a second insulating layer to cover the semiconductor layer and the second conductive layer; forming a third conductive layer to be electrically connected to the second conductive layer; performing first heat treatment after forming the semiconductor layer and before forming the second insulating layer; and performing second heat treatment after forming the second insulating layer. | 2015-07-09 |
20150194510 | SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench. | 2015-07-09 |
20150194511 | SILICON-CONTROLLED RECTIFICATION DEVICE WITH HIGH EFFICIENCY - A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. | 2015-07-09 |
20150194512 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer. | 2015-07-09 |
20150194513 | Semiconductor Device and Method - A semiconductor device includes a first compound semiconductor material including a first doping concentration and a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material including a different material than the first compound semiconductor material. The semiconductor device further includes a control electrode and at least one buried semiconductor material region including a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the first compound semiconductor material in a region other than a region of the first compound semiconductor material being covered by the control electrode. | 2015-07-09 |
20150194514 | COMPOUND SEMICONDUCTOR DEVICE HAVING A GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME - On a surface of a compound semiconductor layer including inner wall surfaces of an electrode trench, an etching residue | 2015-07-09 |
20150194515 | Programmable antenna controlled impedance mosfet - Hop frequency radio technologies use dynamic modulation frequency control through a single antenna with non-ideal performance as antenna length is inversely proportional to modulation frequency. The Programmable Antenna Controlled Impedance Mosfet is a digitally controlled variable length antenna that can be used to maximize power and bandwidth efficiencies in hop frequency applications. | 2015-07-09 |
20150194516 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling. | 2015-07-09 |
20150194517 | GATE STACK AND CONTACT STRUCTURE - A process for fabrication of semiconductor devices, particularly FinFETs, having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length. | 2015-07-09 |
20150194518 | METHOD AND APPARATUS FOR MITIGATING EFFECTS OF PARASITIC CAPACITANCE IN SEMICONDUCTOR DEVICES - Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer; and a first contact and a second contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance. | 2015-07-09 |
20150194519 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To improve the reliability of a semiconductor device. In particular, the reading of incorrect information from a memory cell is suppressed. A first low-concentration region is formed in a well, and is located under a side wall insulating film in a planar view. The first low-concentration region has a second conductivity type, and the second conductivity-type impurity concentration is lower than the impurity concentration in a drain. A second low-concentration region is formed in the well, and is located under a spacer insulating film in a planar view. In addition, a second conductivity type impurity concentration in the second low-concentration region is lower than the second conductivity-type impurity concentration in the first low-concentration region, and is higher than the second conductivity-type impurity concentration in a portion located under the insulating film of the well. | 2015-07-09 |
20150194520 | NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film. | 2015-07-09 |
20150194521 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 2015-07-09 |
20150194522 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 2015-07-09 |
20150194523 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. At least two active fins protrude from a substrate. A gate pattern crosses the at least two active fins, covering part of each active fin. A seed layer is disposed on other part of the each active fin. The other part of the each active fin is not covered with the gate pattern. An epitaxial layer is disposed on the seed layer. | 2015-07-09 |
20150194524 | FINFET DEVICE AND METHOD - A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions. | 2015-07-09 |
20150194525 | SILICON GERMANIUM FINFET FORMATION BY GE CONDENSATION - A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film. | 2015-07-09 |
20150194526 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH RECESS, EPITAXIAL GROWTH AND DIFFUSON - A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate. | 2015-07-09 |
20150194527 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE - A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate. | 2015-07-09 |
20150194528 | SEMICONDUCTOR DEVICE - A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate. | 2015-07-09 |
20150194529 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of a bottom part of the pillar-shaped silicon layer is equal to a width of a top part of the fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of a contact. | 2015-07-09 |
20150194530 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping at least a portion of the gate electrode, a plurality of etch stoppers on the semiconductor layer, and a source electrode and a drain electrode spaced apart from each other and disposed on the etch stoppers and the semiconductor layer, wherein a plurality of channel regions are defined in the semiconductor layer by the etch stoppers on the semiconductor layer. | 2015-07-09 |